JPS6316644A - Manufacture of package for housing semiconductor element - Google Patents
Manufacture of package for housing semiconductor elementInfo
- Publication number
- JPS6316644A JPS6316644A JP16139186A JP16139186A JPS6316644A JP S6316644 A JPS6316644 A JP S6316644A JP 16139186 A JP16139186 A JP 16139186A JP 16139186 A JP16139186 A JP 16139186A JP S6316644 A JPS6316644 A JP S6316644A
- Authority
- JP
- Japan
- Prior art keywords
- unfired ceramic
- ceramic body
- unfired
- holes
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 35
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000000919 ceramic Substances 0.000 claims abstract description 82
- 238000000034 method Methods 0.000 claims abstract description 14
- 229910052751 metal Inorganic materials 0.000 claims description 29
- 239000002184 metal Substances 0.000 claims description 29
- 238000010030 laminating Methods 0.000 claims description 3
- 238000010304 firing Methods 0.000 claims description 2
- 238000007639 printing Methods 0.000 abstract description 3
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 18
- 239000000758 substrate Substances 0.000 description 8
- 238000003860 storage Methods 0.000 description 4
- 239000000843 powder Substances 0.000 description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 239000011148 porous material Substances 0.000 description 2
- 238000004080 punching Methods 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000007606 doctor blade method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009429 electrical wiring Methods 0.000 description 1
- 239000012777 electrically insulating material Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000007858 starting material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路素子（ＩＣ）を収納するための
半導体素子収納用パッケージの製造法に関し、より詳細
には広面積の未焼成セラミックシートを出発材料として
小面積の半導体素子収納用パフケージを可能な限り多数
個集約的に、かつ生産性良く得る方法に関するものであ
る。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a package for accommodating a semiconductor integrated circuit (IC), and more particularly, it relates to a method for manufacturing a package for accommodating a semiconductor integrated circuit (IC), and more specifically, it relates to a method for manufacturing a package for accommodating a semiconductor integrated circuit (IC). The present invention relates to a method for obtaining as many small-area puff cages for storing semiconductor elements as possible in an intensive manner and with high productivity using a starting material.
（従来の技術）
従来、半導体素子、特に半導体集積回路素子を収納する
ための半導体素子収納用パッケージは第３図に示すよう
に、アルミナセラミックス等の電気絶縁材料から成り、
その略中央部に半導体素子を取着するためのキャビティ
Ａ及び該キャビティＡ周辺より側面を介し上面にまで導
出されたタングステン（Ｗ）、モリブデン（？ｔｏ）等
の金属粉末から成るリード金属層１２を有する絶縁基体
１１と蓋体１３とから構成されており、その内部に半導
体素子１４が収納され、気密封止されて半導体装置とな
る。(Prior Art) Conventionally, semiconductor element housing packages for housing semiconductor elements, particularly semiconductor integrated circuit elements, are made of electrically insulating materials such as alumina ceramics, as shown in FIG.
A cavity A for attaching a semiconductor element is provided approximately at the center thereof, and a lead metal layer 12 made of metal powder such as tungsten (W) or molybdenum (?to) is led out from the vicinity of the cavity A to the upper surface through the side surface. The semiconductor element 14 is housed inside the insulating base 11 and the lid 13, and the semiconductor element 14 is hermetically sealed to form a semiconductor device.
この従来の半導体素子収納用パッケージは、そのキャビ
ティＡ底面に半導体素子１４を取着し、該半導体素子１
４の各電極をキャビティＡ周辺のリード金属層１２にボ
ンディングワイヤを介し接続するとともに気密に封止し
た後、裏向きにしてリード金属層１２の基体１１上面部
を電気回路基板１５の電気配線１５ａ上に載置させ、リ
ード金属層１２と電気配線１５ａとを半田等の接着材を
介し取着することによって電気回路基板１５上に取着さ
れ、絶縁基体１１の底面部には半導体素子１４の発する
熱を外部に良好に放出するために銅（Ｃｕ）等から成る
放熱体１６が取着される。This conventional semiconductor element storage package has a semiconductor element 14 attached to the bottom surface of the cavity A, and the semiconductor element 1
After each electrode of 4 is connected to the lead metal layer 12 around the cavity A via a bonding wire and hermetically sealed, the top surface of the base 11 of the lead metal layer 12 is connected face down to the electric wiring 15a of the electric circuit board 15. The semiconductor element 14 is mounted on the electrical circuit board 15 by attaching the lead metal layer 12 and the electrical wiring 15a through an adhesive such as solder. A heat radiator 16 made of copper (Cu) or the like is attached to effectively radiate the generated heat to the outside.
かかる従来の半導体素子収納用パフケージは、その絶縁
基体１１が通常、以下に述べる方法によって製作される
。The insulating base 11 of such a conventional puff cage for housing semiconductor devices is usually manufactured by the method described below.
即ち、第４図に示すように、まず貫通孔２２の配列によ
って複数の区画に区分された第１の未焼成セラミックシ
ート２１と、該第１の未焼成セラミックシート２１と実
質的に同一孔径、同一配列の貫通孔２７を有し、かつ内
部に半導体素子の各電極が接続される配線パターン２８
を設けた３枚のシート２４゜２５．２６から成る第２の
未焼成セラミックシート２３を準備するとともにこれら
を貫通孔の位置を合わせて積層し、積層未焼成セラミッ
ク体２９を得る。That is, as shown in FIG. 4, first, there is a first unfired ceramic sheet 21 divided into a plurality of sections by the arrangement of through holes 22, and a hole having a diameter substantially the same as that of the first unfired ceramic sheet 21; A wiring pattern 28 having through holes 27 in the same arrangement and to which each electrode of the semiconductor element is connected.
A second unfired ceramic sheet 23 consisting of three sheets 24.degree. 25.26 is prepared, and these sheets are laminated with the through holes aligned to obtain a laminated green ceramic body 29.
次に前記積層未焼成セラミック体２９の上面及び貫通孔
２２．２７内壁に、前記配線パターン２日に電気的に接
続させて金属ペーストを印刷塗布し、配線パターン２８
を積層未焼成セラミック体２９の上面に導出させるべく
リード用金属層３０を形成する。そして次にこれを還元
雰囲気中、高温で焼成し、リード金属層１２及び焼成セ
ラミック体を形成する。Next, a metal paste is printed and coated on the upper surface of the laminated unfired ceramic body 29 and the inner wall of the through hole 22.27 so as to be electrically connected to the wiring pattern 2.
A lead metal layer 30 is formed so as to lead out to the upper surface of the laminated green ceramic body 29. Then, this is fired at a high temperature in a reducing atmosphere to form the lead metal layer 12 and the fired ceramic body.
そして最後に前記焼成セラミック体を貫通孔２２．２７
の配列による区分線に沿って切断分離し、これよって多
数個の半導体素子収納用パッケージの絶縁基体１１が一
度に製作される。Finally, the fired ceramic body is inserted into the through hole 22.27.
The insulating substrates 11 of a large number of semiconductor element storage packages are manufactured at one time by cutting and separating along the dividing line according to the arrangement.
（発明が解決しようとする問題点）
しかし乍ら、この従来の半導体素子収納用パッケージの
製造法によれば、積層未焼成セラミック体２９の上面及
び貫通孔２２．２７内壁に金属ペーストを印刷塗布し、
リード用金属層３０を形成した場合、金属ペーストの一
部が該金属ペースト自身の有する流動性により未焼成セ
ラミック体２９の底面に流れて付着してしまい、その結
果、個々の絶縁基体１１に切断分離し、各絶縁基体１１
の底面に放熱体１６を取着した場合、絶縁基体１１の底
面に付着したリード金属［１２が放熱体１６に接触し、
各リード金属層１２間が短絡して半導体装置としての機
能に支障を来すという欠点を有していた。(Problems to be Solved by the Invention) However, according to this conventional manufacturing method of a package for storing semiconductor elements, a metal paste is printed and coated on the upper surface of the laminated unfired ceramic body 29 and the inner wall of the through holes 22 and 27. death,
When the lead metal layer 30 is formed, a part of the metal paste flows and adheres to the bottom surface of the unfired ceramic body 29 due to the fluidity of the metal paste itself, and as a result, the metal paste is cut into individual insulating substrates 11. Separate each insulating substrate 11
When the heat sink 16 is attached to the bottom surface of the insulating base 11, the lead metal [12 attached to the bottom surface of the insulating base 11 comes into contact with the heat sink 16,
This has the drawback that the lead metal layers 12 are short-circuited, which impedes the function of the semiconductor device.
（発明の目的）
本発明は上記欠点に鑑み案出されたものでその目的は積
層未焼成セラミック体の上面及び貫通孔内壁に金属ペー
ストを印刷塗布し、リード用金属層を形成したとしても
、金属ペーストの一部が積層未焼成セラミック体の底面
に流れて付着するのを皆無となし、半導体素子の各電極
と電気的に接続するリード金属層が絶縁基体の底面に取
着される放熱体によって短絡するのを有効に防止するこ
とができる半導体素子収納用パッケージの製造法を提供
することにある。(Object of the Invention) The present invention was devised in view of the above-mentioned drawbacks, and its purpose is to print and apply a metal paste on the upper surface of a laminated unfired ceramic body and the inner wall of a through hole to form a lead metal layer. A heat sink in which a part of the metal paste does not flow and adhere to the bottom surface of a laminated green ceramic body, and a lead metal layer electrically connected to each electrode of a semiconductor element is attached to the bottom surface of an insulating base. It is an object of the present invention to provide a method for manufacturing a package for housing a semiconductor element, which can effectively prevent short circuits caused by short circuits.
Ｃ問題点を解決するための手段〕
本発明は多数の貫通孔の配列により複数の区画に区分さ
れた第１の未焼成セラミックシート上に、該第１の未焼
成セラミックシートの貫通孔と孔径を異にし、かつ配列
を実質的に同一とした貫通孔を有する第２の未焼成セラ
ミックシートを積層し、積層未焼成セラミック体を得る
工程と、前記積層未焼成セラミック体のうち第２の未焼
成セラミックシートの少なくとも貫通孔内壁に金属ペー
ストを塗布する工程と、
前記金属ペーストが塗布された積層未焼成セラミック体
を焼成し、金属層を有する焼成セラミック体を得るとと
もに該焼成セラミック体を貫通孔の配列による区分線に
沿って切断し、各半導体素子収納用パフケージに分離す
る工程と
より成ることを特徴とするものである。Means for Solving Problem C] The present invention provides a first unfired ceramic sheet divided into a plurality of sections by an arrangement of a large number of through holes, and a through hole and a hole diameter of the first unfired ceramic sheet. a step of laminating second unfired ceramic sheets having through-holes having different diameters and substantially the same arrangement to obtain a laminated green ceramic body; a step of applying a metal paste to at least the inner wall of the through hole of the fired ceramic sheet; firing the laminated unfired ceramic body coated with the metal paste to obtain a fired ceramic body having a metal layer; This method is characterized by the step of cutting along the dividing lines according to the arrangement of the semiconductor devices and separating them into puff cages for storing semiconductor devices.
次に本発明の半導体素子収納用パッケージの製造法を第
１図（ａ）、（ｂ）及び第２図に示す実施例に基づき詳
細に説明する。Next, a method for manufacturing a package for housing a semiconductor element according to the present invention will be explained in detail based on the embodiment shown in FIGS. 1(a) and 2(b) and FIG.
第１図（ａ）は本発明の半導体素子収納用パッケージの
製造法を説明するための部分分解斜視図、第１図（ｂ）
は第１図（ａ）の積層した状態の部分断面図である。FIG. 1(a) is a partially exploded perspective view for explaining the manufacturing method of the semiconductor element storage package of the present invention, and FIG. 1(b) is a partially exploded perspective view.
is a partial sectional view of the stacked state shown in FIG. 1(a).
図において全体として１で示される積層未焼成セラミッ
ク体は広面積の第１の未焼成セラミックシート２と３枚
のシート３ａ、３ｂ、３ｃから成る第２の未焼成セラミ
ックシート３から構成されている。The laminated green ceramic body, designated as a whole by 1 in the figure, is composed of a first green ceramic sheet 2 having a large area and a second green ceramic sheet 3 consisting of three sheets 3a, 3b, 3c. .
前記第１及び第２の未焼成セラミックシート２．３はア
ルミナ（Ａｌ□０．）、シリカ（ＳｉＯ□）等のセラミ
ック原料粉体に適当な溶剤、溶媒を添加混合して泥漿物
を作り、これを従来周知のドクターブレード法等により
シート状と成すことによって形成される。The first and second unfired ceramic sheets 2.3 are made by adding and mixing a suitable solvent to ceramic raw material powder such as alumina (Al□0.) and silica (SiO□) to form a slurry. This is formed into a sheet shape by a conventionally well-known doctor blade method or the like.
前記第１の未焼成セラミックシート２はその上面に半導
体素子を載置取着するためのダイアタッチ用金属層４が
複数個、印刷塗布されており、該ダイアタッチ用金属層
４はタングステン（Ｗ）、モリブデン（Ｍｏ）等の高融
点金属粉末に適当な溶剤、溶媒を添加混合し、ペースト
状となした金属ペーストを従来周知のスクリーン印刷法
を採用することによって第１の未焼成セラミックシート
２の上面に印刷塗布される。The first unfired ceramic sheet 2 has a plurality of die attach metal layers 4 printed and coated on its upper surface for mounting and attaching semiconductor elements, and the die attach metal layers 4 are made of tungsten (W). ), a high melting point metal powder such as molybdenum (Mo), and a suitable solvent are added and mixed to form a paste, and a metal paste is made into a paste by employing a conventionally well-known screen printing method to form the first unfired ceramic sheet 2. Printing is applied to the top surface of the
また前記第１の未焼成セラミックシート２には、該セラ
ミックシート２を複数の区画に区分する如く多数の貫通
孔５が配列形成されており、貫通孔５は従来周知の打抜
き加工法によって形成される。Further, a large number of through holes 5 are arranged in the first unfired ceramic sheet 2 so as to divide the ceramic sheet 2 into a plurality of sections, and the through holes 5 are formed by a conventionally well-known punching method. Ru.
前記３枚のシー）３ａ、３ｂ、３ｃから成る第２の未焼
成セラミックシート３には、該第２の未焼成セラミック
シート３を複数の区画に区分す如く多数の貫通孔６が配
列形成されており、貫通孔６は第２の未焼成セラミック
シー） ３ （３ａ、３ｂ、３ｃ）を所望する絶縁基
体の形状に対応した形状の複数の区画に区分するととも
に後述するリード用金属層を引き廻す際の通路として作
用する。この第２の未焼成セラミックシート３に設けた
貫通孔６は第１の未焼成セラミックシート２に設けた貫
通孔５に比し、その孔径を大に、また配列を実質的に同
一としてなしてあり、従来周知の打抜き加工法によって
第２の未焼成セラミックシート３に形成される。A large number of through holes 6 are arranged and formed in the second unfired ceramic sheet 3 consisting of the three sheets 3a, 3b, and 3c so as to divide the second unfired ceramic sheet 3 into a plurality of sections. The through hole 6 is used to divide the second unfired ceramic sheet (3a, 3b, 3c) into a plurality of sections each having a shape corresponding to the desired shape of the insulating substrate, and to draw a lead metal layer to be described later. Acts as a passage when turning. The through holes 6 provided in the second unfired ceramic sheet 3 have a larger diameter and substantially the same arrangement as the through holes 5 provided in the first unfired ceramic sheet 2. and is formed into the second green ceramic sheet 3 by a conventionally known punching process.
尚、前記第２の未焼成セラミックシート３に設ける貫通
孔６は第１の未焼成セラミックシートに受けた貫通孔５
に比し、その孔径を小としておいてもよい。Note that the through hole 6 provided in the second unfired ceramic sheet 3 is similar to the through hole 5 provided in the first unfired ceramic sheet.
The pore size may be smaller than that of the pore size.
また前記第２の未焼成セラミックシート３のうちシー）
３ａにはその上面に一端が貫通孔６に達するよう多数の
配線パターン７が印刷塗布されており、該配線パターン
７は前述のダイアタッチ用金属層４と同様に金属ペース
トをスクリーン印刷により塗布することによって形成さ
れる。この配線パターン７は内部に収納する半導体素子
の各電極を外部回路に接続する際の導電路として作用す
る。Also, among the second unfired ceramic sheets 3)
A large number of wiring patterns 7 are printed and coated on the upper surface of 3a so that one end reaches the through hole 6, and the wiring patterns 7 are coated with a metal paste by screen printing in the same manner as the metal layer 4 for die attach described above. formed by This wiring pattern 7 acts as a conductive path when connecting each electrode of a semiconductor element housed inside to an external circuit.
前記第１及び第２の未焼成セラミックシート２゜３は次
に第１図（ｂ）に示すように各貫通孔５，６の中心を合
わせて順次積層され、約１５０℃に加熱したホットプレ
ス機によって熱圧着されて積層未焼成セラミック体１が
作成される。The first and second unfired ceramic sheets 2゜3 are then stacked one on top of the other with the centers of the through holes 5 and 6 aligned as shown in FIG. A laminated green ceramic body 1 is created by thermocompression bonding using a machine.
次に、前記積層未焼成セラミック体１は第２の未焼成セ
ラミックシート３の貫通孔６内壁及び上面に金属ペース
トの印刷傅布によるリード用金属層８が形成され、前記
第２の未焼成セラミックシート３内に形成した配線パタ
ーン７を貫通孔６の内壁を引き廻して積層未焼成セラミ
ック体１の上面へ導出させる。この場合、積層未焼成セ
ラミック体ｌは第１の未焼成セラミックシート２に設け
た貫通孔５と第２の未焼成セラミックシート３に設けた
貫通孔６との孔径がそれぞれ異なっていることから貫通
孔の途中に第２図に示すような段部Ｂを有することとな
り、そのため第２の未焼成セラミックシート３の貫通孔
６内壁に金属ペーストを印刷塗布し、リード用金属層８
を形成した場合、金属ペーストの流れは前記段部Ｂで遮
断されることとなり積層未焼成セラミック体１の底面に
まで流れて付着することは一切ない。Next, the laminated unfired ceramic body 1 has a lead metal layer 8 formed by printing a metal paste on the inner wall and upper surface of the through hole 6 of the second unfired ceramic sheet 3, and the second unfired ceramic The wiring pattern 7 formed in the sheet 3 is routed around the inner wall of the through hole 6 and led out to the upper surface of the laminated green ceramic body 1. In this case, the laminated unfired ceramic body 1 is penetrated because the through holes 5 provided in the first unfired ceramic sheet 2 and the through holes 6 provided in the second unfired ceramic sheet 3 have different hole diameters. The hole has a stepped portion B in the middle as shown in FIG.
In the case where the metal paste is formed, the flow of the metal paste is blocked by the stepped portion B, and the metal paste never flows to the bottom surface of the laminated green ceramic body 1 and does not adhere thereto.
そして次に、前記未焼成セラミック体１は還元雰囲気中
（Ｈｚ−Ｎｚガス中）、約１４００〜１６００℃の温度
で焼成され、積層未焼成セラミック体１とダイアタッチ
用金属層４及びリード用金属Ｎ８とを焼結一体化させ、
焼成セラミック体、ダイアタッチ金属層及びリード金属
層が形成される。Then, the green ceramic body 1 is fired in a reducing atmosphere (in Hz-Nz gas) at a temperature of about 1400 to 1600°C, and the laminated green ceramic body 1, the metal layer 4 for die attachment, and the metal for leads are fired. By sintering and integrating N8,
A fired ceramic body, die attach metal layer and lead metal layer are formed.
最後に、前記焼成セラミック体は貫通孔の配列による区
分線Ｃに沿って切断分離され、これによって個々の絶縁
基体が製作される。Finally, the fired ceramic body is cut and separated along the dividing line C according to the arrangement of through holes, thereby producing individual insulating substrates.
かくして本発明の半導体素子収納用パフケージの製造法
によれば、多数の貫通孔の配列により複数の区画に区分
された第１の未焼成セラミックシート上に、該第１の未
焼成セラミックシートの貫通孔と孔径を異にし、かつ配
列を実施的に同一とした貫通孔を有する第２の未焼成セ
ラミックシートを積層し、積層未焼成セラミック体を得
たことから該積層未焼成セラミック体はその貫通孔の途
中に段部を有することとなり、第２の未焼成セラミック
シートの貫通孔内壁に金属ペーストを印刷塗布し、リー
ド用金属層を形成したとしても金属ペーストの流れは前
記段部で遮断され積層未焼成セラミック体の底面に付着
することは一切ない。Thus, according to the method of manufacturing a puff cage for storing semiconductor devices of the present invention, the first green ceramic sheet is divided into a plurality of sections by the arrangement of a large number of through holes, and the first green ceramic sheet is A laminated green ceramic body was obtained by laminating a second unfired ceramic sheet having through-holes with different hole diameters and substantially the same arrangement. Since the hole has a step in the middle, even if a metal paste is printed and coated on the inner wall of the through hole of the second unfired ceramic sheet to form a lead metal layer, the flow of the metal paste is blocked by the step. There is no adhesion to the bottom surface of the laminated green ceramic body.
したがって個々の絶縁基体に切断分離し、各絶縁基体の
底面に放熱体を取着しても該放熱体にリード金属層が接
触することは皆無であり、半導体装置としての機能に支
障を来すようなリード金属層間の短絡を有効に防止する
ことができる。Therefore, even if the insulating substrate is cut and separated into individual insulating substrates and a heat sink is attached to the bottom surface of each insulating substrate, the lead metal layer will never come into contact with the heat sink, which will impede the function of the semiconductor device. Such short circuits between lead metal layers can be effectively prevented.
第１図（ａ）は本発明の半導体素子収納用パフケージの
製造法を説明するための部分分解斜視図、第１図（ｂ）
は第１図（ａ）の積層した状態の部分断面図、第２図は
第１図（ｂ）の貫通孔の部分を説明するための部分斜視
図、第３図は従来の半導体素子収納用パッケージの断面
図、第４図は第３図のパッケージの製造法を説明するた
めの部分断面図である。
１：積層未焼成セラミック体
２：第１の未焼成セラミックシート
３：第２の未焼成セラミックシート
５：第１の未焼成セラミックシートに設けた貫通孔６；
第２の未焼成セラミックシートに設けた貫通孔７：配線
パターン
８：リード用金属層
Ｂ：段部
出願人 （６６３）京セラ株式会社
第１図（Ｑ’）
第１図（シ）FIG. 1(a) is a partially exploded perspective view for explaining the manufacturing method of the puff cage for storing semiconductor elements of the present invention, and FIG. 1(b) is a partially exploded perspective view.
is a partial cross-sectional view of the stacked state shown in FIG. 1(a), FIG. 2 is a partial perspective view for explaining the through-hole portion of FIG. 1(b), and FIG. 3 is a conventional semiconductor device storage device. FIG. 4 is a partial cross-sectional view for explaining a method of manufacturing the package shown in FIG. 3. 1: Laminated green ceramic body 2: First green ceramic sheet 3: Second green ceramic sheet 5: Through hole 6 provided in the first green ceramic sheet;
Through hole 7 provided in second unfired ceramic sheet: Wiring pattern 8: Lead metal layer B: Step applicant (663) Kyocera Corporation Figure 1 (Q') Figure 1 (C)
Claims (1)
１の未焼成セラミックシート上に、該第１の未焼成セラ
ミックシートの貫通孔と孔径を異にし、かつ配列を実質
的に同一とした貫通孔を有する第２の未焼成セラミック
シートを積層し、積層未焼成セラミック体を得る工程と
、 前記積層未焼成セラミック体のうち第２の未焼成セラミ
ックシートの少なくとも貫通孔内壁に金属ペーストを塗
布する工程と、 前記金属ペーストが塗布された積層未焼成セラミック体
を焼成し、金属層を有する焼成セラミック体を得るとと
もに該焼成セラミック体を貫通孔の配列による区分線に
沿って切断し、各半導体素子収納用パッケージに分離す
る工程と より成ることを特徴とする半導体素子収納用パッケージ
の製造法。[Claims] On a first unfired ceramic sheet divided into a plurality of sections by an arrangement of a large number of through holes, the first unfired ceramic sheet has through holes having different diameters and arrangement. laminating second unfired ceramic sheets having substantially identical through holes to obtain a laminated green ceramic body; at least the through holes of the second green ceramic sheets of the laminated green ceramic body; a step of applying a metal paste to the inner wall; and firing the laminated unfired ceramic body coated with the metal paste to obtain a fired ceramic body having a metal layer; 1. A method for manufacturing a package for housing a semiconductor element, the method comprising the steps of: separating the package into individual packages for housing the semiconductor element;
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16139186A JPS6316644A (en) | 1986-07-08 | 1986-07-08 | Manufacture of package for housing semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16139186A JPS6316644A (en) | 1986-07-08 | 1986-07-08 | Manufacture of package for housing semiconductor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6316644A true JPS6316644A (en) | 1988-01-23 |
Family
ID=15734200
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16139186A Pending JPS6316644A (en) | 1986-07-08 | 1986-07-08 | Manufacture of package for housing semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6316644A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5319521A (en) * | 1992-08-17 | 1994-06-07 | Rockwell International Corporation | Ceramic frames and capsules for Z-axis modules |
| JP2001024079A (en) * | 1999-07-05 | 2001-01-26 | Seiko Epson Corp | Electronic component sealing structure |
| JP2006185971A (en) * | 2004-12-24 | 2006-07-13 | Kyocera Corp | Substrate for mounting electronic components |
-
1986
- 1986-07-08 JP JP16139186A patent/JPS6316644A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5319521A (en) * | 1992-08-17 | 1994-06-07 | Rockwell International Corporation | Ceramic frames and capsules for Z-axis modules |
| JP2001024079A (en) * | 1999-07-05 | 2001-01-26 | Seiko Epson Corp | Electronic component sealing structure |
| JP2006185971A (en) * | 2004-12-24 | 2006-07-13 | Kyocera Corp | Substrate for mounting electronic components |
| JP4514597B2 (en) * | 2004-12-24 | 2010-07-28 | 京セラ株式会社 | Electronic component mounting board |
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