JP3502302B2 - Frequency synthesizer - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency synthesizer for generating an arbitrary frequency from a reference frequency.

[0002]

2. Description of the Related Art FIG. 11 shows a conventional phase interpolation type direct digital synthesizer (DDS) (reference: H. Nosaka,
T. Nakagawa, and A. Yamagishi, "A phase interpola
tion direct digital synthesizer with a digitally c
ontrolled delay generator, "in l997 Symp. VLSI Circ
uits Dig., June 1997, pp.75-76). In the figure, 50 is an n-bit accumulator, 51 is a data conversion circuit, 52 is a delay generator, 53 is an output circuit, 5
4 is a clock signal input terminal for inputting a clock signal having a clock cycle T, 55 is a setting data K input terminal for inputting setting data K (K is an arbitrary natural number of 2 ^n-1 -1 or less),
56 is an output terminal. Then, the accumulator 50 cumulatively adds the setting data K for each input of the clock signal, and when the cumulative addition result reaches 2 ⁿ , the excess is set as an initial value and the cumulative addition of the setting data K is repeated again, and the cumulative addition is performed. The result, that is, the output signal θ is output. Therefore, if the clock frequency of the clock signal is f _CLK ,
The accumulator 50 outputs K pulses as overflow signals within a time of 2 ⁿ T. Therefore, the output frequency f _OUT of the overflow signal of the accumulator 50 is expressed by the following equation.

[0003]

## EQU1 ## f _OUT = (K / 2 ⁿ ) f _CLK Here, when the setting data K is 2 ^m (m is a natural number), the pulses included in the overflow signal are arranged at equal intervals, but otherwise , The pulses are not evenly spaced,
Will have jitter. If the output signal of the accumulator 50 at that time is θ, the time shift of each pulse of the overflow signal from the ideal pulse train arranged at equal intervals, that is, the jitter amount t ₄ (unit: time) is given by the following equation. expressed.

[0004]

Since Equation 2] ^{_{t 4 = {(2 n -θ}} ) / K} T accumulator 50 the operation of 2 ⁿ T period, jitter t ₄ varies periodically. When there is periodic jitter, a high-level unwanted wave (spurious) component is included in addition to the output frequency f _OUT expressed by the equation (1), and thus it cannot be applied to the local oscillator of the radio device as it is. Therefore, the delay generator 52 is inserted in order to accurately cancel this periodic jitter, and the data conversion circuit 51 is inserted for the calculation of the numerator 2 ⁿ -θ in the formula (2). . As the output circuit 53, a one-shot multivibrator or T-FF (toggle flip-flop) can be used. When a one-shot multivibrator is used as the output circuit 53, it is possible to obtain a low spurious output signal having a frequency represented by the equation (1) with respect to the setting data K. Also,
When a T-FF is used as the output circuit 53, a rectangular wave having a frequency of 1/2 of the equation (1) and a duty ratio of 50% can be obtained.

In the above description, the accumulator 50
Although the method for delaying the overflow signal of (1) has been described, as described in the above-mentioned reference, by delaying the most significant bit (MSB) of the output signal θ of the accumulator 1, a frequency synthesizer with a low spurious output can be obtained. Can be configured. In this case, the jitter amount t
₅ is expressed by the following equation using the output signal θ _p of the accumulator 50 immediately before the output signal θ of the most significant bit rises.

[0006]

## EQU3 ## t ₅ = {(2 ^n-1 -θ _p ) / K} T The delay represented by the equation (3) is given by the delay generator 52 to the output signal θ (MSB signal) of the most significant bit. By doing so, a frequency synthesizer with a low spurious output can be constructed.

[0007]

[Problems to be Solved by the Invention] As described above,
The conventional phase interpolation type direct digital synthesizer can obtain the output signal of the output frequency f _OUT represented by the equation (1). K / 2 ^n, which is the fractional part of equation (1)
In K, the numerator K can be set to an arbitrary natural number of 2 ⁿ −1 −1 or less, whereas the denominator is fixed to 2 ⁿ by hardware, and there is a drawback in lacking flexibility in setting the output frequency. Also, the fact that the denominator can select only a multiple of 2 instead of a multiple of 10 has a drawback that the relationship between the output frequency f _OUT and the clock cycle T cannot be freely selected. For example, 1MHz,
To obtain 3 kinds of output frequencies of 2MHz and 3MHz, select n = 8, f _CLK = 256MHz, K = 1,
If set to 2 and 3, the respective output frequencies f _OUT can be obtained. Conversely speaking, this is the output frequency f with good cutting.
_The clock frequency f _CLK required to output _OUT is 1
It means that the frequency becomes an odd number in the 0-base system.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a frequency synthesizer in which the relationship between the clock frequency and the output frequency can be freely selected.

[0009]

[0010]

[Means for Solving the Problems]
Therefore, in the present invention, the setting data K which is a natural number, and the setting data M which is a natural number and is larger than the setting data K.
And a clock signal having a clock cycle T, and the setting data K is cumulatively added for each input of the clock signal.
When the cumulative addition result reaches the setting data M, an overflow signal is output, and the value obtained by subtracting the setting data M from the cumulative addition result is used as an initial value to perform cumulative addition again, and the cumulative addition result, that is, the output signal. An expansion accumulator that outputs θ, a data conversion circuit that inputs the setting data M and the output signal θ, calculates and outputs a control signal M−θ, and the control signal M−θ that is input Is a constant time of τ, the delay generator delays the pulse of the overflow signal by the delay time {(M−θ) / K} T + τ, and the output pulse of the delay generator is input to make the pulse width constant. And an output circuit for outputting.

Further, setting data K which is a natural number, setting data M which is a natural number and is larger than the setting data K, and a clock signal having a clock cycle T are input, and the setting data K is cumulatively added every time the clock signal is input. Then, cumulative addition is performed again with the value obtained by subtracting the setting data M from the cumulative addition result as the initial value, and the cumulative addition result, that is, the output signal θ, and the output signal of the most significant bit of the expansion accumulator are output. A data conversion circuit for inputting the output signal θ _p just before the rise of θ and the setting data M, calculating and outputting the control signal (M / 2) −θ _p , and the output signal θ and the setting data M type, a comparator for outputting a pulse at θ ≧ M / 2 condition, enter the control signal (M / 2) -θ _p, an arbitrary constant time is τ The comparator output pulses and [{(M / 2) -θ p} / K] T + τ delayed generator for delaying an output of and outputting constant pulse width receives the output pulses of the delay generator when And a circuit.

[0012]

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIG. 1 is a diagram showing a frequency synthesizer according to the present invention. In the figure, 1 is an extended accumulator, 2 is a data conversion circuit, and 3 is a data conversion circuit.
Is a delay generator, 4 is an output circuit, 5 is a clock signal input terminal for inputting a clock signal having a clock cycle T, 6 is a setting data K input terminal for inputting setting data K which is a natural number, and 7 is a natural number and is set A setting data M input terminal for inputting setting data M larger than the data K, and 8 is an output terminal.

FIG. 2 is a time chart showing the operation of the frequency synthesizer shown in FIG. 1 when K = 3 and M = 10. 2A shows the output signal θ of the extended accumulator 1, FIG. 2B shows the overflow signal OF of the extended accumulator 1, and FIG. 2C shows the output signal of the output circuit 4 (output terminal 8). The extended accumulator 1 cumulatively adds the setting data K for each input of the clock signal, outputs an overflow signal OF when the cumulative addition result reaches the setting data M, and subtracts the setting data M from the cumulative addition result. Is again used as an initial value, and cumulative addition is performed again, and the cumulative addition result, that is, the output signal θ is output (the detailed operation principle of the extended accumulator 1 will be described later). Therefore, the operation cycle of the extended accumulator 1 can be MT. In the case of FIG. 2, since M = 10, the operation cycle of the extended accumulator 1 is 10 clock cycles (10T). Further, the overflow signal OF of the expanded accumulator 1 includes K pulses within the time MT. In the case of FIG.
Since K = 3, the overflow signal OF has time M
Three pulses are included in T. Therefore, the output frequency (fundamental frequency) f _{OUT of} the overflow signal OF
Is expressed by the following equation.

[0015]

[Mathematical formula-see original document] f _OUT = (K / M) f _{CLK When the} setting data M is divisible by the setting data K, the pulses of the overflow signal OF line up at equal intervals. It will have jitter instead of lining up at equal intervals. The time shift of each pulse of the overflow signal OF from the ideal pulse train arranged at equal intervals shown in FIG. 2C, that is, the jitter amount t ₁ (unit: time)
Is expressed by the following equation using the output signal θ of the extended accumulator 1 at that time.

[0016]

T ₁ = {(M−θ) / K} T Since periodic jitter becomes a spurious component, the delay generator 3 delays each pulse so as to cancel the jitter. That is, the data conversion circuit 2 inputs the setting data M and the output signal θ, calculates and outputs the control signal M−θ,
The delay generator 3 receives the control signal M-θ and delays the pulse of the overflow signal OF by a delay time {(M-θ) / K} T. For example, as shown in FIG.
Is the first pulse of the overflow signal OF {(10-
9) / 3} T = (1/3) T, and the second pulse is delayed by {(10-8) / 3} T = (2/3) T. As a result, it coincides with the ideal pulse train lined up at equal intervals shown in FIG. This ideal pulse train arranged at equal intervals is the output signal of the frequency synthesizer shown in FIG. The delay time generated by the delay generator 3 is (Equation 5)
Add an arbitrary constant time τ to the equation.

A one-shot multivibrator or a T-FF can be used as the output circuit 4 which inputs the output pulse of the delay generator 3 and outputs it with a constant pulse width. When a one-shot multivibrator is used as the output circuit 4, it is possible to obtain a low spurious output signal having a frequency represented by the formula (4). When a T-FF is used as the output circuit 4, it is possible to obtain a rectangular wave whose frequency is 1/2 of the expression (4) and whose duty ratio is 50%.

FIG. 3 is an expanded accumulator of the frequency synthesizer shown in FIG. 1 (reference: Japanese Patent Laid-Open No. 10-1161).
81). In the figure, 9 is a full adder, 10 is a comparator, 11 is a NAND gate, 12
Is a full adder, 13 is a latch, 14 is a clock signal input terminal, 15 is a setting data M input terminal, 16 is a setting data K
An input terminal, 17 is an output terminal for outputting an overflow signal OF of the extended accumulator 1, and 18 is an output terminal for outputting an output signal of the latch 13, that is, an output signal θ of the extended accumulator 1.

FIG. 4 is a diagram showing an operation example of the extended accumulator shown in FIG. 3 when M = 10 and K = 3. Figure 4
(A) is a clock signal input to the clock signal input terminal 14, (b) is an output signal of the full adder 9, (c) is an overflow signal OF, (d) is an output signal of the full adder 12, and (e) ) Is the output signal θ of the extended accumulator 1 (latch 13). The output signal θ increases by 0, 3, 6 and K = 3 each time the clock signal is input. When θ = 9, the comparator 10
The overflow signal OF becomes high, 9 + 3 = 12, not 9 + 3 = 12, is set at the input of the latch 13, and θ = 2 is output at the input of the next clock signal. After that, the output signal θ again starts cumulative addition and changes to 2, 5, and 8. In this way, the extended accumulator 1 operates for M clock cycles, and K
Output pulses.

FIG. 5 is a delay generator of the frequency synthesizer shown in FIG. 1 (reference: H. Nosaka, T. Nakagawa, and A.
Yamagishi, "A phase interpolation direct digital
synthesizer with a symmetrically structured delay
generator ", in 1998 Asia-Pacific Microwave Confere
nce Dig., Dec, 1998, pp.1343-1346). In the figure, 19 and 20 are current switch arrays and 2
Reference numerals 1 and 22 are switches, 23 and 24 are capacitors, 25 is a comparator, 26 and 27 are leak signal input terminals, 28 is a setting data input terminal, 29 is a control signal input terminal, and 30 is an output terminal. The current switch array 19, the switch 21, and the capacitor 23 constitute a ramp wave generating circuit, and the current switch array 19 provides the capacitor 23 with a current according to the setting data K input from the setting data input terminal 28, and the ramp wave. generating circuit generates a slope proportional to the setting data K ramp V _R, also switch 21 is provided in parallel with the capacitor 23, the switch 21 is turned on by a leakage signal input from the leak signal input terminal 26. The current switch array 20, the switch 22, and the capacitor 24 form a threshold voltage generating circuit, and the current switch array 20 provides the capacitor 24 with a current according to the control signal M−θ input to the control signal input terminal 29. The threshold voltage generating circuit generates a threshold voltage V _T proportional to the control signal M−θ, the switch 22 is provided in parallel with the capacitor 24, and the switch 22 is turned on by a leak signal input from the leak signal input terminal 27. .
The comparator 25 compares the ramp V _R and the threshold voltage V _T, the ramp V _R and the threshold voltage V _T outputs a pulse that rises at the matching timing to an output terminal 30.

FIG. 6 is a time chart showing the operation of the frequency synthesizer shown in FIG. 1 including the time change of the internal voltage of the delay generator shown in FIG. 6A shows the output signal θ of the extended accumulator 1, FIG. 6B shows the overflow signal OF of the extended accumulator 1, and FIG. 6C shows the internal voltage of the delay generator 3, that is, the ramp wave V _R (solid line) and the threshold voltage V.
_T (dotted line) and (d) are output signals of the output circuit 4 (output terminal 8). The threshold voltage V _{T that} is reached after the threshold voltage (ramp wave) V _T of one clock cycle period having a slope proportional to the control signal M-θ of the data conversion circuit 2 is generated is held. At the same time that the threshold voltage V _T is held, the ramp wave V _R having a slope proportional to the setting data K starts to be generated. The time from the start of generation of the ramp wave V _R to the time when the ramp wave V _R matches the threshold voltage V _T is represented by the equation (5). In the operation example shown in FIG. 6, for the time 2T until ramp V _R from the rise overflow signal OF is to start generating the actual delay time (number 5) of the delay generator 3 constant expression time 2T Has been added. Such addition of constant time has no meaning for the purpose of canceling periodic jitter.

As described above, in the frequency synthesizer shown in FIG. 1, the denominator of the fractional expression K / M in the equation (4) representing the output frequency f _OUT is set by the external setting data M.
Since it can be set with, there is an advantage that the relationship between the clock frequency f _CLK and the output frequency f _OUT can be freely selected. In the conventional phase interpolation type direct digital synthesizer, since the operation cycle is limited to 2 ⁿ , when it is desired to obtain the output frequency f _OUT which is well cut by the decimal system, the binary system is good but the decimal system is not. Halfway clock frequency f
I had to choose _CLK . On the other hand, in the frequency synthesizer shown in FIG. 1, since the operation cycle is not limited to 2 ⁿ , both the output frequency f _OUT and the clock frequency f _CLK can be selected so that they can be cut in decimal notation. For example, 1MH
If three output frequencies f _{OUT of} z, 2 MHz, and 3 MHz are required and a clock frequency f _CLK = 100 MHz can be prepared, set M = 100, and set K = 1, 2, and 3, respectively. f _OUT is obtained. Such flexibility of the set frequency not only has the advantage of being easy for humans to understand, but also brings the advantage that the same hardware and the same clock signal can be used for various applications, thus reducing the cost and designing the local oscillator. Effective for simplification. Therefore, it is possible to provide a frequency synthesizer applicable to a local oscillator of a wireless communication device, which has a high degree of freedom in setting an output frequency, has low power consumption, and has a short frequency switching time.

(Second Embodiment) FIG. 7 is a diagram showing another frequency synthesizer according to the present invention. In the figure,
31 is an expanded accumulator, 48 is a comparator, 32
Is a data conversion circuit, 33 is a delay generator, 34 is an output circuit, 35 is a clock signal input terminal for inputting a clock signal having a clock cycle T, and 36 is a setting data K which is a natural number.
Is a setting data K input terminal, 37 is a natural number and is a setting data M input terminal for inputting setting data M which is larger than the setting data K, and 38 is an output terminal.

FIG. 8 is a time chart showing the operation of the frequency synthesizer shown in FIG. 7 when K = 3 and M = 10. 8A shows the output signal θ of the extended accumulator 31, FIG. 8B shows the output signal of the comparator 48, and FIG. 8C shows the output signal of the output circuit 34 (output terminal 38). The expanded accumulator 31 cumulatively adds the setting data K for each input of the clock signal, outputs an overflow signal OF when the cumulative addition result reaches the setting data M, and subtracts the setting data M from the cumulative addition result. The initial value is used as the initial value to perform cumulative addition again, and the cumulative addition result, that is, the output signal θ is output. Therefore, the operation cycle can be MT. In the case of FIG. 8, since M = 10, the operation cycle of the extended accumulator 31 is 10 clock cycles (10T).
Has become. Further, the comparator 48 inputs the output signal θ and the setting data M, compares the output signal θ with M / 2, and outputs a pulse when θ ≧ M / 2. The output signal of the comparator 48 includes K pulses within the time MT. In the case of FIG. 8, since K = 3, the output signal of the comparator 48 includes three pulses within the time MT. Therefore, the output frequency (fundamental frequency) f _OUT of the output signal of the comparator 48 is expressed by the following equation.

[0025]

[Equation 6] f _OUT = (K / M) f _{CLK When the} setting data M is divisible by the setting data K, the pulses of the output signal of the comparator 48 are arranged at equal intervals.
In other cases, the pulses are not arranged at equal intervals and have jitter. The time shift of each pulse of the comparator 48 from the ideal pulse train arranged at equal intervals shown in FIG. 8C, that is, the jitter amount t ₂ (unit: time) is just before the rise of the output signal θ of the most significant bit. It is expressed by the following equation using the output signal θ _p of the extended accumulator 31.

[0026]

## EQU7 ## t ₂ = [{(M / 2) −θ _p } / K] T Since periodic jitter is a spurious component, the delay generator 33 delays each pulse so as to cancel the jitter. That is, the data conversion circuit 32 inputs the output signal θ _p and the setting data M immediately before the output signal θ of the most significant bit of the expansion accumulator 31 rises, and outputs the control signal.
(M / 2) −θ _p is calculated and output, and the delay generator 33 inputs the control signal (M / 2) −θ _p to output the output pulse of the comparator 48 to the delay time [{(M / 2) Delay by −θ _p } / K] T. For example, as shown in FIG.
Is the first output pulse of the comparator 48 {(5-3)
/ 3} T = (2/3) T, and the second output pulse is delayed by {(5-2) / 3} T = (3/3) T. As a result, it coincides with the ideal pulse train lined up at equal intervals shown in FIG. The ideal pulse train lined up at these equal intervals is shown in FIG.
This is the output signal of the frequency synthesizer shown in. In addition,
For the delay time generated by the delay generator 33, an arbitrary constant time τ is added to the equation (7).

A one-shot multivibrator or T-FF can be used as the output circuit 34 which inputs the output pulse of the delay generator 33 and outputs it with a constant pulse width. When a one-shot multivibrator is used as the output circuit 34, it is possible to obtain a low spurious output signal having a frequency represented by the equation (6). When a T-FF is used as the output circuit 34, it is possible to obtain a rectangular wave whose frequency is 1/2 of the expression (6) and whose duty ratio is 50%.

The signal M / 2 in the comparator 48 and the data conversion circuit 32 can be easily obtained by shifting the setting data M by 1 bit in the direction of lower digit and connecting.

As described above, also in the frequency synthesizer shown in FIG. 7, the denominator of the fractional expression K / M in the equation (6) representing the output frequency f _OUT can be set by the setting data M from the outside. Clock frequency f _CLK and output frequency f
There is an advantage that you can freely choose the relationship with _OUT .

Reference Example FIG. 9 is a diagram showing a frequency synthesizer of a reference example . In the figure, 39 is an extended accumulator, 40 is a D-FF.
(D-flip-flop), 41 is a data conversion circuit, 4
2 is a delay generator, 43 is an output circuit, 44 is a clock signal input terminal for inputting a clock signal of a clock cycle T, 4
5 is setting data K for inputting setting data K which is a natural number
An input terminal, 46 is a setting data M input terminal for inputting setting data M which is a natural number and is larger than the setting data K,
47 is an output terminal.

FIG. 10 is a time chart showing the operation of the frequency synthesizer shown in FIG. 9 when K = 3 and M = 10. 10A shows the output signal θ of the extended accumulator 39, FIG. 10B shows the output signal of the D-FF 40, and FIG. 10C shows the output signal of the output circuit 43 (output terminal 47). The extended accumulator 39 cumulatively adds the setting data K for each input of the clock signal, outputs an overflow signal OF when the cumulative addition result reaches the setting data M, and subtracts the setting data M from the cumulative addition result. The initial value is used as the initial value to perform cumulative addition again, and the cumulative addition result, that is, the output signal θ is output. Further, the D-FF 40 delays the pulse of the overflow signal OF by the clock cycle T. Therefore, the output frequency (fundamental frequency) f _OUT of the output of the D-FF 40 is expressed by the following equation.

[0032]

[Formula 8] f _OUT = (K / M) f _{CLK If the} setting data M is divisible by the setting data K, D
-The pulses of the output signal of the FF 40 are arranged at equal intervals, but in other cases, the pulses are not arranged at equal intervals and have jitter. The time shift of each pulse of the overflow signal OF from the ideal pulse train arranged at equal intervals shown in FIG. 10C, that is, the jitter amount t ₃ (unit: time)
Is expressed by the following equation using the output signal θ of the extended accumulator 39 at that time.

[0033]

T ₃ = {(K−θ) / K} T Since periodic jitter is a spurious component, the delay generator 42 delays each pulse so as to cancel the jitter. That is, the data conversion circuit 41 inputs the output signal θ and the setting data K, calculates and outputs the control signal K−θ, and the delay generator 42 inputs the control signal K−θ and outputs D
-The output pulse of the FF 40 is delayed by {(K-θ) / K} T. For example, as shown in FIG. 10, the delay generator 42 outputs the first output pulse of the D-FF 40 to {(3-2) / 3} T.
= (1/3) T and delay the second output pulse by {(3
-1) / 3} T = (2/3) T is delayed. As a result,
This coincides with the ideal pulse train lined up at equal intervals shown in FIG. The ideal pulse train arranged at equal intervals is the output signal of the frequency synthesizer shown in FIG. The delay time generated by the delay generator 42 may be obtained by adding an arbitrary constant time τ to the expression (9).

A one-shot multivibrator or T-FF can be used as the output circuit 43 for inputting the output pulse of the delay generator 42 and outputting it with a constant pulse width. When a one-shot multivibrator is used as the output circuit 43, it is possible to obtain a low spurious output signal having a frequency represented by the equation (8). When a T-FF is used as the output circuit 43, it is possible to obtain a rectangular wave whose frequency is 1/2 of the equation (8) and whose duty ratio is 50%.

As described above, also in the frequency synthesizer shown in FIG. 9, the denominator of the fractional expression K / M in the equation (8) representing the output frequency f _OUT can be set by the setting data M from the outside. Clock frequency f _CLK and output frequency f
There is an advantage that you can freely choose the relationship with _OUT .

[0036]

As described above, in the frequency synthesizer according to the present invention, since the denominator of the denominator of the expression representing the output frequency can be externally set by the setting data,
The relationship between the clock frequency and the output frequency can be freely selected.

[Brief description of drawings]

FIG. 1 is a diagram showing a frequency synthesizer according to the present invention.

FIG. 2 is a time chart showing the operation of the frequency synthesizer shown in FIG.

FIG. 3 is a diagram showing an extended accumulator of the frequency synthesizer shown in FIG.

FIG. 4 is a diagram showing an operation example of the extended accumulator shown in FIG.

5 is a diagram showing a delay generator of the frequency synthesizer shown in FIG. 1. FIG.

FIG. 6 is a time chart showing the operation of the frequency synthesizer shown in FIG.

FIG. 7 is a diagram showing another frequency synthesizer according to the present invention.

8 is a time chart showing the operation of the frequency synthesizer shown in FIG.

FIG. 9 is a diagram showing a frequency synthesizer of a reference example .

10 is a time chart showing the operation of the frequency synthesizer shown in FIG.

FIG. 11 is a diagram showing a conventional phase interpolation type direct digital synthesizer.

[Explanation of symbols]

1 ... Expanded accumulator 2 ... Data conversion circuit 3 ... Delay generator 4 ... Output circuit 31 ... Expanded accumulator 32 ... Data conversion circuit 33 ... Delay generator 34 ... Output circuit 39 ... Expanded accumulator 40 ... D-FF 41 ... Data conversion circuit 42 ... Delay generator 43 ... Output circuit 48 ... Comparator

Continuation of front page (56) Reference JP-A-1-174118 (JP, A) JP-A-55-136704 (JP, A) JP-A-2-292911 (JP, A) (58) Fields investigated (Int .Cl. ⁷ , DB name) H03B 28/00

Claims (2)

(57) [Claims] 1. Setting data K which is a natural number, setting data M which is a natural number and is larger than setting data K, and a clock signal having a clock cycle T are inputted and said setting data K is set.
Is cumulatively added for each input of the clock signal, an overflow signal is output when the cumulative addition result reaches the setting data M, and a value obtained by subtracting the setting data M from the cumulative addition result is used as an initial value again. An extended accumulator that performs cumulative addition and outputs the cumulative addition result, that is, an output signal θ; and a data conversion circuit that inputs the setting data M and the output signal θ and calculates and outputs a control signal M−θ, A delay generator for inputting the control signal M-θ and delaying the pulse of the overflow signal by a delay time {(M-θ) / K} T + τ when an arbitrary constant time is τ, and the delay generator. And an output circuit for inputting the output pulse of the above and outputting with a fixed pulse width. 2. The setting data K which is a natural number, the setting data M which is a natural number and is larger than the setting data K, and a clock signal having a clock cycle T are input, and the setting data K is set.
An accumulator for performing cumulative addition for each input of the clock signal, performing cumulative addition again with a value obtained by subtracting the setting data M from the cumulative addition result as an initial value, and outputting the cumulative addition result, that is, an output signal θ. A data conversion circuit that inputs the output signal θ _p just before the output signal θ of the most significant bit of the expansion accumulator rises and the setting data M, and calculates and outputs the control signal (M / 2) −θ _p . Input the output signal θ and the setting data M and output a pulse under the condition of θ ≧ M / 2, and the control signal (M / 2) −θ _p to input an arbitrary constant time. When τ, the output pulse of the comparator is delayed by [{(M / 2) −θ _p } / K] T + τ, and the output pulse of the delay generator is input to make the pulse width constant. Output Frequency synthesizer, characterized by comprising an output circuit.