JP3501048B2 - Chattering generator - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chattering generator for generating a simulated signal on which chattering is superimposed for use in testing electronic circuits.

[0002]

2. Description of the Related Art Conventionally, as a vehicle speed sensor mounted on a vehicle to detect a vehicle speed, one which generates a pulse signal having a cycle corresponding to the rotational speed of a wheel is known. In this case, generally, in an ECU that performs processing for obtaining the vehicle speed from the detection signal of the vehicle speed sensor, the pulse signal is sent to the CPU.
The vehicle speed is detected by measuring the interval of occurrence of the interrupt with a timer or the like and obtaining the generation period of the pulse signal.

As one of such vehicle speed sensors, there is known one constituted by using a reed switch. However, since the reed switch has mechanical contacts,
If the contact bounces during the intermittent operation of the contact, chattering will be superimposed on the detection signal of the vehicle speed sensor. The chattering superimposed on the detection signal causes an unnecessary interrupt to the CPU, resulting in a decrease in vehicle speed detection accuracy and, in some cases, a hang-up of the CPU due to multiple interrupts. There was a fear.

For this reason, when a sensor composed of an element having a mechanical contact such as a reed switch is used, C is removed in order to remove chattering superimposed on the detection signal.
Measures are taken such as providing an R filter circuit and performing mask processing so that the CPU does not accept an interrupt due to the same signal in a short period of time.

When manufacturing the ECU, etc.,
It is necessary to test whether the CR filter circuit and the mask processing can remove the influence of chattering as designed.

[0006]

However, at present, C
The problem is that it is only possible to inspect the characteristics of the R filter circuit itself or to inspect whether the mask processing normally operates, and it is not possible to actually input the detection signal on which chattering is superimposed to confirm the operation. was there.

That is, the chattering occurs depending on various factors such as the characteristics of the reed switch itself and the environment in which the reed switch is used, that is, the chattering occurrence timing (rising edge / falling edge) and the chattering pulse width. However, since the durations (the number of times of bounces) and the like are different and there is no apparatus for generating arbitrary chattering corresponding to these, the actual operation cannot be confirmed.

Therefore, an object of the present invention is to provide a chattering generator capable of arbitrarily generating a signal on which chattering is superimposed in order to solve the above problems.

[0009]

In the chattering generator of the present invention made to achieve the above object, the chattering signal generating means generates a chattering signal having a waveform specified by preset waveform information. The mask signal generation means generates a mask signal which is repeatedly generated and becomes an active level for a duration specified by preset period information from a start timing specified by preset timing information. To do. Then, while the mask signal generated by the mask signal generation means is at an active level, the signal synthesizing means synthesizes the chattering signal generated by the chattering signal generating means with the original signal on which chattering should be superimposed and outputs the synthesized signal. To do. In addition,
The waveform information that defines the waveform of the chattering signal is
Of the high level period and low level period of the chattering signal.
Information specifying the length is used. And Chatterin
In the signal generator, the timer counter is
Counting according to the clock, preset settings
Outputs a timing signal when counting for the value
Together with the count value setting means, this timer counter
As the setting value of, the count corresponding to the high level period
Value and the count value corresponding to the low level period alternately
Set. In other words, the chattering signal generation means is
The timing signal generated by the counter
Indicates the timing at which the signal level of the
The chattering signal is generated by the timing signal.

Therefore, according to the chattering generator of the present invention, the original signal (vehicle speed signal or the like) on which chattering is superimposed can be generated, and the setting of the waveform information, the timing information, and the period information is appropriately changed. As a result, various types of chattering can be realized. As a result, it can be suitably used for inspection of various electronic circuits in which chattering may be superimposed on the input signal.

As can be seen from the example of the reed switch described above, chattering normally occurs at the edge at which the signal level is inverted. Therefore, the timing information for determining the timing of superimposing chattering is defined in claim 2.
As described above, either the rising edge, the falling edge, or both edges of the original signal may be set.

In this case, the mask signal generation means includes, for example, a rising-side mask generation section that sets the mask signal to the active level for a duration from the rising edge of the original signal,
After the falling edge of the original signal, the operation to permit the operation of the falling-side mask generation unit that sets the mask signal to the active level and the operation of the rising-side generation unit and the falling-side generation unit according to the timing information setting for the duration. It can be configured with a permission unit.

When chattering is generated at the edge at which the signal level of the original signal is inverted in this way, the chattering signal generating means has a chattering signal generating means in which the signal level of the chattering signal is a rising edge of the original signal. It is desirable to reset the generation timing of the chattering signal at both edges of the original signal so that it becomes high level at the timing of and the low level at the timing of the falling edge of the original signal.

That is, for example, when the chattering signal is at a low level at the timing of the rising edge of the original signal, combining the two signals substantially delays the timing of the rising edge of the original signal. However, by resetting the timing as described above, the chattering signal can be superimposed while the timings of the rising edge and the falling edge of the original signal are faithfully maintained.

[0015]

Further, as the period information for specifying the chattering continuation period, for example, as described in claim 4 ,
The number of chattering bounces can be used. In this case, the mask signal generation means uses an edge counter that counts the number of times the signal level of the chattering signal is inverted, and outputs a timing signal when counting for a preset threshold value after the start timing, using a threshold value. According to the setting of the period information, the value setting means sets the number of inversions of the signal level of the chattering signal within the duration determined by the number of bounds as the threshold value of the edge counter, and as a result, the timing signal output by the edge counter. The timing may be configured to generate the mask signal as the end timing of the active level.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the overall configuration of an ECU inspection device to which the present invention is applied.

As shown in FIG. 1, the ECU inspection device 2 of this embodiment is connected to an inspection target ECU 8 and inputs and outputs various signals to and from the inspection target ECU 8.
And a control device 6 including a workstation for inputting various commands for controlling the signal processing device 4 and displaying a detection result of the signal processing device 4.

Of these, the signal processing device 4 is the inspection target E.
A signal generator 10 that generates various signals to be input to the CU 8.
And outputs various signals generated by the signal generator 10 to the ECU to be inspected, and based on these signals, for idle speed control (ISC), fuel injection control, ignition control, fuel pump control, etc. , E for inputting various signals generated by driving an actuator (load) in the inspection target ECU 8 from the inspection target ECU 8
A CU interface unit 12, a load unit 14 in which various actuators driven by input signals from the inspection target ECU 8 are mounted, and a signal measuring unit 1 for measuring the states of various signals input via the ECU interface unit 12.
6 and a command from the control device 6, the signal generator 10
And a control unit 18 that performs processing such as setting a signal to be generated in step S1 or determining the operation state of the inspection target ECU 8 based on the measurement result of the signal measurement unit 16 and transferring the determination result to the control device 6. Is equipped with.

Of these, the signal generator 10 generates a simulation signal for detection signals and setting signals of various sensors and switches mounted on the vehicle, and includes a knock sensor, a water temperature sensor, an intake air temperature sensor, and a throttle. A pulse signal that generates a pulse signal that simulates the detection signal of a pulse-based sensor such as a vehicle speed sensor, which generates an analog signal that simulates the detection signal output by an opening sensor, a crank angle sensor, an air flow meter, or the like. The generating circuit 10b includes a digital signal generating circuit 10c that generates a digital signal simulating a setting signal from switches such as an ignition (IGSW) switch and an air conditioner switch.

On the other hand, the load section 14 is equipped with the same actuators that are actually mounted in the vehicle, such as an injector for injecting gasoline, a rotary solenoid used for idle control, a fuel pump relay, and the like. Further, the signal measuring unit 16 measures the states of the injection pulse width, the ignition timing, the rotary solenoid drive duty ratio, the fuel pump relay, etc., for example.

The ECU interface section 12 is for matching the electrical interface between the signal processing device 4 side and the inspection target ECU 8 side, and specifically,
For example, the power source voltage VDD (for example, 5
V) level and battery voltage on the ECU side to be inspected + B
It is configured to perform mutual conversion and the like with (for example, 12 V) level.

Here, the pulse signal generating circuit 10b which is the main part of the present invention will be described in detail. The pulse signal generation circuit 10b includes N signal generation blocks B1 to BN and is configured to generate N types of pulse signals at the same time. Then, each signal generation block Bi (i =
1, 2, ..., N) is a normal mode (see FIG. 2A) that outputs a pulse signal (also referred to as “original signal”) on which chattering is not superimposed, and chattering is superimposed only on the falling edge of the original signal. Falling edge mode (see FIG. 2B) that outputs a pulsed pulse signal, rising edge mode (see FIG. 2C) that outputs a pulse signal in which chattering is superimposed only on the rising edge of the original signal, the original signal Both-edge mode in which chattering is superimposed on both edges of
(See (d)), there are four kinds of operation modes, and the operation is performed in any operation mode selected appropriately.

The signal generation blocks B1 to BN are
Since all have the same configuration, only one signal generation block Bi will be described here. However, FIG. 3 is a block diagram showing the detailed configuration of the signal generation block Bi, and FIG. 4 is a timing diagram showing the operation of each part thereof.

As shown in FIG. 3, the signal generation block Bi
Is an original signal generator 20 for generating an original signal Sg on which chattering is superimposed, and a chattering signal generator 22 for generating a chattering signal Sc synchronized with the original signal Sg.
And a mask signal S representing a period in which chattering should be superimposed.
and a mask signal Sm for generating a mask signal Sm.
Designating part 2 for designating the generation timing of
6 and the mask signal Sm, a pulse signal So is generated by combining the original signal Sg and the chattering signal Sc,
Signal synthesizer 28 supplied to ECU interface 12
Consists of.

The original signal generator 20 is connected to the controller 18
The register 30a to which the count value C1 is written and the register 30b to which the count value C2 is also written by the operation of, and count operation according to the reference clock CLK (cycle Tck) are carried out when the count value C1 fetched from the register 30a is finished. The counter 31a outputs the signal Y1 and the counter 31b outputs the carry signal Y2 when the count value C2 fetched from the register 30b is finished.

Each of the counters 31a and 31b is connected to use the carry signal Y1 of the counter 31a as a load signal for fetching the count values C1 and C2, and the cycle (T
The same counting process is repeatedly executed for each ck · C1).

Further, the original signal generator 20 includes a counter 31.
Carry signal from a (hereinafter "rise timing signal")
(Also called) Y1 set input, carry signal from counter 31b (hereinafter also referred to as "falling timing signal")
SR flip-flop circuit 3 having Y2 as a reset input
2 to generate an original signal Sg (cycle Tck · C1, duty ratio C2 / C1) that rises at the timing of the rising timing signal Y1 and falls at the timing of the falling timing signal Y2.

That is, as shown in FIG. 4, the counter 31
The timing signal Y1 generated by a represents the delimiter timing for each cycle of the original signal Sg, and the timing signal Y2 generated by the counter 31b represents the inversion timing of the signal level within one cycle of the original signal Sg. It represents.

Next, as shown in FIG. 3, the chattering signal generation unit 22 operates the control unit 18 to count the count value C.
3 and the register 33b in which the count value C4 is similarly written, and one of the count values C3 and C4 stored in these registers 33a and 33b is used as the original signal Sg and the chattering signal Sc.
A selector 34 that selects and outputs according to the reference clock CLK, a counter 35 that counts according to the reference clock CLK, and that outputs a carry signal Y3 when the counting of the count value fetched through the selector 34 ends, and a carry signal Y.
3, a logical sum (OR) circuit 36 that receives the rising timing signal Y1 and the falling timing signal Y2 as input and generates a chattering edge signal Y4, and a frequency divider that divides the chattering edge signal Y4 from the OR circuit 36 The flip-flop (FF) circuit 37 connected in this manner is provided, and the output of the frequency divider formed by the FF circuit 37 is used as the chattering signal Sc.

The counter 35 is connected to use the chattering edge signal Y4 as a load signal for fetching the count value C3 or C4, and the count values C3 and C4 are alternately set according to the signal level of the chattering signal Sc. Selector 34 to supply to counter 35
Is configured to supply the count value C3 as an initial value when the original signal Sg is at a high level and the count value C4 as an initial value when the original signal Sg is at a low level.
Further, although not shown, the FF circuit 37 is configured so that its output is set by the rising timing signal Y1 and preset by the falling timing signal Y2.

That is, the chattering signal Sc generated by the chattering signal generator 22 has a high level width tH (= T) corresponding to the count value C3, as shown in FIG.
ck · C3) and a low level width tL (= Tck · C4) corresponding to the count value C4, and at the rising timing of the original signal Sg, it always becomes a high level, and at the falling timing of the original signal Sg. The timing is reset at both edges of the original signal Sg so that it is always at the low level. The chattering edge signal Y4 is
The inversion timing of the chattering signal Sc and the inversion timing of the original signal Sg are shown.

Next, as shown in FIG. 3, the timing designating section 26 is a register 44 into which the mode designating value M set according to the above-mentioned operation mode is written by the operation of the control section 18, and the mode designating value M. Accordingly, the gate circuit 45 permits / prohibits the supply of the timing signals Y1 and Y2 to the SRFF circuits 42a and 42b of the mask signal generation unit 24 described later.

The mode designation value M is 2 bits (00 /
01/10/11), in the gate circuit 45, the upper bit of the mode designation value M is associated with the rising timing signal Y1 and the lower bit is associated with the falling timing signal Y2, and the bit value is "0". If so, the signal supply is prohibited, and if it is "1", the signal supply is performed.

Next, the mask signal generator 24 is connected to the controller 1
8, the register 40a to which the count value C5 is written, the register 40b to which the count value C6 is also written, and the count value C5 fetched from the register 40a using the rising timing signal Y1 as a load signal. Is provided with a counter 41a that outputs a carry signal Y5 when the count of the above is finished, and a counter 41b that outputs the carry signal Y6 when the count of the count value C6 fetched from the register 40b using the falling timing signal Y2 as a load signal is finished. ing.

In other words, the counter 41a counts the number of times the signal level of the chattering signal Sc is inverted after the rising of the original signal Sg, while the counter 41b is inverted the signal level of the chattering signal Sc after the falling of the original signal Sg. It is supposed to count the number of times you do.

Further, the mask signal generator 24 receives the rising timing signal Y1 supplied through the gate circuit 45 as a set input and the carry signal Y5 as a reset input to generate the rising side mask signal Smu, and the SRFF circuit 42a.
And a SRFF circuit 42b that generates a falling-side mask signal Smd using the timing signal Y2 supplied through the gate circuit 45 as a set input and the carry signal Y6 as a reset input, and a rising-side mask signal Smu and a falling-side mask. An OR circuit 43 that receives the signal Smd and generates a mask signal Sm is provided.

That is, as shown in FIG. 4, as for the rising side mask signal Smu generated by the SRFF circuit 42a, the timing designating unit 26 permits the supply of the timing signal Y1 (mode designating value M = 'X1'). In this case, from the timing of the rising timing signal Y1 to the timing of the carry signal Y5, that is, during the period corresponding to the count value C5 from the rising of the original signal Sg, the active level (here, high level) is set, while the SRFF circuit 42b
The trailing-side mask signal Smd generated at is carried from the timing of the trailing timing signal Y2 when the timing designating unit 26 permits the supply of the timing signal Y2 (mode designation value M = '1X'). Until the timing of the signal Y6, that is, during the period corresponding to the count value C6 from the fall of the original signal Sg, the active level (here, high level) is obtained.

Then, in the signal synthesizing section 28, the selector 46 that selects the chattering signal Sc while the signal level is at the active level and the original signal Sg during the other periods according to the mask signal Sm is used as the original signal Sg. The chattering signal Sc is combined and the pulse signal So is output.

That is, the signal generation block Bi configured as described above follows the mask signal Sm which becomes the active level for the period specified by the count values C5 and C6 at the timing specified by the mode specifying value M. A pulse signal So is generated by superimposing a chattering signal Sc having a waveform defined by the count values C3 and C4 on an original signal Sg having a waveform defined according to the count values C1 and C2.

Next, the control section 18 for setting the mode designation value M for defining the pulse signal So generated by the signal generation block Bi and the count values C1 to C6 will be described. The control unit 18 is composed of a well-known microcomputer mainly composed of a CPU, a ROM, and a RAM, and has an IO port for inputting / outputting data to / from the signal measuring unit 16 and the signal generating unit 10, and a control device 6. An external interface circuit or the like for transmitting and receiving data to and from is provided.

Then, various commands and set values input by operating the control device 6 are fetched through the external interface circuit, and the signal measuring section 16 and the signal generating section 10 are operated in accordance with these commands and set values. . As setting items for the signal generation block Bi, as shown in FIG. 5, in addition to the above-described operation mode (normal / falling edge / rising edge / both edges), the chattering signal has a high level width tH and a low level width tL. , The chattering bound number n1 at the rising edge and the chattering bound number n2 at the falling edge. Of these, the high level width tH and the low level width tL are 0.1 m.
With a resolution of sec, it is set in the range of 0.1 to 10 msec, while the number of bounds n1 and n2 is 1 in both cases.
It is set within a range of up to 15 times.

The contents of these setting items are specifically set by the controller 6 using the chattering setting screen shown in FIG. On the chattering setting screen, the chattering signal high level width tH, low level width tL, and the number of bounds n1 and n2 are set to the signal name (S
P1: first vehicle speed sensor, SP2: second vehicle speed sensor,
NC0: engine speed sensor, etc.), and signal generation blocks B1 to B according to these signal names.
It is associated so that any one of N is specified.

Then, the control unit 18, which has received the setting contents relating to the signal generation block Bi from the control device 6, first sets the period Tg of the original signal Sg specified by the signal name, the duty ratio DT, and the signal generation block Bi. The count values C1 and C2 are obtained according to the equations (1) and (2) based on the cycle Tck (1 μsec in the present embodiment) of the reference clock CLK used in the above.

However, the period Tg of the original signal Sg and the duty ratio DT are the parameters NO. For each type of the inspection target ECU 8 managed by (see FIG. 6), the inspection target ECU 8
A fixed value is set in advance in accordance with the characteristics of each sensor mounted in. C1 = Tg / Tck (1) C2 = Tg.DT / Tck = C1.DT (2) Further, based on the high level width tH and low level width tL of the chattering signal Sc and the reference clock cycle Tck,
The count values C3 and C4 are obtained according to the equations (3) and (4).

C3 = tH / Tck (3) C4 = tL / Tck (4) Further, based on the number of rising bounds n1 and the number of falling bounds n2, the count value C is calculated according to the equations (5) and (6).
Determine 5 and C6.

C5 = 2 · n1 (5) C6 = 2 · n2 (6) Further, according to the setting of the operation mode, M = '00 'in the normal mode, M = in the falling edge mode.
'01', M = '10' in rising edge mode,
In the case of the double edge mode, the mode designation value M is set so that M = '11 '.

The control unit 18 controls the count values C1 to C6 and the mode designation value M calculated and set in this manner.
Each register 30a, 30b, 33a, 33b, 40a, 40b of the signal generation block Bi specified by the signal name,
Set to 44. As a result, the desired pulse signal So in which chattering is superimposed according to the setting content on the chattering setting screen is generated in each signal generation block Bi, and is inspected via the ECU interface unit 12 as the inspection target EC.
It will be supplied to U8.

As described above, in the ECU inspection apparatus 2 of the present embodiment, the pulse signal So with chattering superimposed is arbitrarily generated in each of the signal generation blocks B1 to BN forming the pulse signal generation circuit 10b. It is possible,
Moreover, the high level width tH, the low level width tL of the chattering signal Sc, and the number of bounds of chattering n1, n
Various types of chattering can be realized by appropriately setting 2.

As a result, various pulse signals that may cause chattering, such as the detection signals of the vehicle speed sensor and the engine speed sensor, can be simulated and generated, and the chattering superimposed on these detection signals can be removed. It is possible to actually confirm whether or not the countermeasures (filter circuit, mask processing, etc.) that have been taken to do so operate effectively, and it is possible to perform highly reliable inspection on the inspection target ECU 8.

Although the chattering is superposed on the pulse signal here, it may be applied to any signal as long as it has a digital waveform. In the present embodiment, the chattering signal generation unit 22 is the chattering signal generation means, the mask signal generation unit 24, and the timing designation unit 26 is the mask signal generation means, the signal synthesis unit 28.
Is signal synthesizing means, count values C3, C4 are waveform information, count values C5, C6 are period information, and mode designation information M is timing information. Further, the register 40a, the counter 41a, and the SRFF circuit 42a are the rising-side mask generator, the register 40b, the counter 41b, and the SRFF circuit 4.
2b corresponds to the trailing-side mask generation unit, and the gate circuit 45 corresponds to the operation permission unit. Further, the counter 35 corresponds to a timer counter, the registers 33a and 33b and the selector 34 correspond to count value setting means, the counters 41a and 41b correspond to edge counters, and the registers 40a and 40b correspond to threshold value setting means.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of an ECU inspection device.

FIG. 2 is an explanatory diagram showing operation modes of a signal generation block.

FIG. 3 is a circuit diagram showing a configuration of a signal generation block.

FIG. 4 is a timing chart showing the operation of each part of the signal generation block.

FIG. 5 is an explanatory diagram showing setting items related to a signal generation block.

FIG. 6 is an explanatory diagram showing a chattering setting screen.

[Description of Reference Signs] 2 ... ECU inspection device 4 ... Signal processing device 6 ... Control device 8 ... Inspection target ECU 10 ... Signal generation unit 10a ... Analog signal generation circuit 10b ... Pulse signal generation circuit 10c ... Digital signal generation circuit 12 ... ECU Interface unit 14 ... Load unit 16 ... Signal measuring unit 18 ... Control unit 20 ... Original signal generating unit 22 ... Chattering signal generating unit 24 ... Mask signal generating unit 26 ... Timing designating unit
28 ... Signal synthesizers 30a, 30b, 33a, 33b, 40a, 40b, 4
4 ... Registers 31a, 31b, 35, 41a, 41b ... Counters 32, 42a, 42b ... SR flip-flop circuits 34, 46 ... Selectors 36, 43 ... OR circuits 3
7 ... FF circuit 45 ... Gate circuit Bi ... Signal generation block

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) G01R 31/00 G01R 31/3183 H01H 9/54 H03K 3/64

Claims (4)

(57) [Claims] 1. A chattering signal generating means for repeatedly generating a chattering signal having a waveform specified by preset waveform information, and a start timing specified by preset timing information. Mask signal generating means for generating a mask signal that becomes an active level for the duration specified by the period information, and chattering is superimposed while the mask signal generated by the mask signal generating means is at an active level. in should do the original signal, the chattering apparatus and a signal synthesizing means for synthesizing and outputting a chattering signal generated by the chattering signal generating means, as the waveform information, the chattering signal to be generated Ha
Information that identifies the length of the level and low-level periods
Is set, the chattering signal generating means counts according to a predetermined reference clock, and is set in advance.
When the count for the set value that has been set is performed, the timing signal
And a high-level period as a set value of the timer counter.
Corresponding to the count value and low level period
A count value setting means for alternately setting the count value, and the timing signal output from the timer counter.
Signal level at the timing of the timing signal.
It is characterized by generating a chattering signal in which
A chattering generator. 2. The chattering generator according to claim 1, wherein the timing information is set to a rising edge, a falling edge, or both edges of the original signal, and the mask signal generating means A rising-side mask generation unit that sets the mask signal to an active level during the continuation period from the rising edge of the original signal, and sets the mask signal to an active level during the continuation period after the falling edge of the original signal. The chattering occurrence according to claim 1, further comprising: a falling-side mask generation unit, and an operation permission unit that permits the operations of the rising-side generation unit and the falling-side generation unit according to the setting of the timing information. apparatus. 3. The chattering generator according to claim 1 or 2, wherein the chattering signal generating means changes the signal level of the chattering signal to a high level at a timing of a rising edge of the original signal, and further, the original signal. A chattering generation device, wherein the generation timing of the chattering signal is reset at both edges of the original signal so that the chattering signal becomes low level at the timing of the falling edge thereof. 4. The chattering generator according to claim 1 , wherein a chattering bound number is set as the period information, and the mask signal generation means sets the number of times of inversion of the chattering signal. And an edge counter that outputs a timing signal when a preset threshold value is counted after the start timing, and according to the setting of the period information, the edge counter within the continuation period determined by the number of bounds. Threshold value setting means for setting the number of inversions of the signal level of the chattering signal as the threshold value of the edge counter, and a mask for setting the timing of the timing signal output by the edge counter as the end timing of the active level. Chattering generation characterized by generating a signal Location.