JPH09304488A - Method and apparatus for calibrating timing generator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To correctly measure the delay time of every delay time set area, by inserting fixed delay elements of different delay times, changing a self- running oscillation cycle of a self-running oscillation circuit, and shifting a delay time area influenced by a driving frequency of a thermal insulation circuit to another area. SOLUTION: A selecting means 31, adding a calibration device 30 to a measuring means 16, selectively connects fixed delay elements D1 -Dn of different delay times in a closed loop constituted of a timing generator 10 and a feedback circuit 15. A first memory 31 stores delay data of the elements D1 -Dn . An operation means 33 calculates a difference of delay data of the element D1 -Dn and a delay time of the generator 10. A second memory 34 stores difference data and a coincidence detection means 35 decides the difference data by majority. A controller 36 controls the means 31, 33, 35 and memories 32, 34, etc. Accordingly, The delay time of the generator 10 can be correctly measured without being influenced by a clock PX to a thermal insulation circuit 20.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a calibration method and a calibration device for a timing generator used in, for example, an IC test device.

[0002]

2. Description of the Related Art FIG. 4 shows a schematic structure of a conventional timing generator and its calibration device. 10 in the figure
Indicates a timing generator. This timing generator 10
Is a coarse delay circuit 12 that switches the delay time in units of one cycle of the clock PC supplied to the input terminal 11A, and a pulse delayed roughly by this coarse delay circuit 12 is slightly delayed by the number of cascade connections of the minute delay element 13A. Micro delay circuit 13
And are connected in cascade.

The coarse delay circuit 12 is set up to determine which pulse is output from the reference clock P ₀ shown in FIG. 5A. When the timing memory 14, for example, "3" is set, the coarse delay circuit 12 starts at the same time of the clock PC counting the supply of the reference clock P _0, open the gate, for example, 3 th pulses, the reference clock P ₀ From the position of clock P
A pulse P ₁ delayed by 2τ for two C cycles is output.

The pulse delayed by the coarse delay circuit 12 is given to the minute delay circuit 13. The minute delay circuit 13 is set to a delay time corresponding to the number of cascade connection of the minute delay elements 13A. That is, the minute delay circuit 13 includes the minute delay element 13A.
, A switching circuit 13B, and an OR gate 13C are connected in cascade, for example, about 10 stages.
The switching circuit 13B is switched to a state in which the input terminal X is connected to either the output terminal Y or the output terminal Y according to the logical value of the control signal supplied from the delay setter 13D to the control terminal C.
By connecting the input terminal X to the output terminal Z, the minute delay element 13A is cascade-connected to the coarse delay circuit 12, and the delay time Δτ is set within the range of one cycle τ of the clock PC with a resolution of 1/2000, for example. . As an example, when one cycle τ of the clock PC is τ = 4 ns, the delay time Δτ is set with a resolution of 2PS.

[0005] As shown in FIG. 5D in this manner, the reference clock P T ₀ plus the delay time Δτ of the delay time 2τ and fine delay circuit 13 of the coarse delay circuit 12 from the timing of the ₀
= 2.tau + a Δτ timing pulse P ₂ which is delayed is outputted to the output terminal 11B, by the timing pulse P _2, for example, the start timing of reading time or logical comparison operation of the output waveform of the IC is applied.

In the test of IC, many timing pulses are required in addition to the timing pulse P ₂ . Therefore, the timing generator 10 shown in FIG. 4 is provided by the required number of timing pulses, and each timing generator outputs a pulse delayed by a desired timing from the timing of the reference clock P ₀ , and outputs the pulse. Use IC
It controls the operation of each part of the test equipment.

In the IC test apparatus, each timing generator 10
The timing of the pulse output from is required to be accurate. Since the delay time τ of the coarse delay circuit 12 is determined by the cycle of the clock PC, the delay time can be maintained accurately. On the other hand, the delay time of the minute delay circuit 13 is, for example, C
Since a logic element such as a gate circuit formed in the MOS IC 100 is used as a delay element, the delay time easily changes. Therefore, conventionally, the delay time of the minute delay circuit 13 is correctly measured, and the measured value is used to set the delay time.

Therefore, the timing generator 10 has been conventionally used.
A calibration device is provided for each of them so that the delay time of each timing generator 10 can be measured, the correct delay time can always be grasped, and the delay time obtained by the measurement can be used for setting. In FIG. 4, reference numeral 30 indicates a calibration device. Calibration device 30
Is a feedback circuit 15 for feeding back the output signal of the timing generator 10 to the input side, a measuring means 16 for measuring the period of the pulse fed back through the feedback circuit 15, and the feedback circuit 1.
And a mode switching circuit 18 for controlling opening and closing of the switch circuit 17
And a start pulse generator 1 for applying a start pulse to the timing generator 10 with the feedback circuit 15 connected.
9.

By controlling the switch circuit 17 to be in an open (on) state, the feedback circuit 15 is set to the timing generator 1.
A loop circuit is formed by connecting the output terminal 11B of 0 to the input terminal 11A. When a start pulse is input from the start pulse generator 19 to this loop circuit, this start pulse is output to the output terminal 11 after the delay time Δτ of the timing generator 10 (the delay time of the coarse delay circuit 12 is 0).
B. The pulse output to the output terminal 11B is fed back to the input side through the feedback circuit 15, is re-input to the timing generator 10, and is output again to the output terminal 11B after a delay time Δτ. By repeating this, the timing generator 10 becomes a free-running oscillation state and outputs a continuous pulse train signal. The pulse cycle of this pulse train corresponds to the delay time Δτ of the minute delay circuit 13 of the timing generator 10. Therefore, by measuring the period τ of the pulse fed back through the feedback circuit 15, the timing generator 10
The delay time of can be measured. The measuring means 16 measures the period of the pulse fed back to the timing generator 10 and, as a result, each minute delay element 13 of the minute delay circuit 13.
When the delay time of A is measured and the delay time of the minute delay circuit 13 does not match the preset delay time, the measured delay time is stored in the delay setter 13D, and then the stored delay time is stored. The timing is set using time so that the correct timing can be set.

By the way, the timing generator 10 described above is used.
Is generally integrated into an IC in order to downsize the IC test apparatus. CMOS type IC with low power consumption among ICs
It consists of. The power consumption of the CMOS type IC is small in a steady state, but the power consumption increases in proportion to the operation, and the temperature inside the IC tends to rise accordingly. That is, in the CMOS type IC, the power consumption is extremely small when the operation is stationary, and the power is consumed each time the internal active element performs the inverting operation. As a result, when the stationary state changes to the operating state, the temperature inside the semiconductor chip fluctuates,
There is a drawback that the delay time of the minute delay circuit 13 is greatly changed due to this temperature change.

In order to eliminate this drawback, CMO has hitherto been used.
The S-type IC 100 is provided with a heat retaining circuit 20 which is constantly maintained in an operating state and maintains the IC chip temperature at a constant value. The clock PX is given to this heat retention circuit 20,
The elements formed in the CMOS IC 100 are operated in the cycle of the clock PX to maintain the temperature inside the chip at a constant value.

[0012]

When calibrating the delay time of the timing generator 10 having a structure in which the heat insulation circuit 20 is installed in parallel, the free-running oscillation frequency of the timing generator 10 is the clock PX supplied to the heat insulation circuit 20. When the frequency approaches the frequency, the free-running oscillation frequency of the timing generator 10 is pulled into the frequency of the clock PX, and even if the delay time Δτ of the timing generator 10 is changed within a certain region S (see FIG. 6), the self-oscillation frequency of the clock PX is changed. The phenomenon that the running frequency does not change occurs. The horizontal axis X shown in FIG. 6 represents the delay time set value Δτ set in the timing generator 10, and the vertical axis Y represents the measured delay time. In the region S, the free-running oscillation frequency of the timing generator 10 is drawn into the frequency of the clock PX of the heat retention circuit 20 even if the set value Δτ of the delay time is changed, and shows a region where it does not change. In the area S, there arises a disadvantage that an accurate delay time cannot be known for the delay setting value Δτ. This inconvenience is C
When a delay time is measured by forming a free-running oscillation circuit without limiting to the timing generator formed in the MOS type IC, and there is another circuit that handles a signal of a constant frequency in the vicinity of the free-running oscillation circuit. appear. Therefore, in this invention, the CMO
The present invention is not limited to S-type ICs, and can be applied to timing generators configured with other types of circuit structures.

Although the area S is shown as one location in FIG. 6, the same phenomenon occurs at the harmonic position of the clock PX. Therefore, the area S occurs at a plurality of positions. This inconvenience has not been a particularly fatal defect because ICs having relatively slow operating speeds have been tested conventionally.
However, this inconvenience becomes a serious problem when testing a high-speed operation type IC.

An object of the present invention is to provide a timing generator in which a circuit for handling a signal of a constant frequency is arranged in close proximity to all the delay time setting areas without being affected by the frequency of a clock driving another circuit. The delay time of can be measured accurately. An object of the present invention is to provide a calibration method and a calibration device for a timing generator.

[0015]

According to the present invention, a free-running oscillation circuit is configured by connecting a feedback circuit to a timing generator, and the delay time of the timing generator is measured by measuring the free-running oscillation period. In the calibration method of the timing generator, a free-running oscillation circuit configured by the timing generator is inserted each time a fixed delay element having a different delay time is inserted in the feedback circuit and the delay time of the fixed delay element is changed. The free-running oscillation cycle of is changed, and the delay time area affected by the drive frequency of the heat retention circuit is shifted to another area by the change of this free-running oscillation cycle. S
It proposes the calibration method of the timing generator which can measure the true delay time in.

According to the present invention, as the calibration device adopting the above-mentioned calibration method, the selecting means for inserting the fixed delay elements having different delay times into the feedback circuit connected to the timing generator, and the measured value of the delay time of the fixed delay element. Each time the first memory for storing the data is connected to the fixed delay element having a different delay time, the free-running oscillation cycle of the timing generator is measured, and the fixed delay element stored in the first memory from the measured value for each measurement. Calculating means for obtaining the delay time after removing the delay time of No. 2, a second memory for storing the calculation result of this calculating means, and a delay time decided by a majority decision from the delay times stored in the second memory, The coincidence detecting means for determining this delay time as the true delay time constitutes the calibration device for the timing generator.

According to the method and apparatus for calibrating a timing generator according to the present invention, the delay time of the timing generator is calibrated even if the circuits for handling signals of constant frequency are arranged adjacent to each other. In this case, even if it is affected by the frequency of the clock applied to another circuit, the delay time of the affected area S can be accurately measured. Therefore, it is possible to obtain an accurate delay time over the entire range of the delay time setting range of the timing generator, which provides an advantage that an accurate test can be performed even when testing a high-speed operation type IC. .

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment of a calibration device using the timing generator calibration method according to the present invention.
In this example, the timing generator 10 is formed in a CMOS IC. In FIG. 1, reference numeral 100 denotes a CMOS type IC as in the description of FIG. This CMOS IC1
00, the timing generator 10 and the heat insulation circuit 20 described in FIG.
Is maintained to consume a constant amount of power, and the power consumption is used to maintain the temperature of the semiconductor chip forming the CMOS IC 100 at a constant value.

A feedback circuit 15 is connected to the timing generator 10. In the calibration mode, the feedback circuit 15 is connected to the input terminal side under the control of the mode switching circuit 18 to form a closed loop and a free-running oscillation circuit. For this free-running oscillator circuit, a start pulse oscillator 19
Then, the timing generator 10 is caused to self-oscillate, and the free-running oscillation period is measured by the measuring means 16 to measure the delay time set in the timing generator 10. The description so far is the same as the description of FIG.

In the present invention, the calibration device 30 is provided with the measuring means 16
In addition to the above, in the closed loop composed of the timing generator 10 and the feedback circuit 15, the selection means 3 for selectively connecting the fixed delay elements D1, D2, ... Dn having different delay times from each other.
1, a first memory 32 for storing the delay data of the fixed delay elements D1, D2, ... Dn, the delay data of the fixed delay element stored in the first memory 32, and the timing generator 1
Calculation means 33 for calculating the difference with the delay time of 0, and second memory 3 for storing the difference data calculated by this calculation means 33.
4, the coincidence detecting means 35 that takes the majority of the difference data stored in the second memory 34, the selecting means 31, the first memory 32, the calculating means 33, the second memory 34, the coincidence detecting means 35, and the like. And the controller 36 that operates. Here, the fixed delay elements D1, D2, ... D
If the number of n is n, the first memory 32 and the second memory 34 have n addresses.

The calibration procedure will be described below. First, the delay times of the fixed delay elements D1, D2, ... Dn are measured. For this purpose, the controller 36 sets the delay time of the timing generator 10 to 0, and in this state, the selecting means 31 sequentially connects the fixed delay elements D1, D2, ... Dn one by one to the free-running oscillation loop. The measuring means 16 includes fixed delay elements D1 and D.
Each time 2, ..., Dn is connected to the free-running oscillation loop, the cycle of the pulse train generated in the free-running oscillation loop is measured, and the delay data M1, M2, ... Mn (see FIG. 2) are obtained from the cycle. The delay data M1, M2, ... Mn are transferred to the first memory 3
It is stored in n addresses of 2.

Next, the controller 36 sets the delay time of the timing generator 10 (the delay time of the minute delay circuit) to the settable minimum delay time τ ₁ . In this setting state, the selecting means 31 again connects the fixed delay elements to the free-running oscillation loop one by one in the order of D1, D2, ... Dn. Measuring means 16
Each Each fixed delay elements D1, D2, which is ... Dn are connected to the free-running oscillation loop, the period of the pulse train generated in the free-running oscillation loop is measured, the delay data L _11, L _12, seeking ... L _1n .

The measuring means 16 uses the delay data L ₁₁ , L ₁₂ , ...
Every time L _1n is output, the calculation means 33 outputs L ₁₁ −M ₁ =
_{J 11, L 12 -M 2 =} J 12, L 13 -M 3 = J 13 ... L 1n -M
_n = J _1n is calculated, and the calculation results J ₁₁ , J ₁₂ , ... J _1n are stored in n addresses of the second memory 34. The coincidence detecting means 35 extracts the data having the largest number of coincidences from the data stored in the second memory 34, transfers this data to the timing generator 10, and stores it as the minimum delay time value τ ₁ ′.

The reason why the data having the largest number of coincidence among the data fetched in the second memory 34 becomes the true delay time τ ₁ ′ of the timing generator 10 is as follows. Straight _{E 1, E 2, E 3} ... E n are fixed delay elements D1 shown in FIG. 2,
Measurement in which the delay time of the micro delay circuit 13 (see FIG. 4) of the timing generator 10 is changed from the minimum value to the maximum value while the D2, ... The values obtained by plotting the values L _{11 to} L _1n , L _{21 to} L _2n , ... Each straight line _{E 1, E 2, E 3} ... E n are fixed delay elements D1, D2, ... delay time M ₁ of Dn,
Except for M ₂ , M ₃ ... M _n , the straight line shown in FIG. 3 coincides with the inclination and the origin position. That the measurement value on the straight lines _{E 1 ~E n L 11, L} 12, L 13 ... fixed delay elements D1 from L _1n,
D2, ... delay time M _1, M ₂ of the Dn, the original by removing the ... M _n should be all matched values. However,
If there is a measured value included in the region S affected by the clock PX that continues to be applied to the heat retention circuit 20 in each measured value L ₁₁ , L ₁₂ , L ₁₃ ... L _1n , the measured value of the fixed delay element The value obtained by removing the delay time is different from the values of other data. In the example shown in FIG. 2, the value L ₁₁ measured with the set value τ ₁ is included in the region S, and therefore the calculated value L _{11 is obtained.}
-M ₁ = J ₁₁ becomes a value different from the other calculation result _{J 12, J 13 ... J 1n} , all other operations result J _12, J ₁₃ ... J _1n coincidence. That is, J ₁₁ ≠ J ₁₂ = J ₁₃ = J ₁₄ ... = J _1n . The data in which the number of coincidences is large indicates the value of the delay time of the true timing generator 10, and the true delay time of the timing generator 10 can be measured.

In this way, the timing generator 10
Delay setting value is τ_Two, Τ_Three, Τ_FourEvery time you change to ...
Switching the constant delay elements D1, D2, ... Dn, and switching
From the free-running oscillation period, the delay time measurement value L_{twenty one}, L_{twenty two}
... L_2n, L₃₁... L_3n,… Is measured, and L is measured for each measurement._{twenty one}
-M₁= J_{twenty one}, L_{twenty two}-M_Two= J_{twenty two}, ... L_2n-M_n=
J _2n, L₃₁-M₁= J₃₁, L₃₂-M_Two= J₃₂, ... L_3n−
M_n= J_3nInsulation circuit
True delay that eliminates the effect of clock PX on 20
Obtain the total time (delay time of the timing generator 10).
Can be. The delay time thus obtained is used as the timing generator 1
0 stored in the timing memory 14 (see FIG. 4).
Timing pulse P2 (see FIG. 5D)
It is possible to set the time of occurrence of the with a correct known value.

In the above description, the fixed delay elements D1, D2,
Although the example in which Dn is provided has been described, the fixed delay elements D1, D
2, ... Dn, instead of the coarse delay circuit 12 described in FIG.
The same calibration as described above can be performed by using. Further, the first memory 32, the calculating means 33, the second memory 34, the coincidence detecting means 35, the controller 36, etc. can be configured by software in a higher-level computer.

[0027]

As described above, according to the present invention, the delay time of the timing generator 10 can be accurately measured without being affected by the clock PX that gives the heat insulation circuit 20, and the measured value thereof can be obtained. Is stored in the timing generator 10, the timing generator 10 is calibrated after calibration.
Since the set value of is correctly corrected and the time position of the timing pulse generated from the timing generator 10 can be correctly known, it is possible to obtain an actual benefit that an accurate test can be performed even in a high-speed operation type IC.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a calibration device for a timing generator according to the present invention.

FIG. 2 is a graph for explaining the operation of the main part of the present invention.

FIG. 3 is a graph similar to FIG.

FIG. 4 is a block diagram for explaining a conventional technique.

FIG. 5 is a waveform chart for explaining the operation of FIG. 4;

FIG. 6 is a graph for explaining the inconvenience of the conventional timing generator.

[Explanation of symbols]

 10 Timing Generator 11A Input Terminal 11B Output Terminal 12 Coarse Delay Circuit 13 Minute Delay Circuit 14 Timing Memory 15 Feedback Circuit 16 Measuring Means 18 Mode Switching Means 19 Start Pulse Generator 20 Insulation Circuit 100 CMOS IC

Claims (2)

[Claims] 1. A free-running oscillation loop in a calibration method for connecting the output and the input of a timing generator with a feedback circuit, measuring the delay time set in the timing generator by causing free-running oscillation, and calibrating the delay time. A fixed delay element having a different delay time is selectively inserted into the fixed delay element, and the connection of the fixed delay element moves the delay area affected by the clock given to the circuit provided in the vicinity of the timing generator.
A method for calibrating a timing generator, wherein a correct delay time can be measured over the entire delay setting range set in the timing generator by moving the delay region affected by the clock. 2. A. Selecting means for inserting fixed delay elements having different delay times into a feedback circuit connected to the timing generator; and B. A first memory for storing a measurement value of a delay time of the fixed delay element; C. Each time a fixed delay element with a different delay time is connected,
Calculating means for measuring the free-running oscillation period of the timing generator, and for each measurement, obtaining a delay time by removing the delay time of the fixed delay element stored in the first memory from the measured value; A second memory for storing the calculation result of the calculating means; A coincidence detecting means for extracting a delay time determined by a majority decision from the delay times stored in the second memory and determining the delay time as a true delay time. Calibration device.