JP3497751B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a gate contact of a MOSFET (insulated gate type field effect transistor) or an IGBT (insulated gate type bipolar transistor) having a trench sidewall as a channel region. And a method for forming the same, and is used, for example, in a power device.

[0002]

2. Description of the Related Art As a kind of power device, a trench M having a sidewall of a trench as a channel region is formed on a semiconductor substrate.
A semiconductor device in which a large number of OSFETs are arranged in parallel (hereinafter referred to as U-MO
S) or a semiconductor device in which a large number of trench IGBTs are arranged side by side on a semiconductor substrate (hereinafter referred to as U-IGBT).
It has been known.

FIGS. 6A to 6C show a conventional U-MO.
The manufacturing process of S is shown schematically. FIG. 7 (a) is shown in FIG.
FIG. 7B schematically shows a sectional structure taken along the line AA ′ in FIG. 6C, and FIG. 7B schematically shows a sectional structure taken along the line B′-B in FIG. 6C. ing.

Hereinafter, FIGS. 6A to 6C and FIG.
An outline of a conventional U-MOS manufacturing process will be described with reference to (a) and (b).

First, the silicon substrate (drain region) 13
A base region 12 is formed in the surface layer portion of the above, based on the source pattern 1 and the base pattern 2 as shown in FIG. 6A, and a source region 11 is formed in the surface layer portion of the base region 12.

Next, in the source region 11, as shown in FIG.
A large number of trenches having the lattice pattern 3 as shown in FIG. 3B are formed to penetrate the base region 12 and reach the inside of the drain region 13.

At this time, in order to form a gate electrode lead-out portion described later in a part of the source region 11, the lattice-shaped trenches are not formed in a part of the source region 11. That is, a part of the lattice pattern of the trench is missing.

After that, a gate insulating film (eg, SiO ₂ film) 9 is formed on the surface of the substrate including the inner wall surface of the trench.

Next, in order to form a gate electrode, impurity-doped polysilicon 8 is buried in the trench and deposited on the entire surface of the substrate (gate insulating film 9).

Thereafter, the doped polysilicon 8 is patterned based on the trench / gate drawing pattern 4 as shown in FIG. 6 (c), and the gate electrode is drawn to the missing portion of the lattice pattern of the trench. A wide pad 8a for contacting the gate electrode and a connection pattern for connecting this to the gate electrode in the trench are left.

Next, after depositing an interlayer insulating film 15 on the entire surface of the substrate, the pad 8a for contacting the gate electrode is formed.
A large contact hole for drawing out a gate electrode is opened above the interlayer insulating film 15, and an opening for drawing out a source / base is formed in the interlayer insulating film around the opening of the trench and the gate insulating film on the substrate surface thereunder. To form.

Next, a metal wiring layer (for example, an aluminum wiring layer) is formed on the entire surface of the substrate by a sputtering method, and required patterning is performed to form the source / base electrode 10 and the gate electrode 16. Further, a drain electrode (not shown) is formed on the back surface of the substrate.

By the way, in recent years, the power U-MOS has been required from the market for further miniaturization, energy saving, and cost reduction. For example, the stripe pattern of the source region and its pitch are each about 0.8 μm, and the gate trench of the gate trench. It is necessary to reduce the width to about 0.35 μm.

However, with such miniaturization, the contact area between the source / base electrode 10 and the base region 12 / source region 11 on the bottom surface of the opening for source / base extraction in the gate insulating film becomes insufficient. The contact resistance of the contact part may increase.

When using the above U-MOS, the source S / back gate region (base region B) is normally grounded and a voltage of 20 to 500 V is applied to the drain D, but other than having a trench gate. Power device, such as a U-IGBT drain D for example 5
The above-mentioned problems also occur in a device that is used by applying a voltage of 00 V or more.

[0016]

As described above, in the conventional U-MOS and U-IGBT, the contact area between the source / base electrode and the base region / source region becomes insufficient due to the miniaturization of the pattern. There is a problem that the contact resistance of the contact portion becomes high.

The present invention has been made in order to solve the above-mentioned problems, and the shortage of the contact area between the source / base electrode and the source region / base region due to the miniaturization of the pattern in the U-MOS or U-IGBT. Can be resolved, and
It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same that can ensure a sufficient contact area between the gate electrode and the gate electrode contact pad.

[0018]

The semiconductor device of the present invention comprises:
The MOS transistor includes a first conductivity type silicon substrate serving as a drain region of the MOS transistor and a second conductivity type semiconductor layer formed on the surface layer of the silicon substrate and opposite to the first conductivity type. A base region serving as a gate region, a first conductivity type source region formed in a surface layer portion of the base region, a gate electrode trench formed in the source region to a depth penetrating the base region, A gate insulating film formed on the inner wall surface of the gate electrode trench and the substrate surface at the peripheral edge of the opening and on the substrate surface of the gate extraction region, a buried gate electrode buried in the gate electrode trench, and the buried gate A gate made of doped polysilicon that is continuous with the electrode and is formed on the gate insulating film in the gate extraction region. An opening for source / base extraction is formed on a pole extraction pad and a substrate including the gate insulating film and the gate electrode extraction pad on an intermediate portion between the trenches existing in the source region. An interlayer insulating film in which a plurality of holes are formed on the inner region of the gate extraction region and for forming a plurality of gate extraction electrode contacts, and a lower portion of each of the plurality of source / base extraction openings. Source formed to a depth reaching the base region
A base contact trench, a gate lead-out electrode contact trench formed in the gate electrode lead-out pad at a lower part of each of the plurality of gate electrode contact holes, and a part of the interlayer insulating film and a continuous line therewith. Source formed in the plurality of source / base leading openings and source / base contact trenches and connected to the source region and the base region in the middle between the trenches existing in the source region. A base electrode, a part of the interlayer insulating film, and a plurality of holes for contacting the gate extraction electrode and a trench for contacting the gate extraction electrode formed so as to be continuous therewith, and connected to the pad for extracting the gate electrode And a gate extraction electrode.

The semiconductor device manufacturing method of the present invention is
Forming a base region of a second conductivity type opposite to the first conductivity type on the surface layer of the first conductivity type silicon substrate; and forming a source region of the first conductivity type on the surface layer of the base region. A step of forming a gate electrode trench having a buried gate pattern in the source region to a depth penetrating the base region, and then forming a gate insulating film on the substrate surface including the inner wall surface of the trench; A gate insulating film in the gate lead-out region is formed by depositing doped polysilicon on the entire upper surface and burying the doped polysilicon for the gate electrode in the trench for the gate electrode and patterning the doped polysilicon on the substrate. A step of forming a pad for drawing the gate electrode on the upper surface,
A step of depositing an interlayer insulating film on the entire surface of the substrate; and an opening for source / base extraction on an intermediate portion between the gate electrode trenches existing in the source region with respect to the interlayer insulating film. And forming a plurality of holes for contacting the gate extraction electrode on the gate electrode extraction pad, each of which has a smaller opening width than the opening for extracting the source / base, and the source / base extraction. A source / base contact trench is formed at a depth reaching the base region below a gate opening, and a gate lead-out electrode contact is formed on the gate electrode lead-out pad below the gate lead-out electrode contact hole. And forming a metal trench on the entire surface of the substrate. Burying a metal on the source base contact trenches and the gate lead-out electrode contact trenches, performs a required patterning,
Forming a source / base electrode connected to the source / base contact trench and a gate electrode connected to the gate extraction electrode contact trench.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

First, the outline of the present invention will be described.

As a method of miniaturizing the U-MOS, FIG.
As shown in (b), in the source region 11 of the substrate surface layer portion (base region 12 surface layer portion) at the center of the bottom surface of the source / base extraction opening opened in the interlayer insulating film 15,
A contact trench is formed deeper than the source region 11, and a part of the source / base electrode 10 is buried in the contact trench via the gate insulating film 9.

With such a structure, the source region 11
The contact area between the base region 12 and the source / base electrode 10 is increased, and the contact resistance of the contact portion is reduced.

On the other hand, when forming the contact trench, if the source region 11 and the base region 12 are etched by, for example, RIE (reactive ion etching),
At the same time, the portion of the gate electrode contact pad 8a corresponding to the bottom surface of the contact hole for leading out the gate electrode, which is opened in the interlayer insulating film 15 above the pad 8a, is also etched. In this case, the etching rate of the doped polysilicon of the gate electrode contact pad 8a is higher than that of the silicon of the source region 11 and the base region 12.

Now, the thickness of the interlayer insulating film 15 is, for example, 1.
The thickness of the gate electrode contact pad 8a is, for example, about 0.5, the depth of the source region 11 is, for example, about 0.3 to 0.5 μm, and the depth of the base region 12 is, for example, about 0.7 μm. Assuming that the etching is performed so that the depth of the contact trench becomes, for example, about 0.5 μm when the opening width of the source / base extraction opening is 0.8 μm.

At this time, the thickness (about 0.5 μm) of the gate electrode contact pad 8a which is simultaneously etched.
Consider a case where the sum of the thickness of the gate insulating film 9 on the surface of the substrate and the thickness thereof is equal to or smaller than the depth of the contact trench due to process variations.

In this case, the bottom surface of the contact hole for pulling out the gate has the base region 12 below the pad 8a.
Of the gate electrode 16 in a later step.
When this is formed, there is a problem that the gate electrode 16 and the base region 12 are short-circuited and connected through the contact hole.

If Br is used as an etchant for RIE when forming the contact trench, it is necessary to consider that the pad 8a for contacting the gate electrode, which is simultaneously etched, has a microphone loading effect.

The microphone loading effect is that, in RIE using a predetermined etchant, the etching rate of polysilicon (the material of the pad 8a) is the gate extraction of the interlayer insulating film 15 above the pad as shown in FIG. 3, for example. It depends on the opening width of the contact hole (for a circular hole, it depends on the radius).

From the characteristics shown in FIG. 3, it can be seen that the etching rate of the doped polysilicon 8a increases as the opening width of the etching mask increases. Therefore,
As described above, in order to prevent the bottom surface of the contact hole for pulling out the gate from reaching the base region 12 below the pad 8a, it is desirable to reduce the opening width of the contact hole for pulling out the gate.

However, if the opening width of the contact hole for extracting the gate is simply reduced, the gate electrode 16
There is a possibility that the contact area between the pad and the gate electrode contact pad 8a becomes insufficient, and the contact resistance of the contact portion becomes high.

By the way, the contact hole for gate extraction has an opening width of 10 μm (about 100 μm at present).
It was confirmed that the contact resistance of the gate contact portion was increased, which adversely affected the threshold voltage of the U-MOS and the waveform of the output signal.

Therefore, a large number of contact holes for gate extraction having a smaller opening width than the opening for source / base extraction are provided, for example, in a matrix arrangement, and the total opening area of the contact holes for gate extraction is large. Is, for example, 100 μm □ or more.

<First Embodiment> FIGS. 1A to 1D show
1 schematically shows a manufacturing process of a U-MOS according to a first embodiment of the present invention.

FIG. 2 (a) schematically shows a sectional structure taken along the line AA 'in FIG. 1 (d), and FIG. 2 (b) is B'- in FIG. 1 (c). The cross-sectional structure along the line B is schematically shown.

Hereinafter, FIGS. 1 (a) to 1 (d) and FIG.
The UM according to the first embodiment with reference to (a) and (b)
The manufacturing process of the OS will be described.

First, for example, as shown in FIG.
After a p-type base region (back gate region) 12 is formed based on the base pattern 2 and the source pattern 1 as shown in (a), an n-type source region is formed on the surface layer portion of the internal region of the base region 12. 11 is formed.

Next, in the source region 11, for example, a large number of gate trenches having a grid-like pattern 3 as shown in FIG. 1B are penetrated through the base region 12 into the drain region 13. Form to the depth it reaches.

At this time, in order to form a gate electrode lead-out portion which will be described later in a part of the source region 11, the lattice-shaped trenches are not formed in a part of the source region 11. That is, a part of the grid-like pattern is missing (the missing part of the gate trench pattern is indicated by 3a).
It has become.

Thereafter, a gate insulating film (eg, SiO ₂ film) 9 is formed on the surface of the substrate including the inner wall surface of the trench.

Next, in order to form a gate electrode, impurity-doped polysilicon 8 is buried in the trench and is deposited on the entire surface of the substrate (gate insulating film 9).

Thereafter, the doped polysilicon 8 is patterned based on the trench / gate drawing pattern 4 as shown in FIG. 1C to draw the gate electrode to the missing portion 3a of the gate trench pattern. A wide pad 8a for contacting the gate electrode and a connection pattern for connecting this to the gate electrode in the trench are left.

Then, a CVD insulating film 15 is deposited as an interlayer insulating film on the entire surface of the substrate by, for example, the CVD method. Thereafter, as shown in FIG. 1D, a plurality of small-diameter contact holes 15b for drawing out the gate electrode are formed in the interlayer insulating film 15 on the pad 8a for contacting the gate electrode, for example, in a matrix, and the source region is formed. An opening (not shown in FIG. 1D) for drawing out the source / base is formed in the interlayer insulating film 15 around the opening of the trench existing in 11 and the gate insulating film 9 on the substrate surface thereunder. Form.

In this case, the opening width b of each hole for gate extraction is formed smaller than the opening width a of each opening for source / base extraction, and the number of holes for gate extraction is within the range of about 100 to 6000. In this case, the opening area of the entire gate extraction hole is 100 μm, for example.
It should be formed to have a size of m □ or more.

Here, for example, a = 0.8 μm □, b =
If it is 0.5 μm, about 200 holes for drawing out the gate will be provided.

Next, as shown in FIG. 1 (c), by using RIE using, for example, Br as an etchant,
A contact trench is formed deeper than the source region 11 in the source region 11 of the substrate surface layer portion (base region 12 surface layer portion) at the center of the bottom surface of the base lead-out opening. At the same time, a portion of the gate electrode contact pad 8a corresponding to the bottom surface of the gate electrode drawing hole is also etched.

In this case, the source region 11 and the base region 1
Pad 8 for contacting the gate electrode rather than silicon 2
The doped polysilicon of a has a higher etching rate.

Now, the thickness of the interlayer insulating film 15 is, for example, 1.
The thickness of the gate electrode contact pad 8a is, for example, about 0.5, the depth of the source region 11 is, for example, about 0.3 to 0.5 μm, and the depth of the base region 12 is, for example, about 0.7 μm. Assuming that, when the opening width a of the source / base extraction opening is 0.8 μm □, etching is performed so that the depth of the contact trench becomes, for example, about 0.5 μm.

At this time, the thickness (about 0.5 μm) of the gate electrode contact pad 8a which is etched at the same time
Consider a case where the sum of the thickness of the gate insulating film 9 on the surface of the substrate and the thickness thereof is equal to the depth of the contact trench.

In this case, the doped polysilicon of the gate electrode contact pad 8a to be etched is
For example, in consideration of the presence of the microphone loading effect such as the characteristic shown in FIG. 3, the opening width b of the gate extraction hole is formed small as described above, so that the pad is formed on the bottom surface of the gate extraction hole. The holes formed in 8a are prevented from reaching the lower base region 12.

Next, a metal wiring layer (for example, an aluminum wiring layer) is formed on the entire surface of the substrate by a sputtering method, and required patterning is performed to form the source / base electrode 10 and the gate electrode 16. Further, a drain electrode (not shown) is formed on the back surface of the substrate.

At this time, the source and
Although part of the base electrode 10 is buried and part of the gate electrode 16 is buried in the hole formed in the pad 8a, the gate electrode 16 and the base region 12 are not short-circuited and connected.

FIG. 4 shows an equivalent circuit of the U-MOS having the structure shown in FIGS. 2 (a) and 2 (b).

As shown in this equivalent circuit, the source (S)
In addition to the n-channel MOS transistor having a region 11, a back gate (BG) region 12, a drain (D) region 13, and a gate (G) electrode 16, the drain region 1
3, the source region 11 corresponds to the collector C, the emitter E
And a parasitic np in which the base region 12 becomes the base B.
There are n-transistors.

That is, the U-MOS having the structure shown in FIGS. 2A and 2B is formed on the first conductivity type silicon substrate which becomes the drain region of the MOS transistor and the surface layer portion of the silicon substrate. A base region which is a second conductivity type semiconductor layer opposite to the first conductivity type and serves as a back gate region of the MOS transistor; and a first conductivity type source region formed in a surface layer portion of the base region, A gate electrode trench formed in the source region to a depth penetrating the base region, a gate surface formed on the inner wall surface of the gate electrode trench and the substrate surface of the opening peripheral portion, and the substrate surface of the gate extraction region. An insulating film, a buried gate electrode buried in the trench for the gate electrode, and a gate lead-out region connected to the buried gate electrode. Of the gate electrode lead-out pad made of doped polysilicon formed on the gate insulating film, and on the substrate including the gate insulating film and the gate electrode lead-out pad, each existing in the source region. An interlayer insulating film in which an opening for source / base extraction is formed on an intermediate portion between the trenches, and a plurality of holes for contacting a gate extraction electrode are opened in an inner region of the gate extraction region; A source / base contact trench formed to a depth reaching the base region at a lower portion of each of the plurality of source / base leading openings, and a lower portion of each of the plurality of gate electrode contact holes. A gate lead-out electrode contact trench formed in the gate electrode lead-out pad; Wherein the plurality of sources so as to be continuous and on its part of the interlayer insulating film,
A source / base electrode formed in the opening for drawing out the base and the source / base contact trench and connected to the source region and the base region at an intermediate portion between the trenches existing in the source region; and the interlayer. A gate which is formed on a part of the insulating film and so as to be continuous therewith in the plurality of holes for contacting the gate extraction electrodes and in the trenches for contacting the gate extraction electrodes, and which is connected to the polar polysilicon at the gate electrode extraction pads. And a lead electrode.

Further, in the manufacturing process of the U-MOS of the first embodiment, the first layer is formed on the surface layer portion of the silicon substrate of the first conductivity type.
Forming a base region of a second conductivity type opposite to the conductivity type, forming a source region of the first conductivity type in a surface layer portion of the base region, and having a buried gate pattern in the source region Forming a gate electrode trench to a depth penetrating the base region, and then forming a gate insulating film on the substrate surface including the inner wall surface of the trench, and depositing doped polysilicon on the entire surface of the substrate and forming the gate electrode Filling the gate electrode with doped polysilicon for the gate electrode and patterning the doped polysilicon on the substrate to form a gate electrode extraction pad on the gate insulating film in the gate extraction region; First, a step of depositing an interlayer insulating film on the entire surface of the substrate, and a step of depositing an interlayer insulating film on each surface of the substrate in the source region with respect to the interlayer insulating film. A plurality of openings for leading out the source / base are formed on intermediate portions between the trenches for the gate electrodes, and a plurality of openings each having a smaller opening width than the opening for leading out the source / base are formed on the pad for leading out the gate electrode. A step of opening a hole for contacting the gate lead-out electrode, and forming a trench for source-base contact at a depth reaching the base region below the contact hole for pulling out the source-base, Forming a gate lead-out electrode contact trench in the gate electrode lead-out pad below the contact hole;
Next, a metal layer is formed on the entire surface of the substrate, a metal is buried in the source / base contact trench and the gate lead electrode contact trench, and the required patterning is performed to form a source connected to the source / base contact trench. A step of forming a gate electrode connected to the base electrode and the gate lead-out electrode contact trench.

According to the U-MOS of the first embodiment described above, the contact trench structure increases the contact area between the source / base electrode 10 and the source region 11 / base region 12, and reduces the contact resistance of the contact portion. It is possible to let

Although the individual opening widths of the gate lead-out holes are made small, the contact area between the gate electrode 16 and the gate electrode contact pad 8a is sufficiently secured by forming a large number of gate lead-out holes. Therefore, the contact resistance of the contact portion can be reduced.

In the above embodiment, for example, U- having a stripe-shaped source pattern as shown in FIG.
Although an example in which the present invention is applied assuming a MOS has been shown, the present invention is not limited to the stripe-shaped source pattern, and for example, FIG.
The present invention can also be applied to a U-MOS having an offset mesh source pattern as shown in FIG.

In the above embodiment, the n-channel type U-
Although the MOS has been described, the same effect as that of the above-described embodiment can be obtained by manufacturing the n-channel U-IGBT according to the above-described embodiment. In this case, when the source pattern of the U-IGBT is miniaturized to, for example, about 2 μm,
The drain / source regions correspond to the collector / emitter correspondingly, and the base-emitter resistance distance of the parasitic npn transistor whose base region is the base becomes short,
The base-emitter resistance rbb is reduced and parasitic np
It is possible to increase the latch-up current of the n-channel MOS transistor due to the n-transistor.

[0061]

As described above, according to the semiconductor device and the method of manufacturing the same of the present invention, the source / base electrode and the source accompanying the miniaturization of the pattern in the semiconductor device having the trench gate such as U-MOS and U-IGBT. The shortage of the contact area between the region and the base region can be solved, and further, the shortage of the contact area between the gate electrode and the gate electrode contact pad can be solved.

[Brief description of drawings]

FIG. 1 is a diagram schematically showing a manufacturing process of a U-MOS according to a first embodiment of the present invention.

FIG. 2 is a diagram schematically showing a cross-sectional structure taken along line AA ′ and line B′-B in FIG.

3A and 3B are views for explaining a microphone loading effect in which an etching rate changes depending on an opening width of a contact hole of an upper interlayer insulating film in RIE of polysilicon in a U-MOS manufacturing process of the first embodiment. FIG.

4 is a diagram showing an equivalent circuit of a U-MOS having the structure of FIG.

FIG. 5 is a diagram showing different examples of source patterns in the U-MOS of the present invention.

FIG. 6 is a diagram schematically showing a conventional U-MOS manufacturing process.

FIG. 7 is a view schematically showing a cross-sectional structure taken along line AA ′ and line B′-B in FIG. 6 (c).

[Explanation of symbols]

8 ... Doped polysilicon, 8a ... Gate electrode pad, 9 ... Gate insulating film, 10 ... Source / base electrode, 11 ... n-type source region, 12 ... p-type base region, 13 ... n-type silicon substrate (drain region), 15 ... Interlayer insulating film, 16 ... Gate electrode.

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-10-56174 (JP, A) JP-A-9-219519 (JP, A) JP-A-3-11765 (JP, A) JP-A-9- 69622 (JP, A) (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 29/78 653

Claims (10)

(57) [Claims] 1. A first-conductivity-type silicon substrate that serves as a drain region of a MOS transistor, and a second-conductivity-type semiconductor layer formed on the surface layer of the silicon substrate and opposite to the first-conductivity type, A base region serving as a back gate region of the MOS transistor, a source region of the first conductivity type formed in a surface layer portion of the base region, and a gate electrode formed in the source region to a depth penetrating the base region. Trench, a gate insulating film formed on the substrate surface of the inner wall surface of the gate electrode trench and the opening peripheral edge and the substrate surface of the gate extraction region, and a buried gate electrode embedded in the gate electrode trench And a doped poly silicon continuous with the buried gate electrode and formed on the gate insulating film in the gate extraction region. And a gate electrode lead-out pad formed on the substrate including the gate insulating film and the gate electrode lead-out pad, the gate electrode lead-out pad being formed on the intermediate portion between the gate electrode trenches existing in the source region. An interlayer insulating film in which an opening for source / base extraction is formed and a plurality of holes for contacting a gate extraction electrode are opened on an inner region of the gate extraction region; and an opening for extraction of the plurality of sources / bases. Source / base contact trenches formed to a depth reaching the base region at respective lower portions of the gate portions, and the gate electrode lead-out pads formed at respective lower portions of the plurality of gate electrode contact holes. A gate extraction electrode contact trench, and a part of the interlayer insulating film and the trench Are formed in the plurality of openings for leading out the source / base and the trenches for source / base contact so as to be connected to each other, and are connected to the source region and the base region in an intermediate portion between the trenches existing in the source region. A source / base electrode, a plurality of holes for the gate extraction electrode contacts and a plurality of gate extraction electrode contact trenches which are formed so as to be continuous with and part of the interlayer insulating film, and connected to the gate electrode extraction pad. And a gate extraction electrode that is formed into a semiconductor device. 2. The semiconductor device according to claim 1, wherein each of the gate lead electrode contact trenches has an opening width smaller than that of each of the source / base lead openings, and the plurality of gate lead electrode contact trenches. Is formed in the range of about 100 to 6000 semiconductor devices. 3. A step of forming a base region of a second conductivity type opposite to the first conductivity type on a surface layer part of a first conductivity type silicon substrate, and a step of forming the base region of the first conductivity type on the surface layer part of the base region. Forming a source region, and forming a gate electrode trench having a buried gate pattern in the source region to a depth that penetrates the base region, and then forming a gate insulating film on the substrate surface including the inner wall surface of the trench And the step of depositing doped polysilicon on the entire surface of the substrate, burying the doped polysilicon for the gate electrode in the trench for the gate electrode, patterning the doped polysilicon on the substrate, and extracting the gate. Forming a gate electrode extraction pad on the gate insulating film in the region; depositing an interlayer insulating film on the entire surface of the substrate; The interlayer insulating film, to form a respective on an intermediate opening for the source base lead between the trenches cross for each gate electrode present in said source region,
A step of opening a plurality of holes for contacting the gate extraction electrodes each having an opening width smaller than the opening for extracting the source / base on the gate electrode extraction pad; and below the openings for extracting the source / base. Forming a trench for source / base contact to a depth reaching the base region at a portion, and forming a trench for contacting the gate lead-out electrode on the pad for pulling out the gate electrode at a lower portion of the hole for contacting the gate lead-out electrode. A step of forming a metal layer on the entire surface of the substrate and burying a metal in the source / base contact trench and the gate lead-out electrode contact trench, and performing a required patterning to connect to the source / base contact trench. Source-based power And a method of manufacturing a semiconductor device characterized by comprising a step of forming a gate electrode connected to the gate extraction electrode contact trenches. 4. The method for manufacturing a semiconductor device according to claim 3, wherein when forming the source / base contact trench and the gate lead electrode contact trench, Br is formed.
A method of manufacturing a semiconductor device, characterized by performing reactive ion etching using as an etchant. 5. A first conductivity type semiconductor including a drain region.
A substrate and a semiconductor layer of the second conductivity type formed on the surface layer of the semiconductor substrate.
A base region composed of a body layer and a saw of the first conductivity type formed on a surface layer portion of the base region.
And source region, to a depth which penetrates the base region in said source region
Formed on the inner surfaces of the plurality of formed gate electrode trenches and the plurality of gate electrode trenches, respectively.
Formed inside the gate insulating film and each of the plurality of gate electrode trenches.
Formed in the gate lead-out region, connected to the formed gate electrode and the gate electrode.
Between the gate electrode lead-out wiring and the plurality of gate electrode trenches.
A gate opening is formed and
A hose for contacting the gate extraction electrode is formed on the exposed region.
Of the interlayer insulating film with the opening of the source and the source / base opening below the source insulating film.
Saw formed from the base region to the base region
The base and base contact trench and the gate electrode contact hole below the gate.
Gate lead-out electrode formed on the gate electrode lead-out wiring
Pole contact trench, source / base extraction opening and source / base
It is formed in the contact trench and covers the source region and
And a source electrode connected to the base region, and a hole and a gate for contacting the gate extraction electrode.
Formed in the trench for the extraction electrode contact,
Gate extraction connected to the gate electrode extraction wiring
A semiconductor device comprising an electrode . 6. The semiconductor device according to claim 5 , wherein the trench for the gate lead electrode contact is
Opening width is smaller than each source / base opening
A semiconductor device characterized in that 7. The semiconductor according to claim 5 or 6.
In the body device, the trench for the gate extraction electrode contact is
A semi-conductor characterized by an opening area of 100 μm or more
Body device. 8. The semiconductor according to claim 5,
In the body device, the plurality of gate lead electrode contact trenches are
That it is formed within the range of about 100 to 6000
Characteristic semiconductor device. 9. The semiconductor device according to claim 5,
In the body device, the source electrode and the gate extraction electrode are metal wirings.
A semiconductor device comprising: 10. The half according to any one of claims 5 to 9.
In the conductor device, the gate lead-out wiring is made of polysilicon.
A semiconductor device characterized by: