JP2000183343A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To fully secure a contact region between a source/base electrode and a source region/base region and the contact region between a gate electrode and a gate electrode contact pad thinning a pattern in a semiconductor device having a trench gate. SOLUTION: A U-MOS is provided with source/base electrodes 10 which are buried in source/base contact trenches formed in depth reaching a base region 12 in plural first opening part for source/base pull-out on a source region 11 and at the respective lower parts and which are connected to the source region and the base region, and gate electrodes 16 which are buried in gate pull-out electrode contact trenches formed in gate electrode pull-out pads 8a, which are formed of doped polysilicon in plural second opening parts for gate pull-out electrode contact on a gate pull-out region and respective lower parts and which are connected to the gate electrode lead-out pads.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a gate contact of a MOSFET (insulated gate type field effect transistor) or an IGBT (insulated gate type bipolar transistor) having a side wall of a trench as a channel region. And a method of forming the same, for example, used for a power device.

[0002]

2. Description of the Related Art As a kind of power device, a trench M having a side wall of a trench as a channel region is formed on a semiconductor substrate.
A semiconductor device having a large number of OSFETs arranged side by side (hereinafter referred to as U-MO
S) or a semiconductor device in which a number of trench IGBTs are juxtaposed on a semiconductor substrate (hereinafter referred to as U-IGBT)
It has been known.

FIGS. 6A to 6C show a conventional U-MO.
4 schematically shows a manufacturing process of S. FIG. 7A shows FIG.
FIG. 7B schematically illustrates a cross-sectional structure along the line AA ′ in FIG. 6C, and FIG. 7B schematically illustrates a cross-sectional structure along the line B′-B in FIG. 6C. ing.

FIGS. 6A to 6C and FIG.
An outline of a conventional U-MOS manufacturing process will be described with reference to FIGS.

First, a silicon substrate (drain region) 13
The base region 12 is formed on the surface layer of the base region 12 based on the source pattern 1 and the base pattern 2 as shown in FIG. 6A, and the source region 11 is formed on the surface layer of the base region 12.

Next, in the source region 11, FIG.
A number of trenches having a lattice pattern 3 as shown in FIG. 3B are formed to a depth penetrating the base region 12 and reaching the drain region 13.

At this time, the lattice-shaped trench is not formed in a part of the source region 11 in order to form a gate electrode lead portion described later in a part of the source region 11. That is, a part of the lattice pattern of the trench is missing.

Thereafter, a gate insulating film (for example, SiO ₂ film) 9 is formed on the surface of the substrate including the inner wall surface of the trench.

Next, in order to form a gate electrode, polysilicon 8 doped with an impurity is buried in the trench and deposited over the entire surface of the substrate (on the gate insulating film 9).

Thereafter, the doped polysilicon 8 is patterned based on the trench / gate leading pattern 4 as shown in FIG. 6 (c), and a gate electrode is led to a missing portion of the lattice pattern of the trench. Wide pad 8a for contacting the gate electrode and a connection pattern for connecting this to the gate electrode in the trench are left.

Next, after an interlayer insulating film 15 is deposited on the entire surface of the substrate, the pad 8a for the gate electrode contact is formed.
A large contact hole for extracting a gate electrode is opened in the interlayer insulating film 15, and an opening for extracting a source / base is formed in the interlayer insulating film around the opening of the trench and the gate insulating film on the surface of the substrate therebelow. To form

Next, a metal wiring layer (for example, an aluminum wiring layer) is formed on the entire surface of the substrate by a sputtering method, and a required patterning is performed to form a source / base electrode 10 and a gate electrode 16. Further, a drain electrode (not shown) is formed on the back surface of the substrate.

In recent years, the power U-MOS has been required from the market for further miniaturization, energy saving, and cost reduction. For example, the stripe pattern of the source region and its pitch are each about 0.8 μm, and the gate trench is not used. It is necessary to reduce the width to about 0.35 μm.

However, with such miniaturization, the contact area between the source / base electrode 10 and the base region 12 / source region 11 on the bottom surface of the source / base lead-out opening in the gate insulating film becomes insufficient. There is a possibility that the contact resistance of the contact portion becomes high.

When the U-MOS is used, usually, the source S and the back gate region (base region B) are grounded, and a voltage of, for example, 20 to 500 V is applied to the drain D. Power device, for example, 5 to drain D like U-IGBT
The above-described problem also occurs in a device used by applying a voltage of 00 V or more.

[0016]

As described above, in the conventional U-MOS and U-IGBT, the contact area between the source / base electrode and the base region / source region becomes insufficient due to the miniaturization of the pattern. There is a problem that the contact resistance of the contact portion is increased.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is intended to solve the problem of insufficient contact area between a source / base electrode and a source / base region due to miniaturization of a pattern in a U-MOS or U-IGBT. Can be resolved, and
An object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which can ensure a sufficient contact area between a gate electrode and a pad for gate electrode contact.

[0018]

According to the present invention, there is provided a semiconductor device comprising:
A first conductivity type silicon substrate serving as a drain region of the MOS transistor; and a second conductivity type semiconductor layer formed on a surface layer of the silicon substrate and opposite to the first conductivity type. A base region serving as a gate region, a first conductivity type source region formed in a surface layer of the base region, a gate electrode trench formed in the source region to a depth penetrating the base region, A gate insulating film formed on an inner wall surface and a peripheral surface of the opening of the gate electrode trench and on a substrate surface of the gate lead-out region; a buried gate electrode buried in the gate electrode trench; A gate formed of doped polysilicon connected to an electrode and formed on a gate insulating film in the gate lead-out region A pole-leading pad and a source / base lead-out opening on an intermediate portion between the trenches which are deposited on the substrate including the gate insulating film and the gate electrode leading-out pad and are present in the source region. And an interlayer insulating film in which a plurality of gate lead-out electrode contact holes are formed on the internal region of the gate lead-out region, and a lower part of each of the plurality of source / base lead-out openings. A source formed to a depth reaching the base region;
A base contact trench, a gate lead electrode contact trench formed in the gate electrode lead pad below each of the plurality of gate electrode contact holes, and a part of the interlayer insulating film and connected thereto And a source connected to a source region and a base region in an intermediate portion between trenches existing in the source region, the openings being formed in the plurality of source / base extraction openings and the source / base contact trench. A base electrode, formed in the plurality of holes for the gate extraction electrode contact and in the trench for the gate extraction electrode contact so as to be connected to a part of the interlayer insulating film and connected thereto, and connected to the gate electrode extraction pad; And a gate extraction electrode.

Further, a method of manufacturing a semiconductor device according to the present invention
Forming a base region of a second conductivity type opposite to the first conductivity type in a surface layer portion of a silicon substrate of the first conductivity type, and forming a source region of the first conductivity type in a surface layer portion of the base region; Forming a gate electrode trench having a buried gate pattern in the source region to a depth penetrating the base region, and then forming a gate insulating film on a substrate surface including an inner wall surface of the trench; A gate insulating film in the gate lead-out region by depositing doped polysilicon on the entire upper surface and burying the doped polysilicon for the gate electrode in the trench for the gate electrode, and patterning the doped polysilicon on the substrate; Forming a gate electrode lead-out pad thereon; and
Depositing an interlayer insulating film on the entire surface of the substrate, and opening the source / base with respect to the interlayer insulating film in an intermediate portion between the trenches for the gate electrodes existing in the source region. Forming a portion and opening a plurality of gate lead-out electrode contact holes, each having a smaller opening width than the source / base lead-out opening, on the gate electrode lead-out pad; A source / base contact trench is formed at a depth below the base opening to reach the base region, and a gate lead electrode contact is formed in the gate electrode lead pad below the gate lead electrode contact hole. Forming a trench for forming, and forming a metal layer on the entire surface of the substrate. Burying a metal on the source base contact trenches and the gate lead-out electrode contact trenches, performs a required patterning,
Forming a source / base electrode connected to the source / base contact trench and a gate electrode connected to the gate lead electrode contact trench.

[0020]

Embodiments of the present invention will be described below in detail with reference to the drawings.

First, the outline of the present invention will be described.

FIG. 2 shows a U-MOS miniaturization method.
As shown in (b), the source region 11 of the substrate surface layer (base region 12 surface layer) at the center of the bottom surface of the source / base lead-out opening formed in the interlayer insulating film 15 is formed as follows:
A contact trench is formed deeper than the source region 11, and a part of the source / base electrode 10 is buried in the contact trench via the gate insulating film 9.

With such a structure, the source region 11.
The contact area between the base region 12 and the source / base electrode 10 is increased, and the contact resistance of the contact portion is reduced.

On the other hand, when forming the contact trench, if the source region 11 and the base region 12 are etched by, for example, RIE (reactive ion etching),
At the same time, the portion of the gate electrode contact pad 8a corresponding to the bottom surface of the gate electrode lead-out contact hole opened in the interlayer insulating film 15 thereon is also etched. In this case, the etching rate of the doped polysilicon of the pad 8a for the gate electrode contact is higher than that of the silicon of the source region 11 and the base region 12.

Now, the thickness of the interlayer insulating film 15 is, for example, 1.
The thickness of the gate electrode contact pad 8a is, for example, about 0.5, the depth of the source region 11 is, for example, about 0.3 to 0.5 μm, and the depth of the base region 12 is, for example, about 0.7 μm. It is assumed that when the opening width of the source / base lead-out opening is 0.8 μm, etching is performed so that the depth of the contact trench is, for example, about 0.5 μm.

At this time, the thickness of the gate electrode contact pad 8a which is simultaneously etched (about 0.5 μm)
It is assumed that the sum of the thickness of the gate insulating film 9 and the thickness of the gate insulating film 9 on the underlying substrate surface is equal to or smaller than the depth of the contact trench due to process variations.

In this case, the bottom surface of the contact hole for pulling out the gate is connected to the base region 12 below the pad 8a.
Of the gate electrode 16 in a later step.
Is formed, a problem arises that the gate electrode 16 and the base region 12 are short-circuited through the contact hole.

If, for example, Br is used as an RIE etchant when forming the contact trench, it is necessary to consider that a microloading effect is present on the gate electrode contact pad 8a which is simultaneously etched.

In the micro-loading effect, the etching rate of polysilicon (the material of the pad 8a) is reduced by the gate extraction of the interlayer insulating film 15 above the pad, as shown in FIG. 3, for example, in RIE using a predetermined etchant. In the case of a circular hole (in the case of a circular hole, it depends on the radius).

From the characteristics shown in FIG. 3, it is understood that the etching rate of the doped polysilicon 8a increases as the opening width of the etching mask increases. Therefore,
As described above, in order to prevent the bottom surface of the gate drawing contact hole from reaching the base region 12 below the pad 8a, it is desirable to reduce the opening width of the gate drawing contact hole.

However, if the opening width of the contact hole for drawing out the gate is simply reduced, the gate electrode
The contact area between the gate electrode and the pad 8a for contact with the gate electrode may be insufficient, and the contact resistance of the contact portion may be increased.

Incidentally, the opening width of the contact hole for drawing out the gate is 10 μm square (currently about 100 μm
(Smaller than □) as a result, it was confirmed that the contact resistance of the gate contact portion was increased, and that the threshold voltage of the U-MOS and the waveform of the output signal were adversely affected.

In view of this, a large number of gate lead-out contact holes having an opening width smaller than the source / base lead-out opening are provided, for example, in a matrix arrangement, and the entire opening area of the large number of gate lead-out contact holes is provided. Is set to, for example, 100 μm square or more.

<First Embodiment> FIGS. 1A to 1D show the first embodiment.
1 schematically illustrates a manufacturing process of a U-MOS according to a first embodiment of the present invention.

FIG. 2A schematically shows a cross-sectional structure along the line AA ′ in FIG. 1D, and FIG. 2B shows a cross-sectional structure along the line B′- in FIG. 3 schematically shows a cross-sectional structure along the line B.

Hereinafter, FIGS. 1A to 1D and FIG.
UM according to the first embodiment with reference to (a) and (b)
The manufacturing process of the OS will be described.

First, for example, as shown in FIG. 1 on the surface layer portion of an n-type semiconductor
After a p-type base region (back gate region) 12 is formed on the basis of the base pattern 2 and the source pattern 1 as shown in (a), an n-type source region is formed in a surface layer of an inner region of the base region 12. 11 is formed.

Next, a plurality of gate trenches having a lattice pattern 3 as shown in FIG. 1B are formed in the source region 11 through the base region 12 and in the drain region 13. Formed to a depth that reaches.

At this time, the lattice-shaped trench is not formed in a part of the source region 11 in order to form a gate electrode lead-out part described later in a part of the source region 11. That is, a part of the lattice pattern is missing (a missing portion of the gate trench pattern is indicated by 3a).
It has become.

Thereafter, a gate insulating film (for example, SiO ₂ film) 9 is formed on the substrate surface including the inner wall surface of the trench.

Next, in order to form a gate electrode, polysilicon 8 doped with an impurity is buried in the trench and deposited on the entire surface of the substrate (on the gate insulating film 9).

Thereafter, the doped polysilicon 8 is patterned based on the trench / gate lead-out pattern 4 as shown in FIG. 1 (c), and a gate electrode is drawn out to the notch 3a of the gate trench pattern. Wide pad 8a for the gate electrode contact and a connection pattern for connecting the same to the gate electrode in the trench are left.

Next, a CVD insulating film 15 is deposited as an interlayer insulating film on the entire surface of the substrate by, for example, a CVD method. Thereafter, as shown in FIG. 1D, a large number of small-diameter contact holes 15b for extracting gate electrodes are formed in the interlayer insulating film 15 on the pad 8a for gate electrode contact, for example, in a matrix, and the source region is formed. An opening (not shown in FIG. 1 (d)) for leading out a source and a base is formed in the interlayer insulating film 15 around the opening of the trench existing in the gate insulating film 11 and the gate insulating film 9 on the lower surface of the substrate. Form.

In this case, the opening width b of each gate lead-out hole is formed smaller than the opening width a of each source / base lead-out opening, and the gate lead-out hole is formed in a range of about 100 to 6,000. The opening area of the entire gate lead-out hole is, for example, 100 μm.
It should be formed so as to be not less than m □.

Here, for example, a = 0.8 μm □, b =
If it is 0.5 μm square, about 200 holes for drawing out the gate will be provided.

Next, by RIE using, for example, Br as an etchant, as shown in FIG.
A contact trench is formed deeper than the source region 11 in the source region 11 of the substrate surface layer (base region 12 surface layer) at the center of the bottom surface of the base lead-out opening. At the same time, a portion of the gate electrode contact pad 8a corresponding to the bottom surface of the gate electrode lead-out hole is also etched.

In this case, the source region 11 and the base region 1
Pad 8 for gate electrode contact than silicon 2
The doped polysilicon a has a higher etching rate.

Now, if the thickness of the interlayer insulating film 15 is, for example, 1.
The thickness of the gate electrode contact pad 8a is, for example, about 0.5, the depth of the source region 11 is, for example, about 0.3 to 0.5 μm, and the depth of the base region 12 is, for example, about 0.7 μm. In the case where the opening width a of the source / base lead-out opening is 0.8 μm square, etching is performed so that the depth of the contact trench is, for example, about 0.5 μm.

At this time, the thickness of the gate electrode contact pad 8a which is simultaneously etched (about 0.5 μm)
It is assumed that the sum of the thickness of the gate insulating film 9 and the thickness of the gate insulating film 9 on the underlying substrate surface is equal to the depth of the contact trench.

In this case, the doped polysilicon of the gate electrode contact pad 8a to be etched includes:
For example, the opening width b of the gate lead-out hole is formed small as described above in consideration of the micro-loading effect such as the characteristic shown in FIG. The hole formed in 8a is prevented from reaching the base region 12 below.

Next, a metal wiring layer (for example, an aluminum wiring layer) is formed on the entire surface of the substrate by sputtering, and the required patterning is performed to form the source / base electrode 10 and the gate electrode 16. Further, a drain electrode (not shown) is formed on the back surface of the substrate.

At this time, the source trench is formed in the contact trench.
Part of the base electrode 10 is buried, and part of the gate electrode 16 is buried in the hole formed in the pad 8a. However, the gate electrode 16 and the base region 12 are not short-circuited.

FIG. 4 shows an equivalent circuit of a U-MOS having the structure shown in FIGS. 2A and 2B.

As shown in this equivalent circuit, the source (S)
In addition to an n-channel MOS transistor having a region 11, a back gate (BG) region 12, a drain (D) region 13, and a gate (G) electrode 16, the drain region 1
3. The source region 11 corresponds to the collector C and the emitter E
And the parasitic np in which the base region 12 becomes the base B
There are n transistors.

That is, the U-MOS having the structure shown in FIGS. 2A and 2B is formed on a first conductivity type silicon substrate serving as a drain region of a MOS transistor and a surface layer portion of the silicon substrate. A base region comprising a semiconductor layer of a second conductivity type opposite to the first conductivity type and serving as a back gate region of the MOS transistor; and a source region of a first conductivity type formed in a surface portion of the base region. A gate electrode trench formed in the source region to a depth penetrating the base region; a gate formed on an inner wall surface and a peripheral surface of the opening of the gate electrode trench; and a gate formed on the substrate surface of the gate lead-out region. An insulating film, a buried gate electrode buried inside the gate electrode trench, and a continuation of the buried gate electrode; A gate electrode lead-out pad made of doped polysilicon formed on the gate insulating film, and a gate electrode lead-out pad deposited on the substrate including the gate insulating film and the gate electrode lead-out pad and present in the source region. An interlayer insulating film in which an opening for source / base extraction is formed on an intermediate portion between the trenches, and a plurality of holes for gate extraction electrode contacts are opened on an inner region of the gate extraction region; A source / base contact trench formed at a depth reaching the base region below each of the plurality of source / base lead-out openings, and a plurality of gate electrode contact holes under each of the plurality of openings. A gate extraction electrode contact trench formed in the gate electrode extraction pad; Wherein the plurality of sources so as to be continuous and on its part of the interlayer insulating film,
A source / base electrode formed in an opening for extracting a base and a trench for source / base contact, connected to a source region and a base region in an intermediate portion between trenches existing in the source region, and A gate formed on a part of the insulating film and connected to the plurality of holes for the gate extraction electrode contact and the trench for the gate extraction electrode contact so as to be continuous with the gate, and connected to the polysilicon for the electrode on the gate electrode extraction pad And a lead electrode.

Further, the manufacturing process of the U-MOS of the first embodiment includes the step of forming the first conductive type silicon substrate on the surface layer portion thereof.
Forming a base region of a second conductivity type opposite to the conductivity type, forming a source region of the first conductivity type in a surface layer of the base region, and having a buried gate pattern in the source region Forming a gate electrode trench to a depth penetrating the base region, forming a gate insulating film on the surface of the substrate including the inner wall surface of the trench, depositing doped polysilicon over the entire surface of the substrate, and forming the gate electrode; Forming a gate electrode leading pad on the gate insulating film in the gate leading region by burying doped polysilicon for a gate electrode in the inside of the trench for patterning and patterning the doped polysilicon on the substrate; Depositing an interlayer insulating film on the entire surface of the substrate, and forming each of the gates present in the source region on the interlayer insulating film. A plurality of openings for forming a source and a base are respectively formed on an intermediate portion between the trenches for the gate electrode, and a plurality of openings each having a smaller opening width than the opening for drawing the source and the base are provided on the gate electrode leading pad. Forming a source / base contact trench at a depth reaching the base region below the source / base lead contact hole, and forming the gate lead electrode. Forming a gate extraction electrode contact trench in the gate electrode extraction pad below the contact hole;
Next, a metal layer is formed on the entire surface of the substrate, and a metal is buried in the trench for the source / base contact and the trench for the gate lead-out electrode contact. Forming a gate electrode connected to the base electrode and the trench for contacting the gate lead-out electrode.

According to the U-MOS of the first embodiment, the contact trench structure increases the contact area between the source / base electrode 10 and the source region 11 / base region 12, and reduces the contact resistance of the contact portion. It becomes possible to do.

Although the opening width of each of the gate drawing holes is reduced, a large contact area between the gate electrode 16 and the gate electrode contact pad 8a is ensured by forming a large number of gate drawing holes. Therefore, the contact resistance of the contact portion can be reduced.

In the above embodiment, for example, a U-type semiconductor device having a stripe-shaped source pattern as shown in FIG.
Although an example in which the present invention is applied assuming a MOS has been described, the present invention is not limited to a stripe-shaped source pattern. For example, FIG.
The present invention can also be applied to a U-MOS having an offset mesh source pattern as shown in FIG.

In the above embodiment, the n-channel U-type
Although the MOS has been described, an effect similar to that of the above-described embodiment can be obtained by manufacturing an n-channel U-IGBT according to the above-described embodiment. In this case, when the source pattern of the U-IGBT is miniaturized to, for example, about 2 μm,
The drain region and the source region correspond to the collector and the emitter, respectively, and the base-emitter resistance distance of the parasitic npn transistor whose base region is the base is shortened.
The base-emitter resistance rbb is reduced, and the parasitic np
It is possible to increase the latch-up current of the n-channel MOS transistor caused by the n transistor.

[0061]

As described above, according to the semiconductor device of the present invention and the method of manufacturing the same, according to the semiconductor device having a trench gate, such as a U-MOS or a U-IGBT, the source / base electrode and the source associated with the miniaturization of the pattern The shortage of the contact area between the region and the base region can be solved, and the shortage of the contact area between the gate electrode and the gate electrode contact pad can be solved.

[Brief description of the drawings]

FIG. 1 is a view schematically showing a manufacturing process of a U-MOS according to a first embodiment of the present invention.

FIG. 2 is a diagram schematically showing a cross-sectional structure along line AA ′ and line B′-B in FIG. 1 (c).

FIG. 3 is a view for explaining a micro-loading effect in which an etching rate changes depending on an opening width of a contact hole in an upper interlayer insulating film during RIE of polysilicon in a manufacturing process of a U-MOS of the first embodiment. FIG.

FIG. 4 is a diagram showing an equivalent circuit of a U-MOS having the structure of FIG. 2;

FIG. 5 is a diagram showing different examples of source patterns in the U-MOS of the present invention.

FIG. 6 is a view schematically showing a manufacturing process of a conventional U-MOS.

FIG. 7 is a diagram schematically showing a cross-sectional structure along the line AA ′ and the line B′-B in FIG. 6 (c).

[Explanation of symbols]

 Reference Signs List 8: doped polysilicon, 8a: gate electrode pad, 9: gate insulating film, 10: source / base electrode, 11: n-type source region, 12: p-type base region, 13: n-type silicon substrate ( Drain region), 15: interlayer insulating film, 16: gate electrode.

Claims (4)

[Claims] A first conductivity type silicon substrate serving as a drain region of a MOS transistor; and a second conductivity type semiconductor layer formed on a surface layer of the silicon substrate and opposite to the first conductivity type. A base region serving as a back gate region of the MOS transistor; a first conductivity type source region formed in a surface layer of the base region; and a gate electrode formed in the source region to a depth penetrating the base region. A trench, a gate insulating film formed on a substrate surface of an inner wall surface and an opening peripheral portion of the gate electrode trench, and a substrate surface of the gate lead-out region, and a buried gate electrode embedded in the gate electrode trench. And a doped polysilicon formed on the gate insulating film in the gate lead-out region following the buried gate electrode. A gate electrode lead-out pad formed on the gate insulating film and a substrate including the gate electrode lead-out pad, and on an intermediate portion between the gate electrode trenches existing in the source region, respectively. An interlayer insulating film in which an opening for extracting a source and a base is formed and a plurality of holes for contacting a gate extraction electrode are formed in an inner region of the gate extraction region; and an opening for extracting the plurality of sources and bases A source / base contact trench formed at a depth reaching the base region at a lower portion of each of the portions, and a gate electrode leading pad formed at a lower portion of each of the plurality of gate electrode contact holes. Gate extraction electrode contact trench, a part of the interlayer insulating film and the same Are formed in the plurality of source / base extraction openings and source / base contact trenches so as to be connected to the source and base regions at an intermediate portion between the trenches existing in the source region. A plurality of holes for the gate extraction electrode contact and a plurality of the gate extraction electrode contact trenches so as to be connected to and partially connected to the interlayer insulating film, and are connected to the gate electrode extraction pad. A semiconductor device, comprising: 2. The semiconductor device according to claim 1, wherein each of the trenches for the gate lead-out electrode contacts has a smaller opening width than each of the openings for the source / base lead-out, and the plurality of trenches for the gate lead-out electrode contacts. Is formed in the range of about 100 to 6000 semiconductor devices. Forming a base region of a second conductivity type opposite to the first conductivity type on a surface portion of a silicon substrate of the first conductivity type; and forming a base region of the first conductivity type on a surface portion of the base region. Forming a source region; forming a gate electrode trench having a buried gate pattern in the source region to a depth penetrating the base region; and forming a gate insulating film on the substrate surface including the inner wall surface of the trench. Depositing doped polysilicon over the entire surface of the substrate, filling the doped polysilicon for the gate electrode inside the trench for the gate electrode, patterning the doped polysilicon on the substrate, and drawing out the gate. Forming a gate electrode lead-out pad on a gate insulating film in a region; depositing an interlayer insulating film on the entire surface of the substrate; The interlayer insulating film, to form a respective on an intermediate opening for the source base lead between the trenches cross for each gate electrode present in said source region,
Opening a plurality of gate lead-out electrode contact holes each having a smaller opening width than the source / base lead-out opening on the gate electrode lead-out pad; and below the source / base lead-out opening. Forming a trench for a source / base contact at a depth reaching the base region at a portion, and forming a trench for a gate extraction electrode contact on the gate electrode extraction pad below the hole for the gate extraction electrode contact. Forming a metal layer on the entire surface of the substrate and embedding a metal in the source / base contact trench and the gate extraction electrode contact trench; performing a required patterning to connect to the source / base contact trench Source-based power And a method of manufacturing a semiconductor device characterized by comprising a step of forming a gate electrode connected to the gate extraction electrode contact trenches. 4. The method of manufacturing a semiconductor device according to claim 3, wherein when forming the trench for the source / base contact and the trench for the gate extraction electrode contact, Br is used.
A method of manufacturing a semiconductor device, wherein the method is performed by reactive ion etching using as an etchant.