JP3490857B2 - Semiconductor device and method of manufacturing semiconductor device - Google Patents
Semiconductor device and method of manufacturing semiconductor deviceInfo
- Publication number
- JP3490857B2 JP3490857B2 JP31385196A JP31385196A JP3490857B2 JP 3490857 B2 JP3490857 B2 JP 3490857B2 JP 31385196 A JP31385196 A JP 31385196A JP 31385196 A JP31385196 A JP 31385196A JP 3490857 B2 JP3490857 B2 JP 3490857B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- groove
- semiconductor substrate
- trench
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 49
- 238000004519 manufacturing process Methods 0.000 title claims description 20
- 239000000758 substrate Substances 0.000 claims description 39
- 239000010410 layer Substances 0.000 claims description 26
- 239000002344 surface layer Substances 0.000 claims description 18
- 239000012535 impurity Substances 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 230000001590 oxidative effect Effects 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 239000004020 conductor Substances 0.000 claims description 3
- 238000009792 diffusion process Methods 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 1
- 238000009413 insulation Methods 0.000 claims 1
- 238000000034 method Methods 0.000 description 9
- 230000005684 electric field Effects 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 239000012141 concentrate Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体装置の製造方
法に関し、さらに詳しくいえば、トレンチ型の縦型パワ
ー半導体装置の製造方法の改善に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to improvement of a method of manufacturing a trench type vertical power semiconductor device.
【０００２】[0002]
【従来の技術】以下で従来例に係る半導体装置について
図面を参照しながら説明する。この半導体装置は、図７
に示すようなトレンチ型のパワーＭＯＳＦＥＴである。
これを形成するには、図６に示すようなウエハ、すなわ
ち基板１の面方位が（１００）であって、オリエンテー
ション・フラット面２の面方位が（１１０）であるよう
なウエハを用いる。2. Description of the Related Art A semiconductor device according to a conventional example will be described below with reference to the drawings. This semiconductor device is shown in FIG.
It is a trench type power MOSFET as shown in FIG.
To form this, a wafer as shown in FIG. 6, that is, a wafer in which the plane orientation of the substrate 1 is (100) and the orientation flat surface 2 is (110) is used.
【０００３】図７のパワーＭＯＳＦＥＴにおいては、Ｎ
+ 型の半導体基板１の表層にＮ- 型の共通ドレイン層２
がエピタキシャル成長法によって形成され、この共通ド
レイン層２の表層に、Ｐ+ 型の不純物が拡散されること
でチャネル層３が形成されている。またチャネル層３の
表層の一部には、Ｎ+ 型の不純物が拡散されることによ
りソース領域４が形成されており、これらを貫通するよ
うに溝（トレンチ）が設けられている。In the power MOSFET of FIG. 7, N
The N-type common drain layer 2 is formed on the surface layer of the + type semiconductor substrate 1.
Are formed by an epitaxial growth method, and the channel layer 3 is formed by diffusing P + type impurities in the surface layer of the common drain layer 2. A source region 4 is formed in a part of the surface layer of the channel layer 3 by diffusing N + type impurities, and a trench is provided so as to penetrate these.
【０００４】このトレンチは、側壁がオリエンテーショ
ン・フラット面２の面方位と一致するように形成されて
いるので、トレンチの側壁の面方位が（１１０）とな
り、トレンチの底面及び基板表面の面方位が（１００）
となっている。このトレンチの表層にはゲート絶縁膜５
が形成され、ゲート絶縁膜５上にはこのトレンチを充填
するようにポリシリコンゲート６が形成されている。Since the side wall of this trench is formed so as to coincide with the plane orientation of the orientation flat surface 2, the plane orientation of the side wall of the trench becomes (110), and the plane orientation of the bottom surface of the trench and the surface orientation of the substrate surface. (100)
Has become. A gate insulating film 5 is formed on the surface of this trench.
And a polysilicon gate 6 is formed on the gate insulating film 5 so as to fill this trench.
【０００５】上記のパワーＭＯＳＦＥＴを製造するにお
いては、トレンチを形成した後に熱酸化などで内壁及び
底面に酸化膜を成長させる事によってゲート絶縁膜５を
形成していた。In manufacturing the above-described power MOSFET, the gate insulating film 5 is formed by growing an oxide film on the inner wall and the bottom surface by thermal oxidation after forming the trench.
【０００６】[0006]
【発明が解決しようとする課題】上記の半導体装置によ
れば、図７に示すようにトレンチの側壁の面方位が（１
１０）となり、トレンチの底面及び基板表面の面方位が
（１００）となる。ゲート絶縁膜５を形成するには、上
述のようにトレンチを形成した後に、熱酸化によって酸
化膜をトレンチ内で成長させているが、酸化膜の形成工
程においては、面方位が（１００）の場合が成長速度が
最も遅く、次いで（１１１），（１１０）の順に速くな
るので、面方位が（１１０）であるトレンチの側壁での
酸化膜が、面方位が（１００）であるトレンチの底面及
び基板表面での酸化膜よりも速く成長して、トレンチ側
壁でのゲート絶縁膜の膜厚が厚くなる。According to the above semiconductor device, as shown in FIG. 7, the plane orientation of the side wall of the trench is (1
10), and the plane orientations of the bottom surface of the trench and the substrate surface are (100). To form the gate insulating film 5, after forming the trench as described above, an oxide film is grown in the trench by thermal oxidation. In the oxide film forming step, the plane orientation is (100). In this case, the growth rate is the slowest, and then increases in the order of (111) and (110). Therefore, the oxide film on the side wall of the trench whose plane orientation is (110) is the bottom surface of the trench whose plane orientation is (100). Also, the gate insulating film grows faster than the oxide film on the substrate surface and becomes thicker on the side wall of the trench.
【０００７】従って、トレンチ側壁の酸化膜を閾値電圧
コントロールのために、所定の膜厚に設定すると、トレ
ンチ底部の膜厚が薄くなり、絶縁耐量の低下が生じる。
また、トレンチの開口側の角部ＫＢに電界が集中するこ
とにより、この角部ＫＢにおいてゲート絶縁膜が破壊し
てしまうなどという問題が生じる。このような問題を改
善するために、基板面の面方位とトレンチ側壁の面方位
とを同じ（１００）にして、側壁と底面での成長速度を
同じにして、トレンチ溝内に均一な酸化膜を形成すると
いう試みがなされていた（特開平２−４６７１６）。こ
の方法によると、トレンチの側壁で成長する酸化膜と、
底面で成長する酸化膜の膜厚を均一にすることで、トレ
ンチ底部での絶縁耐量低下を防止できるが、トレンチ開
口側の角部での絶縁破壊を防止するという点では、まだ
十分ではなかった。Therefore, if the oxide film on the side wall of the trench is set to have a predetermined film thickness for controlling the threshold voltage, the film thickness at the bottom of the trench becomes thin and the dielectric strength is lowered.
Further, the electric field is concentrated on the corner portion KB on the opening side of the trench, which causes a problem that the gate insulating film is broken at the corner portion KB. In order to improve such a problem, the plane orientation of the substrate surface and the plane orientation of the trench side wall are set to the same (100), the growth rates on the side wall and the bottom surface are made the same, and a uniform oxide film is formed in the trench groove. Attempts have been made to form a film (Japanese Patent Laid-Open No. 2-46716). According to this method, an oxide film grown on the sidewall of the trench,
By making the thickness of the oxide film that grows on the bottom uniform, it is possible to prevent a decrease in the dielectric strength at the bottom of the trench, but it was still insufficient in terms of preventing dielectric breakdown at the corner on the trench opening side. .
【０００８】[0008]
【課題を解決するための手段】本発明は上記従来の欠点
に鑑み成されたもので、図１に示すように、基板面及び
オリエンテーション・フラット面の面方位がともに（１
００）である一導電型の半導体基板と、前記半導体基板
の表層に形成された一導電型のドレイン領域と、前記ド
レイン領域の表層に設けられた逆導電型のチャネル領域
と、前記チャネル領域と前記ドレイン領域とを貫通する
ように設けられ、側壁の面方位が前記オリエンテーショ
ン・フラット面と一致し、かつ角部が切除され、切除後
に露出する面の面方位が（１１０）となる溝と、前記溝
の内壁及び前記角部を被覆するように設けられたゲート
絶縁膜と、前記ゲート絶縁膜上に設けられ、前記溝を充
填するように形成されたゲート電極と、前記溝の近傍に
設けられ、一導電型の不純物拡散層よりなるソース領域
とを有する事を特徴とする半導体装置や、基板表面の面
方位とオリエンテーション・フラット面の面方位とがと
もに（１００）面である一導電型の半導体基板の表層に
一導電型のドレイン領域層を形成し、前記ドレイン領域
層の表層に逆導電型のチャネル領域層を形成する工程
と、前記半導体基板の表面に第１の絶縁膜を形成し、前
記チャネル領域層に一導電型の不純物を注入・拡散して
ソース領域を形成する工程と、前記ソース領域近傍の領
域の前記第１の絶縁膜及び前記半導体基板を選択的にエ
ッチングして、側壁の面方位が前記オリエンテーション
・フラット面と一致するような溝を形成する工程と、前
記溝の開口の角部を選択的に除去し、除去された後に現
れる面の面方位を（１１０）とする工程と、前記溝の内
壁及び前記角部を酸化して、第２の絶縁膜を形成する工
程と、前記溝を充填し、かつ前記半導体基板全面を被覆
する導電体層を形成する工程と、前記導電体層をエッチ
ングにより除去し、前記溝内に残存させてゲート電極を
形成する工程とを有する事を特徴とする半導体装置の製
造方法により、上記課題を解決するものである。SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned drawbacks of the prior art. As shown in FIG. 1, the plane orientations of the substrate surface and the orientation flat surface are both (1
00), a semiconductor substrate of one conductivity type, a drain region of one conductivity type formed in a surface layer of the semiconductor substrate, a channel region of an opposite conductivity type provided in a surface layer of the drain region, and the channel region. A groove which is provided so as to penetrate the drain region, has a side wall whose surface orientation matches that of the orientation flat surface, and whose corners are cut off, and whose surface orientation exposed after cutting is (110). A gate insulating film provided so as to cover the inner wall and the corner of the groove, a gate electrode provided on the gate insulating film so as to fill the groove, and provided in the vicinity of the groove And a semiconductor device characterized by having a source region formed of an impurity diffusion layer of one conductivity type, and a plane orientation of a substrate surface and a plane orientation of an orientation flat surface are both (100) planes. Forming a drain region layer of one conductivity type on the surface layer of a semiconductor substrate of one conductivity type, and forming a channel region layer of the opposite conductivity type on the surface layer of the drain region layer; and forming a first region on the surface of the semiconductor substrate. Forming an insulating film, implanting and diffusing one conductivity type impurity in the channel region layer to form a source region, and selectively forming the first insulating film and the semiconductor substrate in a region near the source region. Etching to form a groove in which the plane orientation of the side wall coincides with the orientation flat surface, and the corner portion of the opening of the groove is selectively removed, and the plane orientation of the surface that appears after the removal (110), a step of oxidizing the inner wall and the corner of the groove to form a second insulating film, and a conductor layer filling the groove and covering the entire surface of the semiconductor substrate. And a step of forming Collector layer is removed by etching, by the method of manufacturing a semiconductor device, characterized in that a step of forming a gate electrode is left in the groove, it is to solve the above problems.
【０００９】[0009]
【発明の実施の形態】以下で、本発明の実施形態に係る
トレンチ構造のパワーＭＯＳＦＥＴについて図面を参照
しながら説明する。しかしながら本発明は以下の実施形
態に限るものではない。図１は本実施形態に係るパワー
ＭＯＳＦＥＴの構造を説明する断面図であり、図２は本
実施形態に係るパワーＭＯＳＦＥＴの製造に用いるウエ
ハを説明する図である。BEST MODE FOR CARRYING OUT THE INVENTION A power MOSFET having a trench structure according to an embodiment of the present invention will be described below with reference to the drawings. However, the present invention is not limited to the following embodiments. FIG. 1 is a cross-sectional view illustrating the structure of the power MOSFET according to this embodiment, and FIG. 2 is a view illustrating a wafer used for manufacturing the power MOSFET according to this embodiment.
【００１０】この半導体装置は、図２に示すようなウエ
ハ、すなわち基板１１の面方位が（１００）であって、
オリエンテーション・フラット面１０の面方位が（１０
０）であるようなウエハを用いて形成されている。この
パワーＭＯＳＦＥＴにおいては、図１に示すようにＮ+
型の半導体基板１１の表層にＮ- 型の共通ドレイン層１
２がエピタキシャル成長法によって形成され、この共通
ドレイン層１２の表層に、Ｐ+ 型の不純物が拡散される
ことでチャネル層１３が形成されている。In this semiconductor device, the wafer as shown in FIG. 2, that is, the substrate 11 has a plane orientation of (100),
The orientation of the orientation flat surface 10 is (10
0) is used to form the wafer. In this power MOSFET, as shown in FIG.
-Type common drain layer 1 on the surface layer of the n-type semiconductor substrate 11
2 is formed by an epitaxial growth method, and a channel layer 13 is formed in the surface layer of the common drain layer 12 by diffusing P + type impurities.
【００１１】またチャネル層１３の表層の一部には、Ｎ
+ 型の不純物が拡散されることによりソース領域１４が
形成されており、これらを貫通するようにトレンチ
（溝）が設けられている。トレンチの側壁の面方位は図
１に示すようにオリエンテーション・フラット面１０の
面方位と同じ（１００）である。さらに、トレンチの角
部ＫＢは切除されており、切除された後に現れる角部の
面（後述の切除面）の面方位は（１１０）になるように
設定されている。Further, N is formed on a part of the surface layer of the channel layer 13.
The source region 14 is formed by diffusing + type impurities, and a trench is provided so as to penetrate these. The plane orientation of the side wall of the trench is the same as that of the orientation flat surface 10 (100) as shown in FIG. Further, the corner portion KB of the trench is cut off, and the plane orientation of the surface of the corner portion (cutting surface described later) that appears after cutting is set to (110).
【００１２】そして、トレンチの表層にはゲート絶縁膜
１５が形成され、ゲート絶縁膜１５上にはこのトレンチ
を充填するようにポリシリコンゲート１６が形成されて
いる。ゲート絶縁膜１５は、図１に示すようにトレンチ
の側壁の膜厚と、底面の膜厚とがほぼ同じであって、ま
た、角部ＫＢでの膜厚はトレンチ及び底面の膜厚よりも
厚くなっている。どのようにしてこのようなゲート絶縁
膜が形成されるかについては後述の製造方法で詳述す
る。A gate insulating film 15 is formed on the surface layer of the trench, and a polysilicon gate 16 is formed on the gate insulating film 15 so as to fill the trench. As shown in FIG. 1, the gate insulating film 15 has substantially the same film thickness on the side wall of the trench and the film thickness on the bottom surface, and the film thickness at the corner portion KB is smaller than the film thickness on the trench and the bottom surface. It's getting thicker. How to form such a gate insulating film will be described in detail later in the manufacturing method.
【００１３】本実施形態に係る半導体装置によれば、図
１に示すように、トレンチの側壁の膜厚と、底面の膜厚
とがほぼ同じであるため、トレンチ底面の絶縁耐量低下
という問題を抑止する事が可能になる。また、角部が切
除されてなだらかになっているためこの部分で電界が集
中しにくくなっており、しかも角部でのゲート絶縁膜１
５の膜厚が他の領域よりも厚くなっているので、トレン
チの開口側の角部ＫＢに電界が集中することにより、こ
の角部ＫＢにおいてゲート絶縁膜が破壊してしまうなど
という問題を抑止する事が可能になる。According to the semiconductor device of this embodiment, as shown in FIG. 1, since the film thickness of the side wall of the trench and the film thickness of the bottom surface are almost the same, there is a problem that the dielectric strength of the bottom surface of the trench is lowered. It becomes possible to deter. Further, since the corners are cut off and are gentle, it is difficult for the electric field to concentrate in these parts, and the gate insulating film 1 at the corners is also formed.
Since the film thickness of 5 is thicker than other regions, it is possible to prevent the problem that the gate insulating film is broken at the corner portion KB of the opening side of the trench due to the concentration of the electric field. It becomes possible to do.
【００１４】以下で、上記半導体装置の製造方法につい
て図面を参照しながら説明する。図３〜図５は、本実施
形態に係るパワーＭＯＳＦＥＴの製造方法を説明する断
面図である。まず、基板として図２に示すように、基板
面の面方位とオリエンテーション・フラット面の面方位
がともに（１００）である半導体基板１１を用意する。A method of manufacturing the above semiconductor device will be described below with reference to the drawings. 3 to 5 are cross-sectional views illustrating the method for manufacturing the power MOSFET according to this embodiment. First, as shown in FIG. 2, as a substrate, a semiconductor substrate 11 in which the plane orientation of the substrate surface and the orientation of the orientation flat surface are both (100) is prepared.
【００１５】そして、図３に示すようにｎ+ 型のシリコ
ンからなるこの半導体基板１１の表層にｎ- 型のドレイ
ン層１２をエピタキシャル成長法で形成し、その表層に
ｐ+型のチャネル層１３を形成する。さらにそのチャネ
ル層１３上にシリコン酸化膜１６を形成し、Ｎ+ 型不純
物である例えば、砒素（Ａｓ）をドーズ量１×１０16ｃ
ｍ-2の条件でチャネル層の表層に選択的に注入・拡散し
て、ソース領域１４を形成する。その後、ソース領域１
４近傍のシリコン酸化膜１６及び半導体基板１１を選択
的にドライエッチングして幅１μｍ、深さ１．５〜３μ
ｍ、好ましくは２μｍ程度のトレンチ１７を形成する。Then, as shown in FIG. 3, an n-type drain layer 12 is formed on the surface layer of this semiconductor substrate 11 made of n + type silicon by an epitaxial growth method, and a p + type channel layer 13 is formed on the surface layer. Form. Further, a silicon oxide film 16 is formed on the channel layer 13 and an N + type impurity such as arsenic (As) is dosed at 1 × 10 16 c.
Source region 14 is formed by selectively injecting and diffusing into the surface layer of the channel layer under the condition of m-2. Then source area 1
The silicon oxide film 16 and the semiconductor substrate 11 near 4 are selectively dry-etched to have a width of 1 μm and a depth of 1.5-3 μm.
A trench 17 having a thickness of m, preferably about 2 μm is formed.
【００１６】次に、図４に示すようにトレンチ１７の開
口側の角部１８を、基板面と４５°の傾斜をなすように
エッチングして除去する。この除去された後の角部の面
（以下でこれを切除面１８と称する）の面方位は（１１
０）となる。その後図５に示すように全面を熱酸化し
て、トレンチ１７の内壁に膜厚５００Å程度のシリコン
酸化膜からなるゲート絶縁膜１５を形成する。Next, as shown in FIG. 4, the corner portion 18 on the opening side of the trench 17 is removed by etching so as to form an inclination of 45 ° with the substrate surface. The surface orientation of the corner surface (hereinafter referred to as the cut surface 18) after the removal is (11
0). Thereafter, as shown in FIG. 5, the entire surface is thermally oxidized to form a gate insulating film 15 made of a silicon oxide film with a film thickness of about 500 Å on the inner wall of the trench 17.
【００１７】この成長工程において、トレンチ１７の底
面の面方位と側壁の面方位は共に（１００）であるた
め、酸化膜の成長速度は等しくなり、トレンチ１７の底
面の膜厚と側壁の膜厚とは等しくなる。さらに、切除面
１８の面方位は上述の通り（１１０）となる。この面に
おける酸化膜の成長速度は、トレンチ１７の底面及び側
壁の酸化膜の成長速度よりも速いので、図５に示すよう
に切除面１８上で成長する酸化膜の膜厚をトレンチの底
面及び側壁の酸化膜の膜厚よりも厚くすることができ、
トレンチ１７の底面の膜厚と側壁の膜厚とが等しく、か
つ切除面１８での膜厚がこれらの膜厚よりも厚いゲート
絶縁膜１５を形成する事が可能になる。In this growth step, since the plane orientation of the bottom surface and the plane orientation of the side wall of the trench 17 are both (100), the growth rate of the oxide film becomes equal, and the film thickness of the bottom surface and the film thickness of the side wall of the trench 17 are equal. Is equal to. Further, the plane orientation of the cut surface 18 is (110) as described above. Since the growth rate of the oxide film on this surface is faster than the growth rate of the oxide film on the bottom surface and the side wall of the trench 17, the thickness of the oxide film grown on the cut surface 18 is set to the bottom surface of the trench and the trench film as shown in FIG. Can be made thicker than the thickness of the oxide film on the side wall,
It is possible to form the gate insulating film 15 in which the film thickness of the bottom surface and the film thickness of the side wall of the trench 17 are equal and the film thickness of the cut surface 18 is larger than these film thicknesses.
【００１８】その後、全面にポリシリコンを堆積してト
レンチ内を充填した後に、これをパターニングすること
により、図１に示すようなトレンチ型のパワーＭＯＳＦ
ＥＴを製造する事ができる。以上説明したように、本実
施形態に係る半導体装置の製造方法によれば、基板面の
面方位とオリエンテーション・フラット面１０の面方位
がともに（１００）である半導体基板１１を用意し、オ
リエンテーション・フラット面１０の面方位とトレンチ
１７の側壁の面方位をともに（１００）にしたのちに、
トレンチ１７の角部を除去して面方位が（１１０）とな
る切除面１８を形成し、酸化することでゲート絶縁膜１
５を形成しているので、トレンチ１７の底面の膜厚と側
壁の膜厚とが等しく、かつ切除面１８での膜厚がこれら
の膜厚よりも厚いゲート絶縁膜１５を形成する事がで
き、図１に示すような本実施形態に係る半導体装置を製
造することが可能になる。After that, polysilicon is deposited on the entire surface to fill the inside of the trench, and this is patterned to obtain a trench type power MOSF as shown in FIG.
Can manufacture ET. As described above, according to the method for manufacturing a semiconductor device of this embodiment, the semiconductor substrate 11 in which both the plane orientation of the substrate surface and the orientation flat surface 10 are (100) is prepared, and the orientation After setting both the plane orientation of the flat surface 10 and the plane orientation of the sidewall of the trench 17 to (100),
The gate insulating film 1 is formed by removing a corner portion of the trench 17 to form a cut surface 18 having a plane orientation of (110) and oxidizing the cut surface 18.
5 is formed, it is possible to form the gate insulating film 15 in which the film thickness of the bottom surface of the trench 17 is equal to the film thickness of the side wall and the film thickness of the cut surface 18 is larger than these film thicknesses. It becomes possible to manufacture the semiconductor device according to the present embodiment as shown in FIG.
【００１９】[0019]
【発明の効果】以上説明したように、本発明に係る半導
体装置によれば、トレンチの側壁の膜厚と、底面の膜厚
とがほぼ同じであるため、トレンチ底面の絶縁耐量低下
を抑止する事が可能になる。また、角部が切除されてな
だらかになっているためこの部分で電界が集中しにくく
なっており、しかも角部でのゲート絶縁膜の膜厚が他の
領域よりも厚くなっているので、トレンチの開口側の角
部に電界が集中することにより、ゲート絶縁膜が破壊し
てしまうなどという問題も抑止する事が可能になる。As described above, according to the semiconductor device of the present invention, since the film thickness of the side wall of the trench and the film thickness of the bottom surface are substantially the same, it is possible to suppress the decrease in the dielectric strength of the bottom surface of the trench. Things will be possible. Also, since the corners are cut off and are gentle, it is difficult for the electric field to concentrate in this part, and the gate insulating film at the corners is thicker than other regions, so the trench It is possible to prevent the problem that the gate insulating film is destroyed due to the concentration of the electric field in the corners on the opening side.
【００２０】また、本発明に係る半導体装置の製造方法
によれば、基板面の面方位とオリエンテーション・フラ
ット面の面方位がともに（１００）である半導体基板を
用意し、オリエンテーション・フラット面の面方位とト
レンチの側壁の面方位をともに（１００）にしたのち
に、トレンチの角部を除去して面方位が（１１０）とな
る切除面を形成し、酸化することでゲート絶縁膜を形成
しているので、トレンチの底面の膜厚と側壁の膜厚とが
等しく、かつ角部での膜厚がこれらの膜厚よりも厚いゲ
ート絶縁膜を形成する事ができ、上述の作用効果を奏す
る本発明に係る半導体装置を製造する事が可能になる。Further, according to the method of manufacturing a semiconductor device of the present invention, a semiconductor substrate having both the plane orientation of the substrate surface and the orientation flat surface of the orientation flat surface is prepared, and the orientation flat surface is prepared. After setting both the orientation and the plane orientation of the side wall of the trench to (100), the corner portion of the trench is removed to form a cut surface having a plane orientation of (110), and the gate insulating film is formed by oxidation. Therefore, it is possible to form a gate insulating film in which the film thickness of the bottom surface and the film thickness of the side wall of the trench are equal and the film thickness at the corners is thicker than these film thicknesses, and the above-mentioned effects are obtained. It is possible to manufacture the semiconductor device according to the present invention.
【図１】本発明の実施形態に係る半導体装置の構造を説
明する断面図である。FIG. 1 is a sectional view illustrating a structure of a semiconductor device according to an embodiment of the present invention.
【図２】本発明の実施形態に係る半導体装置の製造に用
いる半導体基板を説明する図である。FIG. 2 is a diagram illustrating a semiconductor substrate used for manufacturing a semiconductor device according to an embodiment of the present invention.
【図３】本発明の実施形態に係る半導体装置の製造方法
を説明する第１の断面図である。FIG. 3 is a first cross-sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the invention.
【図４】本発明の実施形態に係る半導体装置の製造方法
を説明する第２の断面図である。FIG. 4 is a second sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the invention.
【図５】本発明の実施形態に係る半導体装置の製造方法
を説明する第３の断面図である。FIG. 5 is a third cross-sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the invention.
【図６】従来例に係る半導体装置の製造に用いる半導体
基板を説明する図である。FIG. 6 is a diagram illustrating a semiconductor substrate used for manufacturing a semiconductor device according to a conventional example.
【図７】従来例に係る半導体装置の構造を説明する断面
図である。FIG. 7 is a cross-sectional view illustrating a structure of a semiconductor device according to a conventional example.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 東條 潤一郎 大阪府守口市京阪本通２丁目５番５号 三洋電機株式会社内 (72)発明者 斎藤 洋明 大阪府守口市京阪本通２丁目５番５号 三洋電機株式会社内 (72)発明者 福井 計 大阪府守口市京阪本通２丁目５番５号 三洋電機株式会社内 (56)参考文献 特開 平７−263692（ＪＰ，Ａ) 特開 平２−46716（ＪＰ，Ａ) 特開 平７−249769（ＪＰ，Ａ) 特開 昭59−8375（ＪＰ，Ａ) 特開 平５−109984（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 29/78 652 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Junichiro Tojo 2-5-5 Keihan Hondori, Moriguchi City, Osaka Prefecture Sanyo Electric Co., Ltd. (72) Inventor Hiroaki Saito 2-5 Keihan Hondori, Moriguchi City, Osaka Prefecture No. 5 Sanyo Electric Co., Ltd. (72) Inventor Kei Fukui 2-5-5 Keihan Hondori, Moriguchi City, Osaka Sanyo Electric Co., Ltd. (56) Reference JP-A-7-263692 (JP, A) Japanese Patent Application Laid-Open No. 2-46716 (JP, A) Japanese Patent Application Laid-Open No. 7-249769 (JP, A) Japanese Patent Application Laid-Open No. 59-8375 (JP, A) Japanese Patent Application Laid-Open No. 5-109984 (JP, A) (58) Fields investigated (Int .Cl. 7 , DB name) H01L 29/78 652
Claims (3)
ト面の面方位がともに（１００）である一導電型の半導
体基板と、 前記半導体基板の表層に形成された一導電型のドレイン
領域と、 前記ドレイン領域の表層に設けられた逆導電型のチャネ
ル領域と、 前記チャネル領域と前記ドレイン領域とを貫通するよう
に設けられ、側壁の面方位が前記オリエンテーション・
フラット面と一致し、かつ角部が切除され、切除後に露
出する面の面方位が（１１０）となる溝と、 前記溝の内壁及び前記角部を被覆するように設けられた
ゲート絶縁膜と、 前記ゲート絶縁膜上に設けられ、前記溝を充填するよう
に形成されたゲート電極と、 前記溝の近傍に設けられ、一導電型の不純物拡散層より
なるソース領域とを有する事を特徴とする半導体装置。1. A semiconductor substrate of one conductivity type in which the plane orientations of the substrate surface and the orientation flat surface are both (100), a drain region of one conductivity type formed in a surface layer of the semiconductor substrate, and the drain region. A channel region of the opposite conductivity type provided in the surface layer of, and a surface orientation of the side wall that is provided so as to penetrate the channel region and the drain region.
A groove that coincides with a flat surface and has a corner cut off, and a surface exposed after cutting has a plane orientation of (110); and a gate insulating film provided so as to cover the inner wall of the groove and the corner. A gate electrode formed on the gate insulating film so as to fill the groove, and a source region formed in the vicinity of the groove and formed of an impurity diffusion layer of one conductivity type, Semiconductor device.
り、 前記ゲート絶縁膜は、前記トレンチの内壁及び角部を酸
化して得られるシリコン酸化膜であることを特徴とする
請求項１記載の半導体装置。2. The semiconductor substrate according to claim 1, wherein the semiconductor substrate is a silicon substrate, and the gate insulating film is a silicon oxide film obtained by oxidizing an inner wall and a corner of the trench. apparatus.
・フラット面の面方位とがともに（１００）面である一
導電型の半導体基板の表層に一導電型のドレイン領域層
を形成し、前記ドレイン領域層の表層に逆導電型のチャ
ネル領域層を形成する工程と、 前記半導体基板の表面に第１の絶縁膜を形成し、前記チ
ャネル領域層に一導電型の不純物を注入・拡散してソー
ス領域を形成する工程と、 前記ソース領域近傍の領域の前記第１の絶縁膜及び前記
半導体基板を選択的にエッチングして、側壁の面方位が
前記オリエンテーション・フラット面と一致するような
溝を形成する工程と、 前記溝の開口の角部を選択的に除去し、除去された後に
現れる面の面方位を（１１０）とする工程と、 前記溝の内壁及び前記角部を酸化して、第２の絶縁膜を
形成する工程と、 前記溝を充填し、かつ前記半導体基板全面を被覆する導
電体層を形成する工程と、 前記導電体層をエッチングにより除去し、前記溝内に残
存させてゲート電極を形成する工程とを有する事を特徴
とする半導体装置の製造方法。3. A one-conductivity-type drain region layer is formed on a surface layer of a one-conductivity-type semiconductor substrate in which the plane direction of the substrate surface and the plane direction of the orientation flat surface are both (100) planes. Forming a channel region layer of opposite conductivity type on the surface layer of the layer; forming a first insulating film on the surface of the semiconductor substrate; and implanting and diffusing one conductivity type impurity into the channel region layer to form a source region. And a step of forming a groove in which the plane orientation of the side wall coincides with the orientation flat surface by selectively etching the first insulating film and the semiconductor substrate in a region near the source region. A step of selectively removing a corner portion of the opening of the groove and setting a plane orientation of a surface that appears after the removal to (110); oxidizing an inner wall of the groove and the corner portion; Insulation film And a step of forming a conductor layer that fills the groove and covers the entire surface of the semiconductor substrate, and removes the conductor layer by etching and leaves the groove in the groove to form a gate electrode. A method of manufacturing a semiconductor device, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31385196A JP3490857B2 (en) | 1996-11-25 | 1996-11-25 | Semiconductor device and method of manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31385196A JP3490857B2 (en) | 1996-11-25 | 1996-11-25 | Semiconductor device and method of manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH10154809A JPH10154809A (en) | 1998-06-09 |
| JP3490857B2 true JP3490857B2 (en) | 2004-01-26 |
Family
ID=18046277
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP31385196A Expired - Fee Related JP3490857B2 (en) | 1996-11-25 | 1996-11-25 | Semiconductor device and method of manufacturing semiconductor device |
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| Country | Link |
|---|---|
| JP (1) | JP3490857B2 (en) |
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|---|---|---|---|---|
| JP3715971B2 (en) | 2003-04-02 | 2005-11-16 | ローム株式会社 | Semiconductor device |
| JP5123622B2 (en) * | 2007-09-13 | 2013-01-23 | 株式会社日立製作所 | Semiconductor device and manufacturing method thereof |
| JP5879732B2 (en) * | 2011-04-18 | 2016-03-08 | 富士電機株式会社 | Trench insulated gate type semiconductor device |
| JP5806600B2 (en) | 2011-11-21 | 2015-11-10 | 住友電気工業株式会社 | Method for manufacturing silicon carbide semiconductor device |
| JP6235298B2 (en) * | 2013-10-21 | 2017-11-22 | 新日本無線株式会社 | Semiconductor device and manufacturing method thereof |
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1996
- 1996-11-25 JP JP31385196A patent/JP3490857B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH10154809A (en) | 1998-06-09 |
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