JP2002299618A - Semiconductor device and method for manufacturing it - Google Patents

Semiconductor device and method for manufacturing it

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Publication number
JP2002299618A
JP2002299618A JP2001208540A JP2001208540A JP2002299618A JP 2002299618 A JP2002299618 A JP 2002299618A JP 2001208540 A JP2001208540 A JP 2001208540A JP 2001208540 A JP2001208540 A JP 2001208540A JP 2002299618 A JP2002299618 A JP 2002299618A
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JP
Japan
Prior art keywords
semiconductor region
semiconductor
region
semiconductor device
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2001208540A
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Japanese (ja)
Other versions
JP3709814B2 (en
Inventor
Masahito Kigami
雅人 樹神
Tsutomu Uesugi
勉 上杉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toyota Central R&D Labs Inc
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Toyota Central R&D Labs Inc
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Priority to JP2001208540A priority Critical patent/JP3709814B2/en
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Publication of JP3709814B2 publication Critical patent/JP3709814B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform

Abstract

PROBLEM TO BE SOLVED: To lower the ON resistance of a vertical semiconductor device, to improve breakdown voltage and to lower the temperature dependency of ON resistance in addition. SOLUTION: This vertical semiconductor device 2 is obtained by laminating a first semiconductor region 10, a second semiconductor area 12, a third semiconductor region 16 and a fourth semiconductor region 18 from the side of the front surface of the device 2. The first semiconductor region 10 and the third semiconductor region 16 are the same conductive type. The second semiconductor region 12 is an opposite conductive type. At least a pair of trenches reaching the depth of the third semiconductor region 16 or the fourth semiconductor region 18 from the surface of the device 2 are formed. A conductor 20 is formed within the trenches. The impurity concentration of at least a part of the third semiconductor region 16 is higher than that of the second semiconductor region 12. Since the impurity concentration of the third semiconductor region 16 is high, the temperature dependency of ON resistance is suppressed sufficiently.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】 本発明は半導体装置に関す
る。特に、耐圧が高く、ＯＮ抵抗（半導体装置がＯＮし
た状態での抵抗をいう）が低い半導体装置を実現する技
術に関する。本発明はまたＯＮ抵抗の温度依存性が低い
半導体装置を実現する技術にも関する。[0001] The present invention relates to a semiconductor device. In particular, the present invention relates to a technique for realizing a semiconductor device having a high withstand voltage and a low ON resistance (meaning a resistance when the semiconductor device is ON). The present invention also relates to a technology for realizing a semiconductor device in which the ON resistance has low temperature dependency.

【０００２】[0002]

【従来の技術】 特開平７−７１４９号公報に縦型半導
体装置の原型が記載されている。この縦型半導体装置
は、半導体装置の表面側から、第１半導体領域（具体的
にはソース領域）、第２半導体領域（具体的にはボディ
領域またはベース領域）、第３半導体領域（具体的には
ドリフト領域）、第４半導体領域（具体的にはドレイン
領域）の順に積層されている。第１と第３半導体領域は
同じ導電型であり、第２半導体領域は反対の導電型であ
る。この結果縦方向にトランジスタが形成される。ま
た、半導体装置の表面から、第１半導体領域と第２半導
体領域を貫いて、第３半導体領域の深部または第４半導
体領域に達する少なくとも一対のトレンチが形成されて
いる。そのトレンチ内には導体が形成されている。その
導体がゲート電極となる。トレンチ内の導体（ゲート電
極）と、第１から第４半導体領域のそれぞれは絶縁層
（具体的には酸化層）で絶縁されている。この縦型半導
体装置は、トレンチ内導体（ゲート電極）に電圧が印加
されたときに第２半導体領域（ボディ領域）のうちのゲ
ート電極に向い合う部分にチャネルが形成されてＯＮす
る。2. Description of the Related Art Japanese Patent Application Laid-Open No. 7-7149 discloses a prototype of a vertical semiconductor device. This vertical semiconductor device includes a first semiconductor region (specifically, a source region), a second semiconductor region (specifically, a body region or a base region), and a third semiconductor region (specifically, from the surface side of the semiconductor device). , A drift region) and a fourth semiconductor region (specifically, a drain region). The first and third semiconductor regions are of the same conductivity type, and the second semiconductor region is of the opposite conductivity type. As a result, a transistor is formed in the vertical direction. At least one pair of trenches is formed from the surface of the semiconductor device, penetrating the first semiconductor region and the second semiconductor region, and reaching the deep portion of the third semiconductor region or the fourth semiconductor region. A conductor is formed in the trench. The conductor becomes a gate electrode. The conductor (gate electrode) in the trench and each of the first to fourth semiconductor regions are insulated by an insulating layer (specifically, an oxide layer). In this vertical semiconductor device, when a voltage is applied to the conductor in the trench (gate electrode), a channel is formed in a portion of the second semiconductor region (body region) facing the gate electrode, and the channel is turned on.

【０００３】[0003]

【この発明の原点技術】 上記の縦型半導体装置は、耐
圧が高く、ＯＮ抵抗が低いという特性を備えている。本
発明者は、この特性をさらに改善するために、特願２０
００―０３７５９０号に記載の縦型半導体装置を開発し
た。但し、この出願はまだ公開されていない。この縦型
半導体装置は本出願の半導体装置の原型となったもので
あり、一対のトレンチ間の第１半導体領域（ソース領域
あるいはエミッタ領域）の幅よりも第３半導体領域（ド
リフト領域）の幅を狭くすることを特徴とする。第１半
導体領域（ソース領域あるいはエミッタ領域）の幅を広
くすることによって電極との接触面積を確保してＯＮ抵
抗を下げることができ、しかも、第３半導体領域（ドリ
フト領域）の幅を狭くすることによって、一対のトレン
チから側方に伸びる空乏層同士がつながって第３半導体
領域（ドリフト領域）が空乏化され、高い耐圧を確保す
ることができる。[Original Technology of the Invention] The above-described vertical semiconductor device has characteristics of high withstand voltage and low ON resistance. The present inventor has proposed in Japanese Patent Application No.
A vertical semiconductor device described in 00-037590 has been developed. However, this application has not been published yet. This vertical semiconductor device is a prototype of the semiconductor device of the present application, and the width of the third semiconductor region (drift region) is larger than the width of the first semiconductor region (source region or emitter region) between the pair of trenches. Is narrowed. By increasing the width of the first semiconductor region (source region or emitter region), a contact area with the electrode can be secured and the ON resistance can be reduced, and the width of the third semiconductor region (drift region) is reduced. Thereby, the depletion layers extending laterally from the pair of trenches are connected to each other, so that the third semiconductor region (drift region) is depleted, and a high breakdown voltage can be secured.

【０００４】[0004]

【発明が解決しようとする課題】 特願２０００−０３
７５９０号に記載の縦型半導体装置によって、ＯＮ抵抗
をさらに下げ、耐圧電圧をさらに高くすることができ
る。しかしながら、ＯＮ抵抗が温度に依存して大きく変
動するという問題がなおも残っている。本発明の一つの
目的は、ＯＮ抵抗を下げ、耐圧電圧を高くし、さらにそ
の上にＯＮ抵抗の温度依存性を低く抑えられる半導体装
置を実現することである。ＯＮ抵抗の温度依存性が低く
抑えられれば、即ち、ＯＮ抵抗が温度変化に抗してほぼ
一定に維持されれば、半導体装置を用いて制御する各種
電力制御の信頼性が大きく向上する。本発明の他の一つ
の目的は、特願２０００−０３７５９０号に記載された
縦型半導体装置によって実現された「ＯＮ抵抗が低くて
耐圧電圧が高い」という特性を横型半導体装置で実現す
ることである。これが成功すれば、半導体装置の片面に
配線するだけで各種の電力制御装置が構成できる。[Problems to be Solved by the Invention] Japanese Patent Application No. 2000-03
With the vertical semiconductor device described in No. 7590, the ON resistance can be further reduced and the withstand voltage can be further increased. However, there still remains a problem that the ON resistance greatly varies depending on the temperature. An object of the present invention is to realize a semiconductor device in which the ON resistance can be reduced, the withstand voltage can be increased, and the temperature dependency of the ON resistance can be suppressed low. If the temperature dependence of the ON resistance is kept low, that is, if the ON resistance is maintained substantially constant against a temperature change, the reliability of various power controls performed using the semiconductor device is greatly improved. Another object of the present invention is to realize, in a horizontal semiconductor device, the characteristic of “low ON resistance and high withstand voltage” realized by a vertical semiconductor device described in Japanese Patent Application No. 2000-037590. is there. If this is successful, various power control devices can be configured simply by wiring on one side of the semiconductor device.

【０００５】[0005]

【課題を解決するための手段および作用と効果】 本発
明の一つの半導体装置は、特開平７−７１４９号公報に
縦型半導体装置と特願２０００−０３７５９０号の縦型
半導体装置をさらに改良したものであって、その特徴を
箇条書きすると下記のものとなる。 （１）第１半導体領域、第２半導体領域、第３半導体領
域、第４半導体領域を順に備えている。縦方向に順に積
層されていても、あるいは横方向に順に配列されていて
もよい。 （２）第１と第３半導体領域は同じ導電型であり、それ
に対して、第２半導体領域は反対の導電型である。 （３）第３半導体領域は少なくとも一対の電極間に形成
されている。 （４）その電極と、第１から第４半導体領域のそれぞれ
は絶縁層で絶縁されている。 （５）一対の電極間に存在する第３半導体領域は、半導
体装置のオフ時に一対の電極から第３半導体領域内に伸
びる空乏層同士がつながる厚み以下に形成されている。 （６）第３半導体領域の少なくとも一部の不純物濃度
は、第２半導体領域の不純物濃度よりも高い。Means for Solving the Problems, Functions and Effects According to one aspect of the present invention, a vertical semiconductor device disclosed in Japanese Patent Application Laid-Open No. 7-7149 and a vertical semiconductor device disclosed in Japanese Patent Application No. 2000-037590 are further improved. The following is a summary of the features. (1) A first semiconductor region, a second semiconductor region, a third semiconductor region, and a fourth semiconductor region are sequentially provided. They may be sequentially stacked in the vertical direction or may be sequentially arranged in the horizontal direction. (2) The first and third semiconductor regions are of the same conductivity type, whereas the second semiconductor region is of the opposite conductivity type. (3) The third semiconductor region is formed between at least a pair of electrodes. (4) The electrode and each of the first to fourth semiconductor regions are insulated by an insulating layer. (5) The third semiconductor region existing between the pair of electrodes is formed to have a thickness equal to or less than a thickness at which a depletion layer extending from the pair of electrodes into the third semiconductor region when the semiconductor device is off is connected. (6) The impurity concentration of at least a part of the third semiconductor region is higher than the impurity concentration of the second semiconductor region.

【０００６】ＯＮ抵抗の温度依存性は、第３半導体領域
（ドリフト領域）の不純物濃度を高くすることによっ
て、低く抑えられることが知られている。また、第３半
導体領域の不純物濃度を高くすれば、ＯＮ抵抗自体を低
く抑えられることも知られている。しかしながら、第３
半導体領域の不純物濃度を高くすれば、耐圧が低下して
しまう。従来の技術では、必要な耐圧を確保するために
必要な不純物濃度の範囲内でしか不純物濃度を選定でき
ず、おのずと、ＯＮ抵抗を充分に下げることができず、
また、ＯＮ抵抗の温度依存性を充分に抑えることができ
なかった。この発明の半導体装置の場合、一対の電極間
の第３半導体領域は、半導体装置のオフ時に一対の電極
から第３半導体領域内に伸びる空乏層同士がつながって
第３半導体領域が空乏化する厚み以下に形成されてい
る。このために、この発明の半導体装置では、耐圧を下
げないようにしながら第３半導体領域の不純物濃度を高
めることに成功しており、この結果、ＯＮ抵抗を充分に
下げ、さらに、ＯＮ抵抗の温度依存性を充分に抑えるこ
とに成功したものである。この発明の半導体装置は、耐
圧が高く、ＯＮ抵抗が低く、しかも、ＯＮ抵抗の温度依
存性が低いという特性を実現する。It is known that the temperature dependence of the ON resistance can be suppressed low by increasing the impurity concentration of the third semiconductor region (drift region). It is also known that the ON resistance itself can be suppressed low by increasing the impurity concentration of the third semiconductor region. However, the third
If the impurity concentration in the semiconductor region is increased, the breakdown voltage is reduced. With the conventional technology, the impurity concentration can be selected only within the range of the impurity concentration necessary to secure the required breakdown voltage, and naturally the ON resistance cannot be sufficiently reduced.
Further, the temperature dependency of the ON resistance could not be sufficiently suppressed. In the case of the semiconductor device of the present invention, the thickness of the third semiconductor region between the pair of electrodes is such that when the semiconductor device is turned off, depletion layers extending from the pair of electrodes into the third semiconductor region are connected to each other to deplete the third semiconductor region. It is formed as follows. For this reason, the semiconductor device of the present invention succeeds in increasing the impurity concentration of the third semiconductor region while keeping the withstand voltage from lowering. As a result, the ON resistance is sufficiently reduced, and the temperature of the ON resistance is further reduced. It has succeeded in suppressing dependence sufficiently. ADVANTAGE OF THE INVENTION The semiconductor device of this invention implement | achieves the characteristic that withstand voltage is high, ON resistance is low, and the temperature dependency of ON resistance is low.

【０００７】本発明は縦型半導体にも横型半導体にも具
現化することができるが、縦型半導体装置に具現化する
場合には、下記の構成を有することもできる。 （１）半導体装置の表面側から、第１半導体領域、第２
半導体領域、第３半導体領域、第４半導体領域の順に積
層されている。 （２）第１と第３半導体領域は同じ導電型であり、それ
に対して、第２半導体領域は反対の導電型である。 （３）半導体装置の表面から第３半導体領域の深部また
は第４半導体領域に達する少なくとも一対のトレンチが
形成されている。 （４）そのトレンチ内には導体が形成されている。 （５）そのトレンチ内の導体と、第１から第４半導体領
域のそれぞれとは、絶縁層で絶縁されている。 （６）一対のトレンチ間の第１半導体領域の幅よりも第
３半導体領域の幅は狭い。 （７）第２半導体領域の不純物濃度よりも、第３半導体
領域の少なくとも一部の不純物濃度の方が高い。The present invention can be embodied in either a vertical semiconductor or a horizontal semiconductor. However, when it is embodied in a vertical semiconductor device, it can have the following configuration. (1) The first semiconductor region and the second semiconductor region
The semiconductor region, the third semiconductor region, and the fourth semiconductor region are stacked in this order. (2) The first and third semiconductor regions are of the same conductivity type, whereas the second semiconductor region is of the opposite conductivity type. (3) At least one pair of trenches is formed from the surface of the semiconductor device to the deep portion of the third semiconductor region or the fourth semiconductor region. (4) A conductor is formed in the trench. (5) The conductor in the trench and each of the first to fourth semiconductor regions are insulated by the insulating layer. (6) The width of the third semiconductor region is smaller than the width of the first semiconductor region between the pair of trenches. (7) The impurity concentration of at least part of the third semiconductor region is higher than the impurity concentration of the second semiconductor region.

【０００８】この発明の半導体装置の場合、一対のトレ
ンチ間の第３半導体領域の幅を第１半導体領域の幅より
も狭くしたために、第３半導体領域の不純物濃度を高く
しても、一対のトレンチから側方に伸びる空乏層同士が
つながってドリフト領域が空乏化される現象が利用でき
る。このために、この縦型半導体装置では、耐圧を下げ
ないようにしながら第３半導体領域の不純物濃度を高め
ることに成功しており、ＯＮ抵抗を充分に下げ、さら
に、ＯＮ抵抗の温度依存性を充分に抑えることに成功し
ている。In the case of the semiconductor device of the present invention, the width of the third semiconductor region between the pair of trenches is made smaller than the width of the first semiconductor region. A phenomenon in which depletion layers extending laterally from the trench are connected to each other to deplete the drift region can be used. For this reason, in this vertical semiconductor device, it has succeeded in increasing the impurity concentration of the third semiconductor region while keeping the withstand voltage from lowering. Thus, the ON resistance is sufficiently reduced, and the temperature dependence of the ON resistance is further reduced. We have succeeded in suppressing it sufficiently.

【０００９】第３半導体領域の全体において第２半導体
領域よりも不純物濃度が高いことが望ましい。しかしな
がら、必ずしも第３半導体領域の全領域で高い必要はな
く、第３半導体領域の中に第２半導体領域よりも不純物
濃度が低い領域が部分的に存在していても、耐圧が高
く、ＯＮ抵抗が低く、しかも、ＯＮ抵抗の温度依存性が
低いという特性が相当程度に実現される。この場合、第
３半導体領域の全体厚みの半分以上の厚みで、第３半導
体領域の不純物濃度が第２半導体領域の不純物濃度より
も高いことが好ましい。It is desirable that the impurity concentration in the entire third semiconductor region is higher than that in the second semiconductor region. However, the third semiconductor region is not necessarily required to be high in the entire region. Even if a region having a lower impurity concentration than the second semiconductor region partially exists in the third semiconductor region, the withstand voltage is high and the ON resistance is high. , And the temperature dependence of the ON resistance is low. In this case, it is preferable that the impurity concentration of the third semiconductor region is higher than the impurity concentration of the second semiconductor region at a thickness equal to or more than half of the entire thickness of the third semiconductor region.

【００１０】第３半導体領域の全体厚みの半分以上の厚
みで、第３半導体領域の不純物濃度が第２半導体領域の
不純物濃度よりも高いと、耐圧が高く、ＯＮ抵抗が低
く、しかも、ＯＮ抵抗の温度依存性が低いという特性が
顕著に表れる。When the impurity concentration of the third semiconductor region is higher than the impurity concentration of the second semiconductor region at a thickness of half or more of the entire thickness of the third semiconductor region, the withstand voltage is high, the ON resistance is low, and the ON resistance is low. Has a low temperature dependency.

【００１１】この発明の縦型半導体装置では、一対のト
レンチ間の第１半導体領域の幅よりも第３半導体領域の
幅が狭いというだけでなく、半導体装置の内側に位置す
るトレンチ内導体（これはゲート電極として機能する）
と第２半導体領域（即ちボディ領域）は薄い絶縁層で絶
縁されている一方、半導体装置の外郭に位置するトレン
チ内導体（これは素子分離用に機能する）と第２半導体
領域は厚い絶縁層で絶縁されている必要がある。前者の
絶縁層は薄くなければボディ領域にチャネルを形成する
のに必要なゲート電圧が高くなり、後者の絶縁膜が厚く
なければ耐圧を確保できない。In the vertical semiconductor device according to the present invention, not only is the width of the third semiconductor region narrower than the width of the first semiconductor region between the pair of trenches, but also the inner conductor of the trench located inside the semiconductor device (this Functions as a gate electrode)
And the second semiconductor region (that is, the body region) are insulated by a thin insulating layer, while the conductor in the trench located outside the semiconductor device (which functions for element isolation) and the second semiconductor region are formed by a thick insulating layer. Must be insulated by If the former insulating layer is not thin, the gate voltage required to form a channel in the body region increases, and if the latter insulating film is not thick, the breakdown voltage cannot be ensured.

【００１２】絶縁層を形成するために、トレンチの壁面
を酸化させる。このとき、半導体装置の内側に位置する
トレンチの第２半導体領域に接する面では酸化が進行せ
ず、同じトレンチの第３半導体領域に接する面では深く
酸化が進行する一方、半導体装置の外郭に位置するトレ
ンチでは、第２半導体領域に接する面と第３半導体領域
に接する面でともに深く酸化が進むことが好ましい。こ
のような酸化深さのコントロールが得られれば、一対の
トレンチ間の第１半導体領域の幅よりも第３半導体領域
の幅は狭く、ゲート電極として機能する半導体装置の内
側に位置するトレンチ内導体と第２半導体領域は薄い絶
縁層で絶縁され、素子分離用に機能する半導体装置の外
郭に位置するトレンチ内導体と第２半導体領域は厚い絶
縁層で絶縁されている構造を容易に得ることができる。In order to form an insulating layer, the walls of the trench are oxidized. At this time, oxidation does not progress on the surface of the trench located inside the semiconductor device that is in contact with the second semiconductor region, and oxidation progresses deeply on the surface of the same trench that is in contact with the third semiconductor region. In the trench to be oxidized, it is preferable that oxidation proceeds deeply both on the surface in contact with the second semiconductor region and on the surface in contact with the third semiconductor region. If such control of the oxidation depth is obtained, the width of the third semiconductor region is narrower than the width of the first semiconductor region between the pair of trenches, and the conductor in the trench located inside the semiconductor device functioning as the gate electrode The second semiconductor region and the second semiconductor region are insulated by a thin insulating layer, and a structure in which the conductor in the trench located outside the semiconductor device functioning for element isolation and the second semiconductor region are insulated by the thick insulating layer can be easily obtained. it can.

【００１３】本発明の製造方法は、このために開発され
たものであり、半導体装置の内側に位置するトレンチに
第２半導体領域が露出する壁面に耐酸化性の保護膜を形
成し、ついで半導体装置の外郭に位置するトレンチと半
導体装置の内側に位置するトレンチの双方の壁面を同時
に酸化することによって縦型半導体装置を製造する。こ
の製造方法によると、ゲート電極に対向する薄い絶縁膜
と、素子分離用導体に対向する厚い絶縁膜を同一工程で
作成でき、半導体装置の製造に要するステップ数を減少
させることができる。A manufacturing method according to the present invention has been developed for this purpose. An oxidation-resistant protective film is formed on a wall surface where a second semiconductor region is exposed in a trench located inside a semiconductor device. A vertical semiconductor device is manufactured by simultaneously oxidizing the wall surfaces of both the trench located outside the device and the trench located inside the semiconductor device. According to this manufacturing method, a thin insulating film facing the gate electrode and a thick insulating film facing the element isolation conductor can be formed in the same process, and the number of steps required for manufacturing a semiconductor device can be reduced.

【００１４】本発明の他の一つの半導体装置は特願２０
００−０３７５９０号の縦型半導体装置を横型にしたも
のであり、その特徴とを箇条書きすると下記のものとな
る。 （１）第１半導体領域、第２半導体領域、第３半導体領
域、第４半導体領域を横方向に順に備えている。 （２）第１と第３半導体領域は同じ導電型であり、第２
半導体領域は反対の導電型である。 （３）第３半導体領域は少なくとも一対の電極間に形成
されている。 （４）その電極と、第１から第４半導体領域のそれぞれ
は絶縁層で絶縁されている。 （５）一対の電極間に存在する第３半導体領域は、半導
体装置のオフ時に一対の電極から第３半導体領域内に伸
びる空乏層同士がつながる厚み以下に形成されている。Another semiconductor device of the present invention is disclosed in Japanese Patent Application No.
The vertical type semiconductor device of No. 00-037590 is a horizontal type. The features of the vertical type semiconductor device are as follows. (1) A first semiconductor region, a second semiconductor region, a third semiconductor region, and a fourth semiconductor region are sequentially provided in a lateral direction. (2) the first and third semiconductor regions are of the same conductivity type,
The semiconductor region is of the opposite conductivity type. (3) The third semiconductor region is formed between at least a pair of electrodes. (4) The electrode and each of the first to fourth semiconductor regions are insulated by an insulating layer. (5) The third semiconductor region existing between the pair of electrodes is formed to have a thickness equal to or less than a thickness at which a depletion layer extending from the pair of electrodes into the third semiconductor region when the semiconductor device is off is connected.

【００１５】この横型半導体装置の場合、一対の電極間
に存在する第３半導体領域は、半導体装置のオフ時に一
対の電極から第３半導体領域内に伸びる空乏層同士がつ
ながって第３半導体領域が空乏化する厚み以下に形成さ
れている。このために、この発明の半導体装置では耐圧
が高い。また、第１半導体領域に電極に対する充分な接
触面積を確保することができ、ＯＮ抵抗を下げることが
できる。また、第３半導体領域が空乏化するために、耐
圧を下げることなく第３半導体領域の不純物濃度を高め
ることができ、不純物濃度を高めると、ＯＮ抵抗さらに
下げ、さらに、ＯＮ抵抗の温度依存性を充分に抑えるこ
とができる。In the case of this lateral semiconductor device, the third semiconductor region existing between the pair of electrodes is connected to a depletion layer extending from the pair of electrodes into the third semiconductor region when the semiconductor device is turned off. The thickness is set to be equal to or less than the depletion thickness. Therefore, the semiconductor device of the present invention has a high breakdown voltage. Further, a sufficient contact area with the electrode can be ensured in the first semiconductor region, and the ON resistance can be reduced. Further, since the third semiconductor region is depleted, the impurity concentration of the third semiconductor region can be increased without lowering the breakdown voltage. When the impurity concentration is increased, the ON resistance is further reduced, and the temperature dependence of the ON resistance is further reduced. Can be sufficiently suppressed.

【００１６】[0016]

【実施の形態】 下記に説明する実施例の特徴を先に整
理しておく。 （形態１） 請求項２に記載の縦型半導体装置の第３半
導体領域は、第３半導体領域上層と第３半導体領域下層
を有し、第３半導体領域下層の不純物濃度が第２半導体
領域の不純物濃度よりも高い。 （形態２） 形態１において、第３半導体領域上層の不
純物濃度は第２半導体領域の不純物濃度よりも低い。こ
の場合、第２半導体領域の下面から第３半導体領域上層
のなかに空乏層が伸びるために、高い耐圧を確保するこ
とができる。 （形態３） ＯＮ抵抗の温度係数が０．０８mΩmm２／
℃以下の半導体装置。これ程に低い温度係数をもつ半導
体装置は、本発明ではじめて実現される。 （形態４） 第３半導体領域の不純物濃度が１０１７cm
−３以上である半導体装置。この濃度は従来の半導体装
置の１０倍以上の濃度であり、従来の半導体装置でこの
ような高濃度とすると耐圧が確保されない。本発明では
じめて実現された高濃度である。 （形態５） 縦型半導体装置では、縦型半導体装置の内
側に位置するトレンチ形成部にまず第２半導体領域を貫
通する浅いトレンチを形成し、その壁面に窒化膜を形成
し、その後に、半導体装置の外郭と内側の双方において
第３半導体領域の深部または第４半導体領域に達するト
レンチを形成する。 （形態６） 形態５の後で、トレンチの壁面を酸化処理
する。DESCRIPTION OF THE PREFERRED EMBODIMENTS The features of the embodiment described below will be first summarized. (Mode 1) The third semiconductor region of the vertical semiconductor device according to claim 2 has an upper layer of the third semiconductor region and a lower layer of the third semiconductor region, and an impurity concentration of the lower layer of the third semiconductor region is lower than that of the second semiconductor region. Higher than the impurity concentration. (Embodiment 2) In Embodiment 1, the impurity concentration of the upper layer of the third semiconductor region is lower than the impurity concentration of the second semiconductor region. In this case, a high breakdown voltage can be ensured because the depletion layer extends from the lower surface of the second semiconductor region into the upper layer of the third semiconductor region. (Mode 3) The temperature coefficient of the ON resistance is 0.08 mΩmm 2 /
A semiconductor device of less than or equal to ° C. A semiconductor device having such a low temperature coefficient is realized for the first time by the present invention. (Mode 4) The impurity concentration of the third semiconductor region is 10 17 cm.
-3 or more semiconductor devices. This concentration is ten times or more that of the conventional semiconductor device. If such a high concentration is used in the conventional semiconductor device, the withstand voltage cannot be ensured. It is a high concentration realized for the first time in the present invention. (Mode 5) In the vertical semiconductor device, a shallow trench penetrating the second semiconductor region is first formed in a trench forming portion located inside the vertical semiconductor device, a nitride film is formed on a wall surface thereof, and then the semiconductor is formed. A trench is formed to reach the deep portion of the third semiconductor region or the fourth semiconductor region both on the outer and inner sides of the device. (Embodiment 6) After Embodiment 5, the wall surface of the trench is oxidized.

【００１７】[0017]

【実施例】（第１実施例） 第１実施例の縦型半導体装
置を図１を参照して説明する。図１は縦型半導体装置２
のソース電極４が第1半導体領域（以下ソース領域とい
う）１０に接触する部位での断面を示す。参照番号１８
はシリコン基板であり、第４半導体領域（以下ドレイン
領域という）として機能する。ドレイン領域１８はｎ＋
型で、不純物濃度は１０１８／cm ３〜１０２１／cm３で
ある。参照番号１６は第２エピタキシャル層であり、第
３半導体領域下層（以下ドリフト領域下層という）とし
て機能する。ドリフト領域下層１６はｎ−型で、不純物
濃度は２×１０１７／cm３ある。参照番号１４は第１エ
ピタキシャル層であり、第３半導体領域上層（以下ドリ
フト領域上層という）として機能する。ドリフト領域上
層１４はｎ−型で、不純物濃度は１×１０１６／cm３あ
る。参照番号１２はｐドープ層であり、第２半導体領域
（以下ボディ領域という）として機能する。ボディ領域
１２はｐ型で、不純物濃度は１×１０１７／cm３ある。
参照番号１０はｎドープ層であり、第１半導体領域（以
下ソース領域という）として機能する。ソース領域１０
はｎ＋型で、不純物濃度は１０１８／cm３〜１０２１／
cm３である。参照番号６と８は絶縁層である。参照番号
２０はゲート電極である。参照番号２２は素子分離用の
導体である。Embodiment 1 (First Embodiment) A vertical semiconductor device according to a first embodiment is described.
The arrangement will be described with reference to FIG. FIG. 1 shows a vertical semiconductor device 2
Of the first semiconductor region (hereinafter referred to as a source region).
3) shows a cross-section at a portion contacting 10). Reference number 18
Is a silicon substrate, and a fourth semiconductor region (hereinafter referred to as a drain)
Function). The drain region 18 is n+
Type, impurity concentration is 1018/cm 3-1021/cm3so
is there. Reference numeral 16 denotes a second epitaxial layer,
3 Lower layer of semiconductor region (hereinafter referred to as lower layer of drift region)
Function. The drift region lower layer 16 is n−Type, impurities
The concentration is 2 × 1017/cm3is there. Reference numeral 14 indicates the first d.
A layer formed on the third semiconductor region (hereinafter referred to as a “driving layer”).
(Referred to as the upper layer of the shift region). On the drift region
Layer 14 is n−Type, impurity concentration is 1 × 1016/cm3Ah
You. Reference numeral 12 denotes a p-doped layer, which is a second semiconductor region.
(Hereinafter referred to as a body region). Body area
12 is a p-type and has an impurity concentration of 1 × 1017/cm3is there.
Reference numeral 10 denotes an n-doped layer, which is a first semiconductor region (hereinafter referred to as a first semiconductor region).
Function as a lower source region). Source area 10
Is n+Type, impurity concentration is 1018/cm3-1021/
cm3It is. Reference numerals 6 and 8 are insulating layers. reference number
20 is a gate electrode. Reference numeral 22 is for device isolation.
Conductor.

【００１８】図１の断面構造中、ソース領域１０、ボデ
ィ領域１２、ドリフト領域上層１４、ドリフト領域下層
１６、ドレイン領域１８の積層構造、ならびにゲート電
極２０の基本構造は紙面垂直方向に連続している。図１
と異なる断面では、ゲート電極２０群にゲート信号線が
接続されている。図１の断面図ではドレイン電極の図示
が省略されており、ドレイン領域１８の下面にドレイン
電極が固定されている。ドレイン電極には直流１００ボ
ルトが印加される。図１の断面は、半導体装置２の周縁
部での断面を示し、実際には、ソース領域１０とボディ
領域１２とドリフト領域上層１４とドリフト領域下層１
６とドレイン領域１８の積層構造と、ゲート電極２０の
水平方向の互層構造が図示右側に連続している。半導体
装置２の右側周縁での断面は図１をミラー反転したもの
となる。素子分離用の導体２２は、半導体装置２を平面
視したときに、外郭を一巡しており、その内部に多数の
ゲート電極２０群が平行に配置されている。In the sectional structure of FIG. 1, the stacked structure of the source region 10, the body region 12, the drift region upper layer 14, the drift region lower layer 16, and the drain region 18, and the basic structure of the gate electrode 20 are continuous in the direction perpendicular to the paper. I have. FIG.
In a cross section different from the above, a gate signal line is connected to the gate electrode 20 group. The illustration of the drain electrode is omitted in the cross-sectional view of FIG. 1, and the drain electrode is fixed to the lower surface of the drain region 18. 100 VDC is applied to the drain electrode. The cross section of FIG. 1 shows a cross section at the peripheral portion of the semiconductor device 2, and in fact, the source region 10, the body region 12, the drift region upper layer 14 and the drift region lower layer 1
The layered structure of the gate electrode 6 and the drain region 18 and the horizontal alternate layer structure of the gate electrode 20 are continuous on the right side in the figure. The cross section at the right peripheral edge of the semiconductor device 2 is obtained by mirror-inverting FIG. The element isolation conductor 22 loops around the outline when the semiconductor device 2 is viewed in a plan view, and a large number of gate electrodes 20 are arranged in parallel inside the outline.

【００１９】一対のゲート電極２０、２０間に位置する
ソース領域１０の幅W３は、一対のゲート電極２０、２
０間に位置するドリフト領域下層１６の幅W４よりも広
い。また、ゲート電極２０とボディ領域１２間の絶縁層
８ａの厚みＷ２は薄く、ゲート電極２０とドリフト領域
下層１６間の絶縁層８ｂの厚みＷ５は厚く、素子分離用
導体２２とボディ領域１２間の絶縁層８ｃの厚みW１は
厚い。The width W3 of the source region 10 located between the pair of gate electrodes 20, 20 is
It is wider than the width W4 of the drift region lower layer 16 located between zero. Further, the thickness W2 of the insulating layer 8a between the gate electrode 20 and the body region 12 is thin, and the thickness W5 of the insulating layer 8b between the gate electrode 20 and the drift region lower layer 16 is large. The thickness W1 of the insulating layer 8c is large.

【００２０】一対のゲート電極２０、２０間に位置する
ドリフト領域下層１６の幅W４は０．４μｍ以下であ
り、上記不純物濃度の条件下で空乏層となっている。即
ち、一対のゲート電極２０、２０からドリフト領域下層
１６内に側方に伸びる空乏層同士がつながる厚さとなっ
ている。The width W4 of the drift region lower layer 16 located between the pair of gate electrodes 20, 20 is 0.4 μm or less, and serves as a depletion layer under the above-described impurity concentration conditions. That is, the thickness is such that depletion layers extending laterally from the pair of gate electrodes 20 and 20 into the drift region lower layer 16 are connected to each other.

【００２１】この半導体装置は、ソース領域１０が幅広
であり、ソース電極４との接触面積が広く確保でき、Ｏ
Ｎ抵抗が低い。また、一対のゲート電極２０、２０間に
位置するドリフト領域下層１６の幅W４が狭く、ゲート
電極２０から側方に伸びる空乏層が繋がってドリフト領
域下層１６が空乏層となり、耐圧が高い。ゲート電極２
０とボディ領域１２間の絶縁層８ａの厚みＷ２が薄いた
めに、ＯＮ動作に必要なゲート電圧が低い。ゲート電極
２０とドリフト領域下層１６間の絶縁層８ｂの厚みＷ５
は厚く、素子分離用導体２２とボディ領域１２間の絶縁
層８ｃの厚みW1も厚いために耐圧が高い。In this semiconductor device, the source region 10 is wide and a large contact area with the source electrode 4 can be secured.
N resistance is low. Also, the width W4 of the drift region lower layer 16 located between the pair of gate electrodes 20, 20 is narrow, and the depletion layer extending laterally from the gate electrode 20 is connected, so that the drift region lower layer 16 becomes a depletion layer, and the breakdown voltage is high. Gate electrode 2
Since the thickness W2 of the insulating layer 8a between the 0 and the body region 12 is small, the gate voltage required for the ON operation is low. Thickness W5 of insulating layer 8b between gate electrode 20 and drift region lower layer 16
And the withstand voltage is high because the thickness W1 of the insulating layer 8c between the element separating conductor 22 and the body region 12 is also large.

【００２２】さらに、ドリフト領域下層１６の不純物濃
度（２×１０１７／ｃｍ３）が、ボディ領域１２の不純
物濃度（１×１０１７／ｃｍ３）よりも高いために、Ｏ
Ｎ抵抗が低い上に、ＯＮ抵抗の温度依存性も低い。ＯＮ
抵抗の温度係数は、０．０７６mΩmm２／℃であり、従
来の同種半導体装置の温度係数が０．６７ｍΩｍｍ２／
℃であったのに対し、一桁小さな値に抑えられている。
ドリフト領域上層１４の不純物濃度（１×１０１６／ｃ
ｍ３）は、ボディ領域１２の不純物濃度（１×１０１７
／ｃｍ３）よりも低いが、その厚みはドリフト領域下層
１６の厚さよりも薄く、ドリフト領域下層１６の不純物
濃度が高いために、ＯＮ抵抗が低く、ＯＮ抵抗の温度依
存性も低いという特性は失われない。ボディ領域１２の
不純物濃度よりも不純物濃度の高い層がドリフト領域の
全体厚みの半分以上に及んでいれば、ドリフト領域の一
部にボディ領域１２の不純物濃度よりも不純物濃度の低
い層が含まれていても、ＯＮ抵抗が低く、ＯＮ抵抗の温
度依存性も低いという特性は失われない。なお、ドリフ
ト領域上層１４の幅広部はボディ領域１２から伸びる空
乏層となり、耐圧を損ねることもない。Further, since the impurity concentration of the drift region lower layer 16 (2 × 10 17 / cm 3 ) is higher than the impurity concentration of the body region 12 (1 × 10 17 / cm 3 ), O
In addition to the low N resistance, the temperature dependence of the ON resistance is low. ON
Temperature coefficient of resistance is 0.076mΩmm 2 / ℃, the temperature coefficient of the conventional same type semiconductor device 0.67mΩmm 2 /
It was suppressed to an order of magnitude smaller than in ° C.
The impurity concentration of the drift region upper layer 14 (1 × 10 16 / c
m 3 ) is the impurity concentration of the body region 12 (1 × 10 17
/ Cm 3 ), but the thickness is smaller than the thickness of the drift region lower layer 16 and the impurity concentration of the drift region lower layer 16 is high, so that the ON resistance is low and the temperature dependence of the ON resistance is low. Not lost. If a layer having an impurity concentration higher than the impurity concentration of body region 12 extends over half of the entire thickness of drift region, a portion of the drift region includes a layer having an impurity concentration lower than the impurity concentration of body region 12. However, the characteristics that the ON resistance is low and the temperature dependence of the ON resistance is low are not lost. Note that the wide portion of the drift region upper layer 14 becomes a depletion layer extending from the body region 12, and does not impair the breakdown voltage.

【００２３】次に図２以降を参照しながら製造プロセス
を説明する。図２に示すように、ｎ型のシリコン基板３
０（不純物濃度１０１８／cm３〜１０２１／cm３）の上
に、ｎ型の第２エピタキシャル層３２とｎ型の第１エピ
タキシャル層３４を結晶成長させたシリコンウエハ２８
を準備する。第２エピタキシャル層３２の不純物濃度を
２×１０１７／ｃｍ３とし、第１エピタキシャル層３４
の不純物濃度を１×１０１６／ｃｍ３とする。用意され
たシリコンウエハ２８をアニール処理して、完成後にｎ
型ドリフト領域１４，１６となる層の不純物濃度プロフ
ァイルを調整する。Next, the manufacturing process will be described with reference to FIGS. As shown in FIG. 2, an n-type silicon substrate 3
0 (impurity concentration 10 18 / cm 3 to 10 21 / cm 3 ), a silicon wafer 28 in which an n-type second epitaxial layer 32 and an n-type first epitaxial layer 34 are crystal-grown.
Prepare The impurity concentration of the second epitaxial layer 32 is set to 2 × 10 17 / cm 3 ,
Is 1 × 10 16 / cm 3 . The prepared silicon wafer 28 is annealed, and after completion, n
The impurity concentration profiles of the layers that become the mold drift regions 14 and 16 are adjusted.

【００２４】次に、図３に示すように、シリコンウエハ
２８の表面に酸化シリコンの絶縁層３８を形成し、絶縁
層３８を介してｐ型のイオンを第１エピタキシャル層３
４の略上半分にイオン注入し、加熱処理して注入された
イオンを拡散させる。拡散後の不純物濃度が、１×１０
１７／ｃｍ３となるようイオン注入する。このｐ型イオ
ンのｐドープ層３６が完成後にはボディ領域１２とな
る。次に、図４に示すように、シリコンウエハ２８の表
面に、窒化膜４０をＣＶＤ法によって形成する。Next, as shown in FIG. 3, an insulating layer 38 of silicon oxide is formed on the surface of the silicon wafer 28, and p-type ions are injected through the insulating layer 38 into the first epitaxial layer 3.
Ions are implanted into approximately the upper half of 4 and heat treatment is performed to diffuse the implanted ions. The impurity concentration after diffusion is 1 × 10
Ion implantation is performed so as to be 17 / cm3. After the completion of the p-type ion p-doped layer 36, the body region 12 is formed. Next, as shown in FIG. 4, a nitride film 40 is formed on the surface of the silicon wafer 28 by a CVD method.

【００２５】次に、図５に示すように、シリコンウエハ
２８を平面視したときの外郭部４２で、酸化膜３８と窒
化膜４０を除去する。酸化膜３８と窒化膜４０を局所的
に除去するためにホトレジストと異方性エッチング（具
体的にはリアクティブイオンエッチング）技術を利用す
る。ホトレジスト層の形成工程と除去工程は図示省略さ
れている。図５はシリンコンウエハの外郭近傍での断面
を示し、実際には右側に伸びている。右端では、図５の
左右反転させた断面が現れる。次に、図６に示すよう
に、シリコンウエハ２８の表面に、アンドープトガラス
層４４をＣＶＤ法で成形する。シリコンウエハ２８を平
面視したときの外郭部４２では、ｐドープ層３６の表面
にアンドープトガラス層４４が形成される。Next, as shown in FIG. 5, the oxide film 38 and the nitride film 40 are removed from the outer portion 42 when the silicon wafer 28 is viewed in plan. In order to locally remove the oxide film 38 and the nitride film 40, a photoresist and an anisotropic etching (specifically, reactive ion etching) technique are used. The steps of forming and removing the photoresist layer are not shown. FIG. 5 shows a cross section in the vicinity of the outer periphery of the silicon wafer, and actually extends rightward. At the right end, the cross section of FIG. Next, as shown in FIG. 6, an undoped glass layer 44 is formed on the surface of the silicon wafer 28 by a CVD method. An undoped glass layer 44 is formed on the surface of the p-doped layer 36 in the outer portion 42 when the silicon wafer 28 is viewed in plan.

【００２６】次に、図７に示すように、ゲート電極形成
部４８で、絶縁膜３８，４０，４４を除去する。実際に
は、アンドープトガラス層４４の表面にホトレジスト層
を形成し（ただし、ゲート電極形成部４８ではアンドー
プトガラス層４４を露出させておく）、ホトレジスト層
で被覆されていないアンドープトガラス層４４と窒化膜
４０と酸化層３８を異方性エッチング（具体的にはリア
クティブイオンエッチング）して除去する。このとき、
シリコンウエハ２８を平面視したときの外郭部４２（素
子分離用導体２２を形成する部分）ではアンドープトガ
ラス層４４等を除去しない。次に、図８に示すように、
アンドープトガラス層４４等をマスクとして異方性エッ
チング（具体的にはリアクティブイオンエッチング）し
てｐドープ層３６を貫通する浅いトレンチ５２を作成す
る。このトレンチ５２は、ゲート電極２０の形成部に形
成され、素子分離用導体２２の形成部には形成されな
い。次に、図９に示すように、浅いトレンチ５２の側面
と底面にバッファ酸化層５４を形成する。さらにその上
にＣＶＤ法によって窒化層５６を積層する。バッファ酸
化層５４と窒化層５６は、後記する図１３の酸化工程に
おいて、酸化から保護する層として機能する。Next, as shown in FIG. 7, in the gate electrode forming portion 48, the insulating films 38, 40, and 44 are removed. Actually, a photoresist layer is formed on the surface of the undoped glass layer 44 (however, the undoped glass layer 44 is exposed in the gate electrode forming portion 48), and the undoped glass layer 44 not covered with the photoresist layer and the nitride film are formed. 40 and the oxide layer 38 are removed by anisotropic etching (specifically, reactive ion etching). At this time,
The undoped glass layer 44 and the like are not removed from the outer portion 42 (the portion where the element separating conductor 22 is formed) when the silicon wafer 28 is viewed in a plan view. Next, as shown in FIG.
Anisotropic etching (specifically, reactive ion etching) is performed using the undoped glass layer 44 as a mask to form a shallow trench 52 penetrating the p-doped layer 36. The trench 52 is formed in the portion where the gate electrode 20 is formed, and is not formed in the portion where the element isolation conductor 22 is formed. Next, as shown in FIG. 9, a buffer oxide layer 54 is formed on the side and bottom surfaces of the shallow trench 52. Further, a nitride layer 56 is stacked thereon by the CVD method. The buffer oxide layer 54 and the nitride layer 56 function as layers that protect against oxidation in the oxidation step of FIG. 13 described later.

【００２７】次に、図１０に示すように、シリコンウエ
ハ２８を平面視したときの外郭部４２の素子分離用導体
２２を形成する部分で、アンドープトガラス層４４と窒
化層５６を異方性エッチング（具体的にはリアクティブ
イオンエッチング）して除去する。次に、図１１に示す
ように、アンドープトガラス層４４をマスクとして異方
性エッチング（具体的にはリアクティブイオンエッチン
グ）してシリコン基板３０に達するトレンチを形成す
る。ゲート電極形成用のトレンチ６２は深く、素子分離
用導体形成用のトレンチ６０は浅い。第２半導体領域と
なるｐドープ層３６のゲート電極形成用のトレンチ６２
に露出する壁面はバッファ酸化層５４と窒化層５６に覆
われていている。それに対して、第２半導体領域となる
ｐドープ層３６の素子分離用導体形成用のトレンチ６０
に露出する壁面は被覆されておらず、直接に露出してい
る。次に、図１２に示すように、アンドープトガラス層
４４を湿式のエッチング法で除去する。次に、図１３に
示すように、シリコンウエハ２８の表面を、まず犠牲酸
化し、次に犠牲酸化膜を湿式のエッチング法で除去し、
最後に、Ｖ−ＬＯＣＯＳ酸化する。これによって、トレ
ンチ６０、６２の底面と側面、ｐドープ層３６の表面と
側面に酸化層６４が形成される。ここで、バッファ酸化
層５４と窒化層５６からなる耐酸化層で被覆されていた
部分では浅く酸化される。このために、第２半導体領域
となるｐドープ層３６がゲート電極形成用のトレンチ６
２に露出する壁面には薄い絶縁層（酸化層６４ａ）が形
成される。一方、バッファ酸化層５４と窒化層５６から
なる耐酸化層で被覆されていない部分では深く酸化され
る。このために第２半導体領域となるｐドープ層３６が
素子分離用導体形成用のトレンチ６０に露出する壁面に
は厚い酸化層６４ｃが形成される。バッファ酸化層５４
と窒化層５６からなる耐酸化層で被覆されていなかった
シリコン基板３０と第１エピタキシャル層３２と第２エ
ピタキシャル層３４の壁面には、ゲート電極形成用のト
レンチ６２と素子分離用導体形成用のトレンチ６０の双
方において厚い酸化層６４ｂが形成される。Next, as shown in FIG. 10, the undoped glass layer 44 and the nitride layer 56 are anisotropically etched in the portion of the outer portion 42 where the element isolation conductor 22 is to be formed when the silicon wafer 28 is viewed in plan. (Specifically, reactive ion etching) is removed. Next, as shown in FIG. 11, anisotropic etching (specifically, reactive ion etching) is performed using the undoped glass layer 44 as a mask to form a trench reaching the silicon substrate 30. The trench 62 for forming a gate electrode is deep, and the trench 60 for forming a conductor for element isolation is shallow. Trench 62 for forming gate electrode of p-doped layer 36 serving as a second semiconductor region
Is covered with a buffer oxide layer 54 and a nitride layer 56. On the other hand, the trench 60 for forming the element isolation conductor of the p-doped layer 36 to be the second semiconductor region is formed.
The wall surface exposed to is not covered and is directly exposed. Next, as shown in FIG. 12, the undoped glass layer 44 is removed by a wet etching method. Next, as shown in FIG. 13, the surface of the silicon wafer 28 is subjected to sacrificial oxidation first, and then the sacrificial oxide film is removed by a wet etching method.
Finally, V-LOCOS oxidation is performed. Thus, an oxide layer 64 is formed on the bottom and side surfaces of the trenches 60 and 62 and on the surface and side surface of the p-doped layer 36. Here, the portion covered with the oxidation resistant layer including the buffer oxide layer 54 and the nitride layer 56 is oxidized shallowly. Therefore, the p-doped layer 36 serving as the second semiconductor region is formed in the trench 6 for forming the gate electrode.
A thin insulating layer (oxide layer 64a) is formed on the wall surface exposed to 2. On the other hand, portions not covered with the oxidation resistant layer including the buffer oxide layer 54 and the nitride layer 56 are deeply oxidized. For this reason, a thick oxide layer 64c is formed on the wall surface where the p-doped layer 36 serving as the second semiconductor region is exposed to the trench 60 for forming the isolation conductor. Buffer oxide layer 54
On the wall surfaces of the silicon substrate 30, the first epitaxial layer 32, and the second epitaxial layer 34, which were not covered with the oxidation-resistant layer composed of the nitride layer 56, a trench 62 for forming a gate electrode and a trench for forming a conductor for element isolation are formed. Thick oxide layer 64b is formed in both trenches 60.

【００２８】次に、図１４に示すように、トレンチ６２
とトレンチ６０の双方に、ドープされた多結晶シリコン
をＣＶＤ法によって充填する。酸化絶縁層６４の表面に
堆積した多結晶シリコンはエッチングによって除去され
る。ドープされた多結晶シリコンは導電性であり、ゲー
ト電極形成用のトレンチ６２に充填された導体６６がゲ
ート電極２０となり、素子分離用導体形成用のトレンチ
６０に充填された導体６８が素子分離用導体２２とな
る。Next, as shown in FIG.
And trench 60 are filled with doped polysilicon by CVD. Polycrystalline silicon deposited on the surface of the oxide insulating layer 64 is removed by etching. The doped polycrystalline silicon is conductive, and the conductor 66 filled in the trench 62 for forming the gate electrode becomes the gate electrode 20, and the conductor 68 filled in the trench 60 for forming the conductor for element isolation is used for the element isolation. It becomes the conductor 22.

【００２９】次に、図１５に示すように、表面を酸化す
る。次に、図１６に示すように、酸化絶縁層７０を介し
て、ｎ型のイオンをｐドープ層３６の上面に注入する。
次に、図１７に示すように、ＣＶＤ法によって表面をア
ンドープトガラス層７４で被覆する。Next, as shown in FIG. 15, the surface is oxidized. Next, as shown in FIG. 16, n-type ions are implanted into the upper surface of the p-doped layer 36 via the oxide insulating layer 70.
Next, as shown in FIG. 17, the surface is covered with an undoped glass layer 74 by a CVD method.

【００３０】次に、図１８に示すように、ゲート電極２
０となるトレンチ内導体６６間であって、ｐドープ層３
６が存在する部位において、アンドープトガラス層７４
と酸化層７０とｎ型のイオン注入層７２を貫いてｐドー
プ層３６に達する浅い溝７６を形成する。実際には、ア
ンドープトガラス層７４の表面にコンタクトフォト層を
形成し、それをマスクとして異方性エッチング（具体的
にはリアクティブイオンエッチング）し、最後にコンタ
クトフォト層を除去する。次に、図１９に示すように、
溝７６の底面にｐ型のイオン（具体的にはボロン）を注
入する。その後に熱処理して、先に注入されたｎ型のイ
オン７２と、今回注入されたｐ型のイオンを拡散する。
この結果、ｎドープ層８０と、ｐドープ層７８が形成さ
れる。ｎドープ層８０は完成後にソース領域となる。Next, as shown in FIG.
0 between the in-trench conductors 66 and the p-doped layer 3
6 is present in the undoped glass layer 74
Then, a shallow groove 76 that reaches the p-doped layer 36 through the oxide layer 70 and the n-type ion implantation layer 72 is formed. Actually, a contact photo layer is formed on the surface of the undoped glass layer 74, anisotropic etching (specifically, reactive ion etching) is performed using the contact photo layer as a mask, and finally, the contact photo layer is removed. Next, as shown in FIG.
P-type ions (specifically, boron) are implanted into the bottom of the groove 76. Thereafter, heat treatment is performed to diffuse the n-type ions 72 implanted earlier and the p-type ions implanted this time.
As a result, an n-doped layer 80 and a p-doped layer 78 are formed. The n-doped layer 80 becomes a source region after completion.

【００３１】次に、図２０に示すように、絶縁層７４、
７０を湿式エッチングして溝幅を広げる。この結果、ｎ
ドープ層８０の表面が露出する。次に、図２１に示すよ
うに、表面にアルミ層８４をスパッタする。このアルミ
層８４は、ｎドープ層８０に接触している。Next, as shown in FIG.
70 is wet-etched to increase the groove width. As a result, n
The surface of the doped layer 80 is exposed. Next, as shown in FIG. 21, an aluminum layer 84 is sputtered on the surface. This aluminum layer 84 is in contact with n-doped layer 80.

【００３２】トレンチ内導体６６は、図示されない断面
において、アルミ層８４から絶縁された別の導体層に接
続されてゲート電極２０となる。また、シリコン基板３
０の裏面には図示されないドレイン電極が形成される。
素子分離用導体６８（２２）は接地しても良いし、ゲー
ト電極に接続しておいても良い。以上のプロセスを経
て、図１の半導体装置２が完成する。The in-trench conductor 66 is connected to another conductor layer insulated from the aluminum layer 84 to form the gate electrode 20 in a cross section (not shown). In addition, the silicon substrate 3
A drain electrode (not shown) is formed on the back surface of 0.
The element isolation conductor 68 (22) may be grounded or may be connected to a gate electrode. Through the above process, the semiconductor device 2 of FIG. 1 is completed.

【００３３】上記の製造プロセスでは、図１２に明瞭に
示されるように、第２半導体領域となるｐドープ層３６
が半導体装置の内側に位置するトレンチ６２に露出する
壁面に耐酸化性の保護膜５４，５６を形成し、ついで、
図１３に示されるように、半導体装置の外郭に位置する
トレンチ６０と半導体装置の内側に位置するトレンチ６
２の双方の壁面を同時に酸化する。そのことによって、
半導体装置の外郭に位置するトレンチ６０内の導体６８
と第２半導体領域３６は厚い絶縁層６４ｃで絶縁され、
半導体装置の内側に位置するトレンチ６２内の導体６６
と第２半導体領域３６は薄い絶縁層６４ａで絶縁されて
いる半導体装置が得られる。従来は、ゲート電極形成用
のトレンチ６２と、素子分離導体用のトレンチ６０を全
く別の工程で酸化していた。本発明の製造方法による
と、製造過程が大幅に減少する。In the above manufacturing process, as clearly shown in FIG. 12, the p-doped layer 36 serving as the second semiconductor region is formed.
Form oxidation-resistant protective films 54 and 56 on the wall surface exposed to the trench 62 located inside the semiconductor device.
As shown in FIG. 13, the trench 60 located outside the semiconductor device and the trench 6 located inside the semiconductor device
The two walls are simultaneously oxidized. By that,
Conductor 68 in trench 60 located outside the semiconductor device
And the second semiconductor region 36 are insulated by a thick insulating layer 64c,
Conductor 66 in trench 62 located inside semiconductor device
And a semiconductor device in which the second semiconductor region 36 is insulated by the thin insulating layer 64a. Conventionally, the trench 62 for forming the gate electrode and the trench 60 for the element isolation conductor have been oxidized in completely different steps. According to the manufacturing method of the present invention, the manufacturing process is greatly reduced.

【００３４】（第２実施例） 次に、第２実施例の横型
半導体装置を図２２から図２７を参照して説明する。図
２２は第２実施例の横型半導体装置の一部を破断して示
す斜視図を示し、図２３は平面図を示す。図２４は図２
３のＡ−Ａ線の断面図、図２５はＢ−Ｂ線の断面図、図
２６はＣ−Ｃ線の断面図、図２７はＤ−Ｄ線の断面図を
示す。図２２に示す参照番号１１８はｎ+ドープ層であ
り、第４半導体領域（以下、ドレイン領域という）とし
て機能する。ドレイン領域１１８の不純物濃度は１×１
０１８／cm３〜１０２１／cm３である。参照番号１１６
はｎ−ドープ層であり、第３半導体領域（以下、ドリフ
ト領域という）として機能する。ドリフト領域１１６の
不純物濃度は２×１０１７／cm ３である。参照番号１１
２はｐドープ層であり、第２半導体領域（以下、ボディ
領域という）として機能する。ボディ領域１２の不純物
濃度は１×１０１７／cm３ある。ドリフト領域１１６の
不純物濃度は２×１０１７／cm３であり、ボディ領域１
２の不純物濃度よりも高濃度である。参照番号１１０は
ｎ＋ドープ層であり、第１半導体領域（以下、ソース領
域という）として機能する。ソース領域１１０の不純物
濃度は１０１８／cm３〜１０ ２１／cm３である。参照番
号１３０はｎ型のシリコン基板である。参照番号１０８
は絶縁層である。参照番号１２０はゲート電極であり、
参照番号１２１はゲート電極１２０に電圧を供給するゲ
ート電極である。参照番号１２２は素子分離用の導体で
あり、平面視（図２３参照）したときに、シリコン基板
１３０の外周に沿って伸び、素子形成領域を取り囲んで
いる。参照番号１０９はソースコンタクトである。(Second Embodiment) Next, the horizontal type of the second embodiment
The semiconductor device will be described with reference to FIGS. Figure
Reference numeral 22 denotes a part of the horizontal semiconductor device of the second embodiment, which is cut away.
FIG. 23 shows a perspective view, and FIG. 23 shows a plan view. FIG. 24 shows FIG.
3 is a sectional view taken along line AA, FIG. 25 is a sectional view taken along line BB,
26 is a sectional view taken along line CC, and FIG. 27 is a sectional view taken along line DD.
Show. Reference numeral 118 shown in FIG.+Dope layer
As a fourth semiconductor region (hereinafter, referred to as a drain region).
Function. The impurity concentration of the drain region 118 is 1 × 1
018/cm3-1021/cm3It is. Reference 116
Is n−A third semiconductor region (hereinafter referred to as a drift layer)
Function area). Of the drift region 116
The impurity concentration is 2 × 1017/cm 3It is. Reference number 11
Reference numeral 2 denotes a p-doped layer, which is a second semiconductor region (hereinafter referred to as a body).
Function). Impurities in body region 12
The concentration is 1 × 1017/cm3is there. Of the drift region 116
The impurity concentration is 2 × 1017/cm3And body region 1
2 is higher than the impurity concentration. Reference number 110 is
n+A first semiconductor region (hereinafter referred to as a source region);
Function). Impurity of source region 110
The concentration is 1018/cm3-10 21/cm3It is. Reference number
Reference numeral 130 denotes an n-type silicon substrate. Reference number 108
Is an insulating layer. Reference numeral 120 is a gate electrode,
Reference numeral 121 denotes a gate for supplying a voltage to the gate electrode 120.
This is a gate electrode. Reference numeral 122 denotes a conductor for element isolation.
Yes, when viewed in plan (see FIG. 23), the silicon substrate
Extending along the outer periphery of 130 and surrounding the element formation region
I have. Reference numeral 109 is a source contact.

【００３５】図２２と図２４に示すように、ソース領域
１１０、ボディ領域１１２、ドリフト領域１１６、ドレ
イン領域１１８は図示横方向に連続して配置されてい
る。ソース領域１１０とボディ領域１１２は図２２のＸ
方向に連続的に伸び、ドリフト領域１１６は、ゲート電
極１２０と絶縁層１０８によって、Ｘ方向に分断されて
いる。その様子が、図２３のＤ−Ｄ線断面を示す図２７
に明瞭に示されている。図２３のＡ−Ａ線断面を示す図
２４には、ドリフト領域１１６の断面が現れ、図２３の
Ｂ−Ｂ線断面図である図２５には、絶縁体１０８の断面
が現れ、図２３のＣ−Ｃ線断面図である図２６には、ゲ
ート電極１２０の断面が現れている。図２２と図２４に
示すように、ボディ領域１１２とドリフト領域１１６上
には、絶縁層１０８を介して、図２２のＸ方向に伸びる
平板状のゲート電極用ゲート電極１２１が配置されてい
る。図示の明瞭化のために、ソース電極とドレイン電極
の図示が省略されている。図２４に示すように、平板状
のゲート電極１２１の左側でソース領域１１０が露出し
ており、実際にはそのソース領域１１０上にソース電極
が配置される。また平板状のゲート電極１２１の右側で
ドレイン領域１１８が露出しており、実際にはそのドレ
イン領域１１８上にドレイン電極が配置される。なお、
ドレイン電極には直流１００ボルトが印加される。図２
２と図２３に示すように、素子分離用の導体１２２は、
横型半導体装置１０２を平面視したときに外郭を一巡し
ており、図２２の縦方向に伸びている。As shown in FIGS. 22 and 24, the source region 110, the body region 112, the drift region 116 and the drain region 118 are arranged continuously in the horizontal direction in the drawing. The source region 110 and the body region 112 correspond to X in FIG.
The drift region 116 continuously extends in the direction, and is separated in the X direction by the gate electrode 120 and the insulating layer 108. FIG. 27 shows a cross section taken along line DD in FIG.
Are clearly shown. FIG. 24 showing a cross section taken along line AA of FIG. 23 shows a cross section of the drift region 116, and FIG. 25 which is a cross section taken along line BB of FIG. FIG. 26, which is a cross-sectional view taken along the line CC, shows a cross section of the gate electrode 120. As shown in FIGS. 22 and 24, on the body region 112 and the drift region 116, a flat gate electrode 121 for a gate electrode extending in the X direction of FIG. For clarity of illustration, illustration of a source electrode and a drain electrode is omitted. As shown in FIG. 24, the source region 110 is exposed on the left side of the flat gate electrode 121, and the source electrode is actually arranged on the source region 110. The drain region 118 is exposed on the right side of the flat gate electrode 121, and the drain electrode is actually arranged on the drain region 118. In addition,
100 VDC is applied to the drain electrode. FIG.
2 and FIG. 23, the conductor 122 for element isolation
When the horizontal semiconductor device 102 is viewed in a plan view, the horizontal semiconductor device 102 makes a circuit around the outer contour and extends in the vertical direction in FIG.

【００３６】図２４に示すように、平板状のゲート電極
１２１とボディ領域１１２間の絶縁層１０８ａの厚みＷ
８は薄く、平板状のゲート電極１２１とドリフト領域１
１６間の絶縁層１０８ｂの厚みＷ９は厚く、素子分離用
導体１２２とボディ領域１１２間の絶縁層１０８ｃの厚
みW１０は厚い。As shown in FIG. 24, the thickness W of the insulating layer 108a between the flat gate electrode 121 and the body region 112 is increased.
8 is a thin, flat gate electrode 121 and drift region 1
The thickness W9 of the insulating layer 108b between the layers 16 is large, and the thickness W10 of the insulating layer 108c between the element separating conductor 122 and the body region 112 is large.

【００３７】図２２に示す一対のゲート電極１２０、１
２０間に位置するドリフト領域１１６の幅W６は０．４
μm以下であり、一対のゲート電極１２０、１２０にオ
フ電圧が掛けられている間は空乏層となる。即ち、オフ
電圧が掛けられている一対のゲート電極１２０、１２０
からドリフト領域１１６内に側方に伸びる空乏層同士が
つながる厚さとなっている。A pair of gate electrodes 120, 1 shown in FIG.
The width W6 of the drift region 116 located between 20 is 0.4
μm or less, and serves as a depletion layer while an off-voltage is applied to the pair of gate electrodes 120. That is, the pair of gate electrodes 120, 120 to which the off-voltage is applied
And a thickness at which the depletion layers extending laterally into the drift region 116 are connected to each other.

【００３８】図２２に示すように、この横型半導体装置
１０２は、一対のゲート電極１２０、１２０間に位置す
るドリフト領域１１６の幅W６が狭く、ゲート電極１２
０から側方に伸びる空乏層がつながってドリフト領域１
１６が空乏層となるために、耐圧が高い。また、ゲート
電極１２０とドリフト領域１１６間の絶縁層１０８の厚
みＷ７が厚いために、耐圧が高い。また、図２４に示す
ように、平板状のゲート電極１２１とドリフト領域１１
６間の絶縁層１０８ｂの厚みＷ９が厚く、素子分離用導
体１２２とボディ領域１１２間の絶縁層１０８ｃの厚み
W１０も厚いために、耐圧が高い。一方、平板状のゲー
ト電極１２１とボディ領域１１２間の絶縁層１０８ａの
厚みＷ８が薄いために、ＯＮ動作に必要なゲート電圧が
低い。As shown in FIG. 22, in the lateral semiconductor device 102, the width W6 of the drift region 116 located between the pair of gate electrodes 120, 120 is small, and the width of the gate electrode 12 is small.
The depletion layer extending laterally from 0 connects to the drift region 1
Since 16 is a depletion layer, the breakdown voltage is high. In addition, since the thickness W7 of the insulating layer 108 between the gate electrode 120 and the drift region 116 is large, the withstand voltage is high. Further, as shown in FIG. 24, a flat gate electrode 121 and a drift region 11 are formed.
6, the thickness W9 of the insulating layer 108b is large, and the thickness of the insulating layer 108c between the element separating conductor 122 and the body region 112 is large.
Since W10 is also thick, the withstand voltage is high. On the other hand, since the thickness W8 of the insulating layer 108a between the flat gate electrode 121 and the body region 112 is small, the gate voltage required for the ON operation is low.

【００３９】さらに、ドリフト領域１１６の不純物濃度
（２×１０１７／ｃｍ３）が、ボディ領域１１２の不純
物濃度（１×１０１７／ｃｍ３）よりも高いために、Ｏ
Ｎ抵抗が低い上に、ＯＮ抵抗の温度依存性も低い。ＯＮ
抵抗の温度係数は、０．０７６mΩmm２／℃であり、従
来の同種半導体装置の温度係数が０．６７ｍΩｍｍ２／
℃であったのに対し、一桁小さな値に抑えられている。
なお、ＯＮ抵抗の温度依存性が高くても良い場合には、
ドリフト領域１１６の不純物濃度をボディ領域１１２の
不純物濃度よりも低濃度とすることができる。また、Ｏ
Ｎ抵抗の温度依存性を低く抑える必要がある場合にも、
ドリフト領域（第３半導体領域）の全領域でボディ領域
（第２半導体領域）の不純物濃度よりも高濃度である必
要はなく、第３半導体領域の中に第２半導体領域よりも
不純物濃度の低い領域が部分的に存在していてもい。Further, since the impurity concentration of drift region 116 (2 × 10 17 / cm 3 ) is higher than the impurity concentration of body region 112 (1 × 10 17 / cm 3 ), O
In addition to the low N resistance, the temperature dependence of the ON resistance is low. ON
Temperature coefficient of resistance is 0.076mΩmm 2 / ℃, the temperature coefficient of the conventional same type semiconductor device 0.67mΩmm 2 /
It was suppressed to an order of magnitude smaller than in ° C.
If the temperature dependency of the ON resistance may be high,
The impurity concentration of drift region 116 can be lower than the impurity concentration of body region 112. Also, O
When it is necessary to keep the temperature dependence of the N resistance low,
It is not necessary that the impurity concentration in the entire drift region (third semiconductor region) is higher than the impurity concentration in the body region (second semiconductor region), and the impurity concentration in the third semiconductor region is lower than that in the second semiconductor region. The region may partially exist.

【００４０】第２実施例では、ゲート電極１２０が、ド
レイン領域１１６を分離するように半導体装置１０２の
表面から縦方向に伸びている。これに代えて、図２８に
示す埋め込み式のゲート電極２２０を利用しても良い。
図２８において、ゲート電極２２０は図示されない断面
で平板上のゲート電極２２１に接続され、絶縁体２０８
で覆われている。平板上のゲート電極２２１と埋め込み
式のゲート電極２２０の間のドレイン領域２１６の厚み
Ｗ１１は十分に薄く、ゲート電極２２０、２２１にオフ
電圧が掛けられている間はドレイン領域２１６は空乏層
となる。即ち、オフ電圧が掛けられている一対のゲート
電極２２０、２２１からドリフト領域２１６内に上下方
向に伸びる空乏層同士がつながる厚さとなっている。In the second embodiment, the gate electrode 120 extends vertically from the surface of the semiconductor device 102 so as to separate the drain region 116. Instead, an embedded gate electrode 220 shown in FIG. 28 may be used.
In FIG. 28, a gate electrode 220 is connected to a gate electrode 221 on a flat plate at a cross section (not shown),
Covered with. The thickness W11 of the drain region 216 between the gate electrode 221 on the flat plate and the buried type gate electrode 220 is sufficiently thin, and the drain region 216 becomes a depletion layer while an off-voltage is applied to the gate electrodes 220 and 221. . In other words, the thickness is such that depletion layers extending vertically in the drift region 216 from the pair of gate electrodes 220 and 221 to which the off voltage is applied are connected.

【００４１】上記の実施例では、電界効果型トランジス
タに本発明を適用している。しかしながら本発明は、電
界効果型トランジスタに限られるものでなく、バイポー
ラ型のトランジスタやＩＧＢＴにも適用することができ
る。また、当業者は実施例の技術から様々に変形するこ
とが可能であり、例えば、ｐとｎの関係を逆転するこ
と、製造方法のステップ順を適宜変更すること、トレン
チ６０，６２の深さを第３半導体領域の深部に留めるこ
となど、当業者は通常の知識によって自在に変形するこ
とができる。In the above embodiment, the present invention is applied to a field effect transistor. However, the present invention is not limited to a field effect transistor, but can be applied to a bipolar transistor and an IGBT. Further, those skilled in the art can make various modifications from the technique of the embodiment, for example, reversing the relationship between p and n, appropriately changing the step order of the manufacturing method, and changing the depth of the trenches 60 and 62. Those skilled in the art can freely modify the structure with ordinary knowledge, such as keeping the depth in the third semiconductor region.

【図面の簡単な説明】[Brief description of the drawings]

【図１】 第１実施例の縦型半導体装置の断面図。FIG. 1 is a sectional view of a vertical semiconductor device according to a first embodiment.

【図２】 図１の半導体装置を製造する第１段階での断
面図。FIG. 2 is a sectional view at a first stage of manufacturing the semiconductor device of FIG. 1;

【図３】 図１の半導体装置を製造する第２段階での断
面図。FIG. 3 is a sectional view in a second stage of manufacturing the semiconductor device of FIG. 1;

【図４】 図１の半導体装置を製造する第３段階での断
面図。FIG. 4 is a sectional view at a third stage of manufacturing the semiconductor device of FIG. 1;

【図５】 図１の半導体装置を製造する第４段階での断
面図。FIG. 5 is a sectional view at a fourth stage of manufacturing the semiconductor device of FIG. 1;

【図６】 図１の半導体装置を製造する第５段階での断
面図。FIG. 6 is a sectional view of a fifth step of manufacturing the semiconductor device of FIG. 1;

【図７】 図１の半導体装置を製造する第６段階での断
面図。FIG. 7 is a sectional view of a sixth step of manufacturing the semiconductor device of FIG. 1;

【図８】 図１の半導体装置を製造する第７段階での断
面図。FIG. 8 is a sectional view at a seventh stage of manufacturing the semiconductor device of FIG. 1;

【図９】 図１の半導体装置を製造する第８段階での断
面図。FIG. 9 is a sectional view of an eighth step of manufacturing the semiconductor device of FIG. 1;

【図１０】 図１の半導体装置を製造する第９段階での
断面図。FIG. 10 is a sectional view of a ninth step of manufacturing the semiconductor device of FIG. 1;

【図１１】 図１の半導体装置を製造する第１０段階で
の断面図。FIG. 11 is a sectional view at a tenth stage of manufacturing the semiconductor device of FIG. 1;

【図１２】 図１の半導体装置を製造する第１１段階で
の断面図。FIG. 12 is a sectional view of an eleventh stage of manufacturing the semiconductor device of FIG. 1;

【図１３】 図１の半導体装置を製造する第１２段階で
の断面図。FIG. 13 is a sectional view showing a twelfth step of manufacturing the semiconductor device of FIG. 1;

【図１４】 図１の半導体装置を製造する第１３段階で
の断面図。FIG. 14 is a sectional view showing a thirteenth stage of manufacturing the semiconductor device of FIG. 1;

【図１５】 図１の半導体装置を製造する第１４段階で
の断面図。FIG. 15 is a sectional view of a semiconductor device in FIG. 1 in a fourteenth step of manufacturing the semiconductor device;

【図１６】 図１の半導体装置を製造する第１５段階で
の断面図。FIG. 16 is a sectional view showing a fifteenth stage of manufacturing the semiconductor device of FIG. 1;

【図１７】 図１の半導体装置を製造する第１６段階で
の断面図。FIG. 17 is a sectional view of a semiconductor device in FIG. 1 at a sixteenth stage of manufacturing the device;

【図１８】 図１の半導体装置を製造する第１７段階で
の断面図。FIG. 18 is a sectional view of a semiconductor device in FIG. 1 at a seventeenth stage of manufacturing the semiconductor device;

【図１９】 図１の半導体装置を製造する第１８段階で
の断面図。FIG. 19 is a sectional view at an 18th stage of manufacturing the semiconductor device of FIG. 1;

【図２０】 図１の半導体装置を製造する第１９段階で
の断面図。FIG. 20 is a sectional view at a 19th stage of manufacturing the semiconductor device of FIG. 1;

【図２１】 図１の半導体装置を製造する第２０段階で
の断面図。FIG. 21 is a sectional view of a twentieth step of manufacturing the semiconductor device of FIG. 1;

【図２２】 第２実施例の横型半導体装置の斜視図。FIG. 22 is a perspective view of a lateral semiconductor device of a second embodiment.

【図２３】 図２２の横型半導体装置の平面図。FIG. 23 is a plan view of the horizontal semiconductor device of FIG. 22;

【図２４】 図２３の横型半導体装置のＩ−Ｉ線断面
図。24 is a cross-sectional view of the horizontal semiconductor device of FIG. 23 taken along the line II.

【図２５】 図２３の横型半導体装置のII−II線断面
図。25 is a cross-sectional view of the horizontal semiconductor device of FIG. 23, taken along the line II-II.

【図２６】 図２３の横型半導体装置のIII−III線断面
図。26 is a cross-sectional view of the horizontal semiconductor device of FIG. 23, taken along the line III-III.

【図２７】 図２３の横型半導体装置のIV−IV線断面
図。FIG. 27 is a cross-sectional view of the horizontal semiconductor device of FIG. 23 taken along line IV-IV.

【図２８】 第２実施例の横型半導体装置の他の変形例
を示した図。FIG. 28 is a view showing another modification of the lateral semiconductor device of the second embodiment.

【符号の説明】[Explanation of symbols]

２、１０２：半導体装置 １０、１１０：第１半導体領域：ソース領域 １２、１１２：第２半導体領域：ボディ領域 １６、１１６：第３半導体領域：ドリフト領域 １８、１１８：第４半導体領域：ドレイン領域 2, 102: semiconductor device 10, 110: first semiconductor region: source region 12, 112: second semiconductor region: body region 16, 116: third semiconductor region: drift region 18, 118: fourth semiconductor region: drain region

───────────────────────────────────────────────────── フロントページの続き Ｆターム(参考） 5F032 AA35 AA45 AA47 AA84 CA17 CA24 DA25 5F140 AA07 AA30 AC21 BA01 BD18 BD19 BF42 BF43 BF44 BF45 BH02 BH13 BH17 BH30 BH49 BH50 BK32 CB04  ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F032 AA35 AA45 AA47 AA84 CA17 CA24 DA25 5F140 AA07 AA30 AC21 BA01 BD18 BD19 BF42 BF43 BF44 BF45 BH02 BH13 BH17 BH30 BH49 BH50 BK32 CB04

Claims (5)

【特許請求の範囲】[Claims] 【請求項１】 第１半導体領域、第２半導体領域、第３
半導体領域、第４半導体領域を順に備えた半導体装置で
あって、 第１と第３半導体領域は同じ導電型であり、第２半導体
領域は反対の導電型であり、 第３半導体領域は少なくとも一対の電極間に形成されて
おり、 その電極と、第１から第４半導体領域のそれぞれは絶縁
層で絶縁されており、 一対の電極間に存在する第３半導体領域は、半導体装置
のオフ時に一対の電極から第３半導体領域内に伸びる空
乏層同士がつながる厚み以下に形成され、 第３半導体領域の少なくとも一部の不純物濃度は、第２
半導体領域の不純物濃度よりも高いことを特徴とする半
導体装置。A first semiconductor region, a second semiconductor region, and a third semiconductor region;
A semiconductor device comprising a semiconductor region and a fourth semiconductor region in order, wherein the first and third semiconductor regions have the same conductivity type, the second semiconductor region has an opposite conductivity type, and the third semiconductor region has at least one pair. And the first to fourth semiconductor regions are insulated by an insulating layer, and the third semiconductor region present between the pair of electrodes is paired when the semiconductor device is turned off. The thickness of the third semiconductor region is equal to or smaller than the thickness of the second semiconductor region.
A semiconductor device having a higher impurity concentration than a semiconductor region. 【請求項２】 半導体装置の表面側から、第１半導体領
域、第２半導体領域、第３半導体領域、第４半導体領域
の順に積層されており、 第１と第３半導体領域は同じ導電型であり、第２半導体
領域は反対の導電型であり、 表面から第３半導体領域の深部または第４半導体領域に
達する少なくとも一対のトレンチが形成されており、 そのトレンチ内には導体が形成されており、 そのトレンチ内の導体と、第１から第４半導体領域のそ
れぞれが絶縁層で絶縁されており、 一対のトレンチ間の第１半導体領域の幅よりも第３半導
体領域の幅は狭く、かつ、第２半導体領域の不純物濃度
よりも第３半導体領域の少なくとも一部の不純物濃度の
方が高いことを特徴とする縦型半導体装置。2. A semiconductor device comprising: a first semiconductor region, a second semiconductor region, a third semiconductor region, and a fourth semiconductor region, which are stacked in this order from the front side of the semiconductor device, wherein the first and third semiconductor regions have the same conductivity type. The second semiconductor region is of the opposite conductivity type, at least one pair of trenches extending from the surface to the deep portion of the third semiconductor region or the fourth semiconductor region is formed, and a conductor is formed in the trench. A conductor in the trench and each of the first to fourth semiconductor regions are insulated by an insulating layer; a width of the third semiconductor region is smaller than a width of the first semiconductor region between the pair of trenches; A vertical semiconductor device, wherein the impurity concentration of at least a part of the third semiconductor region is higher than the impurity concentration of the second semiconductor region. 【請求項３】 第２半導体領域の不純物濃度よりも不純
物濃度が高い第３半導体領域の厚みが、第３半導体領域
の全体厚みの半分以上であることを特徴とする請求項１
または２に記載の縦型半導体装置。3. The semiconductor device according to claim 1, wherein the thickness of the third semiconductor region having an impurity concentration higher than the impurity concentration of the second semiconductor region is at least half of the total thickness of the third semiconductor region.
Or the vertical semiconductor device according to 2. 【請求項４】 半導体装置の表面側から、第１半導体領
域、第２半導体領域、第３半導体領域、第４半導体領域
の順に積層されており、表面から第３半導体領域の深部
または第４半導体領域に達する複数のトレンチが形成さ
れており、各トレンチ内には導体が形成されており、半
導体装置の外郭に位置するトレンチ内導体と第２半導体
領域は厚い絶縁層で絶縁され、半導体装置の内側に位置
するトレンチ内導体と第２半導体領域は薄い絶縁層で絶
縁されている縦型半導体装置の製造方法であり、 半導体装置の内側に位置するトレンチに第２半導体領域
が露出する壁面に耐酸化性の保護膜を形成し、ついで半
導体装置の外郭に位置するトレンチと半導体装置の内側
に位置するトレンチの双方の壁面を同時に酸化して、上
記の縦型半導体装置を製造する方法。4. A first semiconductor region, a second semiconductor region, a third semiconductor region, and a fourth semiconductor region are stacked in this order from the surface side of the semiconductor device, and a deep portion of the third semiconductor region or a fourth semiconductor region from the surface. A plurality of trenches reaching the region are formed, a conductor is formed in each trench, a conductor in the trench located at the outer periphery of the semiconductor device and the second semiconductor region are insulated by a thick insulating layer, and A method for manufacturing a vertical semiconductor device in which a conductor in a trench located inside and a second semiconductor region are insulated by a thin insulating layer, wherein an acid-resistant surface is provided on a wall where the second semiconductor region is exposed in a trench located inside the semiconductor device. Forming a protective film, and then simultaneously oxidizing both wall surfaces of the trench located on the outer side of the semiconductor device and the trench located on the inside of the semiconductor device to manufacture the above-described vertical semiconductor device. How to. 【請求項５】 第１半導体領域、第２半導体領域、第３
半導体領域、第４半導体領域を横方向に順に備えた半導
体装置であって、 第１と第３半導体領域は同じ導電型であり、第２半導体
領域は反対の導電型であり、 第３半導体領域は少なくとも一対の電極間に形成されて
おり、 その電極と、第１から第４半導体領域のそれぞれは絶縁
層で絶縁されており、 一対の電極間に存在する第３半導体領域は、半導体装置
のオフ時に一対の電極から第３半導体領域内に伸びる空
乏層同士がつながる厚み以下に形成されていることを特
徴とする半導体装置。5. The first semiconductor region, the second semiconductor region, and the third semiconductor region.
A semiconductor device comprising a semiconductor region and a fourth semiconductor region in a lateral direction, wherein the first and third semiconductor regions have the same conductivity type, the second semiconductor region has an opposite conductivity type, and a third semiconductor region. Is formed between at least a pair of electrodes, the electrode and each of the first to fourth semiconductor regions are insulated by an insulating layer, and the third semiconductor region existing between the pair of electrodes is formed of a semiconductor device. A semiconductor device, wherein a thickness of a depletion layer extending from a pair of electrodes into a third semiconductor region when turned off is formed to be equal to or less than a thickness at which the depletion layers are connected.
JP2001208540A 2001-01-24 2001-07-09 Semiconductor device and manufacturing method thereof Expired - Fee Related JP3709814B2 (en)

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US7557395B2 (en) 2002-09-30 2009-07-07 International Rectifier Corporation Trench MOSFET technology for DC-DC converter applications
DE112004000218B4 (en) * 2003-01-29 2016-09-22 International Rectifier Corp. Trench MOSFET technology for DC / DC converter applications
DE102004063946B4 (en) 2004-05-19 2018-03-22 Infineon Technologies Ag Transistor arrangements with an electrode arranged in a separation trench
JP2008504697A (en) * 2004-06-25 2008-02-14 インターナショナル レクティファイアー コーポレイション Power semiconductor device provided with a MOS gate having a source field electrode
DE102005020075A1 (en) * 2005-04-29 2006-11-09 Infineon Technologies Ag Manufacturing method for ditch structure semiconductor device involves forming neighboring ditch structures simultaneously in common process block
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