JP3483581B2 - Semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film semiconductor device such as a thin film transistor having excellent reliability and mass productivity and high yield, and a method for manufacturing the same. The present invention constitutes, as its application field, a driving circuit such as a liquid crystal display or a thin film image sensor, or a three-dimensional integrated circuit.

[0002]

2. Description of the Related Art Conventionally, a semiconductor integrated circuit has been mainly a monolithic type formed on a semiconductor substrate such as silicon, but in recent years, it has been attempted to form it on an insulating substrate such as glass or sapphire. . The reason is that the parasitic capacitance between the substrate and the wiring is reduced and the operation speed is improved, and in particular, the glass material such as quartz has no size limitation like a silicon wafer and is inexpensive, This is because the elements can be easily separated from each other, and in particular, a latch-up phenomenon which is a problem in a CMOS monolithic integrated circuit does not occur. In addition to the above reasons, in liquid crystal displays and contact image sensors,
Since it is necessary to integrate the semiconductor element and the liquid crystal element or the light detection element, it is necessary to form a thin film transistor (TFT) or the like on the transparent substrate.

For these reasons, thin film semiconductor elements have been formed on insulating substrates. FIG. 5 shows a TFT as an example of a conventional thin film semiconductor element. As shown in the figure, a film 503 of silicon oxide or the like is formed as a passivation film on an insulating substrate 501, and a TFT is formed on the film 503 independently of other TFTs. TFT
Is a source (drain) region 507 and a drain (source) region 509, a channel formation region (also simply referred to as a channel region) 508 sandwiched between the source (drain) region 507, the gate insulating film 504, and the gate electrode 510, similarly to the MOSFET of the monolithic integrated circuit. , And source (drain) electrode 511
And a drain (source) electrode 512. Also,
An interlayer insulator 506 such as PSG is provided so that multilayer wiring can be performed.

The example of FIG. 5 is called a forward coplanar type, but in the TFT, it is also called an inverse coplanar type, a forward stagger type, or an inverted stagger type depending on the arrangement of the gate electrode and the channel region. Although there is a form, the details will be left to other documents, and will not be further described here.

[0005]

Even in a monolithic integrated circuit, contamination by alkali ions such as sodium and potassium or transition metal ions such as iron, copper and nickel is a serious problem, and the invasion of these ions is a serious problem. Great care has been taken to stop it. TFT
However, the problem of these ions is just as serious, and attention is paid to cleaning the production process so that contamination is minimized. Moreover, measures are taken to prevent the element from being contaminated with these substances.

The difference between a thin film semiconductor device and a monolithic integrated circuit is that the concentration of contaminant ions in the substrate is relatively high. In other words, the monocrystalline silicon used for monolithic integrated circuits is produced by eliminating these harmful pollutant elements through the accumulation of technology for many years, and those that are commercially available at present are those pollutant elements. Is 10 ¹⁰ cm ⁻³ or less.

However, in general, the concentration of pollutant elements in an insulating substrate for a thin film semiconductor device is not low. Of course, with single crystal substrates such as spinel substrates and sapphire substrates,
Although it is theoretically possible to reduce the concentration of the foreign element that is the pollution source, it is not practical from the viewpoint of profitability. Also,
If a quartz substrate is manufactured by a gas phase reaction using high-purity silane gas and oxygen as raw materials, it is possible to ideally prevent the invasion of foreign elements, but since the structure is amorphous, the foreign elements are taken in once. If this happens, it is difficult to spit this out. In addition, the cost of the substrate used for the liquid crystal display is especially high, so it is necessary to use a low priced substrate. Contains. Some of these foreign elements themselves are not preferable for the semiconductor element, and in the process of adding these foreign elements, they may be mixed in from the outside or contained as impurities in the additive material.

For example, TN glass is an inexpensive glass substrate having good heat resistance and a coefficient of thermal expansion close to that of silicon, so that it is preferable as a substrate for liquid crystal displays, but contains about 5% lithium. A part of this lithium is ionized and penetrates into the semiconductor element as mobile ions, causing deterioration of the element. In addition, it is difficult to produce lithium having a high purity of 99% or more, and it is usually 0.7
It contains about% sodium. The ionization rate of sodium is about 10%, which is extremely large, and this sodium ion has a very serious effect on the characteristics of the device.

In the conventional thin film semiconductor device, as shown in FIG. 5, silicon oxide or the like is used as a passivation film against the invasion of mobile ions, and PSG or BPSG is used as the interlayer insulator. Have been addressed by gettering these mobile ions.
However, it is difficult to prevent contamination sufficiently by these methods. It is an object of the present invention to prevent the element from deteriorating due to invasion of these contaminant elements and ions.

[0010]

According to the present invention, a film having a blocking action against mobile ions such as silicon nitride, aluminum oxide, and tantalum oxide is provided in the lower part and the upper part of a thin film semiconductor device in order to suppress the above contamination. (Blocking film) is formed.

A typical example of the present invention is shown in FIG. FIG. 1 shows a TFT using the present invention. That is, the first blocking film 102 is formed on the insulating substrate 101.
As a first silicon nitride film is formed. The first silicon nitride film has an effect of preventing contamination from the substrate. Then, a film 103 having good adhesion to a silicon material such as silicon oxide is formed on the first silicon nitride film. When the semiconductor film is directly formed on the first silicon nitride without forming the film 103 and the TFT is manufactured, the channel region becomes conductive due to the trap level generated at the interface between the silicon nitride and the semiconductor material, and the TFT is formed. Does not work. Therefore, it is important to provide such a buffer.

A TFT is formed on the film 103. T
FT includes a source (drain) region 107, a drain (source) region 109, and a channel region 10 sandwiched between them.
8, a gate insulating film 104, and a gate electrode 110.
The source, drain, and channel regions of the TFT are formed of a single crystal, polycrystal, or amorphous semiconductor material. As the semiconductor material, for example, silicon, germanium, silicon carbide, and alloys thereof can be used.

Then, a second silicon nitride film is formed as a second blocking film 105 so as to cover the TFT. Here, it is a feature of the present invention that the second silicon nitride film is formed after the fabrication of the TFT and before the electrodes are formed on the source and / or the drain. In the conventional technique, the silicon nitride film as the final passivation film was formed after the electrodes were formed, but the present invention has a different purpose from the silicon nitride film formed in that sense. That is, the second silicon nitride film in the present invention is formed because it encloses the TFT together with the first silicon nitride film, and is intended to prevent contamination in the step of forming an electrode after the TFT is formed. To do. Therefore, a silicon nitride film may be formed as a final passivation film as in the conventional method after the TFT and the electrodes and wirings associated therewith are formed according to the present invention.

After the second silicon nitride film is formed, the interlayer insulating film 106 is formed by using an interlayer back insulating material such as PSG.
Then, a source (drain) electrode 111 and a drain (source) electrode 112 are formed.

In the example of FIG. 1, however, the gate insulating film extends distantly, and there is a possibility that the gate insulating film may enter the inside of the TFT from its end. An improved version of this is the example shown in FIG. 2, in which the gate insulating film is only on the TFT, so there is no problem as in FIG. However, in this case, since the source region and the drain region of the portion adjacent to the channel region are in contact with the silicon nitride film, the silicon nitride in this portion is polarized by the gate voltage or traps electrons to operate the TFT. May interfere with.

An example of overcoming that problem is shown in FIG.
Here, the source region and the drain region adjacent to the channel region are not adjacent to the silicon nitride film. Therefore, the problems of polarization of silicon nitride and electron trap are solved. However, when the self-alignment process using the gate electrode as a mask is adopted for forming the source and drain regions, in this example, as in the example of FIG. 1, an acceptor or donor element must be implanted through the gate insulating film. Therefore, if the ion implantation method is adopted, it is necessary to increase the acceleration energy of ions. At that time, as a result of the implantation of the fast ions, the source and drain regions may spread due to the secondary scattering.

In FIG. 2, 201 is an insulating substrate, 20
2 is a first silicon nitride film, 203 is a buffer insulating film such as silicon oxide, 204 is a gate insulating film, 205 is a second silicon nitride film, 206 is an interlayer insulating film, and 207 is a source (drain).
A region, 208 is a channel region, 209 is a drain (source) region, 210 is a gate electrode, 211 is a source (drain) electrode, and 212 is a drain (source) electrode.
Further, in FIG. 3, 301 is an insulating substrate, 302 is a first silicon nitride film, 303 is a buffer insulating film such as silicon oxide,
304 is a gate insulating film, 305 is a second silicon nitride film, 3
Reference numeral 06 is an interlayer insulating film, 307 is a source (drain) region,
308 is a channel region, 309 is a drain (source) region, 310 is a gate electrode, and 311 is a source (drain).
Electrodes 312 are drain (source) electrodes.

In the present invention, when a silicon nitride film is used as the blocking film, when represented by SiN _x in the chemical formula, x = 1.0 to x = 1.7 is suitable, and particularly x =
Stoichiometric composition from 1.3 to x = 1.35 (x = 1.3
Good results were obtained with 3) or close thereto. Therefore, in the present invention, silicon nitride is used as a reduced pressure CV.
It was better to form by the D method. However, it goes without saying that even with a silicon nitride film formed by the plasma CVD method or the photo CVD method, the reliability of the element is improved as compared with the case where the present invention is not used.

When a silicon nitride film is to be formed by the low pressure CVD method, dichlorosilane (S
iCl ₂ H ₂ ) and ammonia (NH ₃ ) at a pressure of 1
500 to 800 ° C. at 0 to 1000 Pa, preferably 55
The reaction may be performed at 0 to 750 ° C. Of course, silane (SiH ₄ ) or tetrachlorosilane (SiCl ₄ ) may be used.

Further, as described above, aluminum oxide or tantalum oxide is used as the blocking film in addition to silicon nitride. A CVD method or a sputtering method may be used to form these coatings. For example, to form an aluminum oxide film, trimethylaluminum Al (CH ₃ ) ₃ is added to nitric oxide (N ₂ O, NO, NO ₂ )
And the like.

FIG. 4 shows an example of forming a low impurity concentration drain (LDD) which is a known technique using the present invention. First, a silicon nitride film 402 having a thickness of 50 to 1000 nm is formed on an insulating substrate 401 such as quartz or AN glass by a low pressure CVD method. At this time, if not only the front surface of the substrate but also the back surface is covered with the silicon nitride film, the present invention can be carried out more reliably and effectively. That is, in the manufacturing process, mobile ions generated from the back surface (though they are contained in the substrate) often reach the front surface for various reasons, and as a result, for example,
Mobile ions penetrate into the gate oxide film during fabrication. Further, when the back surface is a source of mobile ions, manufacturing equipment such as a film forming apparatus is constantly contaminated by mobile ions. It is necessary to provide it. A buffer silicon oxide film 403 is also formed on the silicon nitride film under reduced pressure CV.
A thickness of 50 to 1000 nm is formed by the D method. At this time, if a gas containing halogen such as hydrogen chloride in a volume ratio of 3% to 6%, for example, about 5% is mixed in the source gas, the halogen element is incorporated into the obtained silicon oxide film. Since this halogen binds to alkali ions such as sodium to fix sodium, a larger effect can be obtained in preventing sodium contamination. However, excessive addition of halogen roughens the film and impairs adhesion and flatness of the surface, which is not preferable.

Next, an amorphous silicon film to which neither a donor nor an acceptor is added is formed by a low pressure CVD method or plasma C
20-500 thickness by VD method or sputtering method
Only nm is formed. Then, this is etched on the island. A gate insulating film with a thickness of 10 to 100 n
A silicon oxide film of m is formed by a low pressure CVD method or a sputtering method. Also in this case, as described above, in the source gas,
Alternatively, a halogen material gas may be mixed in the sputtering gas.

Then, a polycrystalline or microcrystalline silicon film doped with phosphorus to a concentration of about 10 ²¹ cm ^-3 is formed thereon by a low pressure CVD method or a plasma CVD method. Then, this silicon film and the gate insulating film (silicon oxide) thereunder are patterned to form a gate electrode 410 and a gate insulating film 404.

Further, ion implantation is carried out in a self-aligned manner using this gate electrode as a mask, and a source (drain) region 407 and a drain (source) region 408 having a relatively low impurity concentration (about 10 ¹⁷ to 10 ¹⁹ cm ⁻³ ) are used. To form. The portion where the impurities are not implanted remains as the channel region 408. Thus, FIG. 4A is obtained.

Next, as shown in FIG. 4B, low pressure CVD is performed.
The PSG film 413 is formed on the entire surface by the method. Then, this is etched by a known directional etching to form a side wall 414 beside the gate electrode. afterwards,
Ion implantation is performed again, and the source (drain) region 407a and the drain (source) region 4 having a high impurity concentration are formed.
09a is formed. A region having a low impurity concentration is a source (drain) region 407b and a drain (source) region 409.
b, LDD is formed. Thus, FIG. 4 (C)
To get

Thereafter, as shown in FIG. 4D, the reduced pressure C
A silicon nitride film 405 is formed to a thickness of 50 by VD method.
-1000 nm is formed. Then, the silicon film is crystallized by low-temperature annealing at about 600 ° C. to activate the source / drain regions. This step may be performed by laser annealing. In this way, a TFT intermediate is obtained.

It will be appreciated that the example of FIG. 4 is merely an example of the present invention and that the present invention is not limited to the above steps. In the example of FIG. 4, as in the example of FIG. 3, there is no portion where the silicon nitride film, the gate electrode, and the source or drain region are adjacent to each other. That is, unlike the case of FIG. 2, since the side wall 414 is present, there is no problem of concern in FIG. Further, unlike FIG. 3, it has a feature that a donor and an acceptor can be easily added.

[0028]

EXAMPLE The characteristics of the TFT using the present invention will be described. The TFT used in this example is an LDD type TFT manufactured on a quartz glass substrate according to the process of FIG.
First, a silicon nitride film 402 having a thickness of 100 nm is formed on the quartz glass substrate 401 and its back surface and side surfaces (that is, the entire substrate) by a low pressure CVD method, and further, a silicon oxide film (low temperature oxide film) is continuously formed by the low pressure CVD method. (LTO
(Also referred to as a film) 403 was formed to a thickness of 200 nm, and finally, an amorphous silicon film was formed to a thickness of 30 nm by the low pressure CVD method. The maximum process temperature at this time is 6
It was 00 ° C. Next, the amorphous silicon film was patterned into an island shape. Then, a very thin portion of the surface of the amorphous silicon film, having a thickness of 2 to 10 nm, was oxidized by an anodic oxidation method. After that, a silicon oxide film is formed by a sputtering method.
Was formed to a thickness of 00 nm. Here, the sputtering atmosphere was a mixed gas of oxygen and argon or another rare gas, and the partial pressure of oxygen was 80% or more. At this time, the sputter impact causes defects in the underlying film. For example, when the base is a silicon film, oxygen atoms are implanted in the silicon and the oxygen concentration increases. In such a state, silicon has many polar levels. That is, the boundary between silicon and silicon oxide becomes unclear. However, if a thin anodic oxide film is formed in advance as in the present embodiment, since the silicon oxide is already present at the time of sputtering, the above-mentioned mixing of atoms is avoided, and the silicon film and the oxide film are oxidized. The boundary of the silicon film is maintained.

After forming this silicon oxide film, an n ⁺ -type microcrystalline silicon film containing phosphorus of about 10 ²¹ cm ^-3 was formed to a thickness of 300 nm by the low pressure CVD method. The maximum process temperature for forming the above coating was 650 ° C. Then, the gate electrode was patterned to form a gate electrode 410 and a gate insulating film 404. Further, arsenic ions were implanted by 2 × 10 ¹⁸ cm ⁻³ by ion implantation to form source and drain regions 407 and 409. Thus, FIG. 4A was obtained.

Next, as shown in FIG. 4B, a PSG film 413 was formed by a low pressure CVD method, and a side wall 414 shown in FIG. 4C was formed by directional etching.
Further, arsenic ions are added to the region 4 by the ion implantation method.
5x10 ²⁰ cm ^{-3 was} injected into 07a and 409a.

After that, a silicon nitride film 405 is formed on the entire surface under reduced pressure C.
It was formed by the VD method. Thus, FIG. 4D was obtained. Then, anneal in vacuum at 620 ° C for 48 hours,
Regions 407a, 407b, 408, 409a, 409b
Was activated. Then, a PSG film was formed over the entire surface as an interlayer insulator by the low pressure CVD method, holes for electrodes were opened, and aluminum electrodes were formed in the source region and the drain region. Then, finally, for the purpose of passivation, a silicon nitride film was formed again on the entire surface by the low pressure CVD method.

The TFT thus formed was extremely reliable. It was shown that the so-called bias-temperature treatment (BT treatment) did not change the operating characteristics of the device. An example thereof is shown in FIG. Figure 6 shows the BT process.
Wiring was performed as in the circuit diagram shown therein, and a bias voltage V _B was applied between the gate (G), the source (S) and the drain (D) during heating. In particular,
Immediately after fabrication, the gate voltage-drain current characteristics of the TFT are measured at room temperature (V _B = 0), and then a voltage of +20 V is applied to the gate electrode for 1 hour at 150 ° C.
Of the gate voltage-drain current characteristics of (V _B = + 2
0 V), and then again at 150 ° C. for 1 hour, applying a voltage of −20 V to the gate electrode, and then measuring the gate voltage-drain current characteristic of the TFT at room temperature (V _B = −20).
V), and the change in the threshold voltage of the TFT was investigated.

FIG. 6B shows the characteristics of the TFT manufactured by the method described above. Thus, the characteristics were not affected by the bias voltage V _B at all, and as a result of precise measurement, the fluctuation of the threshold voltage was 0.2 V or less.

On the other hand, what is shown in FIG. 6A is manufactured by the same process as the method shown in this embodiment except that the silicon nitride films 402 and 405 are not provided. As described above, the characteristics greatly depend on V _B. It is explained that such characteristic fluctuations (threshold voltage fluctuations) are caused by mobile ions such as sodium in the gate insulating film. The larger the fluctuations, the more mobile ions, and as shown in FIG. 6B. It is explained that those with little fluctuation have a small amount of mobile ions. From the fluctuation width of the threshold voltage, it is estimated that the amount of mobile ions in the gate electrode of the TFT manufactured in this example is about 8 × 10 ¹⁰ cm ⁻³ . That is, it was shown that by providing a silicon nitride film as in the present invention, it is possible to remarkably improve the characteristics of the TFT and improve the reliability.

[0035]

According to the present invention, a thin film semiconductor element such as a TFT which is less affected by mobile ions such as sodium can be manufactured. Conventionally, it is possible to form a TFT even on a substrate in which elements cannot be formed due to the presence of mobile ions. To implement the present invention, a coplanar TFT as shown in FIGS. 1 to 4, or an inverse coplanar TFT, a stagger TFT, or an inverse stagger TFT may be used. In addition, since the present invention does not impose restrictions on the operation of the thin film semiconductor element, the silicon of the transistor may be amorphous, polycrystalline, microcrystalline, or an intermediate state thereof. It will be clear that it may be a single crystal or even a single crystal.

[Brief description of drawings]

FIG. 1 shows an example of a TFT according to the present invention.

FIG. 2 shows an example of a TFT according to the present invention.

FIG. 3 shows an example of a TFT according to the present invention.

FIG. 4 shows an example of manufacturing a TFT according to the present invention.

FIG. 5 shows an example of a conventional TFT.

FIG. 6 shows characteristics of a TFT using the present invention and a TFT not using the present invention.

[Explanation of symbols]

101 insulating substrate 102 first blocking film 103 buffer insulating film 104 Gate insulation film 105 Second blocking film 106 Interlayer insulation film 107 source (drain) region 108 channel region 109 drain (source) region 110 gate electrode 111 Source (drain) electrode 112 Drain (source) electrode

   ─────────────────────────────────────────────────── ─── Continued front page       (56) References JP-A 64-35961 (JP, A)                 JP 58-164268 (JP, A)                 JP-A-59-126673 (JP, A)                 JP 58-93273 (JP, A)

Claims (9)

(57) [Claims] 1. A first silicon nitride film provided on a substrate for preventing contamination from the substrate, an insulating film containing a halogen element provided on the first silicon nitride film, and the insulating property. Source region, drain region, LD on the film
A semiconductor device comprising: a thin film transistor having a semiconductor thin film provided with a D region and a channel formation region; and a second silicon nitride film provided on the thin film transistor for preventing contamination from the outside. 2. A first silicon nitride film provided on a substrate for preventing contamination from the substrate, an insulating film containing a halogen element provided on the first silicon nitride film, and the insulating property. Source region, drain region, LD on the film
A thin film transistor having a semiconductor thin film having a D region and a channel forming region, a gate insulating film and a gate electrode, and a second silicon nitride film provided on the thin film transistor for preventing external contamination. Semiconductor device. 3. A first silicon nitride film provided on a substrate for preventing contamination from the substrate, an insulating film containing a halogen element provided on the first silicon nitride film, and the insulating property. Source region, drain region, LD on the film
A semiconductor device having a thin film transistor having a semiconductor thin film provided with a D region and a channel formation region, a gate insulating film and a gate electrode, and a second silicon nitride film provided on the thin film transistor for preventing external contamination. The semiconductor device is characterized in that the thin film transistor is sandwiched between the first silicon nitride film and the second silicon nitride film. 4. A first silicon nitride film provided on a substrate for preventing contamination from the substrate, an insulating film containing a halogen element provided on the first silicon nitride film, and the insulating property. Source region, drain region, LD on the film
A thin film transistor having a semiconductor thin film provided with a D region and a channel formation region, a gate insulating film and a gate electrode, a second silicon nitride film provided on the thin film transistor for preventing external contamination, and the second thin film. A semiconductor device, comprising: an insulating film on a silicon nitride film, wherein the thin film transistor is sandwiched between the first silicon nitride film and the second silicon nitride film. Wherein said thin film transistor, the semiconductor device according to any one of claims 1 to 4, which is a coplanar type thin film transistor. Wherein said thin film transistor, the semiconductor device according to any one of claims 1 to 4 which is an inverted staggered thin film transistor. 7. A any one of claims 1 6, wherein the semiconductor thin film, wherein a single crystal semiconductor thin film, a polycrystalline semiconductor thin film or an amorphous semiconductor thin film. 8. according to any one of claims 1 to 7, wherein the semiconductor thin film, wherein a is an alloy film of a silicon film or silicon and germanium. 9. A any one of claims 1 8, wherein the halogen element, and wherein a gettering alkali ions.