JP3970891B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a thin film semiconductor device such as a thin film transistor having excellent reliability and mass productivity and high yield, and a method for manufacturing the same. As an application field of the present invention, for example, a driving circuit such as a liquid crystal display or a thin film image sensor, or a three-dimensional integrated circuit is constituted.

  Conventionally, a semiconductor integrated circuit has been mainly a monolithic type formed on a semiconductor substrate such as silicon. However, in recent years, attempts have been made to form it on an insulating substrate such as glass or sapphire. The reason is that the parasitic capacitance between the substrate and the wiring is reduced and the operation speed is improved, and especially the glass material such as quartz is not limited in size as a silicon wafer and is inexpensive. This is because the elements can be easily separated, and a latch-up phenomenon that causes a problem particularly in a CMOS monolithic integrated circuit does not occur. In addition to the above reasons, in a liquid crystal display or a contact image sensor, a thin film transistor (TFT) is formed on a transparent substrate because it is necessary to integrate a semiconductor element and a liquid crystal element or a light detection element. Etc. need to be formed.

  For these reasons, a thin film semiconductor element has been formed on an insulating substrate. As an example of a conventional thin film semiconductor element, a TFT is shown in FIG. As shown in the drawing, a film 503 made of silicon oxide or the like is formed as a passivation film on an insulating substrate 501, and a TFT is formed on the insulating film 501 independently of other TFTs. Like a MOSFET of a monolithic integrated circuit, a TFT includes a source (drain) region 507 and a drain (source) region 509, a channel formation region (also simply referred to as a channel region) 508 sandwiched therebetween, a gate insulating film 504, a gate electrode. 510 and a source (drain) electrode 511 and a drain (source) electrode 512. Further, an interlayer insulator 506 such as PSG is provided so that multilayer wiring is possible.

  The example of FIG. 5 is called a forward coplanar type, but there are other types of TFTs called reverse coplanar type, forward stagger type, and reverse stagger type depending on the arrangement of the gate electrode and the channel region. However, the details are left to other literature and will not be discussed further here.

  Even in monolithic integrated circuits, contamination with alkali ions such as sodium and potassium, or transition metal ions such as iron, copper, and nickel is a serious problem, and great care must be taken to prevent the entry of these ions. I have been. Even in TFTs, the problem of these ions is equally serious, and attention is paid to cleaning the production process so as to minimize contamination. In addition, measures are taken to prevent these elements from being contaminated.

The difference between thin film semiconductor elements and monolithic integrated circuits is that the concentration of contaminating ions in the substrate is relatively high. In other words, single crystal silicon used in monolithic integrated circuits has been produced so as to eliminate these harmful pollutant elements with the accumulation of technology over many years. Is 10 ¹⁰ cm ⁻³ or less.

  However, in general, the contamination element concentration of the insulating substrate for thin film semiconductor elements is not low. Of course, in the case of a single crystal substrate such as a spinel substrate or a sapphire substrate, it is theoretically possible to reduce the concentration of the foreign element that becomes the contamination source, but it is not practical from the profit side. In addition, if the quartz substrate is manufactured by a gas phase reaction using high-purity silane gas and oxygen as raw materials, it is ideally able to stop the invasion of foreign elements. When is taken in, it is difficult to exhale it. In addition, the substrate used for the liquid crystal display has a priority on cost, so it is necessary to use a low-priced one. In such a case, various kinds of foreign elements are used from the beginning to facilitate manufacture and processing. Contains. Some of these foreign elements themselves are not preferable for the semiconductor element, and in the process of adding these foreign elements, they may be mixed from the outside or may be included as impurities in the additive material.

  For example, TN glass is an inexpensive glass substrate, has good heat resistance, and has a thermal expansion coefficient close to that of silicon. Therefore, TN glass is preferable as a substrate for a liquid crystal display, but contains about 5% of lithium. A part of this lithium is ionized and penetrates into the semiconductor element as mobile ions, resulting in deterioration of the element. Further, it is difficult to produce a lithium having a purity of 99% or higher, and usually contains about 0.7% sodium. The ionization rate of sodium is about 10%, which is extremely large, and this sodium ion has a very serious effect on the characteristics of the device.

  In the conventional thin-film semiconductor element, as shown in FIG. 5, with respect to the penetration of the movable ions, silicon oxide or the like is used as a passivation film, and the interlayer insulator is made of PSG or BPSG. It has been addressed by gettering mobile ions. However, it has been difficult to sufficiently prevent contamination by these methods. An object of the present invention is to suppress deterioration of the element due to the entry of these contaminating elements and ions.

In the present invention, a film (blocking film) having a blocking action against mobile ions such as silicon nitride, aluminum oxide, and tantalum oxide is formed on the lower and upper parts of the thin film semiconductor element in order to suppress the contamination as described above. 1 × 10 ^{18 to} 5 × 10 ²⁰ pieces / cm ³ , preferably 1 × of a halogen element such as chlorine or fluorine on one or both of the semiconductor film (channel region) and the gate insulating film constituting the TFT. It is characterized by containing 10 ¹⁹ to 1 × 10 ²⁰ pieces / cm ³ . The halogen element is strongly bonded to mobile ions such as sodium in the semiconductor film or the insulating film, and has the effect of significantly reducing the effect.

  According to the present invention, a thin film semiconductor element such as a TFT having little influence of mobile ions such as sodium can be manufactured. Conventionally, it has become possible to form TFTs even on substrates on which elements could not be formed due to the presence of mobile ions. To implement the present invention, a coplanar type as shown in FIGS. 1 to 4, or a reverse coplanar type, staggered type, or reverse staggered type TFT may be used. In addition, since the present invention does not limit the operation of the thin film semiconductor device, the silicon of the transistor may be amorphous, polycrystalline, microcrystalline, or an intermediate state thereof. Obviously, it may be a single crystal or even a single crystal.

  A typical example of the present invention is shown in FIG. FIG. 1 shows a TFT using the present invention. That is, a first silicon nitride film 102 is formed on the insulating substrate 101 as a first blocking film. The first silicon nitride film has an effect of preventing contamination from the substrate. Then, a film 103 having good adhesion to a silicon material such as silicon oxide is formed on the first silicon nitride film. When the semiconductor film is formed directly on the first silicon nitride without forming the film 103 and a TFT is manufactured, the channel region becomes conductive by the trap level generated at the interface between the silicon nitride and the semiconductor material, and the TFT Will not work. Therefore, it is important to provide such a buffer.

  A TFT is formed on the film 103. The TFT has a source (drain) region 107, a drain (source) region 109, a channel region 108 sandwiched between them, a gate insulating film 104, and a gate electrode 110. Each of the source, drain, and channel regions of the TFT is formed of a monocrystalline, polycrystalline, or amorphous semiconductor material. As the semiconductor material, for example, silicon, germanium, silicon carbide, and alloys thereof can be used.

Then, a second silicon nitride film 105 is formed as a second blocking film so as to cover the TFT. Here, it is a feature of the present invention that the second silicon nitride film is formed after the fabrication of the TFT and before the electrodes are formed on the source and / or the drain. In the conventional technique, a silicon nitride film as a final passivation film is formed after electrode formation, but the present invention has a different purpose from the silicon nitride film formed in that sense. That is, the second silicon nitride film in the present invention is formed to enclose the TFT together with the first silicon nitride film, and is intended to prevent contamination in the electrode forming process after the TFT formation. To do. Therefore, a silicon nitride film may be formed as a final passivation film as in the prior art after forming a TFT and its associated electrodes and wirings according to the present invention.

  After the second silicon nitride film is formed, the interlayer insulating film 106 is formed by using an interlayer insulating material such as PSG, and the source (drain) electrode 111 and the drain (source) electrode 112 are formed. As described above, aluminum oxide or tantalum oxide may be used as the blocking film in addition to silicon nitride.

  In the example of FIG. 1, however, the gate insulating film extends far away, and there is a possibility that movable ions and the like enter the TFT from the end. An improvement of this is the example shown in FIG. 2, and since the gate insulating film is only on the TFT, there is no problem as shown in FIG. However, in this case, since the source and drain regions adjacent to the channel region are in contact with the silicon nitride film, the silicon nitride in this portion is polarized by the gate voltage or traps electrons to operate the TFT. May be disturbed.

  An example of overcoming that problem is shown in FIG. Here, the source region and the drain region adjacent to the channel region are not adjacent to the silicon nitride film. Therefore, the difficulties of silicon nitride polarization and electron traps are solved. However, when a self-alignment process using a gate electrode as a mask is adopted for forming the source and drain regions, in this example, as in the example of FIG. 1, an acceptor or donor element must be implanted through the gate insulating film. Therefore, if the ion implantation method is adopted, it is necessary to increase the acceleration energy of ions. At this time, as a result of fast ion implantation, the source and drain regions may be expanded by the secondary scattering.

  In FIG. 2, 201 is an insulating substrate, 202 is a first silicon nitride film, 203 is a buffer insulating film such as silicon oxide, 204 is a gate insulating film, 205 is a second silicon nitride film, and 206 is an interlayer insulating film. , 207 are source (drain) regions, 208 is a channel region, 209 is a drain (source) region, 210 is a gate electrode, 211 is a source (drain) electrode, and 212 is a drain (source) electrode. 3, 301 is an insulating substrate, 302 is a first silicon nitride film, 303 is a buffer insulating film such as silicon oxide, 304 is a gate insulating film, 305 is a second silicon nitride film, and 306 is an interlayer. An insulating film, 307 is a source (drain) region, 308 is a channel region, 309 is a drain (source) region, 310 is a gate electrode, 311 is a source (drain) electrode, and 312 is a drain (source) electrode.

In the present invention, when a silicon nitride film is used as the blocking film, x = 1.0 to x = 1.7 is suitable when expressed as SiN _x in the chemical formula, and in particular, x = 1.3 to x = 1. Good results have been obtained with 35 stoichiometric compositions (x = 1.33) or close to it. Therefore, in the present invention, it is better to form silicon nitride by the low pressure CVD method. However, it goes without saying that even if a silicon nitride film formed by plasma CVD or photo CVD is used, the reliability of the device is improved as compared with the case where the present invention is not used.

The low pressure CVD method, if an attempt is made to form a silicon nitride film, using dichlorosilane and (SiCl ₂ H ₂₎ and ammonia (NH ₃₎ as a source gas, 500 to 800 ° C. at a pressure 10 to 1000 Pa, preferably 550 to What is necessary is just to make it react at 750 degreeC. Of course, silane (SiH ₄ ) or tetrachlorosilane (SiCl ₄ ) may be used.

In the present invention, even when an aluminum oxide film or a tantalum oxide film is used, a better result is obtained with a composition close to the stoichiometric composition, Al ₂ O ₃ or Ta ₂ O ₅ . These coatings are formed by CVD or sputtering. For example, the aluminum oxide film may be obtained by oxidizing trimethylaluminum Al (CH ₃ ) ₃ with nitrogen oxide (N ₂ O, NO, NO ₂ ).

If the present invention is carried out more effectively, the concentration of hydrogen atoms in the semiconductor film of a thin film semiconductor device such as a TFT is not more than 4 times, preferably not more than 1 time, the concentration of halogen atoms to be added. In addition, it is desirable that the concentration of harmful elements such as carbon, nitrogen and oxygen is 7 × 10 ¹⁹ cm ⁻³ or less, preferably 1 × 10 ¹⁹ cm ⁻³ or less. Furthermore, sodium contained in the semiconductor film, lithium, for the mobile ions such as potassium, its concentration is desired to be at most 5 × 10 ¹⁸ cm ^-3. In order to achieve the above object, it is desirable to pay sufficient attention to the raw material gas and use a high purity gas of 5N or more. Furthermore, in the present invention, the use of an insulating substrate containing a large amount of a mobile ion source is borne in mind. However, if the present invention is implemented more effectively, the first silicon nitride in such a substrate is used. When forming the film, it is preferable to completely cover the periphery of the substrate with a silicon nitride film. In such a state, in the subsequent handling, the probability that mobile ions originating from the substrate are mixed into the element region can be significantly reduced.

FIG. 4 shows an example of forming a low impurity concentration drain (LDD), which is a known technique, using the present invention. First, a silicon nitride film 402 having a thickness of 50 to 1000 nm is formed on an insulating substrate 401 such as quartz or AN glass by a low pressure CVD method. At this time, as described above, if the back surface of the substrate is also covered with the silicon nitride film, the probability that mobile ions generated from the back surface will reach the surface in a later step is significantly reduced. It is also preferable for maintaining cleanliness. A buffering silicon oxide film 403 is similarly formed on the silicon nitride film by a low pressure CVD method to a thickness of 50 to 1000 nm. At this time, 3 to 6%, for example, about 5% by volume of hydrogen chloride (HCl), nitrogen fluoride (NF ₃ or N ₂ F ₄ ), chlorine (Cl ₂ ), fluorine (F ₂ ) ), Various halogen gases such as chlorofluorocarbon gas and carbon tetrachloride (CCl ₄ ) are mixed, and halogen elements such as chlorine and fluorine are taken into the obtained silicon oxide film.

  Since this halogen binds to alkali ions such as sodium and fixes sodium, a greater effect can be obtained in preventing sodium contamination. However, addition of excess halogen is not preferable because it roughens the film and impairs adhesion and surface flatness. In addition, when the coating is formed by a photo CVD method or a plasma CVD method instead of the low pressure CVD method, it is preferable that 2 to 5% by volume of the gas containing the halogen element is mixed in the source gas. Further, when the coating is formed by sputtering, 2 to 20% by volume of the halogen gas may be mixed in the sputtering atmosphere. In the case of the sputtering method, the gas composition in the atmosphere is difficult to be reflected in the composition of the film, so that the concentration needs to be slightly higher than in the case of the CVD method.

Next, an amorphous silicon film or a microcrystalline or polycrystalline silicon film is formed to a thickness of 20 to 500 nm by low pressure CVD, plasma CVD, or sputtering. Then, this is etched on the island. When forming this silicon film, a halogen element is preferably introduced into the film as in the case of forming the film 403 first. As in the case of the coating film 403, the halogen element may be introduced by mixing a halogen-containing gas into the atmosphere during film formation, or by introducing an ion implantation method after forming the film. Good. At this time, the concentration of the raw material gas is such that the concentration of the halogen element in the coating is 1 × 10 ^{18 to} 5 × 10 ²⁰ pieces / cm ³ , preferably 1 × 10 ¹⁹ to 1 × 10 ²⁰ pieces / cm ^3. Must be controlled.

  Furthermore, when the concentration of hydrogen atoms in the film is 4 times or less, preferably 1 or less, the halogen concentration, the effect of halogen addition is further improved. This effect is explained as follows. Hydrogen atoms are necessary for terminating the dangling bond of silicon, but the bond is weak and the bond is easily broken. On the other hand, the halogen element is strongly bonded to silicon. If there is an excess of hydrogen in the silicon (although it also has a lot of dangling bonds in the film), most of the halogens will bind to the silicon and consequently move ions that move through the film Can't getter. Therefore, it is presumed that the effect of halogen addition is small in silicon having a high hydrogen concentration, and that the effect of halogen addition is large in silicon having a low hydrogen concentration.

Further, in a semiconductor film such as silicon, the concentration of carbon, nitrogen, and oxygen as harmful elements other than mobile ions are all 7 × 10 ¹⁹ atoms / cm ³ or less, preferably 1 × 10 ¹⁹ atoms / cm ³ or less. It is desirable to be. This is because these elements are not removed by addition of halogen.

Furthermore, although mobile ions such as sodium, lithium, and potassium can be gettered by addition of halogen, the effect is canceled when they are present in excess, so the concentration of these mobile ions is 5 × 10 5 in all cases. It is desirable that it is ¹⁸ pieces / cm ³ or less.

  Now, a silicon oxide film having a thickness of 10 to 200 nm is formed as a gate insulating film on the thus formed silicon film by a low pressure CVD method or a sputtering method. At this time, as described above, the halogen material gas may be mixed in the raw material gas or the sputtering gas.

Then, a polycrystalline or microcrystalline silicon film doped with phosphorus to about 10 ²¹ cm ⁻³ is formed thereon by low pressure CVD or plasma CVD. Then, this silicon film and the gate insulating film (silicon oxide) thereunder are patterned to form a gate electrode 410 and a gate insulating film 404.

Further, ion implantation is performed in a self-aligned manner using this gate electrode as a mask, and a source (drain) region 407 and a drain (source) region 408 having relatively low impurity concentrations (about 10 ¹⁷ to 10 ¹⁹ cm ⁻³ ) are formed. . A portion where impurities are not implanted remains as a channel region 408. Thus, FIG. 4A is obtained.

  Next, as shown in FIG. 4B, a PSG film 413 is formed on the entire surface by low pressure CVD. Then, this is etched by a known directional etching to form a side wall 414 next to the gate electrode. Thereafter, ion implantation is performed again to form a source (drain) region 407a and a drain (source) region 409a having a high impurity concentration. The regions having a low impurity concentration are a source (drain) region 407b and a drain (source) region 409b to form an LDD. In this way, FIG. 4C is obtained.

  Thereafter, as shown in FIG. 4D, a silicon nitride film 405 is formed to a thickness of 50 to 1000 nm on the entire surface by low pressure CVD. Thereafter, for example, the silicon film is crystallized by low-temperature annealing at about 600 ° C., and the source and drain regions are activated. This step may be performed by laser annealing. In this way, an intermediate of TFT is obtained.

  The example of FIG. 4 is merely an example of the present invention, and it will be apparent that the present invention is not limited to the above steps. In the example of FIG. 4, as in the example of FIG. 3, there is no portion where the silicon nitride film, the gate electrode, and the source or drain region are adjacent to each other. That is, unlike the case of FIG. 2, since the side wall 414 exists, there is no problem which was anxious about FIG. Further, unlike FIG. 3, the donor and acceptor can be easily added without passing through the insulating film.

The characteristics of the TFT using the present invention will be described. The TFT used in this example is an LDD type TFT manufactured on a quartz glass substrate according to the process of FIG. First, a silicon nitride film 402 having a thickness of 100 nm is formed on the quartz glass substrate 401 and on the back surface of the substrate by a low pressure CVD method. Further, a silicon oxide film (low temperature oxide film (LTO film)) is continuously formed by a low pressure CVD method. 403) was formed to a thickness of 200 nm, and finally an amorphous silicon film was formed to a thickness of 30 nm by low pressure CVD. The maximum process temperature at this time was 600 ° C. In the above steps, the film was formed in a CVD apparatus including three reaction chambers arranged in succession. However, in forming the silicon oxide film and the amorphous silicon film, a halogen gas other than the material gas was used. 5 vol% of hydrogen chloride gas (HCl) was added as an additive gas for reaction. As a result, chlorine could be added into the silicon oxide film and the amorphous silicon film. In the analysis by secondary ion mass spectrometry, the concentration of chlorine in the silicon oxide film and the amorphous silicon film is 2.3 × 10 ¹⁹ atoms / cm ³ and 3.1 × 10 ¹⁹ atoms / cm ^{−, respectively.} It was ³ . As the source gas for the silicon nitride film, dichlorosilane (SiCl ₂ H ₂₎ and ammonia (NH _3), as the source gas for the silicon oxide film, disilane (Si ₂ H ₆₎ and oxygen (O ₂₎ Disilane and hydrogen chloride were used as source gases for the hydrogen chloride and amorphous silicon films, respectively. The purity was 6N. It was confirmed that the amount of hydrogen atoms in the silicon oxide film and the amorphous silicon film thus obtained was 1 × 10 ¹⁹ atoms / cm ³ or less. In addition, since the film formation was performed continuously without exposure to the atmosphere, it was confirmed that the concentration of carbon, nitrogen, and oxygen in the silicon film was 1 × 10 ¹⁸ atoms / cm ³ or less.

Next, the amorphous silicon film was patterned into an island shape. Then, a very thin portion of the surface of the amorphous silicon film, a thickness of 2 to 10 nm, was oxidized by an anodic oxidation method. Anodization was carried out by a constant voltage method at 10 to 50 ° C. using N methylacetamide (NMA) or tetrahydrofurfuryl alcohol (THF) to which KNO ₂ was added as an electrolyte and a platinum electrode as a cathode. After completion of the anodic oxidation, annealing was performed at 600 ° C. for 12 hours in an argon atmosphere. Thereafter, a silicon oxide film having a thickness of 100 nm was formed by sputtering. Here, the sputtering atmosphere was a mixed gas of oxygen and argon or other rare gas and hydrogen chloride, and the partial pressure of oxygen was 80% or more. The concentration of hydrogen chloride gas was 10%. In sputter deposition, defects are generated in the underlying film due to sputtering impact. For example, when the base is a silicon film, oxygen atoms are implanted into the silicon, and the oxygen concentration increases. In such a state, silicon has a large number of extreme levels. That is, the boundary between silicon and silicon oxide is not clear. However, if a thin anodic oxide film is formed in advance as in this embodiment, since silicon oxide already exists during sputtering, mixing of atoms as described above is avoided, and the silicon film and the oxide film are oxidized. The boundary of the silicon film is maintained.

After the formation of this silicon oxide film, an n ⁺ type microcrystalline silicon film containing about 10 ²¹ cm ^{−3 of} phosphorus was formed to a thickness of 300 nm by low pressure CVD. The maximum process temperature for the above film formation was 650 ° C. Thereafter, the gate electrode was patterned to form a gate electrode 410 and a gate insulating film 404. Further, arsenic ions were implanted by 2 × 10 ¹⁸ cm ⁻³ by ion implantation to form source and drain regions 407 and 409. Thus, FIG. 4A was obtained.

Next, a PSG film 413 was formed by a low pressure CVD method as shown in FIG. 4B, and a sidewall 414 shown in FIG. 4C was formed by directional etching. Further, arsenic ions were implanted into the regions 407a and 409a by 5 × 10 ²⁰ cm ⁻³ by ion implantation.

  Thereafter, a silicon nitride film 405 was formed on the entire surface by a low pressure CVD method. Thus, FIG. 4D was obtained. Thereafter, annealing was performed in vacuum at 620 ° C. for 48 hours to activate the regions 407a, 407b, 408, 409a, and 409b. Then, a PSG film was formed on the entire surface as an interlayer insulator by a low pressure CVD method, holes for electrodes were formed, and aluminum electrodes were formed in the source region and the drain region. Finally, a silicon nitride film was again formed by a low pressure CVD method for the purpose of passivation.

  The TFT formed in this way was extremely reliable. It has been shown that the operation characteristics of the element do not change even by so-called bias-temperature treatment (BT treatment). The BT process is a process in which a voltage is applied between the source and drain and the gate electrode in a heated state. If the element is a normal element, no problem occurs. For example, in an element including mobile ions, Changes in characteristics can be seen. This is shown in FIG.

FIG. 6A shows a TFT in which mobile ions are present in the gate insulating film and in the channel region. Since mobile alkali ions (shown as A ^{+ in the} figure) are present in the channel region, and the alkali ions serve as donors, the channel region is weakly N-type (N ⁻ -type). This state is referred to as state 1. When a positive bias voltage is applied between the gate electrode and the source / drain of this TFT as shown in FIG. 6B, first, mobile ions (positive ions) in the channel region move away from the gate electrode, and the channel region becomes intrinsic. (I type). This state is referred to as state 2. As a result, the I _D (drain current) -V _G (gate voltage) characteristic of the TFT moves to the right as shown in FIG.

However, when mobile ions are also present in the gate insulating film, the mobile ions gather at the lower part of the gate electrode (on the channel region side) due to the bias voltage applied to the gate electrode. As a result, the channel region has a positive electric field. You will feel. Therefore, there is an electron in the channel region, that is, it becomes weakly N-type again. When this state as 3, as shown in FIG. _{6 (E), I D -V} G characteristics curve from state 2 to state 3 is moved to the left. Eventually, due to the bias voltage, the TFT characteristics are shifted to the right compared to the first.

  On the other hand, when a negative bias is applied, mobile ions gather in the channel region. As a result, the channel region becomes N-type and the drain current cannot be controlled by the gate voltage.

In this example, specifically, the gate voltage-drain current characteristics of the TFT were measured immediately after fabrication at room temperature (V _B = 0), and then a voltage of +20 V was applied to the gate electrode at 150 ° C. for 1 hour. The gate voltage-drain current characteristic of the TFT was measured at room temperature (V _B = + 20 V), and then a voltage of −20 V was applied to the gate electrode again at 150 ° C. for 1 hour, and then the gate voltage of the TFT at room temperature. voltage - drain current characteristics measured (V _B = -20V), examining the change in the threshold voltage of the TFT.

FIG. 7B shows characteristics of the TFT manufactured by the method described above. As described above, the bias voltage V _B is not affected at all by the characteristics, and as a result of precise measurement, the variation of the threshold voltage is 0.2 V or less.

On the other hand, in FIG. 7A, the silicon nitride films 402 and 405 are not provided, and the halogen concentration of any film of the TFT is 1 × 10 ¹⁴ cm ⁻³ or less. Except for this point, it was fabricated by the same process as the method shown in this example, but the characteristic greatly depends on V _B as apparent from the figure. From the fluctuation range of the threshold voltage in FIG. 7B, the amount of mobile ions in the gate electrode of the TFT manufactured in this example is estimated to be about 8 × 10 ¹⁰ cm ⁻³ . After the above measurements, the concentrations of sodium, potassium, and lithium in the silicon film (channel region) and the gate insulating film of the TFT fabricated in this example were examined, and found to be 3 × 10 ¹⁷ cm ⁻³ and 7 × 10, respectively. ^{It was 15} cm ⁻³ and 5 × 10 ¹⁵ cm ⁻³ . In spite of the presence of such a large amount of alkali element, it is assumed that the amount of mobile ions is small because it is immobilized by halogen (in this case, chlorine). In the TFT manufactured for comparison, when the concentrations of sodium, potassium, and lithium were examined, a large amount of 7 × 10 ¹⁸ cm ⁻³ , 2 × 10 ¹⁶ cm ⁻³ , and 4 × 10 ¹⁹ cm ⁻³ was obtained. It was included in. From this, the blocking effect by the silicon nitride film of the present invention is also estimated. That is, by providing a silicon nitride film as in the present invention and adding a halogen element to the TFT (in this case, the silicon film including the channel region and the gate insulating film), the characteristics of the TFT are remarkably improved and the reliability is improved. It was shown that it is possible to improve the performance.

An example of a TFT according to the present invention is shown. An example of a TFT according to the present invention is shown. An example of a TFT according to the present invention is shown. An example of manufacturing a TFT according to the present invention will be described. An example of a conventional TFT is shown. The influence of the movable ions on the TFT characteristics is shown. The characteristics of the TFT using the present invention and the TFT not using it are shown.

Explanation of symbols

Reference Signs List 101 insulating substrate 102 first blocking film 103 buffer insulating film 104 gate insulating film 105 second blocking film 106 interlayer insulating film 107 source (drain) region 108 channel region 109 drain (source) region 110 gate electrode 111 source (drain) ) Electrode 112 Drain (source) electrode

Claims (11)

An insulating substrate containing mobile ions;
A silicon nitride film formed in contact with the insulating substrate;
A silicon oxide film containing a halogen element formed on and in contact with the silicon nitride film;
A semiconductor film formed on and in contact with the silicon oxide film;
A gate insulating film containing a halogen element formed on and in contact with the semiconductor film;
A gate electrode formed on the gate insulating film,
A semiconductor device, wherein a channel formation region, a source region, and a drain region are provided in the semiconductor film. An insulating substrate containing mobile ions;
A silicon nitride film formed in contact with the insulating substrate;
A silicon oxide film containing a halogen element formed on and in contact with the silicon nitride film;
A semiconductor film formed on and in contact with the silicon oxide film;
A gate insulating film containing a halogen element formed on and in contact with the semiconductor film;
A gate electrode formed on the gate insulating film,
A semiconductor device, wherein a channel formation region, a source region, a drain region, and an LDD region are provided in the semiconductor film. An insulating substrate containing mobile ions;
A silicon nitride film formed in contact with the insulating substrate;
A first silicon oxide film containing a halogen element formed on and in contact with the silicon nitride film;
A semiconductor film containing a halogen element formed on and in contact with the first silicon oxide film;
A second silicon oxide film containing a halogen element formed on and in contact with the semiconductor film;
A gate electrode formed on the semiconductor film via the second silicon oxide film,
A semiconductor device, wherein a channel formation region, a source region, and a drain region are provided in the semiconductor film. An insulating substrate containing mobile ions;
A silicon nitride film formed in contact with the insulating substrate;
A first silicon oxide film containing a halogen element formed on and in contact with the silicon nitride film;
A semiconductor film containing a halogen element formed on and in contact with the first silicon oxide film;
A second silicon oxide film containing a halogen element formed on and in contact with the semiconductor film;
A gate electrode formed on the semiconductor film via the second silicon oxide film,
A semiconductor device, wherein a channel formation region, a source region, a drain region, and an LDD region are provided in the semiconductor film. 5. The semiconductor device according to claim 3 , wherein the concentration of the halogen element in the semiconductor film is 1 × 10 ^{18 to} 5 × 10 ²⁰ atoms / cm ³ .   6. The semiconductor device according to claim 1, wherein the halogen element is chlorine.   6. The semiconductor device according to claim 1, wherein the halogen element is fluorine.   8. The semiconductor device according to claim 1, wherein the semiconductor film is made of an amorphous, polycrystalline, or single crystal semiconductor.   9. The semiconductor device according to claim 1, wherein the semiconductor film is made of silicon, germanium, or an alloy of silicon and germanium. 10. The semiconductor device according to claim 1, wherein the silicon nitride film is represented by a chemical formula SiN _x (1.0 ≦ x ≦ 1.7). 11.   11. The semiconductor device according to claim 1, wherein the silicon nitride film has a thickness of 50 to 1000 nm.

Images