JP3469825B2 - PLL circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL circuit, and more particularly to a line lock type PLL circuit which generates an operation clock synchronized with a horizontal synchronizing signal of a television receiver.

[0002]

2. Description of the Related Art Generally, a PLL circuit compares the phase difference between a reference signal and a comparison signal, outputs the comparison result in positive and negative pulse forms, smooths this pulse signal with a loop filter, and supplies it to a voltage controlled oscillator. The frequency of the comparison signal is locked to the frequency synchronized with the reference signal. And as the low-pass filter used for the loop filter, a non-inverting type using passive components such as CR,
There is an inverting type that uses an active component such as an OP amplifier and is selectively used according to the application (see Transistor Technology June 1999 page 239).

[0003]

By the way, it is desired to selectively use an inverting type and a non-inverting type as a loop filter according to the application, but since the polarity of the signal is inverted between the inverting type and the non-inverting type, There is a problem that the circuit design work is complicated because it is necessary to design the circuit according to them. Therefore, an object of the present invention is to provide a PLL circuit in which an inverting type filter and a non-inverting type filter can be switched and used, and the handling thereof is good.

[0004]

The PLL circuit of the present invention is
As described in claim 1, a phase comparator that compares the phase difference between the reference signal and the comparison signal and selectively outputs positive and negative pulses based on the comparison result; and a smoothed output of this comparator A loop filter having a plurality of inverting and non-inverting filters, a voltage controlled oscillator that generates a clock signal having a frequency corresponding to the output voltage of the filter, and the comparison signal obtained by dividing the clock signal of the oscillator. In the PLL circuit including a frequency divider, the comparator is characterized by including switching means for switching between positive and negative polarities of its output.

According to another aspect of the PLL circuit of the present invention, a voltage-controlled oscillator, a frequency divider for dividing a clock signal output from the oscillator, a horizontal synchronizing signal, and the frequency divider. In a line-lock type PLL circuit comprising a phase comparator for comparing and outputting the phase difference of the frequency signals and a loop filter for smoothing the output of the comparator and supplying a voltage to the voltage controlled oscillator, the comparator Is equipped with a switching means for switching between positive and negative of its output, and the loop filter is provided with a plurality of inverting type and non-inverting type filters so that they can be switched.

[0006]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings by taking a line-lock type PLL circuit for generating a clock signal synchronized with a horizontal synchronizing signal of a television as an example.

The PLL circuit 1 compares the phases of the reference signal and the comparison signal, obtains the phase difference, and outputs the phase difference.
A loop filter 3 for smoothing and outputting the output of this comparator, a voltage controlled oscillator 4 for generating a clock signal CL1, and a clock signal CL for dividing the clock signal CL1.
A frequency divider 5 for generating 2 is provided.

The phase comparator 2 has a horizontal synchronizing signal HS supplied from a synchronizing signal separating circuit (not shown) as a reference signal.
Is input, the divided clock signal CL2 output from the frequency divider 5 is input as a comparison signal, and the phase comparison unit 6 and the output stage 7 for comparing the phases of these signals are provided. Comparison unit 6
Is a pulse-shaped signal corresponding to the phase difference, UP and DOWN 2
Output from the two output terminals to the output stage 7. The output stage 7 is U
The polarity of the pulsed output output from the P and DOWN output terminals is inverted, and then both are combined and output. Further, the output stage 7 is provided with a polarity switching circuit for switching the polarity of the two outputs of the comparison section 6 by the control signal LPFCONT. The output stage 7 including this switching circuit has two three-state buffers B
The two outputs of the comparison unit 6 are connected to the respective control terminals of F1 and BF2, and the control signal LPFCONT is input to the input of one of the three-state buffers BF1 and the control signal LPFCONT is input to the input of the other buffer BF2 via the inverter INV. It is configured to be connected. The three-state buffers BF1 and BF2 are held in an open state (high impedance state) while no signal is applied to the control terminal, but when the signal is applied to the control terminal, the input signal is output as it is. .

The loop filter 3 includes two types of filters, a non-inverting low-pass filter LPF1 in which the input and output signal polarities are not inverted and an inverting low-pass filter LPF2 in which the signal polarities are inverted. Then, one of these filters LPF1 and LPF2 can be selected by the switching circuit 8. The switching circuit 8 is configured to execute filter switching control in conjunction with the polarity switching of the output stage 7 by the control signal LPFCONT. Here, the non-inverting type is shown in FIG.
A low-pass filter as shown in Fig.
Although the low-pass filter as shown in (b) is adopted, other forms can be adopted. Figure
The low-pass filters 2 (a) and 2 (b) are provided with a bias circuit VB that gives a predetermined intermediate voltage when the output of the output stage 7 is in a high impedance state.

The voltage controlled oscillator 4 has an oscillation frequency set based on the output voltage of the loop filter 3, and in this example, generates a pulsed clock signal CL1 of about 20 MHz. The clock signal CL1 output from the voltage controlled oscillator 4 is supplied to the frequency divider 5 and used as the digital reference clock signal OSC of the display circuit. The frequency divider 5 is a television system such as NTSC and PA.
The frequency division ratio is set according to L, and the clock signal CL2 of around 15 KHz is generated.

Next, the operation of the above configuration will be described.
First, as the loop filter 3, a non-inverting filter L
When selecting PF1, control signal LPFCO
Hold NT at L level. With this signal, an L level signal is input to one of the three-state buffers BF1 and an H level signal is supplied to the other buffer LPF2 via the inverter INV. Loop filter 3
Selects the non-inverting filter LPF1 according to the control signal LPFCONT. The voltage controlled oscillator 4 generates a clock signal CL1 having a frequency determined by the voltage supplied from the filter 3 and outputs it to the frequency divider 5. The frequency divider 5 outputs to the phase comparator 2 the clock signal CL2 after frequency division based on a preset frequency division ratio. The phase comparator 2 obtains the phase difference between the signal CL2 from the frequency divider 5 and the horizontal synchronizing signal HS, and generates a pulse signal from one output terminal. With this pulse-shaped signal, the three-state buffers BF1 and BF2 of the output stage 7 are
One of them becomes an active state, and an L or H level pulse signal is output to the filter 3. The output voltage of the filter LPF1 changes due to this signal, and the oscillation frequency of the voltage controlled oscillator 4 changes accordingly. This kind of operation
This is repeated until there is no phase difference between the two input signals of the phase comparator. When the phase difference disappears, the PLL circuit 1
Becomes a locked state, the frequency of the voltage controlled oscillator 4 is kept constant, and this is supplied to the peripheral circuit as an operating clock signal OSC.

On the other hand, when the filter 3 is switched from one filter LPF1 to the other filter LPF2 to operate it when the television of a different system is used, the control signal LPFCONT is switched from the L level to the H level. By this switching, the polarities of the signals input to the two three-state buffers BF1 and BF2 are inverted, and the loop filter 3 causes the one filter LPF to pass through.
The filter LPF2 is switched from 1 to the other filter. Although this filter LPF2 is an inverting type, as described above, since the output of the phase comparison unit 6 is inverted in polarity at the output stage 7,
The output of the filter 2 is output with the same polarity as that of the filter LPF1. Therefore, even if the non-inverting filter and the inverting filter are switched and used, the circuit can be designed without paying attention to the change in the polarity, and the circuit design can be facilitated. Further, switching of the output stage 7 and switching of the loop filter 3 are controlled by the control signal LPFCONT.
Since it is performed in conjunction with, it is possible to improve the switching workability.

In the above embodiment, the polarity inversion of the output of the comparator 2 and the switching of the filter 3 are performed by the control signal LPFCO.
Although it is performed in conjunction with NT, it can be configured to switch without interlocking.

[0014]

As described above, according to the present invention, since the polarity of the comparator output is switched and outputted, the inverting type filter and the non-inverting type filter are switched and used. The signal processing at this time becomes easy, and the circuit becomes easy to handle.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing an embodiment of the present invention.

2A and 2B are circuit diagrams showing a configuration example of a filter of the same embodiment.

[Explanation of symbols]

1 PLL circuit 2 Phase comparator 3 loop filter 4 Voltage controlled oscillator 5 frequency divider 6 Phase comparator 7 output stages 8 switching circuit

Continuation of the front page (56) Reference JP-A-5-235758 (JP, A) JP-A-7-226679 (JP, A) JP-A-6-140840 (JP, A) (58) Fields investigated (Int .Cl. ⁷ , DB name) H03L 1/00-7/26

Claims (2)

(57) [Claims] 1. A phase comparator that compares the phase difference between a reference signal and a comparison signal and selectively outputs positive and negative pulses based on the comparison result, and an inverting type that smoothes and outputs the output of this comparator. A loop filter including a plurality of non-inverting type filters, a voltage controlled oscillator that generates a clock signal having a frequency according to the output voltage of the filter, and a frequency divider that divides the clock signal of this oscillator to obtain the comparison signal. And a switching circuit for switching between positive and negative polarities of the output of the comparator circuit. 2. A voltage controlled oscillator, a frequency divider for frequency-dividing a clock signal output from the oscillator, and a phase comparator for comparing and outputting a phase difference between a horizontal synchronizing signal and a frequency-divided signal of the frequency divider. And a loop filter for smoothing the output of the comparator and applying a voltage to the voltage controlled oscillator, the line lock type PLL circuit having the switching means for switching between positive and negative of the output. The loop filter is provided with a plurality of inverting and non-inverting filters, which are switchable, and a line-lock type PLL circuit.