JP3469728B2 - Current-voltage conversion circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a current-voltage conversion circuit which has a stable operation at high frequency input.

[0002]

2. Description of the Related Art In a CD reproducing apparatus, reading of data on an optical disk is performed by irradiating the optical disk with laser light and converting it into an electric signal corresponding to the intensity of light reflected by the optical disk. Conventionally, a photodiode is used as an element that converts this reflected light into an electric signal, and the photodiode generates an output current according to the intensity of the reflected light. The output current of the photodiode is
Although the signal is transmitted to the signal processing circuit in the subsequent stage, since the signal processing circuit generally performs signal processing in the voltage mode, an I / V conversion circuit for converting the output current of the photodiode into voltage is required. In the case where such a photodiode and an I / V conversion circuit are integrated on the same substrate, it has been conventionally required to use the structure shown in FIG.
It is configured like.

In FIG. 2, first, the photodiode P
A case will be described where D is not irradiated with light and the photodiode PD does not generate an output current. The reference voltage Vref is applied to the base of the transistor 1 via the resistor 2. When the base voltage Vb3 of the transistor 3 is higher than the base voltage Vb1 of the transistor 1, since the transistors 1 and 3 are differentially connected, the collector current of the transistor 1 decreases and the collector current of the transistor 3 increases. Since the output current of the current mirror circuit 4 for inverting the collector current of the transistor 1 decreases, the transistor 5
The base current of is reduced. Since the transistor 5 current-amplifies this base current, the emitter current of the transistor 5 also decreases due to the decrease in the base current. Transistor 5
The emitter current is fed back to the base of the transistor 3 via the feedback resistor 6. The feedback current is converted into a voltage by the feedback resistor 6, and the base voltage Vb3 of the transistor 3 drops due to the drop of the emitter current of the transistor 5. Therefore,
When the base voltage Vb3 of the transistor 3 becomes higher than the base voltage Vb1 of the transistor 1, the base voltage Vb3 tends to decrease.

On the contrary, the base voltage Vb3 of the transistor 3
Is lower than the base voltage Vb1 of the transistor 1, the collector current of the transistor 1 increases and the collector current of the transistor 3 decreases. The output current of the current mirror circuit 4 increases and the base current of the transistor 5 increases. When the base current of the transistor 5 increases, the emitter current of the transistor 5 also increases and the base voltage Vb3 of the transistor 3 rises. Therefore, when the base voltage Vb2 of the transistor 3 becomes lower than the base voltage Vb1 of the transistor 1, the base voltage Vb3 tends to increase.

Thus, the negative feedback is applied to the base of the transistor 3, so that the circuit of FIG. 2 is in a balanced state, and the base voltage Vb3 of the transistor 3 becomes equal to the base voltage Vb1 of the transistor 1. Here, if the value of the resistor 6 connected to the base of the transistor 3 is the same as the value of the resistor 2, the base currents of the transistors 1 and 3 are equal in the equilibrium state. An output voltage equal to the reference voltage Vref is generated.

In the equilibrium state, the photodiode PD
When light is emitted to the photodiode, an output current I flows through the photodiode PD. Since the base current of the transistor 3 is constant in the balanced state, the output current I of the photodiode PD all flows through the resistor 6. When the value of the resistor 6 is R due to the voltage drop of the resistor 6, an output voltage (Vref + I × R) is generated from the output terminal OUT.

[0007]

By the way, when the conventional circuit of FIG. 2 is integrated, the output voltage of the output terminal OUT of the circuit of FIG. 2 is transmitted to the signal processing circuit of the subsequent stage using the wire. Generally, the wire has a parasitic capacitance, and it can be considered that the capacitor C1 is inserted between the output terminal and the ground. The time constant of the parasitic capacitance C1 causes a phase delay in the feedback signal flowing from the transistor 5 to the resistor 6. This phase delay is likely to occur particularly in a high-frequency input signal, which deteriorates the frequency characteristic of the current-voltage conversion circuit.

When the conventional circuit of FIG. 2 is integrated, a parasitic capacitance C2 is also generated between the base and emitter of the transistor 5. When the frequency of the input signal increases, the output current of the transistor 3 comes to pass through the parasitic capacitance between the base and the emitter of the transistor 5, and the feedback signal has a phase delay due to the time constant of the capacitor. Further, there is a problem that oscillation occurs due to the phase delay of the feedback signal. Microscopically, the circuit of FIG. 2 tends to be in equilibrium, and the base voltage of the transistor 3 varies with the input current. At that time, if the phase of the feedback signal is delayed due to the time constant of the parasitic capacitance and the input current and the feedback signal are in phase, there is a risk of oscillation.

[0009]

According to the present invention, there is provided a first transistor having a base to which a reference voltage is applied, a second transistor differentially connected to the first transistor, and collectors of the first and second transistors. A load connected to the load, a first emitter follower circuit to which an output signal generated in the load is applied, an output signal generated in the load via a resistor, and an output of the first emitter follower circuit A signal includes a second emitter follower circuit via a capacitor, and a feedback resistor for returning an output signal of the second emitter follower circuit to the base of the second transistor, and an input current is applied to one end of the feedback resistor. Supply,
An output voltage is obtained from the other end of the feedback resistor.

Further, a photodiode having a cathode connected to one end of the feedback resistor is constructed. According to the present invention, when the frequency of the input signal is high, the capacitor conducts and the first and second transistors are substantially Darlington connected. As a result, the current supply amount of the second transistor becomes large, and the charge / discharge time constant of the parasitic capacitance can be apparently reduced.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a diagram showing an embodiment of the present invention, in which 7 is a transistor forming a first emitter follower circuit, the base of which is supplied with the collector current of the transistor 3, and 8 is a second transistor. A transistor which constitutes an emitter follower circuit and whose base is supplied with the collector current of the transistor 3 through the resistor 9, 10 is a capacitor connected between the emitter of the transistor 7 and the base of the transistor 8, and 11 is a transistor of the transistor 8. It is a feedback resistor for returning the output signal. In FIG. 1, the same elements as those of the conventional example of FIG. 3 are designated by the same reference numerals.

In FIG. 1, the input signal is the capacitor 1
The operation when the frequency is lower than the cutoff frequency of 0 will be described.
Since the transistors 1 and 3 are differentially connected, a signal a having a phase opposite to the input signal is generated from the connection point between the collector of the transistor 3 and the current mirror circuit 4. The current mirror circuit 4 forms a load on the transistors 1 and 3 which are differentially connected. The signal a is current-amplified by the transistor 7,
The output signal b is generated from the emitter of the transistor 7.
Since the frequency of the amplified signal b from the transistor 7 is lower than the cutoff frequency of the capacitor 10, the amplified signal b cannot pass through the capacitor 12. Therefore, the amplified signal b is only supplied to the constant current source 12.

The signal a is also supplied to the base of the transistor 8 via the resistor 9 and current-amplified. The output signal c generated from the emitter of the transistor 8 is the feedback resistor 11
Is supplied to the base of the transistor 3 via. Signal a
Is negatively fed back through the transistor 8 and the resistor 11, so that the base voltage of the transistor 3 becomes equal to the base voltage of the transistor 1 as in the conventional case. The photodiode PD generates an output voltage (Vref + R × I) at the output terminal OUT by IV conversion.

At this time, parasitic capacitance is generated between the bases and the emitters of the transistors 7 and 8 and the wire for transmitting the output voltage of the output terminal OUT, but the input signal has a low frequency. Therefore, since the time constant of the parasitic capacitance follows the frequency of the input signal, no phase delay occurs in the feedback signal flowing through the transistor 8 and the feedback resistor 11. Next, the operation when the input signal has a higher frequency than the cutoff frequency of the capacitor 10 will be described. A signal a is generated from the connection point between the collector of the transistor 3 and the current mirror circuit 4 in accordance with the input signal, and the signal a is generated by the transistor 7
The output signal b is generated from the emitter of the transistor 7 due to the current amplification by. Since the frequency of the input signal is higher than the cutoff frequency of the capacitor 10, the signal b is supplied to the base of the transistor 8 via the capacitor 10. Signal b is the emitter current of transistor 7,
Since the signal a is the base current of the transistor 7, the magnitude of the signal b is sufficiently larger than that of the signal a.
Are driven substantially by the signal b. As a result, it can be said that the transistors 7 and 8 are substantially Darlington-connected, so that an output current of the magnitude of the square of the signal a is generated from the emitter of the transistor 8. Transistor 8
A part of the output signal from is fed back to the base of the transistor 3 via the feedback resistor 11. Signal a is transistor 7
And 8 and the resistor 11 are negatively fed back, the base voltage of the transistor 3 is the same as in the conventional case.
Equal to the base voltage of. The output current I of the photodiode PD is IV converted, and an output voltage (Vref + R × I) is generated at the output terminal OUT.

Here, the emitter current of the transistor 8 is also supplied to the parasitic capacitance of the wire. The parasitic capacitance generated in the wire may cause a phase delay in the feedback signal because the input signal has a high frequency. However, since the emitter current of the transistor 8 is sufficiently large, the current supplied to the parasitic capacitance is large, and the charging / discharging capability of the parasitic capacitance is high. As a result, the time constant of the parasitic capacitance can be apparently reduced, so that the time constant can follow the high frequency input signal and prevent the occurrence of a phase delay in the feedback signal. The base voltage of the transistor 3 becomes equal to the base voltage of the transistor 1 by negatively feeding back the signal a via the transistors 7 and 8 and the resistor 11. Therefore, even if a high frequency input signal is generated, if the output current I is generated in the photodiode PD, a phase delay is not generated,
An output voltage (Vref + R × I) can be generated at the output terminal OUT.

Further, the parasitic capacitance generated in the transistors 7 and 8 can be regarded as being connected in series when the signal b from the transistor 7 passes through the capacitor 10. Therefore, the added capacitance of the parasitic capacitance becomes smaller than the value of each parasitic capacitance, and the adverse effect of the parasitic capacitance can be reduced.

[0017]

According to the present invention, when the frequency of the input signal is high, the capacitor conducts and the third and fourth transistors are substantially Darlington-connected. As a result, the current supply amount of the second transistor increases, and the charge / discharge time constant of the parasitic capacitance can be apparently reduced. Therefore, the influence of the parasitic capacitance can be removed, and the phase delay of the feedback signal from the fourth transistor to the second transistor can be reduced, so that the frequency characteristic of the current-voltage conversion circuit can be improved and the oscillation can be suppressed. Can be prevented.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a conventional example.

[Explanation of symbols]

1 transistor 2 resistance 3 transistors 4 Current mirror circuit 7 transistors 8 transistors 9 resistance 10 condenser 11 Feedback resistor

─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-6-303050 (JP, A) JP-A-5-14071 (JP, A) JP-A-1-183207 (JP, A) JP-B-46- 17803 (JP, B1) (58) Fields investigated (Int.Cl. ⁷ , DB name) H03F 3/45

Claims (2)

(57) [Claims] 1. A first transistor having a base to which a reference voltage is applied, a second transistor differentially connected to the first transistor, a load connected to collectors of the first and second transistors, and A first emitter follower circuit to which an output signal generated in a load is applied; and an output signal generated in the load is applied via a resistor, and an output signal of the first emitter follower circuit is applied via a capacitor. that a second emitter follower circuit, and a feedback resistor for feeding back to the base of the second transistor an output signal of the second emitter-follower circuit, supplies an input current to one end of the feedback resistor, the feedback A current-voltage conversion circuit characterized in that an output voltage is obtained from the other end of the resistor. 2. The current-voltage conversion circuit according to claim 1, wherein a photodiode having a cathode connected to one end of the feedback resistor is formed.