JPH1013361A - Optical receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make a high speed response characteristic and yield strength against the same code consecution compatible at the start of input of data inverted to each other and high speed tracking to a signal level changing instantaneously by providing an amplitude equalization circuit to a post-stage of a preamplifier circuit. SOLUTION: A photo diode PD converts an optical signal hν into a current signal Iin and the current signal Iin is given to a preamplifier circuit 1. The preamplifier circuit 1 converts the current signal Iin into a voltage signal and provides a signal voltage Vdata and a DC level Vpeak corresponding to the peak level of the signal voltage to an amplifier equalization circuit 2. Then a bottom level detection circuit 21 of the amplifier equalization circuit 2 detects a bottom level of the signal voltage, an intermediate level generating circuit 22 generates an output level Vbottom of the bottom level detection circuit 21 and an intermediate level Vref of the DC level Vpeak being a peak level of the signal voltage received from the preamplifier circuit 1 and a limiter amplifier circuit 23 uses the intermediate level Vref as a threshold level to amplify the signal voltage Vdata.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical receiver for optical communication.

[0002]

2. Description of the Related Art In an optical digital communication system, an optical receiver for amplifying an attenuated signal is indispensable.

In an optical receiver, a function of converting an optical signal into a current signal by a light receiving element (photodiode), converting the current signal into a voltage signal, and amplifying the voltage signal to a voltage amplitude capable of distinguishing logic is required. Is done.

FIG. 7 is a block diagram showing a circuit of a conventional optical receiver.
Is converted to a current signal Iin, and the current signal Iin is input to the preamplifier circuit 1. The preamplifier circuit 1 converts the current signal Iin into a voltage signal, and inputs the signal voltage Vdata to the limiter amplifier circuit 23 of the amplitude equalization circuit 2. The limiter amplifier circuit 23 amplifies the signal voltage Vdata using the intermediate level Vref supplied from the voltage source E as a fixed threshold, and obtains output data at the output terminal 25.

That is, conventionally, low frequency components of an input signal are cut off, the DC level is kept constant regardless of the input signal level, and a signal voltage is amplified by a limiter amplifier circuit based on a fixed threshold level. I was

[0006]

However, in the above-described conventional example, there is a problem that the high-speed response characteristic at the start of data input and the continuity of the same code cannot be compatible.

FIG. 8 is a diagram showing the relationship between each voltage level change (1) and the output data waveform (2) at the start of data input when the low-frequency cutoff frequency is set high. FIG. FIG. 8 is a diagram showing a relationship between each voltage level change (1) at the start of data input and an output data waveform (2) when the frequency is set low. The higher the low-frequency cutoff frequency, the faster the DC level fluctuation, the closer the intermediate level of the input data Vdata to the fixed threshold level Vref in a short time, and the longer the distortion deterioration period at the start of data input. Can be shortened.

FIG. 9 is a diagram showing the relationship between each voltage level change (1) and the output data waveform (2) during one continuous operation when the low-frequency cutoff frequency is set high. FIG. 11 shows the low-frequency cutoff. Each voltage level change during one continuous operation when the frequency is set low
FIG. 3 is a diagram showing a relationship between (1) and an output data waveform (2). FIG.
In FIG. 11, since the DC level change is fast, the logic of the output data is inverted during one continuous operation. On the other hand, FIG. 11 shows that the DC level change is slow and has high tolerance to the same sign continuous.

As can be seen from the above description, in the conventional example, when the low cutoff frequency is set high, a high-speed response characteristic at the start of data input can be obtained, but the homo-code continuity proof strength decreases. Contrary to the above, when the low cutoff frequency is set low, the homo-code continuity tolerance is improved, but there is a trade-off relationship that the high-speed response characteristic at the start of data input is lost.

It is an object of the present invention to provide such a low-band cutoff optical receiver which generally achieves both a high-speed response characteristic at the start of data input and a continuity with the same code, and a signal which changes instantaneously. It is an object of the present invention to provide an optical receiver capable of following a level at a high speed.

[0011]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems and to achieve the object, the present invention provides a preamplifier circuit for outputting a signal voltage and a DC potential corresponding to the peak value of the signal voltage, and a signal voltage circuit provided at a subsequent stage. A bottom value detection circuit, an intermediate level generation circuit that generates an intermediate level between the output of the bottom value detection circuit and the peak value of the signal voltage, and a signal voltage with the output level of the intermediate level generation circuit as a threshold. An amplitude equalizing circuit including a limiter amplifier circuit for amplification is provided.

As a result, the high-speed response characteristic at the start of data input and the continuity of the same code can be compatible, and the high-speed tracking can be performed with the instantaneous change of the signal level.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION
A preamplifier circuit that converts a photocurrent signal detected by a photodiode into a voltage signal, and outputs a DC potential corresponding to the peak value of the signal voltage, and a circuit that detects a bottom value of the signal voltage at a subsequent stage. An intermediate level generating circuit for generating an intermediate level between the output of the bottom value detecting circuit and the peak value of the signal voltage, and a limiter amplifier circuit for amplifying the signal voltage using the output level of the intermediate level generating circuit as a threshold. And has an effect that both high-speed response characteristics at the start of data input and continuity with the same sign can be achieved.

According to a second aspect of the present invention, the preamplifier circuit is a transimpedance type preamplifier circuit in which a feedback resistor is connected to an input / output terminal of the inverting amplifier circuit, and the inverting amplifier circuit has a negative-phase input terminal. , A buffer circuit connected to the signal output terminal of the current mirror load differential amplifier, and a positive-phase input of the current mirror load differential amplifier. A buffer circuit for self-biasing the terminal side and outputting a DC potential corresponding to the peak value of the output signal voltage, and has the same operation as the optical receiver according to the first aspect of the present invention.

Further, according to a third aspect of the present invention, the bottom value detecting circuit has a reset signal terminal outside thereof, and a signal applied to the reset signal terminal causes
The output potential of the bottom value detection circuit and the signal voltage peak value of the output of the preamplifier circuit are set to be substantially equal to each other, and have the effect of being able to follow an instantaneously changing signal level.

(Embodiment 1) FIG. 1 is a block diagram showing a circuit of an optical receiver according to Embodiment 1 of the present invention.
In FIG. 1, a photodiode PD converts an optical signal hν into a current signal Iin, and inputs the current signal Iin to a preamplifier circuit 1. This preamplifier circuit 1 includes a current signal I
in is converted into a voltage signal, and the signal voltage Vdata and the DC potential Vpeak corresponding to the peak value of the signal voltage are converted to an amplitude equalization circuit 2.
Output to The amplitude equalization circuit 2 includes a bottom value detection circuit 21 for detecting a bottom value of the signal voltage, and a bottom value detection circuit for detecting the bottom value.
The intermediate level V between the output potential Vbottom of 21 and the DC potential Vpeak of the peak value of the signal voltage input from the preamplifier circuit 1
ref, and a limiter amplifier circuit that amplifies the signal voltage Vdata using the intermediate level Vref output from the intermediate level generation circuit 22 as a threshold.
23.

FIG. 2 shows the relationship among the respective voltage levels Vdata, Vpeak, Vbottom, and Vref of the optical receiver configured as described above.
Shown in Since the intermediate level Vref is an intermediate value of the signal voltage Vdata irrespective of the input signal level, according to the configuration of the optical receiver, the high-speed response characteristic at the start of data input is the same depending on the charging time constant of the bottom value detection circuit 21. The sign continuity tolerance is determined by the discharge time constant of the bottom value detection circuit 21. Therefore,
By using the bottom value detection circuit 21 having a small charging time constant and a large discharging time constant, it is possible to achieve both high-speed response characteristics at the start of data input and continuity with the same sign.

(Embodiment 2) FIG. 3 is a block diagram showing a circuit of an optical receiver according to Embodiment 2 of the present invention.
The basic configuration of the preamplifier circuit 1 includes an inverting amplifier circuit 11 connected to a photodiode PD,
This is a transimpedance type preamplifier circuit composed of a feedback resistor Rf for applying a feedback to 11.
The transimpedance preamplifier circuit receives the current signal Iin detected by the photodiode PD as an input, converts the signal into a voltage signal, amplifies the signal, and outputs a signal voltage Vdata.

Here, the inverting amplifier circuit 11 in the preamplifier circuit 1 includes transistors Q1, Q2, Q3, Q4 and a current source I
1, a current mirror load type differential amplifier circuit comprising a transistor Q5 and a current source I2;
The buffer circuit includes a transistor Q6 and a current source I3. Q4 is used for self-bias, and the source output of Q5 is connected to the gate of Q2. According to the configuration of this preamplifier circuit, the source output of Q5 has a DC potential Vpeak substantially equal to the peak value of signal voltage Vdata. Therefore, in the second embodiment of FIG. 3, as in the first embodiment, an optical receiver capable of achieving both high-speed response characteristics at the start of data input and continuity with the same code is configured.

(Embodiment 3) FIG. 4 is a block diagram showing a circuit of an optical receiver according to Embodiment 3 of the present invention.
The difference from FIG. 1 is that a reset signal terminal 24 is provided outside the bottom value detection circuit 21. The signal applied to the reset signal terminal 24 causes the bottom value detection circuit
The output potential Vbottom of 21 and the DC potential Vpeak of the peak value of the signal voltage of the preamplifier circuit output become substantially the same potential, and even if the input signal level changes instantaneously, it is possible to quickly follow.

FIG. 5 shows the relationship between the change (1) of each voltage level and the output data waveform (2) when a signal having a level difference is input when there is no reset signal input from the reset signal terminal 24. Things. Large-level signal shown in Fig. 5 (1)
When the small-level signal (a) is input immediately after (a) is input, the discharge time constant of the bottom value detection circuit 21 is large,
The intermediate level Vref of the subsequent small input level signal (a) cannot be accurately generated, and the leading data of the small input level signal is applied as shown by the broken line in FIG. 5 (2). The follow-up speed can be increased by reducing the discharge time constant of the bottom value detection circuit 21, but the homo-code continuity proof strength described in the first and second embodiments decreases.

FIG. 6 shows the relationship between each voltage level change (1) when a reset signal is input to the bottom value detection circuit 21, the reset signal waveform (2), and the output data waveform (3). It is. During the reset signal input period, the value of the output potential Vbottom of the bottom value detection circuit 21 and the value of the DC potential Vpeak of the peak value of the signal voltage of the preamplifier circuit output are forced to be substantially equal to each other, so that the large-level signal (A) Intermediate level Vre of the input voltage of the small input level signal (a) that comes later
f can be generated accurately from the beginning of the data,
High-speed follow-up becomes possible.

[0023]

As described above, according to the present invention, a preamplifier circuit for outputting a signal voltage and a DC potential corresponding to a peak value of the signal voltage, and a circuit for detecting a bottom value of the signal voltage at a subsequent stage. An intermediate level generating circuit for generating an intermediate level between the output of the bottom value detecting circuit and the peak value of the signal voltage, and a limiter amplifier circuit for amplifying the signal voltage using the output level of the intermediate level generating circuit as a threshold value. By providing an amplitude equalization circuit, it is possible to achieve both high-speed response characteristics at the start of data input and continuous proof strength with the same sign.
In addition, there is obtained an effect that an optical receiver that can follow a signal level that changes instantaneously at high speed can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a circuit of an optical receiver according to Embodiment 1 of the present invention.

FIG. 2 is a diagram illustrating a relationship between respective voltage levels of the optical receiver in FIG. 1;

FIG. 3 is a block diagram illustrating a circuit of an optical receiver according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing a circuit of an optical receiver according to a third embodiment of the present invention.

FIG. 5 is a diagram showing a relationship between a change in each voltage level when no reset signal is input and an output data waveform in FIG.

FIG. 6 is a diagram showing a relationship between a change in each voltage level when a reset signal is input in FIG. 4 and a reset signal waveform and an output data waveform.

FIG. 7 is a block diagram showing a circuit of a conventional optical receiver.

FIG. 8 shows changes in voltage levels at the start of data input when a low cutoff frequency is set high in a conventional optical receiver.
FIG. 6 is a diagram illustrating a relationship between (1) and an output data waveform (2).

FIG. 9 is a diagram showing the relationship between each voltage level change (1) and output data waveform (2) during one continuous operation when the low cutoff frequency is set high in the conventional optical receiver.

FIG. 10 shows changes in voltage levels at the start of data input when a low cutoff frequency is set low in a conventional optical receiver.
FIG. 6 is a diagram illustrating a relationship between (1) and an output data waveform (2).

FIG. 11 is a diagram showing a relationship between each voltage level change (1) and output data waveform (2) during one continuous operation when a low cutoff frequency is set low in a conventional optical receiver.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Preamplifier circuit, 2 ... Amplitude equalization circuit, 11 ... Inverting amplifier circuit, 21 ... Bottom value detection circuit, 22 ... Intermediate level generation circuit, 23 ... Limiter amplifier circuit, 24 ... Reset signal terminal, 25 ... Output data output Terminals, Q1-Q6 ...
Transistors, I1 to I3 ... current sources, Rf ... feedback resistors,
PD: light receiving element (photodiode).

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification number Agency reference number FI Technical display location H03F 3/08 H03G 11/00 H04L 25/02 303 25/03

Claims (3)

[Claims] 1. A preamplifier circuit for converting an optical signal into a current signal by a light receiving element, converting the signal current into a signal voltage, and outputting the signal voltage and a DC potential corresponding to a peak value of the signal voltage, and In the stage, a circuit for detecting the bottom value of the signal voltage, an intermediate level generation circuit for generating an intermediate level between the output of the bottom value detection circuit and the peak value of the signal voltage, and a threshold value for the output level of the intermediate level generation circuit An optical receiver, comprising: an amplitude equalizing circuit including a limiter amplifier circuit that amplifies a signal voltage as a value. 2. The preamplifier circuit is a transimpedance type preamplifier circuit in which a feedback resistor is connected to an input / output terminal of an inverting amplifier circuit, and the inverting amplifier circuit has a current mirror load type having an inverting input terminal as a signal input terminal. A differential amplifier circuit, a buffer circuit connected to a signal output terminal side of the current mirror load type differential amplifier circuit, a self-biased input terminal side of the current mirror load type differential amplifier circuit, and an output signal The optical receiver according to claim 1, further comprising: a buffer circuit that outputs a DC voltage corresponding to a peak value of the potential. 3. The bottom value detection circuit has a reset signal terminal outside thereof, and a signal applied to the reset signal terminal determines an output potential of the bottom value detection circuit and a signal voltage peak value of a preamplifier circuit output. 3. The optical receiver according to claim 1, wherein the potentials are substantially the same.