JP3466545B2 - High frequency wiring board - Google Patents

High frequency wiring board

Info

Publication number
JP3466545B2
JP3466545B2 JP2000192742A JP2000192742A JP3466545B2 JP 3466545 B2 JP3466545 B2 JP 3466545B2 JP 2000192742 A JP2000192742 A JP 2000192742A JP 2000192742 A JP2000192742 A JP 2000192742A JP 3466545 B2 JP3466545 B2 JP 3466545B2
Authority
JP
Japan
Prior art keywords
high frequency
thermal expansion
wiring board
glass
porcelain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2000192742A
Other languages
Japanese (ja)
Other versions
JP2001068597A (en
Inventor
吉健 寺師
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2000192742A priority Critical patent/JP3466545B2/en
Publication of JP2001068597A publication Critical patent/JP2001068597A/en
Application granted granted Critical
Publication of JP3466545B2 publication Critical patent/JP3466545B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、半導体素子収納用
パッケージや多層配線基板等に適用される配線基板に関
するものであり、特に、銅や銀と同時焼成が可能であ
り、また、GaAs等のチップ部品やプリント基板など
の有機樹脂からなる外部回路基板に対し、高い信頼性を
もって実装可能である高周波用配線基板に関するもので
ある。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board applied to a package for housing a semiconductor element, a multilayer wiring board, etc., and in particular, it can be co-fired with copper or silver, and is made of GaAs or the like. The present invention relates to a high-frequency wiring board that can be mounted with high reliability on an external circuit board made of an organic resin such as a chip component or a printed board.

【0002】[0002]

【従来技術】従来より、セラミック多層配線基板として
は、アルミナ質焼結体からなる絶縁基板の表面または内
部にタングステンやモリブデンなどの高融点金属からな
る配線層が形成されたものが最も普及している。
2. Description of the Related Art Conventionally, as a ceramic multilayer wiring board, one in which a wiring layer made of a refractory metal such as tungsten or molybdenum is formed on the surface or inside of an insulating substrate made of an alumina sintered body is most popular. There is.

【0003】また、最近に至り、高度情報化時代を迎
え、使用される周波数帯域はますます高周波化に移行し
つつある。このような、高周波の信号の伝送を必要とす
る高周波配線基板においては、高周波信号を損失なく伝
送する上で、配線層を形成する導体の抵抗が小さいこ
と、また絶縁基板の高周波領域での誘電損失が小さいこ
とが要求される。
Further, in recent years, with the era of advanced information technology, the frequency band to be used is shifting to higher frequencies. In such a high-frequency wiring board that requires transmission of high-frequency signals, in order to transmit high-frequency signals without loss, the resistance of the conductor forming the wiring layer is small, and the dielectric of the insulating substrate in the high-frequency region is high. Low loss is required.

【0004】ところが、従来のタングステン(W)や、
モリブデン(Mo)などの高融点金属は導体抵抗が大き
く、信号の伝搬速度が遅く、また、1GHz以上の高周
波領域の信号伝搬も困難であることから、W、Moなど
の金属に代えて銅、銀、金などの低抵抗金属を使用する
ことが必要となっている。このような低抵抗金属からな
る配線層は、融点が低く、アルミナと同時焼成すること
が不可能であるため、最近では、ガラス、またはガラス
とセラミックスとの複合材料からなる、いわゆるガラス
セラミックスを絶縁基板として用いた配線基板が開発さ
れつつある。例えば、特開昭60−240135号のよ
うに、ホウケイ酸亜鉛系ガラスに、Al 23、ジルコニ
ア、ムライトなどのフィラーを添加したものを低抵抗金
属と同時焼成した多層配線基板や、特開平5−2989
19号のように、ムライトやコージェライトを結晶相と
して析出させたガラスセラミック材料が提案されてい
る。
However, conventional tungsten (W),
Refractory metals such as molybdenum (Mo) have large conductor resistance
Signal transmission speed is slow, and high frequency of 1 GHz or more
Since signal propagation in the wave domain is also difficult, W, Mo, etc.
Use low resistance metals such as copper, silver and gold instead of
Is needed. Do not use such low resistance metal
The wiring layer has a low melting point and must be co-fired with alumina.
Recently, glass, or glass because it is impossible
So-called glass, which is made of a composite material of ceramics and ceramics
A wiring board using ceramics as an insulating substrate was developed.
It's getting lost. For example, JP-A-60-240135
Sea urchin, zinc borosilicate glass, Al 2O3, Zirconi
A, low resistance gold with filler such as mullite added
Multi-layer wiring board co-fired with metal, and JP-A-5-2989
As in No. 19, mullite and cordierite are crystal phases.
A glass-ceramic material that has been deposited by
It

【0005】また、多層配線基板や半導体素子収納用パ
ッケージなどの配線基板にGaAsなどのチップ部品を
実装したり、また配線基板をマザーボードなどの有機樹
脂を含むプリント基板に実装する上で、絶縁基板とチッ
プ部品あるいはプリント基板との熱膨張差に起因して発
生する応力により実装部分が剥離したり、クラックなど
が発生するのを防止する観点から、絶縁基板の熱膨張係
数がチップ部品やプリント基板のそれと近似しているこ
とが望まれる。
In addition, when mounting a chip component such as GaAs on a wiring board such as a multilayer wiring board or a package for housing a semiconductor element, or mounting the wiring board on a printed board containing an organic resin such as a mother board, an insulating board is used. The thermal expansion coefficient of the insulating substrate is determined from the viewpoint of preventing the mounting part from peeling or cracking due to the stress caused by the difference in thermal expansion between the chip component and the printed circuit board. It is hoped that it is similar to that of.

【0006】そこで、本出願人は、先に特開平9−17
904号に開示されるように、結晶化が可能なリチウム
珪酸ガラスを用いることにより、絶縁基板の熱膨張係数
を高めることができることを提案した。
[0006] Therefore, the applicant of the present invention previously disclosed in Japanese Patent Laid-Open No. 9-17
As disclosed in No. 904, it has been proposed that the coefficient of thermal expansion of the insulating substrate can be increased by using a crystallizable lithium silicate glass.

【0007】[0007]

【発明が解決しようとする課題】しかしながら、前記従
来のガラスセラミックスは、銅、銀、金などの低抵抗金
属との同時焼成が可能であっても、熱膨張係数が3〜5
ppm/℃程度と低く、GaAs等のチップ部品(熱膨
張係数6〜7.5ppm/℃)を実装したり、プリント
基板(熱膨張係数12〜15ppm/℃)に実装する場
合に、実装の信頼性が低く実用上満足できるものではな
かった。
However, the conventional glass ceramics have a coefficient of thermal expansion of 3 to 5 even if they can be co-fired with a low resistance metal such as copper, silver or gold.
When the chip parts such as GaAs (coefficient of thermal expansion 6 to 7.5 ppm / ° C) are mounted on a printed circuit board (coefficient of thermal expansion 12 to 15 ppm / ° C), the reliability of mounting is low. It was poor in performance and was not satisfactory in practice.

【0008】また、特開平9−17904号に開示され
るようにアルカリ金属を含有するガラスを用いる方法で
は、長時間高温多湿雰囲気に曝されると、アルカリ金属
が大気中の水分と反応し表面にシリケート結晶相が析出
して表面が変質してしまう場合があった。
Further, in the method using glass containing an alkali metal as disclosed in JP-A-9-17904, when the glass is exposed to a high temperature and high humidity atmosphere for a long time, the alkali metal reacts with moisture in the atmosphere and the surface In some cases, the silicate crystal phase was precipitated and the surface was altered.

【0009】また、従来のガラスセラミックスは、ミリ
波などの高周波信号を用いる配線基板の絶縁基板として
具体的に検討されておらず、そのほとんどは誘電損失が
高く、十分満足できる高周波特性を有するものではなか
った。
Further, the conventional glass ceramics have not been specifically studied as an insulating substrate for a wiring substrate using a high frequency signal such as a millimeter wave, and most of them have high dielectric loss and have sufficiently high frequency characteristics. Was not.

【0010】従って、本発明は、金、銀、銅を配線導体
として多層化が可能な800〜1000℃での焼成が可
能であるとともに、GaAs等のチップ部品やプリント
基板の熱膨張係数と近似した熱膨張係数に制御可能であ
り、高周波領域においても低誘電率でかつ誘電損失が低
い磁器を絶縁基板とする配線基板を提供することを目的
とする。
Therefore, the present invention can be fired at 800 to 1000 ° C. in which gold, silver, and copper can be used as wiring conductors and can be multilayered, and is close to the coefficient of thermal expansion of chip parts such as GaAs and printed circuit boards. It is an object of the present invention to provide a wiring board which uses an insulating substrate made of porcelain that can be controlled to the above thermal expansion coefficient and has a low dielectric constant and a low dielectric loss even in a high frequency region.

【0011】[0011]

【課題を解決するための手段】本発明者は、上記課題を
鋭意検討した結果、SiO2、Al23、MgO、Sr
OおよびCaOを含み、ディオプサイド型酸化物結晶相
を析出可能なガラスに対して、クォーツを特定の比率で
配合した組成物を用い、これを成形後、800〜100
0℃の温度で焼成することによって、低誘電率で、かつ
GaAs等のチップ部品やプリント基板の熱膨張係数と
近似した熱膨張係数に制御でき、1GHz以上の高周波
領域においても低誘電損失を有する磁器が得られること
を知見し、本発明に至った。
Means for Solving the Problems As a result of diligent study of the above problems, the present inventor has found that SiO 2 , Al 2 O 3 , MgO, Sr
A composition containing O and CaO in which quartz is compounded in a specific ratio with respect to a glass capable of precipitating a diopside type oxide crystal phase is used.
By firing at a temperature of 0 ° C., it can be controlled to have a low dielectric constant and a coefficient of thermal expansion similar to that of chip parts such as GaAs and printed circuit boards, and low dielectric loss even in a high frequency region of 1 GHz or higher. The present invention has been accomplished by finding that porcelain can be obtained.

【0012】即ち、本発明の高周波用配線基板は、少な
くともMg、Ca、Si、Alを含むディオプサイド型
酸化物結晶相と、クォーツ結晶相とを含有し、且つ室温
から400℃における熱膨張係数が5.5ppm/℃以
上、誘電率が7以下、60〜77GHzでの誘電損失が
30×10−4以下の高周波用磁器を絶縁基板とし、該
絶縁基板の表面および内部にストリップ線路、マイクロ
ストリップ線路、コプレーナ線路、誘電体導波管線路の
うちの少なくとも1種から構成される配線層を具備し、
前記絶縁基板表面にGaAs系のチップ部品が実装され
るとともに、前記絶縁基板のGaAsとの熱膨張差が2
ppm/℃以下であることを特徴とするものである。
That is, the high frequency wiring board of the present invention contains a diopside type oxide crystal phase containing at least Mg, Ca, Si and Al and a quartz crystal phase, and has a thermal expansion from room temperature to 400 ° C. A high frequency porcelain having a coefficient of 5.5 ppm / ° C. or more, a dielectric constant of 7 or less, and a dielectric loss of 30 × 10 −4 or less at 60 to 77 GHz is used as an insulating substrate, and a strip line, a micro line are formed on the surface and inside of the insulating substrate. A wiring layer composed of at least one of a strip line, a coplanar line, and a dielectric waveguide line ,
GaAs chip parts are mounted on the surface of the insulating substrate.
And the thermal expansion difference between the insulating substrate and GaAs is 2
It is characterized in that it is below ppm / ° C.

【0013】ここで、前記高周波用磁器の室温から40
0℃における熱膨張係数が8.5ppm/℃以上である
ことが望ましい。
Here, from the room temperature of the high frequency porcelain to 40
The coefficient of thermal expansion at 0 ° C is preferably 8.5 ppm / ° C or more.

【0014】さらに、前記高周波用磁器が、SiO
Al、MgO、SrOおよびCaOを含み、ディ
オプサイド型酸化物結晶相を析出可能なガラス50〜9
5重量%と、クォーツおよび/またはアモルファスシリ
カの総量で5〜50重量%との割合で含有する高周波用
磁器組成物を成形後、800〜1000℃の温度で焼成
してなること、前記ガラスが、SiO45〜55重量
%と、Al3〜10重量%と、MgO13〜24
重量%と、SrO10〜24重量%と、CaO8〜20
重量%と、からなることが望ましい。
Further, the high frequency porcelain is made of SiO 2 ,
Glasses 50 to 9 containing Al 2 O 3 , MgO, SrO and CaO and capable of precipitating a diopside type oxide crystal phase
5% by weight, quartz and / or amorphous silicon
After molding a high frequency porcelain composition containing 5 to 50% by weight of the total amount of mosquitoes, the composition is fired at a temperature of 800 to 1000 ° C., and the glass has SiO 2 of 45 to 55% by weight, Al 2 O 3 3 to 10 wt% and MgO 13 to 24
Wt%, SrO 10-24 wt%, CaO 8-20
It is desirable to be composed by weight%.

【0015】[0015]

【発明の実施の形態】本発明の高周波用配線基板の絶縁
基板を作製するための高周波用磁器組成物は、Si
2、Al23、MgO、SrOおよびCaOを含み、
ディオプサイド型酸化物結晶相を析出可能なガラス50
〜95重量%と、クォーツ5〜50重量%との割合で含
有するものである。
BEST MODE FOR CARRYING OUT THE INVENTION A high frequency porcelain composition for producing an insulating substrate for a high frequency wiring board of the present invention is made of Si.
Including O 2 , Al 2 O 3 , MgO, SrO and CaO,
Glass 50 capable of depositing diopside type oxide crystal phase
˜95% by weight and 5 to 50% by weight of quartz.

【0016】各成分組成を上記の範囲に限定したのは、
上記ガラスが50重量%よりも少ないと、1000℃以
下の温度での焼成により磁器を緻密化させることが困難
であり、95重量%よりも多いと、ガラスの結晶化が不
十分となり、誘電損失の大きなガラス相が残留し、磁器
の高周波での誘電損失が増大するためである。ガラスの
特に望ましい範囲は、60〜85重量%である。
The reason why the composition of each component is limited to the above range is that
If the amount of the glass is less than 50% by weight, it is difficult to densify the porcelain by firing at a temperature of 1000 ° C. or less, and if the amount of the glass is more than 95% by weight, crystallization of the glass becomes insufficient and dielectric loss occurs. This is because the large glass phase of P remains and the dielectric loss of the porcelain at high frequencies increases. A particularly desirable range for glass is 60-85% by weight.

【0017】クォーツの総量が5重量%よりも少ない
と、ガラスの残存率が高くなり、誘電損失が大きくな
る。逆に、50重量%を越えると、難焼結性となり、1
000℃以下の焼成温度で緻密化することができない。
クォーツの望ましい範囲は、15〜40重量%である。
When the total amount of quartz is less than 5% by weight, the residual rate of glass becomes high and the dielectric loss becomes large. On the other hand, if it exceeds 50% by weight, it becomes difficult to sinter and 1
It cannot be densified at a firing temperature of 000 ° C. or less.
The preferred range of quartz is 15-40% by weight.

【0018】ここで、前記ディオプサイド型酸化物結晶
相を析出可能なガラスは、ガラスの軟化点が500〜8
00℃であることが望ましく、その組成はSiO245
〜55重量%、Al233〜10重量%、MgO13〜
24重量%、SrO10〜24重量%、CaO8〜20
重量%の割合であることが望ましい。
The glass capable of precipitating the diopside type oxide crystal phase has a softening point of 500 to 8
It is desirable that the temperature is 00 ° C., and the composition is SiO 2 45.
55 wt%, Al 2 O 3 3~10 wt%, MgO13~
24 wt%, SrO10-24 wt%, CaO8-20
It is desirable that the ratio is wt%.

【0019】上記のガラスからのディオプサイド型酸化
物結晶相の析出割合を高める上では、ガラス中における
CaOとMgOの合計量が35〜44重量%であること
が望ましい。
In order to increase the precipitation rate of the diopside type oxide crystal phase from the above glass, it is desirable that the total amount of CaO and MgO in the glass is 35 to 44% by weight.

【0020】上記高周波用磁器組成物を用い、磁器を製
造するには、SiO2、Al23、MgO、SrOおよ
びCaOを含みディオプサイド型酸化物結晶相を析出可
能な結晶化ガラスと、クォーツおよび/またはアモルフ
ァスシリカからなる上記組成物の混合粉末を用いて、ド
クターブレード法やカレンダーロール法、あるいは圧延
法、プレス成形法の周知の成型法により所定形状の成形
体を作製した後、該成形体を800〜1000℃の酸化
性雰囲気または非酸化性雰囲気中で焼成することにより
作製することができる。
In order to manufacture a porcelain using the above high frequency porcelain composition, a crystallized glass containing SiO 2 , Al 2 O 3 , MgO, SrO and CaO and capable of precipitating a diopside type oxide crystal phase is used. After using a mixed powder of the above composition consisting of, quartz, and / or amorphous silica to prepare a molded product having a predetermined shape by a known molding method such as a doctor blade method, a calendar roll method, a rolling method, or a press molding method, It can be produced by firing the molded body in an oxidizing atmosphere or a non-oxidizing atmosphere at 800 to 1000 ° C.

【0021】本発明によれば、上記のガラス組成物を用
いることによって、フィラーとしてSiO2のような高
融点化物質を含有するにもかかわらず、1000℃以
下、特に950℃以下、さらには930℃以下での焼成
が可能であることから、後述するように本発明の高周波
用配線基板の配線層として多用されている銅および/ま
たは銀との同時焼成が可能である。
According to the present invention, by using the above-mentioned glass composition, the temperature is 1000 ° C. or lower, particularly 950 ° C. or lower, and further 930 even though it contains a high melting point substance such as SiO 2 as a filler. Since it can be fired at a temperature of not higher than 0 ° C., it can be fired at the same time with copper and / or silver that is often used as the wiring layer of the high-frequency wiring board of the present invention, as will be described later.

【0022】ここで、クォーツを添加する場合には、焼
成によりクォーツの他にクリストバライト、トリジマイ
トなどに相変態してもよいが、クリストバライトは、2
00℃付近に熱膨張係数の屈曲点を有することから熱膨
張挙動、誘電特性の点でクォーツとして残存することが
望ましい。
Here, in the case of adding quartz, it may undergo phase transformation into cristobalite, tridymite, etc. in addition to quartz by firing.
Since it has a bending point of the thermal expansion coefficient near 00 ° C., it is desirable that it remains as quartz in terms of thermal expansion behavior and dielectric properties.

【0023】上記の態様の磁器組成物は、800〜10
00℃の温度範囲での焼成によって相対密度97%以上
まで緻密化することができ、これによって形成される磁
器の全体組成としては、Si、Al、Mg、Srおよび
Caの各金属元素の酸化物換算による合量を100重量
%とした時、SiO2を55〜75重量%、Al23
3〜5重量%、MgOを10〜14重量%、SrOを1
5〜23重量%、CaO14〜19重量%の割合から構
成されることが望ましい。
The porcelain composition of the above embodiment is 800 to 10
By calcination in the temperature range of 00 ° C., the relative density can be densified to 97% or more, and the overall composition of the porcelain thus formed is an oxide of each metal element of Si, Al, Mg, Sr and Ca. When the total amount calculated is 100 wt%, SiO 2 is 55 to 75 wt%, Al 2 O 3 is 3 to 5 wt%, MgO is 10 to 14 wt%, and SrO is 1 wt.
It is desirable to be composed of 5 to 23% by weight and 14 to 19% by weight of CaO.

【0024】一般に、Al23やSiO2を含むガラス
相の熱膨張係数は4〜5ppm/℃と低い。これに対
し、Ca(Mg,Al)(Si,Al)26のディオプ
サイド型酸化物結晶相は、約8〜9ppm/℃の高熱膨
張特性を有することから、上記組成のガラスよりディオ
プサイド型酸化物結晶相を析出させることにより、高熱
膨張化することができる。また、ディオプサイド型酸化
物結晶相は、6〜8の誘電率を有し、かつ高周波帯での
誘電損失が小さい材料である。
Generally, the thermal expansion coefficient of the glass phase containing Al 2 O 3 or SiO 2 is as low as 4 to 5 ppm / ° C. On the other hand, the diopside type oxide crystal phase of Ca (Mg, Al) (Si, Al) 2 O 6 has a high thermal expansion property of about 8 to 9 ppm / ° C., so that it is more preferable than the glass having the above composition. High thermal expansion can be achieved by precipitating the p-side oxide crystal phase. The diopside type oxide crystal phase is a material having a dielectric constant of 6 to 8 and a small dielectric loss in a high frequency band.

【0025】上記磁器組成物によれば、ガラス、クォー
ツおよびアモルファスシリカ(熱膨張係数2〜5ppm
/℃)量を制御することによって、熱膨張係数や誘電率
等を任意に調整することができる。
According to the above porcelain composition, glass, quartz and amorphous silica (coefficient of thermal expansion of 2 to 5 ppm)
/ ° C.) amount, the thermal expansion coefficient, the dielectric constant, etc. can be arbitrarily adjusted.

【0026】例えば、上述した高周波用磁器中にクォー
ツ結晶相またはクォーツ結晶相とアモルファスシリカ相
を存在させることによって、室温から400℃における
熱膨張係数が5.5ppm/℃以上、誘電率が7以下、
60〜77GHzでの誘電損失が30×10-4以下の特
性に制御可能である。
For example, by allowing the quartz crystal phase or the quartz crystal phase and the amorphous silica phase to exist in the above-mentioned high frequency porcelain, the thermal expansion coefficient from room temperature to 400 ° C. is 5.5 ppm / ° C. or more and the dielectric constant is 7 or less. ,
The dielectric loss at 60 to 77 GHz can be controlled to a characteristic of 30 × 10 −4 or less.

【0027】本発明によれば、上記組成のガラスに対し
て、フィラーとしてクォーツを添加することにより、磁
器中にディオプサイド型酸化物結晶相を析出させるとと
もに、13〜20ppm/℃の高熱膨張係数を有するク
ォーツ結晶相を含有させることにより、磁器の熱膨張係
数を8.5ppm/℃以上に高めることができる。その
結果、磁器とGaAs等のチップ部品およびプリント基
板等の有機樹脂からなる外部回路基板との熱膨張係数差
を小さくできることから、本発明の磁器を配線基板の絶
縁基板として用いる場合、実装の信頼性を高めることが
できる。
According to the present invention, by adding quartz as a filler to the glass having the above composition, a diopside type oxide crystal phase is precipitated in a porcelain and a high thermal expansion of 13 to 20 ppm / ° C. By including the quartz crystal phase having a coefficient, the thermal expansion coefficient of the porcelain can be increased to 8.5 ppm / ° C or higher. As a result, the difference in thermal expansion coefficient between the porcelain and the external circuit board made of an organic resin such as a chip component such as GaAs and a printed circuit board can be reduced. Therefore, when the porcelain of the present invention is used as an insulating substrate for a wiring board, the reliability of mounting is improved. You can improve your sex.

【0028】また、クォーツの誘電率が4〜4.5であ
ることから、磁器の誘電率を7以下とすることができ、
基板の高周波信号への影響を小さくできるとともに、ク
ォーツはミリ波帯での誘電損失が小さい材料であること
から、磁器の60〜77GHzでの誘電損失を30×1
-4以下とすることができることから、高周波帯、特に
ミリ波帯での信号の伝送特性が向上する。
Since the permittivity of quartz is 4 to 4.5, the permittivity of porcelain can be set to 7 or less,
Quartz is a material that has a small dielectric loss in the millimeter wave band, while the influence on the high frequency signal of the substrate can be reduced. Therefore, the dielectric loss of porcelain at 60 to 77 GHz is 30 × 1.
Since it can be set to 0 -4 or less, the signal transmission characteristics in the high frequency band, particularly in the millimeter wave band are improved.

【0029】また、上記のようにして作製された磁器
は、図1の磁器組織の概略図に示すように、結晶相とし
て、ガラスから析出する少なくともMgとCaとSiと
Alとを含むディオプサイド型酸化物結晶相Ca(M
g,Al)(Si,Al)26(DI)以外に、SiO
2系相(Si、AM)を含有するものであり、それ以外
にも、Ca2MgSi27(akermanite)、
CaMgSiO4(monticellite)、Ca3
MgSi28(merwinite)等高熱膨張を有す
る類似の相が析出してもよい。
Further, the porcelain manufactured as described above, as shown in the schematic diagram of the porcelain structure in FIG. 1, is a diop containing at least Mg, Ca, Si and Al precipitated from glass as a crystal phase. Side-type oxide crystal phase Ca (M
g, Al) (Si, Al) 2 O 6 (DI), as well as SiO
It contains two phases (Si, AM), and in addition to that, Ca 2 MgSi 2 O 7 (akermanite),
CaMgSiO 4 (monticellite), Ca 3
Similar phases with high thermal expansion such as MgSi 2 O 8 (merwinite) may be precipitated.

【0030】また、本発明によれば、上記組成のガラス
に対して、フィラーとしてアモルファスシリカを主とし
て添加することにより、磁器中ディオプサイド型酸化物
結晶相を析出させるとともに、その粒界をアモルファス
シリカ相により主として形成することにより、アモルフ
ァスシリカの誘電率が3.8〜4.2と低いことから、
磁器の誘電率を5.9以下とすることができ、高周波用
配線基板等に用いる場合、高周波信号の伝送特性への基
板の影響が小さくすることが可能となる。さらに、アモ
ルファスシリカはミリ波帯での誘電損失が小さい材料で
あることから、磁器の60〜77GHzでの誘電損失を
30×10-4以下とすることができる。
Further, according to the present invention, amorphous silica is mainly added as a filler to the glass having the above composition to precipitate a diopside type oxide crystal phase in porcelain and to make its grain boundaries amorphous. Since the amorphous silica has a low dielectric constant of 3.8 to 4.2 because it is mainly formed of a silica phase,
The permittivity of the porcelain can be set to 5.9 or less, and when it is used for a high-frequency wiring board or the like, the influence of the board on the transmission characteristics of high-frequency signals can be reduced. Furthermore, since amorphous silica is a material having a small dielectric loss in the millimeter wave band, the dielectric loss of the porcelain at 60 to 77 GHz can be set to 30 × 10 −4 or less.

【0031】上記磁器組成物は、高周波帯での誘電損失
が低いことから1GHz以上、特に20GHz以上、さ
らには50GHz以上、またさらには70GHz以上の
高周波用配線基板の絶縁層を形成するのに好適である。
上記磁器を配線基板の絶縁基板として用いる場合、高周
波信号の伝送特性への影響を低減するため、誘電率が7
以下、特に5.9以下と低いことが望ましい。
Since the above-mentioned porcelain composition has a low dielectric loss in a high frequency band, it is suitable for forming an insulating layer of a high frequency wiring board of 1 GHz or more, particularly 20 GHz or more, further 50 GHz or more, and further 70 GHz or more. Is.
When the above-mentioned porcelain is used as an insulating substrate of a wiring board, the dielectric constant is 7 in order to reduce the influence on the transmission characteristics of high frequency signals.
It is desirable that it is as low as possible, particularly 5.9 or less.

【0032】その場合、絶縁基板の室温から400℃に
おける熱膨張係数は、実装するチップ部品等やプリント
基板等の熱膨張係数に近似するように前述したように、
基板を構成する磁器の組成、組織を制御して、適宜調整
することが望ましい。
In that case, as described above, the thermal expansion coefficient of the insulating substrate from room temperature to 400 ° C. is approximated to the thermal expansion coefficient of the mounted chip component or printed circuit board.
It is desirable to control and appropriately adjust the composition and structure of the porcelain constituting the substrate.

【0033】これは、上記の絶縁基板の熱膨張係数が実
装されるチップ部品等やプリント基板のそれと差がある
場合、半田実装時や半導体素子の作動停止による繰り返
し温度サイクルによって、チップ部品等やプリント基板
とパッケージとの実装部に熱膨張差に起因する応力が発
生し、実装部にクラック等が発生し、実装構造の信頼性
を損ねてしまうためである。
This is because when there is a difference in the coefficient of thermal expansion of the above-mentioned insulating substrate from that of the chip component or the printed circuit board mounted, the chip component or the like is repeatedly mounted by soldering or by repeated temperature cycles due to the operation stop of the semiconductor element. This is because stress due to the difference in thermal expansion is generated in the mounting portion between the printed circuit board and the package, cracks or the like are generated in the mounting portion, and the reliability of the mounting structure is impaired.

【0034】具体的には、GaAs系のチップ部品との
整合を図る上ではGaAs系のチップ部品との熱膨張係
数の差が2ppm/℃以下であり、一方、プリント基板
との整合を図る上ではプリント基板との熱膨張係数の差
が2ppm/℃以下であることが望ましい。
Specifically, the difference in the coefficient of thermal expansion from the GaAs-based chip component is 2 ppm / ° C. or less in order to achieve the matching with the GaAs-based chip component. Then, it is desirable that the difference in thermal expansion coefficient from the printed circuit board is 2 ppm / ° C. or less.

【0035】具体的に、上記高周波用磁器を用いて、配
線層を具備する本発明の高周波用配線基板を製造する方
法について説明する。上述した組成物からなる混合粉末
に、適当な有機溶剤、溶媒を用い混合してスラリーを調
製し、これを従来周知のドクターブレード法やカレンダ
ーロール法、あるいは圧延法、プレス成形法により、シ
ート状に成形する。そして、このシート状成形体に所望
によりスルーホールを形成した後、スルーホール内に、
銅、金、銀のうちの少なくとも1種を含む金属ペースト
を充填する。そして、シート状成形体表面には、高周波
信号が伝送可能なストリップ線路、マイクロストリップ
線路、コプレーナ線路、誘電体導波管線路のうちの少な
くとも1種からなる高周波線路パターンに前記金属ペー
ストを用いてスクリーン印刷法、グラビア印刷法などに
よって配線層の厚みが5〜30μmとなるように、印刷
塗布する。
A method of manufacturing the high-frequency wiring board of the present invention having a wiring layer using the above high-frequency porcelain will be specifically described. A slurry is prepared by mixing an appropriate organic solvent and a solvent into the mixed powder composed of the above-mentioned composition, and by using a conventionally known doctor blade method, calender roll method, rolling method, or press molding method, a sheet form is formed. To mold. Then, after forming a through hole in the sheet-shaped molded product as desired, in the through hole,
A metal paste containing at least one of copper, gold and silver is filled. Then, on the surface of the sheet-shaped molded body, the metal paste is used for a high-frequency line pattern formed of at least one of a strip line, a microstrip line, a coplanar line, and a dielectric waveguide line capable of transmitting a high-frequency signal. Screen printing, gravure printing, etc. are applied by printing so that the wiring layer has a thickness of 5 to 30 μm.

【0036】その後、複数のシート状成形体を位置合わ
せして積層圧着し、800〜1000℃の窒素ガスや窒
素−酸素混合ガス等の非酸化性雰囲気で焼成することに
より、本発明の配線基板を作製することができる。そし
て、この配線基板の表面に、適宜、半導体素子等のチッ
プ部品を搭載し、配線層と信号の伝達が可能なように接
続する。
After that, a plurality of sheet-shaped compacts are aligned, laminated and pressure-bonded, and fired in a non-oxidizing atmosphere such as nitrogen gas or nitrogen-oxygen mixed gas at 800 to 1000 ° C. to obtain the wiring board of the present invention. Can be produced. Then, a chip component such as a semiconductor element is appropriately mounted on the surface of the wiring board and connected to the wiring layer so that signals can be transmitted.

【0037】接続方法としては、配線層上に直接搭載さ
せて接続させたり、あるいは50μm程度の樹脂、Ag
−エポキシ、Ag−ガラス、Au−Si等の樹脂、金
属、セラミックス等の接着剤によりチップ部品を絶縁基
板表面に固着し、ワイヤーボンディングや、TABテー
プなどにより配線層と半導体素子とを接続する。
As a connection method, the wiring layer may be directly mounted on the wiring layer for connection, or a resin of about 50 μm, Ag, or the like may be used.
-A chip component is fixed to the surface of the insulating substrate with an adhesive such as a resin such as epoxy, Ag-glass, Au-Si, metal, or ceramics, and the wiring layer and the semiconductor element are connected with each other by wire bonding or TAB tape.

【0038】なお、この半導体素子としては、Si系や
GaAs系等のチップ部品が使用できるが、特に熱膨張
係数の近似性の点では、最もGaAs系のチップ部品の
実装に有効である。
As the semiconductor element, Si-based or GaAs-based chip parts can be used, but it is most effective for mounting GaAs-based chip parts in terms of the approximation of the coefficient of thermal expansion.

【0039】さらに、半導体素子が搭載された配線基板
表面に、絶縁基板と同種の絶縁材料や、その他の絶縁材
料、あるいは放熱性が良好な金属等からなり、電磁波遮
蔽性を有するキャップをガラス、樹脂、ロウ材等の接着
剤により接合してもよく、これにより半導体素子を気密
に封止することができる。
Further, on the surface of the wiring substrate on which the semiconductor element is mounted, a cap made of an insulating material similar to that of the insulating substrate, another insulating material, a metal having a good heat dissipation property, or the like and having an electromagnetic wave shielding property is made of glass, They may be joined by an adhesive such as a resin or a brazing material, whereby the semiconductor element can be hermetically sealed.

【0040】本発明の高周波用配線基板の一例である半
導体素子収納用パッケージの具体的な構造とその実装構
造について図2をもとに説明する。図2は、半導体収納
用パッケージ、特に、接続端子がボール状端子からなる
ボールグリッドアレイ(BGA)型パッケージの概略断
面図である。
A specific structure of a package for housing a semiconductor element, which is an example of the high-frequency wiring board of the present invention, and its mounting structure will be described with reference to FIG. FIG. 2 is a schematic cross-sectional view of a semiconductor housing package, in particular, a ball grid array (BGA) type package in which connection terminals are ball-shaped terminals.

【0041】図2によれば、パッケージAは、絶縁材料
からなる絶縁基板1と蓋体2によりキャビティ3が形成
されており、そのキャビティ3内には、GaAs系等の
チップ部品4が前述の接着剤により実装されている。
As shown in FIG. 2, the package A has a cavity 3 formed by an insulating substrate 1 made of an insulating material and a lid body 2. In the cavity 3, a chip component 4 such as a GaAs system is formed as described above. Mounted with adhesive.

【0042】また、絶縁基板1の表面および内部には、
チップ部品4と電気的に接続された配線層5が形成され
ている。この配線層5は、高周波信号の伝送時に導体損
失を極力低減するために、銅、銀あるいは金などの低抵
抗金属からなることが望ましい。また、本発明によれ
ば、この配線層5に1GHz以上の高周波信号を伝送す
る場合には、高周波信号が損失なく伝送されることが必
要となるため、配線層5はストリップ線路、マイクロス
トリップ線路、コプレーナ線路、誘電体導波管線路のう
ちの少なくとも1種から構成されることが重要である。
On the surface and inside of the insulating substrate 1,
A wiring layer 5 electrically connected to the chip component 4 is formed. The wiring layer 5 is preferably made of a low resistance metal such as copper, silver or gold in order to reduce conductor loss as much as possible when transmitting a high frequency signal. Further, according to the present invention, when transmitting a high frequency signal of 1 GHz or more to the wiring layer 5, it is necessary to transmit the high frequency signal without loss. Therefore, the wiring layer 5 is a strip line or a microstrip line. It is important to be composed of at least one of a coplanar line and a dielectric waveguide line.

【0043】また、図2のパッケージAにおいて、絶縁
基板1の底面には、接続用電極層6が被着形成されてお
り、パッケージA内の配線層5と接続されている。そし
て、接続用電極層6には、半田などのロウ材7によりボ
ール状端子8が被着形成されている。
In the package A of FIG. 2, a connection electrode layer 6 is deposited on the bottom surface of the insulating substrate 1 and connected to the wiring layer 5 in the package A. The ball-shaped terminals 8 are formed on the connecting electrode layer 6 by a brazing material 7 such as solder.

【0044】また、上記パッケージAを外部回路基板に
実装するには、図2に示すように、ポリイミド樹脂、エ
ポキシ樹脂、フェノール樹脂などの有機樹脂を含む絶縁
材料からなる絶縁基板9の表面に配線導体10が形成さ
れた外部回路基板Bに対して、ロウ材を介して実装され
る。具体的には、パッケージAにおける絶縁基板1の底
面に取付けられているボール状端子8と、外部回路基板
Bの配線導体10とを当接させてPb−Snなどの半田
等のロウ材11によりロウ付けして実装される。また、
ボール状端子8自体を溶融させて配線導体10と接続さ
せてもよい。
In order to mount the package A on the external circuit board, wiring is performed on the surface of the insulating substrate 9 made of an insulating material containing an organic resin such as polyimide resin, epoxy resin or phenol resin, as shown in FIG. The external circuit board B on which the conductor 10 is formed is mounted via a brazing material. Specifically, the ball-shaped terminal 8 attached to the bottom surface of the insulating substrate 1 in the package A and the wiring conductor 10 of the external circuit board B are brought into contact with each other and the brazing material 11 such as solder such as Pb-Sn is used. It is mounted by brazing. Also,
The ball-shaped terminal 8 itself may be melted and connected to the wiring conductor 10.

【0045】本発明によれば、GaAs等のチップ部品
4をロウ付けや接着剤により実装したり、このようなボ
ール状端子8を介在したロウ付けによりプリント基板等
の外部回路基板Bに実装されるような表面実装型のパッ
ケージにおいて、GaAs等のチップ部品4や外部回路
基板Bの絶縁基板1との熱膨張差を従来のセラミック材
料よりも小さくできることから、かかる実装構造に対し
て、熱サイクルが印加された場合においても、実装部で
の応力の発生を抑制することができる結果、実装構造の
長期信頼性を高めることができる。
According to the present invention, the chip component 4 made of GaAs or the like is mounted on the external circuit board B such as a printed circuit board by brazing or mounting with an adhesive, or by brazing with such a ball-shaped terminal 8 interposed. In such a surface mount type package, the difference in thermal expansion between the chip component 4 such as GaAs and the insulating substrate 1 of the external circuit board B can be made smaller than that of the conventional ceramic material. Even when the voltage is applied, it is possible to suppress the generation of stress in the mounting portion, so that the long-term reliability of the mounting structure can be improved.

【0046】[0046]

【実施例】下記の組成からなる2種のディオプサイド型
酸化物結晶相を析出可能な結晶化ガラスを準備した。
Example A crystallized glass capable of precipitating two diopside type oxide crystal phases having the following compositions was prepared.

【0047】 ガラスA:SiO250.2重量%−Al235.0重
量% −MgO16.1重量%−SrO13.6重量% −CaO15.1重量% ガラスB:SiO247.5重量%−Al234.9重
量% −MgO16.1重量%−SrO20重量% −CaO11.5重量% そして、この結晶化ガラス粉末に対して、平均粒径が5
μmのクオーツあるいは平均粒径が2μmのアモルファ
スシリカ粉末を用いて、表1、表2の組成となるように
混合した。そして、この混合物に有機バインダ、可塑
剤、トルエンを添加し、スラリーを調製した後、このス
ラリーを用いてドクターブレード法により厚さ300μ
mのグリーンシートを作製した。そして、このグリーン
シートを10〜15枚積層し、50℃の温度で100k
g/cm2の圧力を加えて熱圧着した。得られた積層体
を水蒸気含有/窒素雰囲気中、700℃で脱バインダ処
理を行った後、乾燥窒素中で表1、表2の条件で焼成し
絶縁基板用磁器を得た。
Glass A: SiO 2 50.2 wt% -Al 2 O 3 5.0 wt% -MgO 16.1 wt% -SrO 13.6 wt% -CaO 15.1 wt% Glass B: SiO 2 47.5 wt% % -Al 2 O 3 4.9% by weight-MgO 16.1% by weight-SrO 20% by weight-CaO 11.5% by weight And, with respect to this crystallized glass powder, the average particle size is 5
Quartz of μm or amorphous silica powder having an average particle size of 2 μm was used and mixed so as to have the compositions shown in Tables 1 and 2. Then, an organic binder, a plasticizer, and toluene are added to this mixture to prepare a slurry, and the slurry is used to obtain a thickness of 300 μm by a doctor blade method.
m green sheet was produced. Then, 10 to 15 of these green sheets are laminated and 100 k at a temperature of 50 ° C.
A pressure of g / cm 2 was applied for thermocompression bonding. The obtained laminated body was subjected to binder removal treatment at 700 ° C. in a water vapor-containing / nitrogen atmosphere and then fired in dry nitrogen under the conditions shown in Tables 1 and 2 to obtain a porcelain for an insulating substrate.

【0048】得られた磁器について誘電率、誘電損失を
以下の方法で評価した。測定は形状、直径2〜7mm、
厚み1.5〜2.5mmの形状に切り出し、60GHz
にてネットワークアナライザー、シンセサイズドスイー
パーを用いて誘電体円柱共振器法により行った。測定で
は、NRDガイド(非放射性誘電体線路)で、誘電体共
振器の励起を行い、TE021、TE031モードの共振特性
より、誘電率、誘電損失を算出した。
The dielectric constant and the dielectric loss of the obtained porcelain were evaluated by the following methods. Measurement is shape, diameter 2-7mm,
Cut out into a shape with a thickness of 1.5 to 2.5 mm, 60 GHz
The method was performed by the dielectric cylinder resonator method using a network analyzer and a synthesized sweeper. In the measurement, the NRD guide (non-radiative dielectric line) was used to excite the dielectric resonator, and the dielectric constant and dielectric loss were calculated from the resonance characteristics of the TE 021 and TE 031 modes.

【0049】また、室温から400℃における熱膨張曲
線をとり、熱膨張係数を算出した。さらに、焼結体中に
おける主たる結晶相をX線回折チャートから同定した。
結果は表1、表2に示した。
Further, a thermal expansion curve from room temperature to 400 ° C. was taken and the thermal expansion coefficient was calculated. Further, the main crystal phase in the sintered body was identified from the X-ray diffraction chart.
The results are shown in Tables 1 and 2.

【0050】また、一部の試料については、フィラー成
分として、クォーツおよび/またはアモルファスシリカ
に代わり、ZrO2粉末、CaZrO3粉末を用いて同様
に磁器を作製し評価した(試料No.19〜21、35〜
37)。また、上記結晶化ガラスA、Bに代わり、以下
の組成からなるガラスCを用いて同様に評価を行った
(試料No.38、39)。
For some samples, ZrO 2 powder and CaZrO 3 powder were used in place of quartz and / or amorphous silica as the filler component, and porcelain was prepared and evaluated in the same manner (Sample Nos. 19 to 21). 35-
37). Further, a glass C having the following composition was used instead of the crystallized glasses A and B, and the same evaluation was performed (Samples No. 38 and 39).

【0051】ガラスC:SiO210.4重量%−Al2
32.5重量% −B2345.3重量%−CaO35.2重量% −Na2O6.6重量%
Glass C: SiO 2 10.4 wt% -Al 2
O 3 2.5 wt% -B 2 O 3 45.3 wt% -CaO35.2 wt% -Na 2 O6.6 wt%

【0052】[0052]

【表1】 [Table 1]

【0053】[0053]

【表2】 [Table 2]

【0054】表1、2の結果から明らかなように、Si
2、Al23、MgO、SrO、CaOを含むガラス
量が、95重量%を越える試料No.1、22では、誘
電損失が30×10-4を越えてしまい、ガラス量が50
重量%よりも少ない試料No.10、14、18、34
では、低温で焼結することが困難であり、緻密化しなか
った。試料No.19〜21、35〜37は、ガラスへ
の添加成分として、ZrO2やCaZrO3を配合したも
のであるが、焼結体中にZrO2やCaZrO3などが析
出し誘電損失が増大した。また、ガラスとして、B23
を多く含むガラスCを用いた試料No.38では溶融し
てしまい、また、試料No.39では、Bを含むガラス
が多く残留し、誘電損失が大きくなる傾向にあった。
As is clear from the results of Tables 1 and 2, Si
Sample No. in which the amount of glass containing O 2 , Al 2 O 3 , MgO, SrO, and CaO exceeds 95% by weight. In Nos. 1 and 22, the dielectric loss exceeded 30 × 10 −4 and the glass amount was 50.
Sample No. less than wt% 10, 14, 18, 34
Then, it was difficult to sinter at low temperature, and it was not densified. Sample No. Nos. 19 to 21 and 35 to 37 are those in which ZrO 2 or CaZrO 3 was added as an additive component to glass, but ZrO 2 or CaZrO 3 was precipitated in the sintered body and dielectric loss increased. Further, as glass, B 2 O 3
Sample No. using glass C containing a large amount of No. 38 melts, and sample No. In No. 39, a large amount of glass containing B remained, and the dielectric loss tended to increase.

【0055】これに対して、本発明に従い、特定量のク
ォーツ粉末を主として添加した試料No.2〜9、1
5、17、23〜28、32、33では、磁器中にクォ
ーツ相の析出が見られ、また、いずれも熱膨張係数が
8.5ppm/℃以上、60GHzの測定周波数にて、
誘電率7以下、誘電損失が30×10-4以下の優れた特
性を有するものであった。
On the other hand, according to the present invention, the sample No. containing mainly the specified amount of quartz powder was added. 2-9, 1
In 5, 17, 23 to 28, 32, 33, precipitation of a quartz phase was observed in the porcelain, and in all cases, the coefficient of thermal expansion was 8.5 ppm / ° C. or higher at a measurement frequency of 60 GHz,
It had excellent properties such as a dielectric constant of 7 or less and a dielectric loss of 30 × 10 −4 or less.

【0056】また、本発明に従い、特定量のアモルファ
スシリカ粉末を主として添加した試料No.11〜1
3、16、29〜31では、磁器中にアモルファスシリ
カ相が存在し、また、いずれも熱膨張係数が5.5pp
m/℃以上、60GHzの測定周波数にて、誘電率5.
9以下、誘電損失が20×10-4以下の優れた特性を有
するものであった。
Further, according to the present invention, the sample No. containing mainly a specific amount of amorphous silica powder was added. 11-1
In Nos. 3, 16, and 29 to 31, an amorphous silica phase was present in the porcelain and all had thermal expansion coefficients of 5.5 pp.
Dielectric constant of 5. at m / ° C or higher and a measurement frequency of 60 GHz.
It had excellent characteristics of 9 or less and a dielectric loss of 20 × 10 −4 or less.

【0057】[0057]

【発明の効果】以上詳述した通り、本発明の高周波用配
線基板の絶縁基板は、1000℃以下の低温にて焼成で
きることから、銅などの低抵抗金属による配線層を形成
でき、しかも1GHz以上の高周波領域において、低誘
電率、低誘電損失を有することから、高周波信号を極め
て良好に損失なく伝送することができる。
As described in detail above, since the insulating substrate of the high-frequency wiring board of the present invention can be fired at a low temperature of 1000 ° C. or less, a wiring layer made of a low resistance metal such as copper can be formed, and 1 GHz or more. Since it has a low dielectric constant and a low dielectric loss in the high frequency region, it is possible to transmit a high frequency signal very satisfactorily without loss.

【0058】しかも、この絶縁基板は、GaAsチップ
あるいはプリント基板と近似した熱膨張特性に制御でき
ることから、GaAsチップを実装した場合、あるいは
有機樹脂を含む絶縁基板を具備するプリント基板などの
マザーボードに対してロウ材等により実装した場合にお
いて優れた耐熱サイクル性を有し、高信頼性の実装構造
を提供できる。
Moreover, since this insulating substrate can be controlled to have a thermal expansion characteristic similar to that of a GaAs chip or a printed circuit board, when a GaAs chip is mounted or a mother board such as a printed circuit board having an insulating substrate containing an organic resin is used. It is possible to provide a highly reliable mounting structure having excellent thermal cycle resistance when mounted with a brazing material or the like.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の配線基板の絶縁基板の組織を説明する
ための概略図である。
FIG. 1 is a schematic diagram for explaining the structure of an insulating substrate of a wiring board of the present invention.

【図2】本発明の高周波用配線基板の一例である半導体
素子収納用パッケージの実装構造の一例を説明するため
の概略断面図である。
FIG. 2 is a schematic cross-sectional view for explaining an example of a mounting structure of a package for housing a semiconductor element, which is an example of a high-frequency wiring board of the present invention.

【符号の説明】[Explanation of symbols]

DI ディオプサイド型酸化物結晶相 Si SiO2結晶相 AM アモルファスシリカ相 G 非晶質(ガラス)相 A 半導体素子収納用パッケージ(高周波用配線基板) B 外部回路基板 1 絶縁基板 2 蓋体 3 キャビティ 4 チップ部品 5 配線層 6 接続用電極層 7 ロウ材 8 ボール状端子 9 絶縁基板 10 配線導体 11 ロウ材DI Diopside type oxide crystal phase Si SiO 2 crystal phase AM amorphous silica phase G amorphous (glass) phase A semiconductor element storage package (high-frequency wiring board) B external circuit board 1 insulating board 2 lid 3 cavity 4 Chip Component 5 Wiring Layer 6 Connection Electrode Layer 7 Brazing Material 8 Ball Terminal 9 Insulating Substrate 10 Wiring Conductor 11 Brazing Material

Claims (4)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】少なくともMg、Ca、Si、Alを含む
ディオプサイド型酸化物結晶相と、クォーツ結晶相とを
含有し、且つ室温から400℃における熱膨張係数が
5.5ppm/℃以上、誘電率が7以下、60〜77G
Hzでの誘電損失が30×10−4以下の高周波用磁器
を絶縁基板とし、該絶縁基板の表面および内部にストリ
ップ線路、マイクロストリップ線路、コプレーナ線路、
誘電体導波管線路のうちの少なくとも1種から構成され
る配線層を具備し、前記絶縁基板表面にGaAs系のチ
ップ部品が実装されるとともに、前記絶縁基板のGaA
sとの熱膨張差が2ppm/℃以下であることを特徴と
する高周波用配線基板。
1. A diopside type oxide crystal phase containing at least Mg, Ca, Si and Al, and a quartz crystal phase, and having a thermal expansion coefficient of 5.5 ppm / ° C. or more from room temperature to 400 ° C. Dielectric constant of 7 or less, 60-77G
A high frequency porcelain having a dielectric loss at 30 Hz or less of 30 × 10 −4 is used as an insulating substrate, and a strip line, a microstrip line, a coplanar line, and
A wiring layer composed of at least one of the dielectric waveguide lines is provided , and a GaAs-based chip is formed on the surface of the insulating substrate.
Is mounted, and the GaA of the insulating substrate is mounted.
A high-frequency wiring board having a difference in thermal expansion with s of 2 ppm / ° C. or less .
【請求項2】前記高周波用磁器の室温から400℃にお
ける熱膨張係数が8.5ppm/℃以上であることを特
徴とする請求項1記載の高周波用配線基板。
2. The high frequency wiring board according to claim 1, wherein the high frequency porcelain has a thermal expansion coefficient of 8.5 ppm / ° C. or more from room temperature to 400 ° C.
【請求項3】前記高周波用磁器が、SiO、Al
、MgO、SrOおよびCaOを含み、ディオプサイ
ド型酸化物結晶相を析出可能なガラス50〜95重量%
と、クォーツおよび/またはアモルファスシリカの総量
5〜50重量%との割合で含有する高周波用磁器組成
物を成形後、800〜1000℃の温度で焼成してなる
ことを特徴とする請求項1または請求項2記載の高周波
用配線基板。
3. The high frequency porcelain is SiO 2 , Al 2 O
Glass containing 3 , MgO, SrO and CaO and capable of precipitating a diopside type oxide crystal phase 50 to 95% by weight
And the total amount of quartz and / or amorphous silica
3. The high frequency wiring board according to claim 1 or 2, wherein the high frequency ceramic composition containing 5 to 50% by weight is molded and then fired at a temperature of 800 to 1000C. .
【請求項4】前記ガラスが、SiO45〜55重量%
と、Al3〜10重量%と、MgO13〜24重
量%と、SrO10〜24重量%と、CaO8〜20重
量%と、からなることを特徴とする請求項3記載の高周
波用配線基板。
4. The glass contains 45 to 55% by weight of SiO 2.
4. The high-frequency wiring board according to claim 3, comprising: Al 2 O 3 3 to 10 wt%, MgO 13 to 24 wt%, SrO 10 to 24 wt%, and CaO 8 to 20 wt%. .
JP2000192742A 2000-06-27 2000-06-27 High frequency wiring board Expired - Fee Related JP3466545B2 (en)

Priority Applications (1)

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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000192742A JP3466545B2 (en) 2000-06-27 2000-06-27 High frequency wiring board

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP10317736A Division JP3131191B2 (en) 1998-09-29 1998-11-09 High frequency porcelain composition and high frequency porcelain

Publications (2)

Publication Number Publication Date
JP2001068597A JP2001068597A (en) 2001-03-16
JP3466545B2 true JP3466545B2 (en) 2003-11-10

Family

ID=18691830

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP3466545B2 (en)

Also Published As

Publication number Publication date
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