JP2001068597A - High-frequency wiring board - Google Patents

High-frequency wiring board

Info

Publication number
JP2001068597A
JP2001068597A JP2000192742A JP2000192742A JP2001068597A JP 2001068597 A JP2001068597 A JP 2001068597A JP 2000192742 A JP2000192742 A JP 2000192742A JP 2000192742 A JP2000192742 A JP 2000192742A JP 2001068597 A JP2001068597 A JP 2001068597A
Authority
JP
Japan
Prior art keywords
frequency
wiring board
glass
crystal phase
thermal expansion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2000192742A
Other languages
Japanese (ja)
Other versions
JP3466545B2 (en
Inventor
Yoshitake Terashi
吉健 寺師
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2000192742A priority Critical patent/JP3466545B2/en
Publication of JP2001068597A publication Critical patent/JP2001068597A/en
Application granted granted Critical
Publication of JP3466545B2 publication Critical patent/JP3466545B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

PROBLEM TO BE SOLVED: To obtain a high-frequency wiring board, that has a low dielectric constant and low dielectric loss at a high-frequency region and has a thermal coefficient of expansion close to that of such chip components and printed-wiring board as a GaAs and can be surely mounted to them. SOLUTION: Glass (50-95 wt.%) for depositing diopside-type oxide crystal phase (DI) containing SiO2, Al2O3, MgO, SrO, and CaO, and quartz (5-50 wt.%) are formed and are baked at 800-1,000 deg.C as the dioposide-type oxide crystal phase (DI), porcelain that contains SiO2 crystal phase (Si) and has a thermal coefficient of expansion of 5.5 ppm/ deg.C or higher from room temperature to 400 deg.C, a permittivity of 7 or smaller, and a dielectric loss of 30×10-4 or less at 60-77 GHz is set to an insulation substrate 1, and a wiring substrate A for high frequency with a wiring layer 5 which composed by one type out of a strip line, a microstrip line, a coplanar line, and dielectric waveguide line is made.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体素子収納用
パッケージや多層配線基板等に適用される配線基板に関
するものであり、特に、銅や銀と同時焼成が可能であ
り、また、GaAs等のチップ部品やプリント基板など
の有機樹脂からなる外部回路基板に対し、高い信頼性を
もって実装可能である高周波用配線基板に関するもので
ある。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board applied to a package for storing semiconductor elements, a multilayer wiring board, and the like, and more particularly to a wiring board which can be co-fired with copper or silver. The present invention relates to a high-frequency wiring board that can be mounted with high reliability on an external circuit board made of an organic resin such as a chip component or a printed board.

【0002】[0002]

【従来技術】従来より、セラミック多層配線基板として
は、アルミナ質焼結体からなる絶縁基板の表面または内
部にタングステンやモリブデンなどの高融点金属からな
る配線層が形成されたものが最も普及している。
2. Description of the Related Art Conventionally, as a ceramic multilayer wiring board, a ceramic multilayer wiring board in which a wiring layer made of a refractory metal such as tungsten or molybdenum is formed on the surface or inside of an insulating substrate made of an alumina-based sintered body has been most widely used. I have.

【0003】また、最近に至り、高度情報化時代を迎
え、使用される周波数帯域はますます高周波化に移行し
つつある。このような、高周波の信号の伝送を必要とす
る高周波配線基板においては、高周波信号を損失なく伝
送する上で、配線層を形成する導体の抵抗が小さいこ
と、また絶縁基板の高周波領域での誘電損失が小さいこ
とが要求される。
Further, recently, with the era of advanced information, the frequency band to be used is shifting to higher and higher frequencies. In such a high-frequency wiring board that requires transmission of a high-frequency signal, in order to transmit a high-frequency signal without loss, the resistance of the conductor forming the wiring layer is small, and the dielectric of the insulating substrate in the high-frequency region is low. Low loss is required.

【0004】ところが、従来のタングステン(W)や、
モリブデン(Mo)などの高融点金属は導体抵抗が大き
く、信号の伝搬速度が遅く、また、1GHz以上の高周
波領域の信号伝搬も困難であることから、W、Moなど
の金属に代えて銅、銀、金などの低抵抗金属を使用する
ことが必要となっている。このような低抵抗金属からな
る配線層は、融点が低く、アルミナと同時焼成すること
が不可能であるため、最近では、ガラス、またはガラス
とセラミックスとの複合材料からなる、いわゆるガラス
セラミックスを絶縁基板として用いた配線基板が開発さ
れつつある。例えば、特開昭60−240135号のよ
うに、ホウケイ酸亜鉛系ガラスに、Al 23、ジルコニ
ア、ムライトなどのフィラーを添加したものを低抵抗金
属と同時焼成した多層配線基板や、特開平5−2989
19号のように、ムライトやコージェライトを結晶相と
して析出させたガラスセラミック材料が提案されてい
る。
However, conventional tungsten (W),
Refractory metals such as molybdenum (Mo) have high conductor resistance
Signal propagation speed is slow, and high frequency
Since it is difficult to propagate signals in the wave region, W, Mo, etc.
Use low-resistance metals such as copper, silver, and gold instead of metals
It is necessary. Because of such low resistance metal
The wiring layer has a low melting point and should be co-fired with alumina.
Is impossible, because recently, glass, or glass
So-called glass made of composite material of ceramic and ceramic
Wiring board using ceramics as insulating substrate was developed.
It is getting. For example, JP-A-60-240135
In the case of zinc borosilicate glass, TwoOThree, Zirconi
A, low-resistance gold with fillers such as mullite
Multilayer wiring board co-fired with metal
As in No. 19, mullite and cordierite are used as crystalline phases.
Glass ceramic materials deposited by
You.

【0005】また、多層配線基板や半導体素子収納用パ
ッケージなどの配線基板にGaAsなどのチップ部品を
実装したり、また配線基板をマザーボードなどの有機樹
脂を含むプリント基板に実装する上で、絶縁基板とチッ
プ部品あるいはプリント基板との熱膨張差に起因して発
生する応力により実装部分が剥離したり、クラックなど
が発生するのを防止する観点から、絶縁基板の熱膨張係
数がチップ部品やプリント基板のそれと近似しているこ
とが望まれる。
Further, when mounting chip parts such as GaAs on a wiring board such as a multilayer wiring board or a package for housing semiconductor elements, or mounting a wiring board on a printed board containing an organic resin such as a motherboard, an insulating board is required. In order to prevent the mounting part from peeling or cracking due to the stress generated due to the thermal expansion difference between the chip part and the printed circuit board, the thermal expansion coefficient of the It is desired to be close to that of

【0006】そこで、本出願人は、先に特開平9−17
904号に開示されるように、結晶化が可能なリチウム
珪酸ガラスを用いることにより、絶縁基板の熱膨張係数
を高めることができることを提案した。
Therefore, the present applicant has previously disclosed in Japanese Patent Laid-Open No. 9-17 / 1997.
As disclosed in Japanese Patent No. 904, it has been proposed that the use of crystallizable lithium silicate glass can increase the thermal expansion coefficient of an insulating substrate.

【0007】[0007]

【発明が解決しようとする課題】しかしながら、前記従
来のガラスセラミックスは、銅、銀、金などの低抵抗金
属との同時焼成が可能であっても、熱膨張係数が3〜5
ppm/℃程度と低く、GaAs等のチップ部品(熱膨
張係数6〜7.5ppm/℃)を実装したり、プリント
基板(熱膨張係数12〜15ppm/℃)に実装する場
合に、実装の信頼性が低く実用上満足できるものではな
かった。
However, the conventional glass ceramic has a thermal expansion coefficient of 3 to 5 even if it can be co-fired with a low-resistance metal such as copper, silver or gold.
ppm / ° C, which is as low as about 1 ppm / ° C, the reliability of mounting when mounting chip parts such as GaAs (coefficient of thermal expansion: 6 to 7.5 ppm / ° C) or printed circuit boards (coefficient of thermal expansion: 12 to 15 ppm / ° C) The properties were low and were not practically satisfactory.

【0008】また、特開平9−17904号に開示され
るようにアルカリ金属を含有するガラスを用いる方法で
は、長時間高温多湿雰囲気に曝されると、アルカリ金属
が大気中の水分と反応し表面にシリケート結晶相が析出
して表面が変質してしまう場合があった。
In the method using a glass containing an alkali metal as disclosed in Japanese Patent Application Laid-Open No. Hei 9-17904, when exposed to a high-temperature and high-humidity atmosphere for a long time, the alkali metal reacts with the moisture in the atmosphere to produce a surface. In some cases, a silicate crystal phase is precipitated and the surface is deteriorated.

【0009】また、従来のガラスセラミックスは、ミリ
波などの高周波信号を用いる配線基板の絶縁基板として
具体的に検討されておらず、そのほとんどは誘電損失が
高く、十分満足できる高周波特性を有するものではなか
った。
Conventional glass ceramics have not been specifically studied as insulating substrates for wiring boards using high-frequency signals such as millimeter waves, and most of them have high dielectric loss and have satisfactory high-frequency characteristics. Was not.

【0010】従って、本発明は、金、銀、銅を配線導体
として多層化が可能な800〜1000℃での焼成が可
能であるとともに、GaAs等のチップ部品やプリント
基板の熱膨張係数と近似した熱膨張係数に制御可能であ
り、高周波領域においても低誘電率でかつ誘電損失が低
い磁器を絶縁基板とする配線基板を提供することを目的
とする。
Therefore, the present invention can be fired at 800 to 1000 ° C., which can be multilayered using gold, silver and copper as wiring conductors, and has a thermal expansion coefficient close to that of chip parts such as GaAs or a printed circuit board. It is an object of the present invention to provide a wiring board which can control the thermal expansion coefficient to a low value and has a low dielectric constant and a low dielectric loss even in a high-frequency region, using a porcelain as an insulating substrate.

【0011】[0011]

【課題を解決するための手段】本発明者は、上記課題を
鋭意検討した結果、SiO2、Al23、MgO、Sr
OおよびCaOを含み、ディオプサイド型酸化物結晶相
を析出可能なガラスに対して、クォーツを特定の比率で
配合した組成物を用い、これを成形後、800〜100
0℃の温度で焼成することによって、低誘電率で、かつ
GaAs等のチップ部品やプリント基板の熱膨張係数と
近似した熱膨張係数に制御でき、1GHz以上の高周波
領域においても低誘電損失を有する磁器が得られること
を知見し、本発明に至った。
Means for Solving the Problems As a result of diligent study of the above-mentioned problems, the present inventors have found that SiO 2 , Al 2 O 3 , MgO, Sr
For a glass containing O and CaO and capable of precipitating a diopside oxide crystal phase, a composition in which quartz is blended at a specific ratio is used.
By firing at a temperature of 0 ° C., the dielectric constant can be controlled to a low dielectric constant and a thermal expansion coefficient similar to that of a chip component such as GaAs or a printed circuit board, and a low dielectric loss even in a high frequency region of 1 GHz or more. The inventors have found that porcelain can be obtained, and have reached the present invention.

【0012】即ち、本発明の高周波用配線基板は、少な
くともMg、Ca、Si、Alを含むディオプサイド型
酸化物結晶相と、クォーツ結晶相とを含有し、且つ室温
から400℃における熱膨張係数が5.5ppm/℃以
上、誘電率が7以下、60〜77GHzでの誘電損失が
30×10-4以下であることを特徴とする高周波用磁器
を絶縁基板とし、該絶縁基板の表面および内部にストリ
ップ線路、マイクロストリップ線路、コプレーナ線路、
誘電体導波管線路のうちの少なくとも1種から構成され
る配線層を具備することを特徴とするものである。
That is, the high-frequency wiring board of the present invention contains a diopside oxide crystal phase containing at least Mg, Ca, Si, and Al, and a quartz crystal phase, and has a thermal expansion from room temperature to 400 ° C. A high-frequency ceramic having a coefficient of 5.5 ppm / ° C. or more, a dielectric constant of 7 or less, and a dielectric loss at 60 to 77 GHz of 30 × 10 −4 or less as an insulating substrate; Inside, stripline, microstrip line, coplanar line,
It is characterized by including a wiring layer composed of at least one of the dielectric waveguide lines.

【0013】ここで、前記絶縁基板表面にGaAs系の
チップ部品を実装することが望ましく、また、前記高周
波用磁器の室温から400℃における熱膨張係数が8.
5ppm/℃以上であることが望ましい。
Here, it is desirable to mount a GaAs-based chip component on the surface of the insulating substrate, and that the high-frequency ceramic has a coefficient of thermal expansion from room temperature to 400 ° C. of 8.
It is desirable that the concentration be 5 ppm / ° C. or more.

【0014】さらに、前記高周波用磁器が、SiO2
Al23、MgO、SrOおよびCaOを含み、ディオ
プサイド型酸化物結晶相を析出可能なガラス50〜95
重量%と、クォーツ5〜50重量%との割合で含有する
高周波用磁器組成物を成形後、800〜1000℃の温
度で焼成してなること、前記ガラスが、SiO245〜
55重量%と、Al233〜10重量%と、MgO13
〜24重量%と、SrO10〜24重量%と、CaO8
〜20重量%と、からなることが望ましい。
Further, the high frequency porcelain is made of SiO 2 ,
Al 2 O 3, MgO, include SrO and CaO, diopside-type oxide crystal phase can deposit glass 50-95
And weight%, after forming a high-frequency ceramic composition in a proportion of quartz 5-50% by weight, obtained by sintering at a temperature of 800 to 1000 ° C., the glass, SiO 2. 45 to
55% by weight, 3 to 10% by weight of Al 2 O 3 and MgO 13
-24% by weight, SrO 10-24% by weight, CaO 8
-20% by weight.

【0015】[0015]

【発明の実施の形態】本発明の高周波用配線基板の絶縁
基板を作製するための高周波用磁器組成物は、Si
2、Al23、MgO、SrOおよびCaOを含み、
ディオプサイド型酸化物結晶相を析出可能なガラス50
〜95重量%と、クォーツ5〜50重量%との割合で含
有するものである。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A high frequency porcelain composition for producing an insulating substrate of a high frequency wiring board according to the present invention is made of Si.
O 2 , Al 2 O 3 , MgO, SrO and CaO,
Glass 50 capable of precipitating a diopside oxide crystal phase
To 95% by weight and 5 to 50% by weight of quartz.

【0016】各成分組成を上記の範囲に限定したのは、
上記ガラスが50重量%よりも少ないと、1000℃以
下の温度での焼成により磁器を緻密化させることが困難
であり、95重量%よりも多いと、ガラスの結晶化が不
十分となり、誘電損失の大きなガラス相が残留し、磁器
の高周波での誘電損失が増大するためである。ガラスの
特に望ましい範囲は、60〜85重量%である。
The reason for limiting each component composition to the above range is as follows.
If the content of the glass is less than 50% by weight, it is difficult to densify the porcelain by firing at a temperature of 1000 ° C. or less, and if the content is more than 95% by weight, the crystallization of the glass becomes insufficient, and the dielectric loss becomes large. This is because a large glass phase remains and the dielectric loss of the porcelain at high frequencies increases. A particularly desirable range for the glass is 60-85% by weight.

【0017】クォーツの総量が5重量%よりも少ない
と、ガラスの残存率が高くなり、誘電損失が大きくな
る。逆に、50重量%を越えると、難焼結性となり、1
000℃以下の焼成温度で緻密化することができない。
クォーツの望ましい範囲は、15〜40重量%である。
If the total amount of quartz is less than 5% by weight, the residual ratio of the glass increases and the dielectric loss increases. Conversely, if it exceeds 50% by weight, sintering becomes difficult, and
It cannot be densified at a firing temperature of 000 ° C. or lower.
A desirable range of quartz is 15 to 40% by weight.

【0018】ここで、前記ディオプサイド型酸化物結晶
相を析出可能なガラスは、ガラスの軟化点が500〜8
00℃であることが望ましく、その組成はSiO245
〜55重量%、Al233〜10重量%、MgO13〜
24重量%、SrO10〜24重量%、CaO8〜20
重量%の割合であることが望ましい。
Here, the glass capable of precipitating the diopside-type oxide crystal phase has a glass softening point of 500-8.
00 ° C., and the composition is SiO 2 45
55 wt%, Al 2 O 3 3~10 wt%, MgO13~
24% by weight, 10 to 24% by weight of SrO, 8 to 20 of CaO
Desirably, it is in a percentage by weight.

【0019】上記のガラスからのディオプサイド型酸化
物結晶相の析出割合を高める上では、ガラス中における
CaOとMgOの合計量が35〜44重量%であること
が望ましい。
In order to increase the precipitation ratio of the diopside oxide crystal phase from the above glass, it is desirable that the total amount of CaO and MgO in the glass is 35 to 44% by weight.

【0020】上記高周波用磁器組成物を用い、磁器を製
造するには、SiO2、Al23、MgO、SrOおよ
びCaOを含みディオプサイド型酸化物結晶相を析出可
能な結晶化ガラスと、クォーツおよび/またはアモルフ
ァスシリカからなる上記組成物の混合粉末を用いて、ド
クターブレード法やカレンダーロール法、あるいは圧延
法、プレス成形法の周知の成型法により所定形状の成形
体を作製した後、該成形体を800〜1000℃の酸化
性雰囲気または非酸化性雰囲気中で焼成することにより
作製することができる。
In order to manufacture a porcelain using the above-described high frequency porcelain composition, a crystallized glass containing SiO 2 , Al 2 O 3 , MgO, SrO and CaO and capable of precipitating a diopside oxide crystal phase is used. Using a mixed powder of the above composition comprising quartz and / or amorphous silica, a doctor blade method or a calender roll method, or a rolling method, after forming a molded body of a predetermined shape by a known molding method such as a press molding method, It can be produced by firing the molded body in an oxidizing atmosphere or a non-oxidizing atmosphere at 800 to 1000 ° C.

【0021】本発明によれば、上記のガラス組成物を用
いることによって、フィラーとしてSiO2のような高
融点化物質を含有するにもかかわらず、1000℃以
下、特に950℃以下、さらには930℃以下での焼成
が可能であることから、後述するように本発明の高周波
用配線基板の配線層として多用されている銅および/ま
たは銀との同時焼成が可能である。
According to the present invention, the use of the above glass composition makes it possible to use a glass material having a high melting point such as SiO 2 as a filler, at a temperature of 1000 ° C. or less, particularly 950 ° C. or less, and even 930 ° C. Since firing at a temperature of not more than ° C. is possible, simultaneous firing with copper and / or silver, which is frequently used as a wiring layer of the high-frequency wiring board of the present invention, is possible as described later.

【0022】ここで、クォーツを添加する場合には、焼
成によりクォーツの他にクリストバライト、トリジマイ
トなどに相変態してもよいが、クリストバライトは、2
00℃付近に熱膨張係数の屈曲点を有することから熱膨
張挙動、誘電特性の点でクォーツとして残存することが
望ましい。
When quartz is added, it may be transformed into cristobalite, tridymite or the like by sintering in addition to quartz.
Since it has a bending point of the thermal expansion coefficient near 00 ° C., it is desirable that the thermal expansion coefficient and the dielectric properties remain as quartz.

【0023】上記の態様の磁器組成物は、800〜10
00℃の温度範囲での焼成によって相対密度97%以上
まで緻密化することができ、これによって形成される磁
器の全体組成としては、Si、Al、Mg、Srおよび
Caの各金属元素の酸化物換算による合量を100重量
%とした時、SiO2を55〜75重量%、Al23
3〜5重量%、MgOを10〜14重量%、SrOを1
5〜23重量%、CaO14〜19重量%の割合から構
成されることが望ましい。
The porcelain composition of the above embodiment has a composition of 800 to 10
The porcelain can be densified to a relative density of 97% or more by baking in a temperature range of 00 ° C., and the resulting porcelain has an overall composition of oxides of metal elements of Si, Al, Mg, Sr and Ca when the total amount was 100 wt% by translation, the SiO 2 55 to 75 wt%, the Al 2 O 3 3 to 5 wt%, the MgO 10 to 14 wt%, the SrO 1
It is desirable that the composition be 5 to 23% by weight and 14 to 19% by weight of CaO.

【0024】一般に、Al23やSiO2を含むガラス
相の熱膨張係数は4〜5ppm/℃と低い。これに対
し、Ca(Mg,Al)(Si,Al)26のディオプ
サイド型酸化物結晶相は、約8〜9ppm/℃の高熱膨
張特性を有することから、上記組成のガラスよりディオ
プサイド型酸化物結晶相を析出させることにより、高熱
膨張化することができる。また、ディオプサイド型酸化
物結晶相は、6〜8の誘電率を有し、かつ高周波帯での
誘電損失が小さい材料である。
Generally, the glass phase containing Al 2 O 3 or SiO 2 has a low thermal expansion coefficient of 4 to 5 ppm / ° C. On the other hand, the diopside oxide crystal phase of Ca (Mg, Al) (Si, Al) 2 O 6 has a high thermal expansion characteristic of about 8 to 9 ppm / ° C. High thermal expansion can be achieved by precipitating a pside oxide crystal phase. The diopside oxide crystal phase is a material having a dielectric constant of 6 to 8 and having a small dielectric loss in a high frequency band.

【0025】上記磁器組成物によれば、ガラス、クォー
ツおよびアモルファスシリカ(熱膨張係数2〜5ppm
/℃)量を制御することによって、熱膨張係数や誘電率
等を任意に調整することができる。
According to the above porcelain composition, glass, quartz and amorphous silica (coefficient of thermal expansion 2 to 5 ppm)
/ ° C), the coefficient of thermal expansion, the dielectric constant, and the like can be arbitrarily adjusted.

【0026】例えば、上述した高周波用磁器中にクォー
ツ結晶相またはクォーツ結晶相とアモルファスシリカ相
を存在させることによって、室温から400℃における
熱膨張係数が5.5ppm/℃以上、誘電率が7以下、
60〜77GHzでの誘電損失が30×10-4以下の特
性に制御可能である。
For example, the presence of a quartz crystal phase or a quartz crystal phase and an amorphous silica phase in the above-mentioned high frequency porcelain allows a thermal expansion coefficient from room temperature to 400 ° C. of 5.5 ppm / ° C. or more and a dielectric constant of 7 or less. ,
The dielectric loss at 60 to 77 GHz can be controlled to a characteristic of 30 × 10 −4 or less.

【0027】本発明によれば、上記組成のガラスに対し
て、フィラーとしてクォーツを添加することにより、磁
器中にディオプサイド型酸化物結晶相を析出させるとと
もに、13〜20ppm/℃の高熱膨張係数を有するク
ォーツ結晶相を含有させることにより、磁器の熱膨張係
数を8.5ppm/℃以上に高めることができる。その
結果、磁器とGaAs等のチップ部品およびプリント基
板等の有機樹脂からなる外部回路基板との熱膨張係数差
を小さくできることから、本発明の磁器を配線基板の絶
縁基板として用いる場合、実装の信頼性を高めることが
できる。
According to the present invention, by adding quartz as a filler to the glass having the above composition, a diopside oxide crystal phase is precipitated in the porcelain and a high thermal expansion of 13 to 20 ppm / ° C. By including a quartz crystal phase having a coefficient, the thermal expansion coefficient of the porcelain can be increased to 8.5 ppm / ° C. or more. As a result, the difference in the coefficient of thermal expansion between the porcelain and an external circuit board made of an organic resin such as a chip component such as GaAs and a printed board can be reduced. Therefore, when the porcelain of the present invention is used as an insulating substrate of a wiring board, the reliability of mounting is reduced. Can be enhanced.

【0028】また、クォーツの誘電率が4〜4.5であ
ることから、磁器の誘電率を7以下とすることができ、
基板の高周波信号への影響を小さくできるとともに、ク
ォーツはミリ波帯での誘電損失が小さい材料であること
から、磁器の60〜77GHzでの誘電損失を30×1
-4以下とすることができることから、高周波帯、特に
ミリ波帯での信号の伝送特性が向上する。
Further, since the dielectric constant of quartz is 4 to 4.5, the dielectric constant of porcelain can be reduced to 7 or less.
Since the influence of the substrate on the high-frequency signal can be reduced and quartz is a material having a small dielectric loss in the millimeter wave band, the dielectric loss of porcelain at 60 to 77 GHz is reduced by 30 × 1.
Since it can be 0 -4 or less, signal transmission characteristics in a high frequency band, particularly in a millimeter wave band, are improved.

【0029】また、上記のようにして作製された磁器
は、図1の磁器組織の概略図に示すように、結晶相とし
て、ガラスから析出する少なくともMgとCaとSiと
Alとを含むディオプサイド型酸化物結晶相Ca(M
g,Al)(Si,Al)26(DI)以外に、SiO
2系相(Si、AM)を含有するものであり、それ以外
にも、Ca2MgSi27(akermanite)、
CaMgSiO4(monticellite)、Ca3
MgSi28(merwinite)等高熱膨張を有す
る類似の相が析出してもよい。
Further, as shown in the schematic diagram of the porcelain structure of FIG. 1, the porcelain produced as described above has a dioptric phase containing at least Mg, Ca, Si and Al precipitated from glass as a crystal phase. Side-type oxide crystal phase Ca (M
g, Al) (Si, Al) 2 O 6 (DI)
It contains two system phases (Si, AM), and also contains Ca 2 MgSi 2 O 7 (akermanite),
CaMgSiO 4 (Monticellite), Ca 3
Similar phases with high thermal expansion, such as MgSi 2 O 8 (merwinite), may precipitate.

【0030】また、本発明によれば、上記組成のガラス
に対して、フィラーとしてアモルファスシリカを主とし
て添加することにより、磁器中ディオプサイド型酸化物
結晶相を析出させるとともに、その粒界をアモルファス
シリカ相により主として形成することにより、アモルフ
ァスシリカの誘電率が3.8〜4.2と低いことから、
磁器の誘電率を5.9以下とすることができ、高周波用
配線基板等に用いる場合、高周波信号の伝送特性への基
板の影響が小さくすることが可能となる。さらに、アモ
ルファスシリカはミリ波帯での誘電損失が小さい材料で
あることから、磁器の60〜77GHzでの誘電損失を
30×10-4以下とすることができる。
Further, according to the present invention, by adding amorphous silica as a filler to a glass having the above composition, a diopside-type oxide crystal phase is precipitated in porcelain, and the grain boundary is reduced to an amorphous phase. Since the dielectric constant of amorphous silica is as low as 3.8 to 4.2 by being mainly formed by the silica phase,
The dielectric constant of the porcelain can be 5.9 or less, and when used for a high-frequency wiring board or the like, the influence of the board on transmission characteristics of high-frequency signals can be reduced. Furthermore, since amorphous silica is a material having a small dielectric loss in a millimeter wave band, the dielectric loss of porcelain at 60 to 77 GHz can be reduced to 30 × 10 −4 or less.

【0031】上記磁器組成物は、高周波帯での誘電損失
が低いことから1GHz以上、特に20GHz以上、さ
らには50GHz以上、またさらには70GHz以上の
高周波用配線基板の絶縁層を形成するのに好適である。
上記磁器を配線基板の絶縁基板として用いる場合、高周
波信号の伝送特性への影響を低減するため、誘電率が7
以下、特に5.9以下と低いことが望ましい。
The above-mentioned porcelain composition is suitable for forming an insulating layer of a high-frequency wiring board of 1 GHz or more, particularly 20 GHz or more, further 50 GHz or more, or even 70 GHz or more because of its low dielectric loss in a high frequency band. It is.
When the above porcelain is used as an insulating substrate of a wiring board, the dielectric constant is 7 to reduce the influence on the transmission characteristics of high-frequency signals.
Hereafter, it is particularly desirable to be as low as 5.9 or less.

【0032】その場合、絶縁基板の室温から400℃に
おける熱膨張係数は、実装するチップ部品等やプリント
基板等の熱膨張係数に近似するように前述したように、
基板を構成する磁器の組成、組織を制御して、適宜調整
することが望ましい。
In this case, as described above, the coefficient of thermal expansion of the insulating substrate from room temperature to 400 ° C. is similar to the coefficient of thermal expansion of a mounted chip component or a printed circuit board as described above.
It is desirable that the composition and structure of the porcelain constituting the substrate be controlled and appropriately adjusted.

【0033】これは、上記の絶縁基板の熱膨張係数が実
装されるチップ部品等やプリント基板のそれと差がある
場合、半田実装時や半導体素子の作動停止による繰り返
し温度サイクルによって、チップ部品等やプリント基板
とパッケージとの実装部に熱膨張差に起因する応力が発
生し、実装部にクラック等が発生し、実装構造の信頼性
を損ねてしまうためである。
If the thermal expansion coefficient of the insulating substrate is different from that of a mounted chip component or a printed circuit board, the temperature of the chip component or the like may be increased by repeated temperature cycles during solder mounting or by stopping operation of the semiconductor element. This is because a stress due to a difference in thermal expansion is generated in a mounting portion between the printed circuit board and the package, and a crack or the like is generated in the mounting portion, thereby impairing the reliability of the mounting structure.

【0034】具体的には、GaAs系のチップ部品との
整合を図る上ではGaAs系のチップ部品との熱膨張係
数の差が2ppm/℃以下であり、一方、プリント基板
との整合を図る上ではプリント基板との熱膨張係数の差
が2ppm/℃以下であることが望ましい。
More specifically, the difference in the coefficient of thermal expansion between the GaAs-based chip component and the GaAs-based chip component is 2 ppm / ° C. or less. In this case, it is desirable that the difference in the coefficient of thermal expansion from the printed board is 2 ppm / ° C. or less.

【0035】具体的に、上記高周波用磁器を用いて、配
線層を具備する本発明の高周波用配線基板を製造する方
法について説明する。上述した組成物からなる混合粉末
に、適当な有機溶剤、溶媒を用い混合してスラリーを調
製し、これを従来周知のドクターブレード法やカレンダ
ーロール法、あるいは圧延法、プレス成形法により、シ
ート状に成形する。そして、このシート状成形体に所望
によりスルーホールを形成した後、スルーホール内に、
銅、金、銀のうちの少なくとも1種を含む金属ペースト
を充填する。そして、シート状成形体表面には、高周波
信号が伝送可能なストリップ線路、マイクロストリップ
線路、コプレーナ線路、誘電体導波管線路のうちの少な
くとも1種からなる高周波線路パターンに前記金属ペー
ストを用いてスクリーン印刷法、グラビア印刷法などに
よって配線層の厚みが5〜30μmとなるように、印刷
塗布する。
Specifically, a method of manufacturing the high-frequency wiring board of the present invention having a wiring layer using the above-described high-frequency ceramic will be described. A slurry is prepared by mixing a mixed powder of the above-described composition with an appropriate organic solvent and a solvent, and the slurry is formed into a sheet by a conventionally known doctor blade method, calender roll method, or rolling method, press molding method. Mold into Then, after forming a through hole as desired in the sheet-like molded body, in the through hole,
A metal paste containing at least one of copper, gold, and silver is filled. Then, on the surface of the sheet-shaped molded body, the metal paste is used for a high-frequency line pattern including at least one of a strip line, a microstrip line, a coplanar line, and a dielectric waveguide line capable of transmitting a high-frequency signal. Print coating is performed by screen printing, gravure printing, or the like so that the thickness of the wiring layer is 5 to 30 μm.

【0036】その後、複数のシート状成形体を位置合わ
せして積層圧着し、800〜1000℃の窒素ガスや窒
素−酸素混合ガス等の非酸化性雰囲気で焼成することに
より、本発明の配線基板を作製することができる。そし
て、この配線基板の表面に、適宜、半導体素子等のチッ
プ部品を搭載し、配線層と信号の伝達が可能なように接
続する。
Thereafter, a plurality of sheet-like molded bodies are aligned and laminated and pressed, and then fired in a non-oxidizing atmosphere such as a nitrogen gas or a nitrogen-oxygen mixed gas at 800 to 1000 ° C. to obtain the wiring substrate of the present invention. Can be produced. Then, a chip component such as a semiconductor element is appropriately mounted on the surface of the wiring board, and connected to the wiring layer so that signals can be transmitted.

【0037】接続方法としては、配線層上に直接搭載さ
せて接続させたり、あるいは50μm程度の樹脂、Ag
−エポキシ、Ag−ガラス、Au−Si等の樹脂、金
属、セラミックス等の接着剤によりチップ部品を絶縁基
板表面に固着し、ワイヤーボンディングや、TABテー
プなどにより配線層と半導体素子とを接続する。
As a connection method, a connection is made by directly mounting on the wiring layer, or a resin of about 50 μm or Ag is used.
-The chip component is fixed to the surface of the insulating substrate with an adhesive such as a resin such as epoxy, Ag-glass, or Au-Si, a metal, or a ceramic, and the wiring layer and the semiconductor element are connected by wire bonding or TAB tape.

【0038】なお、この半導体素子としては、Si系や
GaAs系等のチップ部品が使用できるが、特に熱膨張
係数の近似性の点では、最もGaAs系のチップ部品の
実装に有効である。
As the semiconductor element, a chip component such as a Si-based or GaAs-based chip can be used, but it is most effective for mounting a GaAs-based chip component in terms of the similarity of the thermal expansion coefficient.

【0039】さらに、半導体素子が搭載された配線基板
表面に、絶縁基板と同種の絶縁材料や、その他の絶縁材
料、あるいは放熱性が良好な金属等からなり、電磁波遮
蔽性を有するキャップをガラス、樹脂、ロウ材等の接着
剤により接合してもよく、これにより半導体素子を気密
に封止することができる。
Further, a cap made of an insulating material of the same kind as the insulating substrate, another insulating material, or a metal having good heat dissipation, and having an electromagnetic wave shielding property is provided on the surface of the wiring board on which the semiconductor element is mounted with glass, The semiconductor element may be hermetically sealed by bonding with an adhesive such as a resin or a brazing material.

【0040】本発明の高周波用配線基板の一例である半
導体素子収納用パッケージの具体的な構造とその実装構
造について図2をもとに説明する。図2は、半導体収納
用パッケージ、特に、接続端子がボール状端子からなる
ボールグリッドアレイ(BGA)型パッケージの概略断
面図である。
A specific structure of a package for housing a semiconductor element, which is an example of the high-frequency wiring board of the present invention, and a mounting structure thereof will be described with reference to FIG. FIG. 2 is a schematic sectional view of a semiconductor storage package, particularly a ball grid array (BGA) type package in which connection terminals are formed of ball-shaped terminals.

【0041】図2によれば、パッケージAは、絶縁材料
からなる絶縁基板1と蓋体2によりキャビティ3が形成
されており、そのキャビティ3内には、GaAs系等の
チップ部品4が前述の接着剤により実装されている。
Referring to FIG. 2, the package A has a cavity 3 formed by an insulating substrate 1 made of an insulating material and a lid 2, in which a chip component 4 of GaAs or the like is formed. Mounted with adhesive.

【0042】また、絶縁基板1の表面および内部には、
チップ部品4と電気的に接続された配線層5が形成され
ている。この配線層5は、高周波信号の伝送時に導体損
失を極力低減するために、銅、銀あるいは金などの低抵
抗金属からなることが望ましい。また、本発明によれ
ば、この配線層5に1GHz以上の高周波信号を伝送す
る場合には、高周波信号が損失なく伝送されることが必
要となるため、配線層5はストリップ線路、マイクロス
トリップ線路、コプレーナ線路、誘電体導波管線路のう
ちの少なくとも1種から構成されることが重要である。
Further, on the surface and inside of the insulating substrate 1,
A wiring layer 5 electrically connected to the chip component 4 is formed. The wiring layer 5 is desirably made of a low-resistance metal such as copper, silver, or gold in order to minimize conductor loss when transmitting a high-frequency signal. Further, according to the present invention, when transmitting a high-frequency signal of 1 GHz or more to the wiring layer 5, the high-frequency signal needs to be transmitted without loss. , A coplanar line, and a dielectric waveguide line.

【0043】また、図2のパッケージAにおいて、絶縁
基板1の底面には、接続用電極層6が被着形成されてお
り、パッケージA内の配線層5と接続されている。そし
て、接続用電極層6には、半田などのロウ材7によりボ
ール状端子8が被着形成されている。
In the package A of FIG. 2, a connection electrode layer 6 is formed on the bottom surface of the insulating substrate 1 and is connected to the wiring layer 5 in the package A. A ball-shaped terminal 8 is formed on the connection electrode layer 6 with a brazing material 7 such as solder.

【0044】また、上記パッケージAを外部回路基板に
実装するには、図2に示すように、ポリイミド樹脂、エ
ポキシ樹脂、フェノール樹脂などの有機樹脂を含む絶縁
材料からなる絶縁基板9の表面に配線導体10が形成さ
れた外部回路基板Bに対して、ロウ材を介して実装され
る。具体的には、パッケージAにおける絶縁基板1の底
面に取付けられているボール状端子8と、外部回路基板
Bの配線導体10とを当接させてPb−Snなどの半田
等のロウ材11によりロウ付けして実装される。また、
ボール状端子8自体を溶融させて配線導体10と接続さ
せてもよい。
In order to mount the package A on an external circuit board, as shown in FIG. 2, wiring is formed on the surface of an insulating substrate 9 made of an insulating material containing an organic resin such as a polyimide resin, an epoxy resin or a phenol resin. The external circuit board B on which the conductor 10 is formed is mounted via a brazing material. Specifically, the ball-shaped terminals 8 attached to the bottom surface of the insulating substrate 1 in the package A and the wiring conductors 10 of the external circuit board B are brought into contact with each other, and the brazing material 11 such as a solder such as Pb-Sn is used. It is mounted with brazing. Also,
The ball-shaped terminal 8 itself may be melted and connected to the wiring conductor 10.

【0045】本発明によれば、GaAs等のチップ部品
4をロウ付けや接着剤により実装したり、このようなボ
ール状端子8を介在したロウ付けによりプリント基板等
の外部回路基板Bに実装されるような表面実装型のパッ
ケージにおいて、GaAs等のチップ部品4や外部回路
基板Bの絶縁基板1との熱膨張差を従来のセラミック材
料よりも小さくできることから、かかる実装構造に対し
て、熱サイクルが印加された場合においても、実装部で
の応力の発生を抑制することができる結果、実装構造の
長期信頼性を高めることができる。
According to the present invention, the chip component 4 such as GaAs is mounted on the external circuit board B such as a printed board by soldering or mounting with an adhesive or by soldering with such ball-shaped terminals 8 interposed therebetween. In such a surface mounting type package, the thermal expansion difference between the chip component 4 such as GaAs and the insulating substrate 1 of the external circuit board B can be made smaller than that of a conventional ceramic material. Is applied, the occurrence of stress in the mounting portion can be suppressed, and as a result, the long-term reliability of the mounting structure can be improved.

【0046】[0046]

【実施例】下記の組成からなる2種のディオプサイド型
酸化物結晶相を析出可能な結晶化ガラスを準備した。
EXAMPLE A crystallized glass capable of precipitating two kinds of diopside oxide crystal phases having the following compositions was prepared.

【0047】 ガラスA:SiO250.2重量%−Al235.0重
量% −MgO16.1重量%−SrO13.6重量% −CaO15.1重量% ガラスB:SiO247.5重量%−Al234.9重
量% −MgO16.1重量%−SrO20重量% −CaO11.5重量% そして、この結晶化ガラス粉末に対して、平均粒径が5
μmのクオーツあるいは平均粒径が2μmのアモルファ
スシリカ粉末を用いて、表1、表2の組成となるように
混合した。そして、この混合物に有機バインダ、可塑
剤、トルエンを添加し、スラリーを調製した後、このス
ラリーを用いてドクターブレード法により厚さ300μ
mのグリーンシートを作製した。そして、このグリーン
シートを10〜15枚積層し、50℃の温度で100k
g/cm2の圧力を加えて熱圧着した。得られた積層体
を水蒸気含有/窒素雰囲気中、700℃で脱バインダ処
理を行った後、乾燥窒素中で表1、表2の条件で焼成し
絶縁基板用磁器を得た。
Glass A: 50.2% by weight of SiO 2 -5.0% by weight of Al 2 O 3 -16.1% by weight of MgO-13.6% by weight of SrO -15.1% by weight of glass B: 47.5% by weight of SiO 2 % -Al 2 O 3 4.9 wt% -MgO16.1 wt% -SrO20 wt% -CaO11.5 wt% Then, with respect to the crystallized glass powder, the average particle size of 5
Using quartz having a particle size of μm or amorphous silica powder having an average particle size of 2 μm, mixing was performed so that the compositions shown in Tables 1 and 2 were obtained. Then, an organic binder, a plasticizer, and toluene were added to the mixture to prepare a slurry.
m green sheets were produced. Then, 10 to 15 green sheets are laminated, and at a temperature of 50 ° C., 100 k
g / cm 2 and a thermocompression bonding. The obtained laminate was subjected to a binder removal treatment in a steam-containing / nitrogen atmosphere at 700 ° C., and then fired in dry nitrogen under the conditions shown in Tables 1 and 2 to obtain a porcelain for an insulating substrate.

【0048】得られた磁器について誘電率、誘電損失を
以下の方法で評価した。測定は形状、直径2〜7mm、
厚み1.5〜2.5mmの形状に切り出し、60GHz
にてネットワークアナライザー、シンセサイズドスイー
パーを用いて誘電体円柱共振器法により行った。測定で
は、NRDガイド(非放射性誘電体線路)で、誘電体共
振器の励起を行い、TE021、TE031モードの共振特性
より、誘電率、誘電損失を算出した。
The obtained ceramics were evaluated for permittivity and dielectric loss by the following methods. The measurement is shape, diameter 2-7mm,
Cut out to 1.5-2.5mm thickness, 60GHz
, And a dielectric cylinder resonator method using a network analyzer and a synthesized sweeper. In the measurement, the dielectric resonator was excited by an NRD guide (non-radiative dielectric line), and the dielectric constant and the dielectric loss were calculated from the resonance characteristics of the TE 021 and TE 031 modes.

【0049】また、室温から400℃における熱膨張曲
線をとり、熱膨張係数を算出した。さらに、焼結体中に
おける主たる結晶相をX線回折チャートから同定した。
結果は表1、表2に示した。
Further, a thermal expansion curve from room temperature to 400 ° C. was taken to calculate a thermal expansion coefficient. Further, the main crystal phase in the sintered body was identified from the X-ray diffraction chart.
The results are shown in Tables 1 and 2.

【0050】また、一部の試料については、フィラー成
分として、クォーツおよび/またはアモルファスシリカ
に代わり、ZrO2粉末、CaZrO3粉末を用いて同様
に磁器を作製し評価した(試料No.19〜21、35〜
37)。また、上記結晶化ガラスA、Bに代わり、以下
の組成からなるガラスCを用いて同様に評価を行った
(試料No.38、39)。
For some of the samples, ZrO 2 powder and CaZrO 3 powder were used in place of quartz and / or amorphous silica as filler components, and porcelain was similarly prepared and evaluated (Sample Nos. 19 to 21). , 35-
37). In addition, the same evaluation was performed using glass C having the following composition instead of the crystallized glasses A and B (Sample Nos. 38 and 39).

【0051】ガラスC:SiO210.4重量%−Al2
32.5重量% −B2345.3重量%−CaO35.2重量% −Na2O6.6重量%
Glass C: SiO 2 10.4% by weight—Al 2
O 3 2.5 wt% -B 2 O 3 45.3 wt% -CaO35.2 wt% -Na 2 O6.6 wt%

【0052】[0052]

【表1】 [Table 1]

【0053】[0053]

【表2】 [Table 2]

【0054】表1、2の結果から明らかなように、Si
2、Al23、MgO、SrO、CaOを含むガラス
量が、95重量%を越える試料No.1、22では、誘
電損失が30×10-4を越えてしまい、ガラス量が50
重量%よりも少ない試料No.10、14、18、34
では、低温で焼結することが困難であり、緻密化しなか
った。試料No.19〜21、35〜37は、ガラスへ
の添加成分として、ZrO2やCaZrO3を配合したも
のであるが、焼結体中にZrO2やCaZrO3などが析
出し誘電損失が増大した。また、ガラスとして、B23
を多く含むガラスCを用いた試料No.38では溶融し
てしまい、また、試料No.39では、Bを含むガラス
が多く残留し、誘電損失が大きくなる傾向にあった。
As is clear from the results in Tables 1 and 2, Si
Sample No. 2 in which the amount of glass containing O 2 , Al 2 O 3 , MgO, SrO, and CaO exceeded 95% by weight. In Nos. 1 and 22, the dielectric loss exceeded 30 × 10 -4 and the glass amount was 50
Sample No. less than wt. 10, 14, 18, 34
In this case, it was difficult to perform sintering at a low temperature, and it was not densified. Sample No. 19~21,35~37 as additive component to the glass, but is obtained by blending the ZrO 2 and CaZrO 3, etc. ZrO 2 and CaZrO 3 is precipitated dielectric loss is increased in the sintered body. Further, as glass, B 2 O 3
Sample No. using glass C containing a large amount of Sample No. 38 melts. In No. 39, a large amount of glass containing B remained and the dielectric loss tended to increase.

【0055】これに対して、本発明に従い、特定量のク
ォーツ粉末を主として添加した試料No.2〜9、1
5、17、23〜28、32、33では、磁器中にクォ
ーツ相の析出が見られ、また、いずれも熱膨張係数が
8.5ppm/℃以上、60GHzの測定周波数にて、
誘電率7以下、誘電損失が30×10-4以下の優れた特
性を有するものであった。
On the other hand, according to the present invention, the sample No. 2-9, 1
In 5, 17, 23 to 28, 32, and 33, precipitation of a quartz phase was observed in the porcelain, and all had a thermal expansion coefficient of 8.5 ppm / ° C. or higher and a measurement frequency of 60 GHz.
It had excellent characteristics with a dielectric constant of 7 or less and a dielectric loss of 30 × 10 −4 or less.

【0056】また、本発明に従い、特定量のアモルファ
スシリカ粉末を主として添加した試料No.11〜1
3、16、29〜31では、磁器中にアモルファスシリ
カ相が存在し、また、いずれも熱膨張係数が5.5pp
m/℃以上、60GHzの測定周波数にて、誘電率5.
9以下、誘電損失が20×10-4以下の優れた特性を有
するものであった。
In addition, according to the present invention, the sample No. 11-1
In 3, 16, 29 to 31, an amorphous silica phase was present in the porcelain, and the thermal expansion coefficient was 5.5 pp.
m / ° C. or higher and a dielectric constant of 5.
9 or less, and excellent characteristics with a dielectric loss of 20 × 10 −4 or less.

【0057】[0057]

【発明の効果】以上詳述した通り、本発明の高周波用配
線基板の絶縁基板は、1000℃以下の低温にて焼成で
きることから、銅などの低抵抗金属による配線層を形成
でき、しかも1GHz以上の高周波領域において、低誘
電率、低誘電損失を有することから、高周波信号を極め
て良好に損失なく伝送することができる。
As described in detail above, the insulating substrate of the high-frequency wiring board of the present invention can be fired at a low temperature of 1000 ° C. or less, so that a wiring layer made of a low-resistance metal such as copper can be formed, and more than 1 GHz. In this high-frequency region, a low dielectric constant and a low dielectric loss allow a high-frequency signal to be transmitted very favorably and without loss.

【0058】しかも、この絶縁基板は、GaAsチップ
あるいはプリント基板と近似した熱膨張特性に制御でき
ることから、GaAsチップを実装した場合、あるいは
有機樹脂を含む絶縁基板を具備するプリント基板などの
マザーボードに対してロウ材等により実装した場合にお
いて優れた耐熱サイクル性を有し、高信頼性の実装構造
を提供できる。
Further, since this insulating substrate can be controlled to have a thermal expansion characteristic similar to that of a GaAs chip or a printed board, it can be mounted on a GaAs chip or on a motherboard such as a printed board having an insulating substrate containing an organic resin. It has excellent heat cycle resistance when mounted with a brazing material or the like, and can provide a highly reliable mounting structure.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の配線基板の絶縁基板の組織を説明する
ための概略図である。
FIG. 1 is a schematic diagram for explaining the structure of an insulating substrate of a wiring board according to the present invention.

【図2】本発明の高周波用配線基板の一例である半導体
素子収納用パッケージの実装構造の一例を説明するため
の概略断面図である。
FIG. 2 is a schematic cross-sectional view illustrating an example of a mounting structure of a package for housing a semiconductor element, which is an example of a high-frequency wiring board according to the present invention.

【符号の説明】[Explanation of symbols]

DI ディオプサイド型酸化物結晶相 Si SiO2結晶相 AM アモルファスシリカ相 G 非晶質(ガラス)相 A 半導体素子収納用パッケージ(高周波用配線基板) B 外部回路基板 1 絶縁基板 2 蓋体 3 キャビティ 4 チップ部品 5 配線層 6 接続用電極層 7 ロウ材 8 ボール状端子 9 絶縁基板 10 配線導体 11 ロウ材DI Diopside-type oxide crystal phase Si SiO 2 crystal phase AM Amorphous silica phase G Amorphous (glass) phase A Semiconductor element storage package (high-frequency wiring board) B External circuit board 1 Insulating substrate 2 Lid 3 Cavity Reference Signs List 4 chip component 5 wiring layer 6 connection electrode layer 7 brazing material 8 ball-shaped terminal 9 insulating substrate 10 wiring conductor 11 brazing material

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】少なくともMg、Ca、Si、Alを含む
ディオプサイド型酸化物結晶相と、クォーツ結晶相とを
含有し、且つ室温から400℃における熱膨張係数が
5.5ppm/℃以上、誘電率が7以下、60〜77G
Hzでの誘電損失が30×10-4以下であることを特徴
とする高周波用磁器を絶縁基板とし、該絶縁基板の表面
および内部にストリップ線路、マイクロストリップ線
路、コプレーナ線路、誘電体導波管線路のうちの少なく
とも1種から構成される配線層を具備することを特徴と
する高周波用配線基板。
1. A composition comprising a diopside oxide crystal phase containing at least Mg, Ca, Si, and Al and a quartz crystal phase, and having a thermal expansion coefficient of 5.5 ppm / ° C. or more from room temperature to 400 ° C. Dielectric constant of 7 or less, 60-77G
A high frequency ceramic insulating substrate, wherein the dielectric loss in Hz is 30 × 10 -4 or less, the surface and inside the stripline of the insulating substrate, a microstrip line, coplanar line, the dielectric waveguide A high-frequency wiring board comprising a wiring layer composed of at least one of the lines.
【請求項2】前記絶縁基板表面にGaAs系のチップ部
品を実装することを特徴とする請求項1記載の高周波用
配線基板。
2. The high-frequency wiring board according to claim 1, wherein a GaAs chip component is mounted on the surface of the insulating substrate.
【請求項3】前記高周波用磁器の室温から400℃にお
ける熱膨張係数が8.5ppm/℃以上であることを特
徴とする請求項1または2記載の高周波用配線基板。
3. The high-frequency wiring board according to claim 1, wherein a thermal expansion coefficient of the high-frequency ceramic from room temperature to 400 ° C. is 8.5 ppm / ° C. or more.
【請求項4】前記高周波用磁器が、SiO2、Al
23、MgO、SrOおよびCaOを含み、ディオプサ
イド型酸化物結晶相を析出可能なガラス50〜95重量
%と、クォーツ5〜50重量%との割合で含有する高周
波用磁器組成物を成形後、800〜1000℃の温度で
焼成してなることを特徴とする請求項1乃至3のいずれ
か記載の高周波用配線基板。
4. The high frequency porcelain is made of SiO 2 , Al
A high frequency ceramic composition containing 2 O 3 , MgO, SrO and CaO and containing 50 to 95% by weight of glass capable of precipitating a diopside oxide crystal phase and 5 to 50% by weight of quartz. The high-frequency wiring board according to any one of claims 1 to 3, wherein the wiring board is fired at a temperature of 800 to 1000C after molding.
【請求項5】前記ガラスが、SiO245〜55重量%
と、Al233〜10重量%と、MgO13〜24重量
%と、SrO10〜24重量%と、CaO8〜20重量
%と、からなることを特徴とする請求項4記載の高周波
用配線基板。
5. The glass according to claim 5, wherein said glass is 45 to 55% by weight of SiO 2.
When the Al 2 O 3 3 to 10 wt%, and MgO13~24 wt%, and SrO10~24 wt%, wiring for high frequency according to claim 4, characterized in that it consists of a CaO8~20 wt%, the substrate .
JP2000192742A 2000-06-27 2000-06-27 High frequency wiring board Expired - Fee Related JP3466545B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000192742A JP3466545B2 (en) 2000-06-27 2000-06-27 High frequency wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000192742A JP3466545B2 (en) 2000-06-27 2000-06-27 High frequency wiring board

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP10317736A Division JP3131191B2 (en) 1998-09-29 1998-11-09 High frequency porcelain composition and high frequency porcelain

Publications (2)

Publication Number Publication Date
JP2001068597A true JP2001068597A (en) 2001-03-16
JP3466545B2 JP3466545B2 (en) 2003-11-10

Family

ID=18691830

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000192742A Expired - Fee Related JP3466545B2 (en) 2000-06-27 2000-06-27 High frequency wiring board

Country Status (1)

Country Link
JP (1) JP3466545B2 (en)

Also Published As

Publication number Publication date
JP3466545B2 (en) 2003-11-10

Similar Documents

Publication Publication Date Title
US6232251B1 (en) Dielectric ceramics
US6753277B2 (en) Ceramics having excellent high-frequency characteristics and method of producing the same
US6201307B1 (en) Ceramics for wiring boards and method of producing the same
JP2001240470A (en) Porcelain composition for high-frequency use, porcelain for high-frequency use and method for producing porcelain for high-frequency use
JP3793559B2 (en) High frequency porcelain composition and high frequency porcelain
JP3085667B2 (en) High frequency porcelain composition, high frequency porcelain and method for producing the same
JP3865967B2 (en) Porcelain and wiring board using the same
JP3064273B2 (en) High frequency porcelain
JP3827491B2 (en) High frequency porcelain composition, high frequency porcelain and method for producing high frequency porcelain
JP3556475B2 (en) High frequency porcelain composition and method for producing high frequency porcelain
JP3131191B2 (en) High frequency porcelain composition and high frequency porcelain
JP3377898B2 (en) Low temperature firing porcelain composition
JP2001015878A (en) High-frequency wiring board and its manufacture
JP3441924B2 (en) Wiring board and its mounting structure
JP3085669B1 (en) High frequency porcelain composition, high frequency porcelain and method for producing the same
JP3441950B2 (en) Wiring board and its mounting structure
JP3441941B2 (en) Wiring board and its mounting structure
JP3466545B2 (en) High frequency wiring board
JP3663335B2 (en) High frequency porcelain composition, high frequency porcelain and method for producing the same
JP3764626B2 (en) Wiring board
JP3793558B2 (en) High frequency porcelain
JP2005101095A (en) Porcelain composition, porcelain, and its manufacturing method
JP3663300B2 (en) High frequency porcelain composition, high frequency porcelain and method for producing the same
JP2005179137A (en) Porcelain having excellent high frequency transmission characteristics
JP3610226B2 (en) Wiring board and its mounting structure

Legal Events

Date Code Title Description
FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080829

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080829

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090829

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100829

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100829

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110829

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110829

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120829

Year of fee payment: 9

LAPS Cancellation because of no payment of annual fees