JP3465464B2 - Semiconductor chip carrier - Google Patents
Semiconductor chip carrierInfo
- Publication number
- JP3465464B2 JP3465464B2 JP1970896A JP1970896A JP3465464B2 JP 3465464 B2 JP3465464 B2 JP 3465464B2 JP 1970896 A JP1970896 A JP 1970896A JP 1970896 A JP1970896 A JP 1970896A JP 3465464 B2 JP3465464 B2 JP 3465464B2
- Authority
- JP
- Japan
- Prior art keywords
- pad
- semiconductor chip
- signal
- power supply
- ground
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体チップキャリ
ヤの改良に関する。半導体チップを配線基板に実装する
上で、半導体チップを半導体チップキャリヤに搭載しこ
の半導体チップキャリヤを配線基板に搭載する方法が用
いられている。この方法では、半導体チップキャリヤの
構造が半導体チップの実装密度やそのデータ処理特性に
対して大きな影響を与えることになるためその性能向上
が望まれている。FIELD OF THE INVENTION The present invention relates to improvements in semiconductor chip carriers. In mounting a semiconductor chip on a wiring board, a method of mounting the semiconductor chip on a semiconductor chip carrier and mounting the semiconductor chip carrier on the wiring board is used. In this method, the structure of the semiconductor chip carrier has a great influence on the mounting density of the semiconductor chips and the data processing characteristics thereof, and therefore it is desired to improve the performance thereof.
【０００２】[0002]
【従来の技術】半導体チップにより高速でデータ処理を
行う場合、半導体チップ内部で発生するスイッチングノ
イズ及び信号線接続部での信号反射により特性が大きく
劣化することが知られている。スイッチングノイズを低
減するためには半導体チップの接地端子と電源端子の間
にデカップリングキャパシタを配置し、また、信号の反
射を抑えるためには信号線上に終端抵抗を配置する必要
がある。デカップリングキャパシタや終端抵抗は半導体
チップのできるだけ近くに配置するのが効果的であり、
そのためには直接半導体チップ上に形成することが望ま
しいが、半導体チップの製作工程が複雑となりコストも
高くなるため困難である。従って、通常は配線基板上に
半導体チップキャリヤとともにキャパシタや抵抗素子を
外付け部品として配置する方法が用いられている。しか
し、この方法では、半導体チップと外付け部品間の配線
距離が長くなるため特性劣化防止の効果が小さくなり、
かつ大きな実装スペースを必要とする。2. Description of the Related Art It is known that when high-speed data processing is performed by a semiconductor chip, the characteristics are greatly deteriorated due to switching noise generated inside the semiconductor chip and signal reflection at a signal line connecting portion. To reduce switching noise, it is necessary to dispose a decoupling capacitor between the ground terminal and the power supply terminal of the semiconductor chip, and to suppress signal reflection, a terminating resistor must be arranged on the signal line. It is effective to place decoupling capacitors and termination resistors as close to the semiconductor chip as possible.
For that purpose, it is desirable to form it directly on the semiconductor chip, but it is difficult because the manufacturing process of the semiconductor chip becomes complicated and the cost becomes high. Therefore, a method of arranging a capacitor and a resistance element together with a semiconductor chip carrier as an external component on the wiring board is usually used. However, this method reduces the effect of preventing characteristic deterioration because the wiring distance between the semiconductor chip and the external component becomes long,
And it requires a large mounting space.
【０００３】そこで、薄膜キャパシタを半導体チップキ
ャリヤと一体化して形成する方法が提案されており、こ
れにより、スイッチングノイズの低減を図るとともに実
装密度の低下を抑えるようにしている（特開昭６０−８
１８４５）。Therefore, there has been proposed a method of integrally forming a thin film capacitor with a semiconductor chip carrier, whereby the reduction of switching noise and the reduction of packaging density are suppressed (Japanese Patent Laid-Open No. 60-60). 8
1845).
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、従来は
信号反射を抑えるための終端抵抗を外付け部品として配
線基板上に配置しており、そのため半導体チップとの接
続距離が長くなって信号反射の抑制効果が充分でなく、
かつ外付け部品を用いたことにより実装密度も大きくで
きないという問題があった。また、薄膜キャパシタの容
量値を大きくすることが困難なためスイッチングノイズ
の低減効果も充分でないという問題があった。However, conventionally, a terminating resistor for suppressing signal reflection is arranged as an external component on the wiring board, which increases the connection distance to the semiconductor chip and suppresses signal reflection. The effect is not enough,
In addition, there is a problem that the mounting density cannot be increased by using the external parts. Further, since it is difficult to increase the capacitance value of the thin film capacitor, the switching noise reduction effect is not sufficient.
【０００５】そこで本発明は、半導体チップキャリヤに
薄膜キャパシタと薄膜抵抗を一体化させることにより実
装密度を低下させることなくスイッチングノイズを低減
しかつ信号反射を抑制することを目的とする。Therefore, an object of the present invention is to integrate a thin film capacitor and a thin film resistor on a semiconductor chip carrier to reduce switching noise and suppress signal reflection without lowering the packaging density.
【０００６】[0006]
【課題を解決するための手段】上記課題の解決は、支持
基板の一方の面に半導体チップが接続され、他方の面に
配線基板が接続される半導体チップキャリヤにおいて、
該支持基板の一方の面に接地層及び電源層からなる一対
の金属膜とその間に挟まれた誘電体層が積層されて成る
薄膜キャパシタが形成されるとともに、該支持基板の他
方の面に薄膜抵抗が形成され、該支持基板の一方の面に
は、該半導体チップの接地端子、電源端子及び信号端子
と接続される第１の接地パッド、第１の電源パッド及び
第１の信号パッドがそれぞれ形成され、該支持基板の他
方の面には、該配線基板の接地端子、電源端子及び信号
端子と接続される第２の接地パッド、第２の電源パッド
及び第２の信号パッドがそれぞれ形成され、該第１の接
地パッド及び該第１の電源パッドは、該支持基板に設け
た貫通導体路を通して第２の接地パッド及び第２の電源
パッドと接続され、該第１の信号パッドは、該貫通導体
路を通して他方の面に設けられた薄膜抵抗の一方の電極
に接続され、該薄膜抵抗のもう一方の電極が第２の信号
パッドに接続されていることを特徴とする半導体チップ
キャリヤ、あるいは、該支持基板の他方の面には、該第
２の信号パッドと該第２の接地パッド間に該薄膜抵抗が
接続されていることを特徴とする上記半導体チップキャ
リヤによって達成される。To solve the above-mentioned problems, a semiconductor chip carrier in which a semiconductor chip is connected to one surface of a supporting substrate and a wiring board is connected to the other surface is provided.
The one pair of metal layer and a dielectric layer sandwiched therebetween to the surface consisting of ground layer and power supply layer of the supporting substrate is a thin film capacitor formed by laminating formation Rutotomoni, other <br/> of the support substrate square surface film resistance is formed on the, on one surface of the supporting substrate, a first ground pad connected ground terminal of the semiconductor chip, a power supply terminal and the signal terminal <br/>, first power supply A pad and a first signal pad are formed respectively, and on the other surface of the support substrate, a second ground pad connected to the ground terminal, the power supply terminal and the signal terminal of the wiring board, a second power supply pad, and formed second signal pads respectively, said first ground pad and the first power supply pad is connected to the second ground pad and the second power supply pads through a through conductor tracks provided on the supporting substrate, first signal pads, through the through conductor paths A semiconductor chip carrier, which is connected to one electrode of a thin film resistor provided on the other surface, and the other electrode of the thin film resistor is connected to a second signal pad, or the supporting substrate. of the other surface, it is achieved by the semiconductor chip carrier, wherein a thin film resistor is connected between the signal pad of the second and the second ground pad.
【０００７】本発明では、半導体チップキャリヤの一方
の面に薄膜キャパシタ、他方の面に薄膜抵抗が形成され
一体化されており、これらをデカップリングキャパシタ
や終端抵抗として用いることにより外付け部品を用いた
場合に比べて実装密度が向上し、かつ半導体チップとの
間の接続距離も短くできるのでスイッチングノイズの低
減や信号反射の抑制の効果が大きい。In the present invention, a thin film capacitor is formed on one surface of the semiconductor chip carrier and a thin film resistor is formed on the other surface of the semiconductor chip carrier, which are integrated and used as a decoupling capacitor or a terminating resistor to use external parts. Compared with the case where the semiconductor chip is mounted, the mounting density is improved and the connection distance between the semiconductor chip and the semiconductor chip can be shortened, so that the effects of reducing switching noise and suppressing signal reflection are great.
【０００８】また、本発明では、支持基板の一方の面に
形成した電源層と接地層をそれぞれパターニングし、こ
れにより第１の接地パッド、第１の電源パッド及び第１
の信号パッドを電源層及び接地層から分離して形成し、
電源層及び接地層自体は薄膜キャパシタの電極として働
くようにしている。従って、電源層及び接地層の面積の
うち、分離された領域を除く全ての領域がキャパシタ面
積として作用するので容量値を大きくすることができ、
スイッチングノイズをより低減することができる。Further, according to the present invention, the power supply layer and the ground layer formed on one surface of the support substrate are respectively patterned, whereby the first ground pad, the first power pad and the first ground pad are formed.
The signal pad of is formed separately from the power layer and the ground layer,
The power supply layer and the ground layer themselves function as the electrodes of the thin film capacitor. Therefore, of the areas of the power supply layer and the ground layer, all the regions except the separated regions act as the capacitor area, so that the capacitance value can be increased.
Switching noise can be further reduced.
【０００９】また、終端抵抗を半導体チップに接続する
方式として半導体チップの信号端子に終端抵抗を直列に
接続する方式及び半導体チップの信号端子と接地端子間
に終端抵抗を並列に接続する方式が知られているが、本
発明では、同じ実装スペースで支持基板の他方の面に形
成された薄膜抵抗を半導体チップの信号端子に直列に挿
入すること及び信号端子と接地端子の間に並列に挿入す
ることができるので、半導体チップの回路構成に応じて
上記いずれの方式にも対応することが可能である。As a method of connecting the terminating resistor to the semiconductor chip, there are known a method of connecting the terminating resistor in series to the signal terminal of the semiconductor chip and a method of connecting the terminating resistor in parallel between the signal terminal of the semiconductor chip and the ground terminal. However, in the present invention, the thin film resistor formed on the other surface of the support substrate in the same mounting space is inserted in series to the signal terminal of the semiconductor chip and in parallel between the signal terminal and the ground terminal. Therefore, it is possible to support any of the above methods depending on the circuit configuration of the semiconductor chip.
【００１０】[0010]
【発明の実施の形態】図１（ａ）は本発明の実施例に係
る半導体チップキャリヤの平面図、図１（ｂ）はそのＡ
Ａ′断面図を示したものである。また、図２は図１に示
した半導体チップキャリヤによる実装状態を示す断面図
であり、半導体チップキャリヤ２の一方の面上に半導体
チップ１が接続され、他方の面が配線基板３上に接続さ
れた状態を示している。以下、図１及び図２を参照して
本発明の実施例について説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1A is a plan view of a semiconductor chip carrier according to an embodiment of the present invention, and FIG.
FIG. 6 is a sectional view taken along line A ′. 2 is a sectional view showing a mounting state by the semiconductor chip carrier shown in FIG. 1, in which the semiconductor chip 1 is connected to one surface of the semiconductor chip carrier 2 and the other surface is connected to the wiring board 3. It shows the state of being performed. An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.
【００１１】半導体チップキャリヤの支持基板４とし
て、面積10mm平方、厚さ0.7mm のアルミナ製基板を用い
る。支持基板４には直径0.1mm の孔が1mm ピッチで設け
られており、孔の内部はAgで埋め込まれて貫通導体路15
が形成されている。支持基板４の一方の面には、接地層
５と電源層６からなる一対の金属膜とその間に挟まれた
誘電体層７が形成されている。As the supporting substrate 4 of the semiconductor chip carrier, an alumina substrate having an area of 10 mm square and a thickness of 0.7 mm is used. Holes having a diameter of 0.1 mm are provided at a pitch of 1 mm in the support substrate 4, and the inside of the holes is filled with Ag so that the through conductor paths 15 are formed.
Are formed. On one surface of the support substrate 4, a pair of metal films composed of a ground layer 5 and a power supply layer 6 and a dielectric layer 7 sandwiched therebetween are formed.
【００１２】デカップリングキャパシタ用の誘電体層７
は、SrとTiの有機塩を溶剤に溶かした溶液( 例えば、高
純度化学社製のMOD 液、STO-6 ) をスピンコート等の方
法により均一に塗布し、室温で放置して乾燥させた後大
気雰囲気中で加熱することによりSrTiO3結晶を析出させ
たものから成っており、上記工程を数回繰り返すことに
より厚さ5000Åの膜厚とする。この誘電体層７には貫通
導体路15に対応した位置にエッチングにより直径0.05mm
の孔が設けられており、これにより前述した支持基板と
同様な貫通導体路16が形成されている。Dielectric layer 7 for decoupling capacitors
Is a solution of an organic salt of Sr and Ti dissolved in a solvent (for example, MOD solution manufactured by Kojundo Chemical Co., Ltd., STO-6), applied uniformly by a method such as spin coating, and left standing at room temperature to dry. After that, it is formed by depositing SrTiO 3 crystals by heating in the atmosphere, and the thickness is 5000 Å by repeating the above process several times. The dielectric layer 7 has a diameter of 0.05 mm at the position corresponding to the through conductor path 15 by etching.
The holes are provided so that the penetrating conductor paths 16 similar to those of the above-mentioned supporting substrate are formed.
【００１３】接地層５及び電源層６はＤＣスパッタ法や
真空蒸着法を用いて形成された金属膜から成る。本実施
例において、接地層５はＤＣスパッタ法によりTiを500
Å、Ptを1500Å積層したものを用い、電源層６は真空蒸
着法によりTiを500 Å、Auを1500Å積層したものを用い
た。半導体チップの接地端子及び信号端子と接続される
第１の接地パッド９及び第１の信号パッド11は、図１
（ａ）に見られるように、電源層６をパターニングする
ことにより電源層６内において島状に分離・形成され
る。第１の接地パッド９及び第１の信号パッド11はいず
れも直径0.1mm の大きさを有する。電源層６内において
第１の接地パッド９及び第１の信号パッド11が形成され
た領域を除く残りの領域は、半導体チップの電源端子と
接続するための第１の電源パッド10として用いられる。
同様にして、接地層５をパターニングすることにより接
地層５内において島状に分離された領域20、21がそれぞ
れ誘電体層７に設けられた貫通導体路16を通して第１の
電源パッド10及び第１の信号パッド11と接続される。接
地層５内において、分離された領域20、21を除く残りの
領域は誘電体層の貫通導体路16を通して第１の接地パッ
ド９と接続される。The ground layer 5 and the power supply layer 6 are made of a metal film formed by the DC sputtering method or the vacuum deposition method. In this embodiment, the ground layer 5 is made of Ti of 500 by DC sputtering.
Å and 1500 Å of Pt were laminated, and the power supply layer 6 was composed of 500 Å of Ti and 1500 Å of Au by vacuum deposition. The first ground pad 9 and the first signal pad 11 connected to the ground terminal and the signal terminal of the semiconductor chip are as shown in FIG.
As shown in (a), by patterning the power supply layer 6, the power supply layer 6 is separated and formed into islands in the power supply layer 6. Both the first ground pad 9 and the first signal pad 11 have a diameter of 0.1 mm. The remaining area in the power supply layer 6 except the area where the first ground pad 9 and the first signal pad 11 are formed is used as the first power supply pad 10 for connecting to the power supply terminal of the semiconductor chip.
In the same manner, by patterning the ground layer 5, island-shaped regions 20 and 21 in the ground layer 5 are respectively passed through the through conductor paths 16 provided in the dielectric layer 7 to form the first power supply pad 10 and the first power pad 10. 1 signal pad 11 is connected. In the ground layer 5, the remaining regions except the separated regions 20 and 21 are connected to the first ground pad 9 through the through conductor paths 16 of the dielectric layer.
【００１４】以上のように、デカップリングキャパシタ
は電源層６と接地層５を一対の電極としその間に挟まれ
た誘電体層７により構成されており、図１（ｂ）に見ら
れるように、電源層６は第１の電源パッド10として用い
られ接地層５は第１の接地パッド９と接続されている。
従って、デカップリングキャパシタは半導体チップの直
下において半導体チップの電源端子と接地端子の間に挿
入されることになり、デカップリングキャパシタと半導
体チップとの間の距離は最小限に抑えられることにな
る。さらに、デカップリングキャパシタの一方の電極と
なる第１の電源パッド10の面積は、図１（ａ）に見られ
るように、電源層６の面積のうち第１の接地パッド９及
び第１の信号パッド11を除く全ての領域を占めている。
そして、第１の接地パッド９及び第１の信号パッド11は
電源層６上において1mm ピッチで設けられておりその大
きさは直径0.1mm に過ぎないことから、電源層６の大部
分の面積がデカップリングキャパシタの一方の電極とし
て作用することがわかる。As described above, the decoupling capacitor is composed of the power supply layer 6 and the ground layer 5 as a pair of electrodes and the dielectric layer 7 sandwiched between them, and as shown in FIG. 1 (b), The power supply layer 6 is used as the first power supply pad 10, and the ground layer 5 is connected to the first ground pad 9.
Therefore, the decoupling capacitor is inserted directly below the semiconductor chip between the power supply terminal and the ground terminal of the semiconductor chip, and the distance between the decoupling capacitor and the semiconductor chip is minimized. Further, as shown in FIG. 1A, the area of the first power supply pad 10 serving as one electrode of the decoupling capacitor is the same as that of the first ground pad 9 and the first signal pad in the area of the power supply layer 6. It occupies the entire area except the pad 11.
The first ground pad 9 and the first signal pad 11 are provided on the power supply layer 6 at a pitch of 1 mm, and the size thereof is only 0.1 mm in diameter. Therefore, most of the area of the power supply layer 6 is small. It can be seen that it acts as one electrode of the decoupling capacitor.
【００１５】同様に、接地層５についてもその面積の大
部分がデカップリングキャパシタのもう一方の電極とし
て作用する。従って、半導体チップキャリヤ上の大部分
の面積がデカップリングキャパシタの実効面積として働
くので大きなキャパシタ値が得られることとなりスイッ
チングノイズの低減効果が大きい。本実施例において
は、半導体チップキャリヤ当たり1.1nF のキャパシタ値
が得られた。Similarly, most of the area of the ground layer 5 also functions as the other electrode of the decoupling capacitor. Therefore, most of the area on the semiconductor chip carrier acts as the effective area of the decoupling capacitor, so that a large capacitor value can be obtained and the effect of reducing switching noise is great. In this example, a capacitor value of 1.1 nF per semiconductor chip carrier was obtained.
【００１６】支持基板４の他方の面には、配線基板の接
地端子、信号端子及び電源端子と接続される第２の接地
パッド12、第２の電源パッド13及び第２の信号パッド14
がそれぞれ形成されており、第１の接地パッド９及び第
１の電源パッド10は、誘電体層７及び支持基板４に設け
られた貫通導体路15、16を通して第２の接地パッド12及
び第２の電源パッド13と接続される。また、第１の信号
パッド11は、誘電体層７及び支持基板４に設けられた貫
通導体路15、16を通して支持基板４の他方の面に設けら
れた薄膜抵抗８の一方の電極に接続され、薄膜抵抗８の
もう一方の電極が第２の信号パッド14に接続されてい
る。以上の構成によれば半導体チップの直下において半
導体チップの信号端子と配線基板の信号端子とをつなぐ
信号線上に薄膜抵抗８が直列に挿入されることになり、
リードインダクタンス等による寄生インピーダンスの影
響が最小限に抑えられる。On the other surface of the support substrate 4, there are provided a second ground pad 12, a second power pad 13 and a second signal pad 14 which are connected to the ground terminal, the signal terminal and the power terminal of the wiring board.
Are formed respectively, and the first ground pad 9 and the first power supply pad 10 pass through the second ground pad 12 and the second ground pad 12 through the through conductor paths 15 and 16 provided in the dielectric layer 7 and the support substrate 4, respectively. Connected to the power supply pad 13 of. Further, the first signal pad 11 is connected to one electrode of the thin film resistor 8 provided on the other surface of the supporting substrate 4 through the dielectric layer 7 and the through conductor paths 15 and 16 provided in the supporting substrate 4. , The other electrode of the thin film resistor 8 is connected to the second signal pad 14. According to the above configuration, the thin film resistor 8 is inserted in series directly below the semiconductor chip on the signal line connecting the signal terminal of the semiconductor chip and the signal terminal of the wiring board.
The influence of parasitic impedance due to lead inductance and the like can be minimized.
【００１７】薄膜抵抗８は、窒素雰囲気中においてTaタ
ーゲットを基板温度450 ℃でスパッタして形成したTa2N
から成り、膜厚1000Å、外形100 ×200 μm にパターニ
ングされたものを用いている。抵抗値は55Ω／個であ
る。The thin film resistor 8 is formed of Ta 2 N by sputtering a Ta target at a substrate temperature of 450 ° C. in a nitrogen atmosphere.
The film thickness is 1000Å and the pattern is 100 × 200 μm. The resistance value is 55Ω / piece.
【００１８】以上述べた半導体チップキャリヤは、図２
に示したように、第１の接地パッド９、第１の電源パッ
ド10及び第１の信号パッド11が半導体チップの接地端
子、電源端子及び信号端子に半田ボール17を介してそれ
ぞれ接続されるとともに、第２の接地パッド12、第２の
電源パッド13及び第２信号パッド14は配線基板の接地端
子、電源端子及び信号端子に半田ボール17を介してそれ
ぞれ接続される。The semiconductor chip carrier described above is shown in FIG.
As shown in FIG. 1, the first ground pad 9, the first power supply pad 10 and the first signal pad 11 are connected to the ground terminal, the power supply terminal and the signal terminal of the semiconductor chip via solder balls 17, respectively. , The second ground pad 12, the second power pad 13 and the second signal pad 14 are connected to the ground terminal, the power terminal and the signal terminal of the wiring board through solder balls 17, respectively.
【００１９】図３は本発明の他の実施例を示す断面であ
り、図１と同一のものには同一番号を付した。この実施
例では、第１の接地パッド９、第１の電源パッド10及び
第１の信号パッド11は、誘電体層７及び支持基板４に設
けた貫通導体路15、16を通して他方の面に設けられた第
２の接地パッド12、第２の電源パッド13及び第２の信号
パッド14にそれぞれ接続されている。そして、第２の信
号パッド14と第２の接地パット12間に薄膜抵抗８が接続
されている。図１に示した実施例では薄膜抵抗が半導体
チップの信号線に直列に挿入されるのに対して、図３に
示した実施例では薄膜抵抗が半導体チップの信号線と接
地端子の間に並列に挿入されることになる。図１及び図
３のいずれの形態を採用するかは半導体チップの回路構
成に依存し、例えば、回路構成がC-MOS 構成となってい
る場合には、終端抵抗として用いられる薄膜抵抗を半導
体チップの信号線に直列に挿入する方式（図１）が用い
られる。FIG. 3 is a sectional view showing another embodiment of the present invention. The same parts as those in FIG. 1 are designated by the same reference numerals. In this embodiment, the first ground pad 9, the first power pad 10 and the first signal pad 11 are provided on the other surface through the through conductor paths 15 and 16 provided in the dielectric layer 7 and the supporting substrate 4. The second ground pad 12, the second power supply pad 13, and the second signal pad 14 are connected to each other. The thin film resistor 8 is connected between the second signal pad 14 and the second ground pad 12. In the embodiment shown in FIG. 1, the thin film resistor is inserted in series to the signal line of the semiconductor chip, whereas in the embodiment shown in FIG. 3, the thin film resistor is connected in parallel between the signal line of the semiconductor chip and the ground terminal. Will be inserted into. Which form of FIG. 1 and FIG. 3 is adopted depends on the circuit configuration of the semiconductor chip. For example, when the circuit configuration is a C-MOS configuration, the thin film resistor used as the termination resistor is a semiconductor chip. The method (FIG. 1) of serially inserting into the signal line of FIG.
【００２０】また、図１及び図３に示した実施例では、
支持基板４の一方の面において表面側に形成した金属膜
を電源層６とし支持基板４側に形成した金属膜を接地層
５としているが、接地層５と電源層６の機能を入れ換え
て逆にしても全く同様な効果を得ることができる。Further, in the embodiment shown in FIGS. 1 and 3,
The metal film formed on the front surface side of one surface of the support substrate 4 is used as the power supply layer 6, and the metal film formed on the support substrate 4 side is used as the ground layer 5. However, the functions of the ground layer 5 and the power supply layer 6 are exchanged and the reverse operation is performed. However, the same effect can be obtained.
【００２１】[0021]
【発明の効果】以上のように、本発明によればデカップ
リングキャパシタとともに終端抵抗をも半導体チップキ
ャリヤと一体化して形成でき、また、半導体チップキャ
リヤの表面積の大部分をデカップリングキャパシタとし
て用いることができるので、半導体チップの実装密度を
向上させかつスイッチングノイズを低減する上で有益で
ある。As described above, according to the present invention, the terminating resistor can be formed integrally with the semiconductor chip carrier together with the decoupling capacitor, and most of the surface area of the semiconductor chip carrier is used as the decoupling capacitor. Therefore, it is useful for improving the packaging density of semiconductor chips and reducing switching noise.
【図面の簡単な説明】[Brief description of drawings]
【図１】 本発明の実施例に係る半導体チップキャリヤ
を示す図であり、（ａ）は平面図、（ｂ）はそのＡＡ′
断面図1A and 1B are views showing a semiconductor chip carrier according to an embodiment of the present invention, in which FIG. 1A is a plan view and FIG. 1B is its AA ′.
Cross section
【図２】 半導体チップキャリヤの実装形態を示す断面
図FIG. 2 is a sectional view showing a mounting form of a semiconductor chip carrier.
【図３】 本発明の他の実施例に係る半導体チップキャ
リヤを示す図であり、（ａ）は平面図、（ｂ）はそのＡ
Ａ′断面図3A and 3B are views showing a semiconductor chip carrier according to another embodiment of the present invention, in which FIG. 3A is a plan view and FIG.
A'cross section
１ 半導体チップ ９ 第１の
接地パッド
２ 半導体チップキャリヤ 10 第１の
電源パッド
３ 配線基板 11 第１の
信号パッド
４ 支持基板 12 第２の
接地パッド
５ 接地層 13 第２の
電源パッド
６ 電源層 14 第２の
信号パッド
７ 誘電体層 15、16 貫
通導体路
８ 薄膜抵抗 17 半田ボ
ール1 Semiconductor Chip 9 First Ground Pad 2 Semiconductor Chip Carrier 10 First Power Pad 3 Wiring Board 11 First Signal Pad 4 Support Board 12 Second Ground Pad 5 Ground Layer 13 Second Power Pad 6 Power Layer 14 Second signal pad 7 Dielectric layers 15 and 16 Through conductor path 8 Thin film resistor 17 Solder ball
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭63−107129（ＪＰ，Ａ) 特開 昭62−265732（ＪＰ，Ａ) 特開 昭59−178768（ＪＰ，Ａ) 特開 昭59−94441（ＪＰ，Ａ) 特開 平７−22757（ＪＰ，Ａ) 特開 平５−175353（ＪＰ，Ａ) 特開 平４−139711（ＪＰ，Ａ) 特開 平３−258101（ＪＰ，Ａ) 特開 平１−114003（ＪＰ，Ａ) 実開 昭62−30346（ＪＰ，Ｕ) 実開 平１−13136（ＪＰ，Ｕ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 23/12 H01L 25/00 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A 63-107129 (JP, A) JP-A 62-265732 (JP, A) JP-A 59-178768 (JP, A) JP-A 59- 94441 (JP, A) JP-A-7-22757 (JP, A) JP-A-5-175353 (JP, A) JP-A-4-139711 (JP, A) JP-A-3-258101 (JP, A) Japanese Unexamined Patent Publication No. 1-114003 (JP, A) Actual development 62-30346 (JP, U) Actual development 1-13136 (JP, U) (58) Fields investigated (Int.Cl. 7 , DB name) H01L 23/12 H01L 25/00
Claims (2)
続され、他方の面に配線基板が接続される半導体チップ
キャリヤにおいて、 該支持基板の一方の面に接地層及び電源層からなる一対
の金属膜とその間に挟まれた誘電体層が積層されて成る
薄膜キャパシタが形成されるとともに、該支持基板の他
方の面に薄膜抵抗が形成され、 該支持基板の一方の面には、該半導体チップの接地端
子、電源端子及び信号端子と接続される第１の接地パッ
ド、第１の電源パッド及び第１の信号パッドがそれぞれ
形成され、 該支持基板の他方の面には、該配線基板の接地端子、電
源端子及び信号端子と接続される第２の接地パッド、第
２の電源パッド及び第２の信号パッドがそれぞれ形成さ
れ、 該第１の接地パッド及び該第１の電源パッドは、該支持
基板に設けた貫通導体路を通して第２の接地パッド及び
第２の電源パッドと接続され、 該第１の信号パッドは、該貫通導体路を通して他方の面
に設けられた薄膜抵抗の一方の電極に接続され、該薄膜
抵抗のもう一方の電極が第２の信号パッドに接続されて
いる ことを特徴とする半導体チップキャリヤ。1. A semiconductor chip carrier in which a semiconductor chip is connected to one surface of a supporting substrate and a wiring board is connected to the other surface of the supporting substrate, wherein a pair of ground layers and power supply layers are provided on one surface of the supporting substrate. metal film and is between the thin film capacitor dielectric layer is formed by laminating sandwiched formation Rutotomoni, is a thin film resistor formed on the other surface of the supporting substrate, on one surface of the supporting substrate, the semiconductor Ground end of chip
A first grounding pad connected to the child, the power supply terminal and the signal terminal.
The first power pad and the first signal pad
And the ground terminal of the wiring board
A second ground pad connected to the source terminal and the signal terminal,
Two power pads and a second signal pad are formed respectively.
The first ground pad and the first power pad are
A second ground pad through a through conductor provided on the substrate;
The second signal pad is connected to the second power pad, and the first signal pad is connected to the other surface through the through conductor path.
Is connected to one electrode of a thin film resistor provided in
The other electrode of the resistor is connected to the second signal pad
A semiconductor chip carrier, characterized in that there.
号パッドと該第２の接地パッド間に該薄膜抵抗が接続さ
れていることを特徴とする請求項１記載の半導体チップ
キャリヤ。 2. The second signal is provided on the other surface of the supporting substrate.
2. The semiconductor chip carrier according to claim 1, wherein the thin film resistor is connected between the No. pad and the second ground pad .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1970896A JP3465464B2 (en) | 1996-02-06 | 1996-02-06 | Semiconductor chip carrier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1970896A JP3465464B2 (en) | 1996-02-06 | 1996-02-06 | Semiconductor chip carrier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH09213835A JPH09213835A (en) | 1997-08-15 |
| JP3465464B2 true JP3465464B2 (en) | 2003-11-10 |
Family
ID=12006796
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1970896A Expired - Fee Related JP3465464B2 (en) | 1996-02-06 | 1996-02-06 | Semiconductor chip carrier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3465464B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010098026A1 (en) | 2009-02-25 | 2010-09-02 | 日本電気株式会社 | Capacitor fabrication method, capacitor fabricating device, capacitor fabricating program, and recording medium |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6657291B1 (en) * | 1997-12-19 | 2003-12-02 | International Business Machines Corporation | Combined resistor-capacitor elements for decoupling in electronic packages |
| KR100294449B1 (en) * | 1998-07-15 | 2001-07-12 | 윤종용 | Semiconductor integrated circuit device with capacitor formed under bonding pad |
| US6617681B1 (en) * | 1999-06-28 | 2003-09-09 | Intel Corporation | Interposer and method of making same |
| JP4628520B2 (en) * | 2000-06-06 | 2011-02-09 | 富士通株式会社 | Manufacturing method of electronic device mounting substrate |
| JP2002299496A (en) * | 2001-03-30 | 2002-10-11 | Fujitsu Ltd | Semiconductor device and its fabricating method |
| JP2007103469A (en) * | 2005-09-30 | 2007-04-19 | Aica Kogyo Co Ltd | Built-in capacitor forming structure of multilayered printed circuit board |
-
1996
- 1996-02-06 JP JP1970896A patent/JP3465464B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010098026A1 (en) | 2009-02-25 | 2010-09-02 | 日本電気株式会社 | Capacitor fabrication method, capacitor fabricating device, capacitor fabricating program, and recording medium |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH09213835A (en) | 1997-08-15 |
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