JP3452043B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure and manufacturing method of a semiconductor device for flip chip connection.

[0002]

2. Description of the Related Art Most semiconductor devices have a laminated structure, and an insulating layer is often arranged between the layers.
An opening is provided in this insulating layer, and a wiring that connects the terminal of the lower layer and the terminal of the upper layer is formed through the opening.

The following methods are adopted as the method for forming the insulating layer. That is, a photosensitive insulating material is applied onto a semiconductor device by a spin coating method, and exposure and development are performed to form an opening portion of the insulating layer. In addition, for the metal wiring that connects the terminal on the lower layer and the terminal on the upper layer, a second photosensitive material is applied to the upper layer of the insulating layer, and a mask is formed by performing exposure and development on the second photosensitive material, and plating with this. By using processes such as sputtering, CVD, and vapor deposition together, a metal wiring that connects the terminal of the insulating layer lower layer and the upper layer is formed. The photosensitive insulating material used as the mask is removed after it is no longer needed.

Through the above steps, it is possible to form a wiring that connects the terminal in the lower layer of the insulating layer and the upper layer. FIG. 3 is a partial cross-sectional view of a semiconductor device formed by such a process.
Shown in 1. In the figure, the aluminum pad 7 is the insulating layer 1.
2 is a lower layer terminal, and the bump pad 3 is an insulating layer upper layer terminal. The insulating layer 12 formed on the semiconductor-formed wafer 9 has an opening formed on the aluminum pad 7. Further, metal wiring 11 is formed from the aluminum pad 7 to the bump pad 3 on the upper layer of the insulating layer 12. Bumps 10 on the bump pads 3
Are formed. Forming the wiring from the aluminum pad 7 to the bump pad 3 in this way is called rewiring. Further, the thickness of the insulating layer 12 at this time is almost equal to the thickness of the metal wiring 11.

Flip-chip connection is one of the forms in which the semiconductor device manufactured through these steps is mounted and connected on a circuit board such as a printed wiring board. Figure 32
FIG. 3 is a cross-sectional view of a flip-chip connected semiconductor device.
The connection between the semiconductor device 13 and the circuit board 14 is realized by solidifying the bumps 10 provided on the terminals of the semiconductor device 13 again on the circuit board. The gap between the semiconductor device 13 and the circuit board 14 is filled with a highly rigid resin. This resin is called underfill 15 and has the effect of reinforcing the connecting portion. Japanese Patent Laid-Open No. 11-1 as an example of flip-chip connection with underfilling
There is a publication of 11768.

[0006]

However, the above-mentioned prior art has the following problems.

First, there is a problem in the method of supplying resin to the gap between the semiconductor device and the circuit board. That is, as a method of supplying the resin to the gap having a gap of generally 0.3 mm or less, a method of utilizing a capillary phenomenon is adopted. However, since the resin material for underfill is a high-viscosity liquid resin, there is a problem that it takes time to fill in the gap and air bubbles are likely to remain.

Second, it is difficult to remove the semiconductor device.
That is, if the semiconductor device connected to the circuit board is defective, even if the semiconductor device is removed from the circuit board,
Since the cured underfill material remains on the circuit board even after the removal, there is a problem that it is difficult to recycle the circuit board.

In order to solve the first and second problems, it is desirable to connect the semiconductor device to the circuit board without performing underfill. However, underfilling is performed for the purpose of preventing the destruction of the connection part due to the distortion that occurs in the connection part due to heat generation etc. when using the finished electrical product. There is a problem that the life is extremely shortened.

An object of the present invention, realize a semiconductor device that enables unnecessary flip chip bonding underfill
That is.

[0011]

In order to achieve the above-mentioned object, the present invention is constructed as in the claims. For example, a semiconductor element having a circuit electrode and the semiconductor
On the semiconductor element so that the circuit electrodes of the body element are exposed
A formed first insulating layer and a layer formed on the first insulating layer.
A second flat part having a flat part and an inclined part at its end.
An insulating layer and an outer layer formed on the flat portion of the second insulating layer
Connection terminal and flat and inclined portions of the second insulating layer
Is formed on the external connection terminal and the semiconductor element.
Wiring that electrically connects the circuit electrodes of the child and the second insulation
A third insulating layer formed on the edge layer and the wiring.
The semiconductor device according to claim 1, wherein the second insulating layer is
Between the conductor device and the substrate on which the semiconductor device is mounted.
It is a layer that relieves the twisting stress and contains particles.
And a semiconductor device.

[0012]

In this specification, this thick film insulating layer is referred to as a stress relaxation layer.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to the drawings. In all of the drawings, the same reference numerals denote the same parts, and therefore redundant description may be omitted, and the dimensional ratio of each part is different from the actual size for ease of description.

First, the structure of the semiconductor device according to the present embodiment will be described. A large number of semiconductor devices are collectively manufactured on a wafer-by-wafer basis. However, in order to facilitate the description, a part of the semiconductor device will be described below. FIG. 1 shows a partial cross-sectional view of the semiconductor device 13 of this embodiment.

The wafer 9 on which the semiconductor circuit is formed is
This is a wafer that has undergone the pre-process in the semiconductor manufacturing process and has not yet been divided into a large number of semiconductor devices 13. External connection terminals, for example, aluminum pads 7 are formed on each semiconductor device 13. This aluminum pad 7
In the conventional semiconductor device 13, the QFP (Quad
When used in a semiconductor package such as a flat package), it is used to connect a gold wire or the like to achieve conduction with an external terminal of the semiconductor package. The surface of the semiconductor device 13 on which the semiconductor circuit is formed is
The protective film 8 covers the aluminum pad 7 and the wafer 9 on which a large number of semiconductors are formed, except for a cutting portion 24 and its periphery when the semiconductor device 13 is cut into chips. For the protective film 8, an insulating resin made of an inorganic material having a thickness of about 1 to 10 μm is used alone or an insulating resin made of an organic material is used in combination. The protective film 8 is made of an inorganic material having a thickness of 1 to 10 micrometers.
An inorganic insulating film is used alone, or a composite film in which an organic insulating film made of an organic material is laminated on the inorganic insulating film is used. When using this composite membrane, the organic insulating film it is desirable to use a photosensitive resin material. Examples of the photosensitive material suitable as the organic insulating film of the protective film 8 in this embodiment include photosensitive polyimide, photosensitive benzocyclobutene, and photosensitive polybenzoxazole. In the present embodiment, not limited to this, from a commonly used inorganic material known as a protective film
Inorganic insulating film, an organic insulating film or a composite film thereof made of an organic material may be used comprising. For example, as the material of the inorganic insulating film , SiN, SiO2 or the like can be used. In addition, the organic
Of course, the insulating film may be formed so as to cover almost the entire surface of the inorganic insulating film , but as shown in FIG. 33, it may be formed only in a region near the aluminum pad 7, and FIG. It may be formed only at arbitrary plural positions on the surface of the inorganic insulating film as shown in FIG. By thus limiting the region of the organic insulating film , the warp of the wafer 9 due to the internal stress of the protective film 8 is reduced, which is advantageous in terms of handling in the manufacturing process and focusing during exposure. In the present embodiment, the area near the aluminum pad 7 means the maximum distance 1 from the end of the aluminum pad 7.
It refers to the area up to mm. Note that FIG. 33 and FIG.
Although the organic insulating film around the aluminum pad 7 is formed in a continuous region, it may be formed in an independent region for each aluminum pad. Specifically, for example, the area is as shown in FIG. Whether to use any form of FIG. 35 from FIG. 33, the pattern accuracy of the photosensitive resin to be used for the organic insulating film is determined in consideration of the elements characteristic of the internal stress, and the semiconductor device of the film. An example of the element characteristics referred to here is that the level of the energy barrier in each active cell (transistor) inside the element varies due to the stress action on the semiconductor device.

A stress relaxation layer 5 having a thickness of 35 to 150 micrometers is selectively formed on the protective film 8. The film thickness of the stress relaxation layer depends on the size of the semiconductor element, the elastic modulus of the stress relaxation layer, the thickness of the semiconductor element, etc., and cannot be generally determined, but the thickness of the semiconductor element generally used is about 150 to 750 μm, and a stress simulation experiment was conducted using a bimetal model composed of a semiconductor element and a stress relaxation layer formed on the surface of the semiconductor device. The required stress relaxation layer film thickness is preferably 10 to 200 μm, more preferably Is 35 to 1
Since it was found that the thickness was 50 micrometers, the film was formed in this thickness range in this example. 35 to 150 my
Chromimeter has a semiconductor element thickness of 750 micrometers
In the case of
This corresponds to a thickness of about 0 to 1/5. If the film thickness is less than 35 μm, the desired stress relaxation cannot be obtained, and if the film thickness exceeds 150 μm, the warp of the wafer occurs due to the internal stress of the stress relaxation layer 5 itself. Occurs, which tends to cause focus deviation in the exposure process, handling defects in the wiring formation process, and the like, resulting in a decrease in productivity. The stress relaxation layer 5 has an elastic modulus significantly smaller than that of the semiconductor wafer 9, for example, 0.1 GPa to 10 GPa at room temperature.
It is formed of a resin material having an elastic coefficient of. If the stress relaxation layer has an elastic coefficient in this range, a reliable semiconductor device can be provided. That is,
In the case of a stress relaxation layer having an elastic coefficient of less than 0.1 GPa, it becomes difficult to support the weight of the semiconductor element itself, and the problem that the characteristics are not stable when used as a semiconductor device tends to occur. On the other hand, when a stress relaxation layer having an elastic coefficient of more than 10 GPa is used, the internal stress of the stress relaxation layer 5 itself causes the wafer to warp, resulting in focus misalignment in the exposure process and handling failure in the wiring formation process. And so on, and there is even a risk that the wafer may break. Stress relaxation layer 5
Has an inclination, and its average gradient is about 5 to 30%. When the inclination angle is less than 5%, the inclination becomes too long and the desired film thickness cannot be obtained. For example, in order to obtain a thickness of 100 micrometers at an inclination angle of 3% on average, a horizontal distance of more than 3 mm is required, and if the left and right edges are combined, the desired film thickness cannot be obtained unless there is approximately 7 mm. It will be. On the other hand, when the inclination angle exceeds 30%, there is no problem in terms of horizontal distance, but conversely there is a high risk that sufficient step coverage cannot be obtained when forming wiring. In particular, there is no process margin in the process of plating resist, exposure, and development, and special skill or technique is required. Further, when the inclination angle is large, a so-called stress concentration effect acts to concentrate stress on the edge portion, and as a result, disconnection of the rewiring wiring 4 tends to occur at the edge portion. There may be a need for special measures. In the case of FIG. 1, since the film thickness is 50 μm at the horizontal distance of 500 μm from the edge of the stress relaxation layer 5, the average gradient is 10%. The rewiring wiring 4 is formed of a conductor such as copper, and connects the aluminum pad 7 and the protruding electrode on the surface of the stress relaxation layer 5, for example, the bump pad 3. Further, gold plating 2 may be provided on the bump pads 3 to prevent the bump pads 3 from being oxidized. The surface of the semiconductor device 13 is covered with the surface protective film 6 except for the cut portions 24 when the wafer 9 on which the bump pads 3 and a large number of semiconductors are formed is cut into the semiconductor devices 13.

Since the protective film 8 and the stress relaxation layer 5 are completely covered with the surface protective film 6 for sealing, the protective film 8 and the stress relaxation layer 5 are separated from the surface of the wafer 9 on which the semiconductor element is formed. It is also possible to prevent intrusion of foreign matter such as ions that cause deterioration of semiconductor performance. Also,
Since the protective film 8, the stress relaxation layer 5, and the surface protective film 6 are all recessed from the cut portion 24, they are not damaged when the semiconductor device 13 is cut and separated.

As the surface protective film 6, various resin materials having electric insulation properties can be used. Since it is necessary to form a pattern, it is preferable that the material is a photosensitive material, but a material that supports high-precision printing such as inkjet may be used to form a film by printing. In addition, a step of solid-forming an insulating film by an inexpensive coating method such as curtain coating, forming an etching resist by using a photolithography process and patterning, etching the insulating film using the resist pattern, and removing the resist. You may form into a film via. As such a material, various materials can be used in the present embodiment, but some examples are as follows: (1) Acrylic-modified photosensitive epoxy resin, photosensitive polyimide resin,
(2) Polyamideimide resin and polyimide resin are preferably used as the ink jet printing material, and modified triazole resin, modified melamine resin, polyimide resin and the like are suitably used as the solid film forming material. More specifically exemplifying the photosensitive material, the surface protective film 6 is a solder resist which is preferably used as an inexpensive photosensitive resin material in a printed circuit board manufacturing process or a photosensitive polyimide which is used for a surface cover of a flexible printed circuit board. It is preferably used. On the other hand, as a solid film forming material, for example, Photo Nice TM manufactured by Toray Industries, Inc. is suitable. In this example, a solder resist was used. Bump pad 3
The bump 1 is formed on the top. This bump 1 is
It is generally formed of a solder material. Here, the bump 1 serves as an external connection terminal.

FIG. 2 is a plan view showing a state in which the semiconductor device 13 shown in FIG. 1 is continuously formed on the wafer without the originally existing bumps 1. The hatched portion in FIG. 2 is the solder resist which is the surface protective film 6. Further, the stress relaxation layer 5 is formed in a rectangular shape with rounded corners, and there is a cutting portion 24 between the semiconductor devices 13 that serves as a cutting margin when the semiconductor devices 13 are separated. To do. The cut margin is preferably located, for example, 10 to 100 μm from the end of the surface protective film 6. If it is shorter than 10 micrometers, chipping tends to be easily induced when separating each semiconductor device, and if it is longer than 100 micrometers, the effective area usable as a semiconductor element decreases.
Therefore, in order to improve the yield of the semiconductor device 13, the distance between the cutting margin and the surface protection layer 6 is 10 to 10 in this embodiment.
It is desirable to locate it at 0 micrometer. In addition,
Although not shown in the figure, an aluminum pad 7 is present in a layer below one end of the rewiring wire 4.

According to this semiconductor device structure, since the stress relaxation layer 5 is present between the rewiring wiring 4 and the wafer 9, the semiconductor device 13 is connected to the circuit board 14 and the bump 1 is applied when it is operated. It is possible to disperse the distortion caused by the heat received by the. Therefore, even when the semiconductor device 13 is mounted on the circuit board 14, the connection life can be extended without performing the underfill 15. Further, since the stress relaxation layer 5 has a gently sloping portion, there is no wiring bent portion which becomes a stress concentration portion in the middle of the rewiring wiring 4.

An example of the manufacturing process of the semiconductor device 13 in this embodiment will be described with reference to the drawings. The first step to the third step will be described with reference to FIG. 3, the fourth step to the sixth step with FIG. 4, and the seventh step to the ninth step with FIG. It should be noted that in each of the drawings, in order to make the sectional structure of the semiconductor device 13 in the present embodiment easy to understand, it is a sectional view in which a part is taken out.

First step: The wafer 9 on which the semiconductor having the aluminum pad 7 for external connection formed thereon is formed is manufactured in the same step as the conventional semiconductor device 13. In the semiconductor device used in this example, the material of the external connection pad was aluminum, but the external connection pad may be copper. This is because in this embodiment, since wire bonding is not used for external connection, it is not necessary to consider the problem of bondability that tends to occur when the external connection pad is copper. If the external connection pad is copper, the electrical resistance of the wiring can be reduced, which is desirable from the viewpoint of improving the electrical characteristics of the semiconductor element.

Second step: The protective film 8 is formed, if necessary. The protective film 8 may be already formed by using an inorganic material in a so-called pre-process in the semiconductor manufacturing process, or may be further formed by stacking an organic material on the inorganic material. In this embodiment, an insulating film made of an inorganic material formed in a so-called pre-process in a semiconductor process, for example, silicon nitride formed by a CVD method or the like, silicon dioxide formed by tetraethoxysilane, or a composite thereof. A photosensitive polyimide, which is an organic material, is applied onto the insulating film formed of a film, and the protective film 8 having a thickness of about 6 μm is formed by exposing, developing and curing the photosensitive polyimide. As a result, the protective film 8 is formed on the wafer 9 on which the semiconductor is formed. In this embodiment, the protective film 8
Although the film thickness of the semiconductor device is 6 μm, the required film thickness varies depending on the type of the semiconductor element, and the range is 1
To about 10 micrometers. The organic film may be formed so as to cover almost the entire surface of the inorganic film as shown in FIG.
As shown in FIG. 5, it may be formed only in the region near the aluminum pad 7. In the case of an insulating film made of only an inorganic material, the film thickness range is 3 micrometers or less. In addition to the photosensitive polyimide used in the examples of the present application, polybenzoxazole, polybenzocyclobutene, polyquinoline, polyphosphazene, etc. can be used.

Third step: A paste-like polyimide material is printed and applied to the place where the stress relaxation layer 5 is to be formed, and then heated to cure it. As a result, the stress relaxation layer 5 is formed on the protective film 8.

Fourth step: After forming the power supply film 16 for use in electroplating by a method such as sputtering, the reverse pattern 17 of the wiring is formed using photoresist.

Fifth step: Electroplating is performed by using the power supply film 16 and the reverse pattern 17 of the wiring to form the rewiring wiring 4 and the bump pad 3. Further, the rewiring wiring 4 has a multi-layer structure by repeating electroplating as necessary.

Sixth step: The reverse pattern 17 of the wiring made of photoresist and the power supply film 16 for electroplating are removed by etching.

Seventh step: The surface protection film 6 is formed using a solder resist. Then, using this pattern, electroless gold plating 2 is performed on the outermost surface of the bump pad 3.

Eighth step: A solder ball is mounted on the bump pad 3 together with flux and heated to connect the solder ball to the bump pad 3 to form the bump 1.

Ninth step: wafer 9 on which a semiconductor is formed
Is cut into semiconductor devices 13 by the wafer dicing technique.

The above third to eighth steps will be described in detail below.

First, the third step will be described. The mask used for printing may have the same structure as the printing mask used for solder paste printing on a printed wiring board. For example, as shown in FIG. 6, a metal mask in which a nickel alloy stencil 25 is attached to a frame 27 via a resin sheet 26 can be used. The pattern opening portion 28 of the printing mask may be made smaller by about 50 μm because the paste spreads after printing after printing. As shown in FIG. 7, in paste printing, the printing mask and the pattern of the wafer 9 on which the semiconductor is formed are brought into close contact with each other in an aligned state, and in this state, the squeegee moves on the stencil 25 to form a pattern opening. The so-called contact printing for printing is performed by filling the portion 28 and then raising the printing mask relative to the wafer 9 on which the semiconductor is formed. The close contact between the wafer and the printing mask here does not necessarily mean that there is no gap between them. This is because the protective film 8 has already been partially formed on the wafer, and thus it is practically difficult to closely adhere the print mask on the protective film 8. In this example, printing was performed under printing conditions such that the gap between the wafer and the printing mask was 0 to 100 micrometers. In addition, the first squeegee coats the entire squeegee surface of the printing mask with paste, and then the second squeegee fills the pattern openings 28 of the printing mask and removes excess paste. After that, there is also a printing method in which the printing mask is raised relatively to the wafer 9 on which the semiconductor is formed. As shown in FIG. 8, when the print mask is raised relative to the wafer 9, it may be raised vertically, but it may be raised while moving so as to have a relative inclination angle. By providing the inclination angle, the plate separation angle when the print mask separates from the wafer is likely to be uniform in the wafer surface. In addition, the print mask moves away from one edge of the wafer toward the other edge, and the last moment of plate release, which tends to make plate release unstable, is performed in a region where there is no semiconductor device. It is also advantageous in terms of yield improvement. Furthermore, when performing continuous printing on a plurality of wafers using the same printing machine, it is advisable to insert a step of wiping the back side of the mask plate at an appropriate timing. For example, in this embodiment, after printing 10 sheets continuously, the back side of the mask plate was cleaned once, and then the 11th sheet was printed.
The timing, the number of times, and the method of cleaning the back side of the mask need to be appropriately adjusted depending on the viscosity of the paste material, the solid content concentration, the filler amount, and the like.

Subsequently, the wafer 9 on which the semiconductor on which the paste is printed and formed is formed is heated step by step using a hot plate or a heating furnace, whereby the paste is hardened and the formation of the stress relaxation layer 5 is completed.

The material for forming the stress relaxation layer 5 used here is a paste-like polyimide, which can be cured by heating after being applied on the protective film 8 by printing. The paste-like polyimide is composed of a polyimide precursor, a solvent, and a large number of polyimide fine particles dispersed therein. As the fine particles, specifically, fine particles having an average particle size of 1 to 2 μm and a particle size distribution with a maximum particle size of about 10 μm were used. When the polyimide precursor used in this example is cured, it becomes the same material as the fine particles of the polyimide. Therefore, when the paste polyimide is cured, the uniform stress relaxation layer 5 made of one type of material is used. Will be formed. In this example, polyimide was used as the stress relaxation layer forming material, but in this example, other than polyimide, an amide imide resin, an ester imide resin, an ether imide resin, a silicone resin, an acrylic resin, a polyester resin, a resin obtained by modifying these, etc. It is also possible to use. When a resin other than polyimide is used, it may be subjected to a treatment for imparting compatibility to the surface of the polyimide fine particles, or a modification may be made to the resin composition so as to improve the affinity with the polyimide fine particles. desirable. Among the resins listed above, resins having an imide bond, such as polyimide, amide imide, ester imide, and ether imide, have excellent thermomechanical properties, such as strength at high temperature, due to the strong skeleton by the imide bond, As a result, the choice of plating power supply film forming method for wiring is expanded. For example, it is possible to select a plating power supply film forming method involving high-temperature processing such as sputtering. In the case of a resin having a portion condensed by a bond other than an imide bond, such as a silicone resin, an acrylic resin, a polyester resin, an amide imide, an ester imide, or an ether imide, the thermo-mechanical property is slightly inferior, but it is advantageous in terms of processability and resin price. There are cases. For example, a polyester imide resin is generally easier to handle because it has a lower curing temperature than polyimide. In this embodiment, these resins are appropriately used in consideration of the element characteristics, the price, the thermomechanical characteristics, etc., among these resins.

Since the viscoelastic properties of the material can be adjusted by dispersing the polyimide fine particles in the paste-like polyimide, it is possible to use a paste having excellent printability. By adjusting the composition of the fine particles, it becomes possible to control the thixotropic property of the paste. Therefore, by combining it with the adjustment of the viscosity, the printing property can be improved. Also, the inclination angle of the stress relaxation layer 5 can be adjusted. The thixotropy characteristic of the paste suitable in the examples of the present application is obtained from the ratio of the viscosity at a rotation speed of 1 rpm measured using a rotational viscometer and the viscosity at a rotation speed of 10 rpm, so-called thixotropic index is 2.0.
It is desirable to be in the range of 3.0. In the case of a paste in which the thixotropy index has temperature dependence, the thixotropy index is 2.0 to 3.0.
High performance can be obtained by printing in the temperature range such that

After the printed paste polyimide is heated and cured, the stress relaxation layer 5 having the cross-sectional shape as shown in FIG. 9 is formed on the wafer 9. When the stress relaxation layer 5 is formed by printing in this manner, there may be a bulge portion at a position of 200 to 1000 micrometers from the edge portion of the stress relaxation layer 5. By adjusting the composition of the paste polyimide or changing various conditions related to printing, it becomes possible to control to some extent. In addition,
Various conditions related to printing in this case include metal mask thickness, squeegee speed, squeegee material, squeegee angle,
Examples include squeegee pressure (printing pressure), plate separation speed, wafer temperature during printing, and humidity of the printing environment. The control of the height and shape of the bulged portion can be achieved by the above printing conditions, but as another control method, there is also a method of adjusting the structure of the protective layer 8. For example, as shown in FIG. 36, if the formation region of the organic layer of the protective film 8 is limited only to the vicinity of the pad 7, it is easy to raise the stress relaxation layer in the portion corresponding to the upper portion of the organic layer.

Further, when the swelling portion is positively formed in the stress relaxation layer 5 as shown in FIG. 1, the slack portion of the wiring 4 can be formed, whereby the stress due to thermal expansion or the like is easily absorbed. The structure makes it possible to further prevent disconnection. Specifically, the maximum thickness of the stress relaxation layer 5 is about 25 μm, preferably 7 μm.
It is preferable that a bulge portion having a height of about 12 to 12 micrometers is formed. A vertex of this degree can be sufficiently formed by mask printing. For example, assuming that the bulge has a semi-cylindrical shape with a radius of 10 micrometers, the half arc length of the bulge is (2 × 3.1).
4 × 10 μm) /2=31.4 μm, and the redundant length of the wiring is 31.4−10 = 21.4 μm for each bulge, and one is formed on each side of the stress relaxation layer. In this case, it is 42.8 micrometers. As described above, since the redundant portion can be provided in the wiring 4, the thermal stress acting on the wiring structure and the solder joint is relieved, and therefore, a highly reliable wiring structure can be provided. The required thickness of this bulge is
The thickness and elastic modulus of the stress relaxation layer 5, the size of the semiconductor element 13, the power consumption of the semiconductor element, the physical properties of the circuit board 14 on which the semiconductor element is mounted, and the like are determined by experiments and simulations. For example, in this embodiment, the diagonal length of the semiconductor element 13 is L millimeters, and the semiconductor element 13 is
And the difference in the coefficient of linear expansion of the circuit board 14 on which it is mounted is 15
ppm / ° C, assuming that the maximum temperature range generated by the semiconductor device 13 board mounting process to ON / OFF during operation is 200 degrees Celsius, the maximum amount of thermal deformation the wiring part receives when the board mounted product is used in an actual use environment , 15 (ppm / ° C) x L / 2 (m
m) × 200 (° C.) = 0.015 × L millimeter. Therefore, it is considered that the redundant length required for the bulge portion is about 0.002 × L millimeters. From this calculation, the bulge portion is approximated by a semi-cylindrical shape, and in this embodiment, the height of the bulge portion falls within the range of L / 2000 to L / 500 millimeters with respect to the average thickness of the stress relaxation layer 5. I did it.

When the required film thickness of the stress relaxation layer 5 is not formed by one printing and heat curing, a predetermined film thickness can be obtained by repeating printing and curing of the material a plurality of times. For example, when a paste having a solid content concentration of 30 to 40% is used and a metal mask having a thickness of 65 μm is used, the film thickness after curing is about 50 in two printings.
You can get a micrometer. Further, in particular, regarding the bumps 1 arranged at locations where strain is likely to be concentrated when the semiconductor device 13 is connected to the circuit board 14, the thickness is increased by limiting only the stress relaxation layer 5 at the relevant location. By doing so, it is possible to reduce the concentration of distortion. For this purpose, for example, the paste-shaped polyimide may be printed on the wafer 9 on which the semiconductor is formed a plurality of times using a metal mask different from that used in the first printing. As a second method, the thickness of the stress relaxation layer can be partially changed by adjusting the structure of the protective layer 8. For example, as shown in FIG. 37, only the protective layer made of an inorganic film is used in the region immediately below the bump X where strain is likely to concentrate, and in the other regions, the composite layer in which an organic film is formed on the inorganic film is protected. The film. When a stress relaxation layer is formed on such a protective film, a gentle sloped portion is formed at the portion A of the stress relaxation layer where the organic film is provided and where the protective film is not provided. Now, the film thickness of the stress relaxation layer is 50 micrometers, its elastic modulus is 1 GPa, and the film thickness of the organic film is 1
Assuming that the elastic modulus is 0 GPm and 3 GPa, the average elastic modulus (GPa / micrometer) of the portion including the organic protective film and the stress relaxation layer is (3 × 10 + 1 × 5).
0) /60≈1.3, while the average elastic modulus of the inclined portion in the portion A is 1. Therefore, with such a structure, the thermal stress of the stress relaxation layer is dispersed from the peripheral portion to the portion where the organic protective film is formed, and the damage of the bump in the peripheral portion where the thermal stress is originally concentrated is prevented. Can be prevented. It should be noted that it is not always necessary to have fine particles in the stress relaxation layer, and even if the fine particles are not dispersed in the paste, the minimum viscoelastic property required for printing may be ensured. However, if the fine particles are not dispersed in the paste, the margin of various conditions related to printing may be extremely narrowed.

Next, the fourth step will be described. In this embodiment, the rewiring wiring 4 has two layers of electrolytic copper plating and electrolytic nickel. In addition, one end of the rewiring wiring 4 is connected to the bump pad 3
You may combine it with. Here, a method of forming a conductor by using electroplating for both copper and nickel has been described, but electroless plating can also be used.

First, the power supply film 16 for performing electroplating is formed on the entire surface of the semiconductor wafer. Here, although vapor deposition, electroless copper plating, CVD, or the like can be used, it is decided to use spatter which has a strong adhesive strength with the protective layer 8 and the stress relaxation layer 5. As a pretreatment for the sputter, sputter etching was performed to ensure electrical continuity between the bonding pad 7 and the rewiring wiring 4 conductor.
As the sputtered film in this example, a chromium (75 nanometer) / copper (0.5 micrometer) multilayer film was formed. The function of chrome here is to secure the adhesion between the copper located above and below and the stress relaxation layer, etc.
The film thickness is desirable to be the minimum that maintains their adhesion.
In addition to the problem that the film formation time increases and the production efficiency decreases as the chromium film thickness increases, the protective layer 8 and the stress relaxation layer 5 are also added.
Is exposed to the high-energy plasma generated in the sputtering chamber for a long time, and there is a risk that the material forming these layers will be deteriorated. The required film thickness varies depending on the sputter etching and sputter conditions, the film quality of chromium, etc.
It is about 0.5 micrometer at maximum. Incidentally, instead of the chromium film used in this example, a titanium film or titanium /
Platinum film, tungsten, etc. can be substituted. On the other hand, the film thickness of sputtered copper is preferably the minimum film thickness that does not cause the film thickness distribution of the plated film when electrolytic copper plating and electrolytic nickel plating that are performed in later steps are performed. The film thickness that does not induce the film thickness distribution is determined in consideration of the amount of film loss due to washing. When the thickness of sputtered copper is unnecessarily large, for example, when the thickness of copper exceeds 1 micrometer, in addition to the problem that the sputtering time becomes long and the production efficiency decreases, the power supply to be performed in a later step When the film 16 is removed by etching, etching is inevitable for a long time, and as a result, side etching of the redistribution wiring 4 becomes large. According to a simple calculation, when the power feeding film having a thickness of 1 μm is etched, the wiring also has a thickness of 1 μm on one side and 2 μm on both sides. In actual production, over-etching is generally performed so that the etching residue of the power supply film does not occur. Therefore, when etching the power supply film of 1 μm, the wiring is side-etched by about 5 μm. Will be. If the side etching becomes large in this way, the wiring resistance becomes large and the disconnection is likely to occur, which easily causes a problem in terms of wiring performance. Therefore, the maximum film thickness of sputtered copper is about 1 micrometer.

Next, using the photolithography technique,
The reverse pattern shape 17 of the rewiring wiring 4 is formed using a resist. The film thickness of the resist at the edge portion of the stress relaxation layer 5 shown by B in FIG. 4 becomes thicker than at other places due to the resist flowing out from the slope portion. Therefore, in order to secure the resolution, the negative type is preferable. When a liquid resist is used as the resist, the resist film thickness tends to be thin on the upper slope of the edge portion of the stress relaxation layer 5 shown by B in FIG. 4, and on the contrary, the resist film tends to be thicker on the lower slope. There is. A wide development margin is required to pattern resists having different film thicknesses on the upper slope and the lower slope under the same exposure amount and the same developing conditions. In general, since the negative photosensitive resist has a wider development margin with respect to the film thickness than the positive photosensitive resist, a negative liquid resist is used in this embodiment. When a film resist is used, the film heat difference between the upper and lower sides of the slope does not occur, so that it can be used with either the negative type or the positive type, but the slope portion is exposed from the lick and the actual optical path length is long. Therefore, even in this case, a good result is often obtained by using the negative type. The negative type is particularly preferable when the edge portion of the stress relaxation layer 5 has a large inclination or when a film resist having weak bleaching characteristics is used. In this embodiment, FIG.
As shown in, an exposure machine of a type in which the exposure mask 21 and the resist 22 are in close contact with each other and a gap 20 is partially used.
The resolution limit in the exposure machine was about 10 micrometers when the exposure mask 21 and the resist 22 were in close contact with each other. According to our experimental results, the relationship between the gap 20 under the exposure mask 21 and the wiring width to be resolved is as shown in Table 1. The values in Table 1 are the optical system of the exposure machine and the developing conditions.
It varies depending on the resist sensitivity, resist curing conditions, wiring width / wiring interval ratio, and the like. The experimental results shown in Table 1 are values when the wiring width / wiring interval ratio is 1.0.

[0043]

[Table 1]

FIG. 11 shows a state in which the connection portion 23 with the aluminum pad and the bump pad 3 are connected by the rewiring wiring 4. In the case of the exposure apparatus used in this example, the gap below the exposure mask, which is the horizontal axis in Table 1, corresponds approximately to the thickness of the stress relaxation layer, so that the stress relaxation layer has a thickness of 6 mm, for example.
If the width is 0 μm, the wiring width can be resolved up to 25 μm. Therefore, wiring can be performed with the wiring width of the signal line being 25 μm and the wiring width of the power supply or ground line being 40 μm. Further, it is possible to make the signal line wiring 25 μm and thicken a part of the signal line.

FIG. 12 is an enlarged view of the rewiring wiring 4 near the inclined portion of the stress relaxation layer 5. As described above, since the resist film thickness is non-uniform near the edge portion of the stress relaxation layer 5, there is a tendency that insufficient development easily occurs in that region. FIG. 13 shows a state where insufficient development actually occurs at the edge portion of the stress relaxation layer 5. In the present embodiment, the solution is solved by improving the wraparound of the developing solution as a countermeasure. More specifically, a measure is to change the wiring pattern shape as shown in FIGS. 14 and 15.

FIG. 14 shows a case where the wiring width is increased from the connection portion 23 with the aluminum pad to the vicinity of the top of the stress relaxation layer 5,
FIG. 15 shows a case where the wiring width is thick only at the edge portion of the stress relaxation layer 5 having poor resolution. In addition, these FIG.
4 and the wiring width in FIG. 15 are determined in consideration of the thickness of the stress relaxation layer 5 and the resolution characteristics shown in Table 1. As another solution, a method of eliminating the undeveloped residue by extending the developing time can be considered. Further, since the light is diffracted on the mask surface, the resolution may be degraded and the pattern accuracy may be degraded due to the existence of the gap 20 under the exposure mask 21.

As a solution to this phenomenon, (1) change the optical system of the exposure device, (2) improve the bleaching property of the resist,
(3) Optimization of resist pre-baking conditions, and (4) Multi-step exposure. As one specific example of the change of the optical system of the exposure machine, the NA value is 0.0001 or more and 0.2.
One of the measures is to use the following exposure machine. The resolution and accuracy of the pattern can be improved not only by the examples given here but also by appropriately combining known and commonly used process ideas.

Since the edge portion of the stress relaxation layer 5 has a structural feature in which stress caused by the difference in the physical property values of the wafer and the stress relaxation layer 5 is likely to concentrate, the wiring should be thick at the sloped portion of the stress relaxation layer 5. Therefore, the disconnection can be effectively prevented. Note that it is not always necessary that all wirings have the same thickness. For example, as shown in FIG. 16, the wiring width may be changed between the power / ground line and the signal line. In this case, it is generally desirable to make the power / ground line thicker than the signal line in consideration of electrical characteristics. This is because when the signal line is thickened, the capacitance component of the wiring increases due to this, and this has an effect on high-speed operation. Power source /
It is rather preferable to make the ground wire thicker, because the effect of stabilizing the power supply voltage can be expected. Therefore, as shown in the figure, the signal wiring should have a thick pattern around the edge so that only the stress concentration part can be relaxed at least, and the power supply or ground wiring should have a thicker slope. Is desirable. On the other hand, in the flat portion where the stress relaxation layer is not formed, the signal wiring is thinned in consideration of the influence of the capacitance component of the wiring. However, this must be taken into consideration each time depending on the type of semiconductor element and its wiring pattern. For example, although it depends on the semiconductor element and its wiring pattern, increasing the thickness of the protective film 8 has a great effect on reducing the capacitance of the wiring. Therefore, the signal wiring must be thickened in the flat portion where the stress relaxation layer is not formed. If not obtained, it is desirable to form the protective film 8 thick.
Specifically, when the wiring width is increased by 10%, it is desirable that the thickness of the protective film 8 is also increased by about 10%.
On the other hand, the wiring width in the upper flat portion of the stress relaxation layer is limited by the wiring density rather than the signal line capacitance. That is, the upper limit value of the wiring width in the upper flat portion of the stress relaxation layer is obtained from the number of wirings passing through the space between the bump pads, the diameter of the bump pads, the positioning accuracy in the wiring forming process, and the like. As an example, the bump pad spacing is 0.5.
When the pad diameter is 300 micrometers and three wires are connected between the pads in millimeters, (500-300) /
The calculation is (3 × 2-1) = 40. From this calculation result, in this embodiment, the average wiring width / wiring interval = 40 micrometers.

The fifth step will be described. In this example, copper plating was performed using a sulfuric acid acidic copper plating solution. Electrolytic copper plating was performed by cleaning with a surfactant, water, cleaning with dilute sulfuric acid, and water, then connecting the power supply film 16 to the cathode and connecting a copper plate containing phosphorus to the anode.

Subsequently, electric nickel plating is performed. Before electroplating with nickel, cleaning with a surfactant,
Washing with water, washing with dilute sulfuric acid, and washing with water tend to make it easy to obtain an electro-nickel plated film having good film quality. The electroless nickel plating was performed by connecting the power supply film 16 to the cathode and connecting the nickel plate to the anode. The electro-nickel plating suitable in this example can be used in any known and commonly used nickel plating bath, and may be a Watt bath system or a sulfamine bath system, but in this Example, a Watt bath system is used and the plating film internal stress is Was adjusted under the plating conditions adjusted so as to be in an appropriate range. The sulfamine bath has the drawback that the plating solution component is more expensive than the Watts bath and that it tends to decompose a little, but the film stress is easy to control. On the other hand, since the Watts bath generally tends to have a large film stress, there is a drawback in that, when a thick film is plated, the risk of cracks in the wiring layer increases due to the film stress (tensile stress) of the Wat bath. Although the Watt bath was used in this example, whether the sulfamine bath or the Watt bath is used,
It is advisable to carry out a model experiment in advance to obtain the appropriate range of the type and concentration of the additive (film stress suppressor), the plating current density, and the plating solution temperature. In the present example, these were properly controlled to obtain the conditions under which the wiring did not crack when the film thickness was 10 μm or less, and then carried out. The plating film stress is one of the indexes related to the metal crystal orientation of the deposited nickel, and it is necessary to appropriately control it in order to suppress the growth of the solder diffusion layer described later. When plating is performed under the condition that the film stress is properly controlled, the plating film comes to co-deposit a specific amount of trace components. For example, in the case of a film containing 0.001 to 0.05% of sulfur, the content of a specific crystal orientation plane is increased. More specifically, the orientation planes 111, 220, 200, 3
The total content of 11 and 50 is 50% or more. The thickness of electro nickel plating depends on the type of solder used in the subsequent steps, reflow conditions, and product characteristics of semiconductor devices (mounting form).
To determine the optimum value. Specifically, the thickness of the alloy layer of solder and nickel formed during solder reflow or mounting repair may be determined to be equal to or greater than the nickel plating thickness. The thickness of the alloy layer increases as the tin concentration in the solder increases, and increases as the reflow upper limit temperature increases. Thus, when a nickel layer is formed on the copper wiring as the rewiring wiring, the rewiring wiring is deformed by the thermal stress acting between the semiconductor device and the circuit board, and when the stress is released thereafter. The rewiring wiring can return to its original shape due to the springiness of the nickel layer. For example, due to the action of thermal stress caused by the operation of the semiconductor device, the stress relaxation layer and the rewiring wiring 4 formed thereon are deformed in close contact with each other. At this time, for the deformation of the redistribution wiring, the flexure portion of the redundant portion of the redistribution wiring in the bulge portion of the stress relaxation layer is used. After that, when the stress relaxation layer returns to its original shape after being released from thermal stress, when the rewiring wiring is only copper wiring, the copper wiring is difficult to return to the original wiring shape due to the springiness of the copper wiring itself. . On the other hand, when a nickel layer is formed on the copper wiring,
Rewiring wiring (copper wiring) due to the springiness of the nickel layer
Can easily return to its original shape. It should be noted that what is formed on the copper wiring is not limited to the nickel layer, but may be one having the same spring property as the nickel layer on the copper wiring. Further, the nickel layer is not always necessary when forming a stretchable wiring instead of the copper wiring.

In the sixth step, after the copper electroplating and the nickel electroplating are performed, the resist 17 which is the reverse pattern of the wiring is removed, and an etching process is performed to remove the power supply film 16 previously formed. For copper etching,
Although there are types such as iron chloride and alkaline etching solutions, in this embodiment, an etching solution containing sulfuric acid / hydrogen peroxide as a main component was used. Control is difficult if the etching time is 10 seconds or more, which is disadvantageous from a practical point of view. However, if etching is performed for a too long time, for example, when etching is performed for more than 5 minutes, side etching becomes large. The etching solution and the etching conditions should be appropriately determined by an experiment, because the problem that the tact becomes long or the tact becomes long occurs. For the subsequent etching of the chromium portion of the power supply film 16, an etching solution containing potassium permanganate and metasilicic acid as main components was used in this example. The electric nickel plating film is the power supply film 16
It also functions as an etching resist during etching. Therefore, the compositional components of the etching solution and the etching conditions may be determined in consideration of the etching selection ratios of nickel and copper and nickel and chromium. For example, specifically, in the sulfuric acid / hydrogen peroxide etchant used for etching copper, the sulfuric acid content is 50% or less at the maximum, and preferably 15% or less. As a result, copper can be etched with an etching selection ratio about 10 times that of nickel.

In the seventh step, the bump pad 3, the cut portion 24, and the surface protective film 6 having an opening only around the cut portion 24 are formed, and then electroless gold plating is performed to deposit gold on the bump pad portion 3. . Here, a solder resist is used as the surface protection film 6, and a pattern is formed by applying this to the entire surface of the semiconductor device 13 and then exposing and developing it. In addition to the solder resist, the surface protective film 6 can be formed using a material such as photosensitive polyimide or printing polyimide. Through the steps described above, the surface protection film 6 completely covers the rewiring wiring 4, the stress relaxation layer 5, the protection film 8, and the like. Therefore, the surface protection film 6 includes the redistribution wiring 4, the stress relaxation layer 5,
It is possible to prevent the protective film 8 from being deteriorated, peeled off, or corroded by the stimulating substance.

By the seventh step, the rewiring wiring 4 from the aluminum pad 7 to the bump pad 3 and the bump pad 3 are formed on the wafer 9 on which the semiconductor is formed, as shown in FIGS. 17 and 2. .

In the eighth step, bumps are formed using a solder ball mounting device and a reflow furnace. That is, a predetermined amount of flux and solder balls are mounted on the bump pads 3 by using the solder ball mounting device. On this occasion,
The solder balls are temporarily fixed on the bump pads by the adhesive force of the flux. When the semiconductor wafer on which the solder balls are mounted is put into a reflow furnace, the solder balls are once melted and then solidified again to form the bumps 1 connected to the bump pads 3 shown in FIG. In addition to this, there is also a method of forming the bumps 1 by printing and applying a solder paste on the bump pads 3 using a printing machine and reflowing the solder paste. With either method, various solder materials can be selected, and most of the solder materials currently on the market can be used.
In addition, although the solder material is limited, there is also a method of forming the bump 1 by using a plating technique. Also,
A bump using a ball having gold or copper as a core or a bump formed using a resin mixed with a conductive material may be used.

By performing the steps from the first step to the ninth step, the rewiring wiring 4 having the stress relaxation layer 5 shown in FIG. 1 is formed in a small number of steps, and the rewiring wiring 4 is formed. It is possible to realize the semiconductor device 13 in which there is no bent portion where stress is concentrated in the middle of 4. Further, by using the printing technique, it is possible to form a pattern of the stress relieving layer 5 which is a thick insulating layer without using an exposure or development technique, and the stress relieving layer 5 forms the rewiring wiring 4. Can have a slope for

According to this embodiment, the connection reliability of the semiconductor device 13 is significantly improved even when the semiconductor device 13 is flip-chip connected without underfilling. Therefore, according to this embodiment, it is possible to perform flip-chip connection without using underfill in many electric products, and it is possible to reduce the price of various electric products. Furthermore, since the underfill is not performed, the semiconductor device 13 can be removed. That is, when the semiconductor device 13 connected to the circuit board is defective, it is possible to remove the semiconductor device 13 from the circuit board and regenerate the circuit board, which also reduces the price of various electric products. It will be possible.

Next, the material of the stress relaxation layer 5 according to this embodiment will be described. The material most preferably used in this embodiment for forming the stress relaxation layer 5 is a paste-like polyimide, but not limited to this, a modified amide imide resin, an ester imide resin, an ether imide resin, a polyester resin, a modified silicone resin, Modified acrylic resin may be used. Among the resins listed above, resins having an imide bond, such as polyimide, amide imide, ester imide, and ether imide, have excellent thermomechanical properties, such as strength at high temperature, due to the strong skeleton by the imide bond, As a result, the choice of plating power supply film forming method for wiring is expanded. For example, it is possible to select a plating power supply film forming method involving high-temperature processing such as sputtering. In the case of a resin having a portion condensed by a bond other than an imide bond, such as a silicone resin, an acrylic resin, a polyester resin, an amide imide, an ester imide, or an ether imide, the thermo-mechanical property is slightly inferior, but it is advantageous in terms of processability and resin price. There are cases. For example, a polyesterimide resin is generally easier to handle because it has a lower curing temperature than polyimide.
In this embodiment, among these resins, the device characteristics, price,
These resins are properly used in consideration of thermo-mechanical properties and the like. As a material for forming the stress relaxation layer 5, for example, a resin such as epoxy, phenol, polyimide, or silicone is used alone or in combination of two or more, and a coupling agent or a coloring agent for improving the adhesiveness to various interfaces is added thereto. It is possible to mix and use.

The elastic modulus of the stress relaxation layer 5 may be about 0.1 to 10.0 GPa at room temperature, but a lower elastic modulus than that of general polyimide is desirable. If the elastic modulus is less than 0.1 GPa and is too small, the wiring portion is likely to be deformed during the formation of a projection electrode described later or the functional test of the semiconductor device, which may cause a problem such as disconnection. Further, if the elastic modulus of the stress relaxation layer 5 exceeds 10.0 G and becomes large, a sufficient stress reducing effect cannot be obtained,
There is a concern that the connection reliability when the semiconductor device is mounted on a substrate is reduced.

Further, it is desirable to use a material for the stress relaxation layer 5 having a curing temperature of 100 ° C. to 250 ° C. If the curing temperature is lower than this, it is difficult to control in the process during semiconductor manufacturing, and if the curing temperature is higher than this, there is a concern that the wafer stress will increase due to heat shrinkage during cooling for curing, or the characteristics of the semiconductor element will change. Because there is. Since the stress relaxation layer after curing is exposed to various processes such as sputtering, plating, and etching, heat resistance, chemical resistance,
Properties such as solvent resistance are also required. Specifically, the glass transition temperature (Tg) of the heat resistance is preferably more than 150 ° C and 400 ° C or less, more preferably Tg of 180 ° C.
As described above, the Tg is most preferably 200 ° C. or higher. Figure 41
Are experimental results showing the relationship between the glass transition temperature (Tg) and the coefficient of linear expansion. From this, it can be seen that if the glass transition temperature (Tg) is 200 ° C. or higher, no crack is generated. From the viewpoint of suppressing the amount of deformation in various temperature treatments during the process, the smaller the linear expansion coefficient (α1) in the region of Tg or less, the better. Specifically, the closer to 3 ppm, the better. In general, a low elastic material often has a large linear expansion coefficient, but the range of the linear expansion coefficient of the material of the stress relaxation layer 5 suitable in this embodiment is preferably in the range of 3 ppm to 300 ppm. The range of 3 ppm to 200 ppm is more preferable, and the most desirable linear expansion coefficient is 3 ppm to 150 pp.
The range is m. On the other hand, the thermal decomposition temperature (Td) is about 300 ℃
The above is desirable. If Tg and Td are below these values, there is a risk that the resin may be deformed, deteriorated, or decomposed in a heat step in the process, for example, a sputter or a sputter etch step. From the viewpoint of chemical resistance, it is desirable that resin deterioration such as discoloration or deformation does not occur by immersion in a 30% sulfuric acid aqueous solution or a 10% sodium hydroxide aqueous solution for 24 hours or more. Solvent resistance includes solubility parameter (S
It is desirable that the P value) be 8 to 20 (cal / cm3) 1/2.
When the material for the stress relaxation layer 5 is a material obtained by modifying a base resin with some components, it is desirable that most of the composition thereof falls within the above-mentioned solubility parameter range.
More specifically, the solubility parameter (SP value) is 8
It is desirable that the content of less than or more than 20 is not contained in more than 50% by weight. Insufficient chemical resistance and solvent resistance may limit the applicable manufacturing process, and may be unfavorable from the viewpoint of manufacturing cost reduction. In reality, it is preferable to determine the material for the stress relaxation layer 5 after comprehensively considering the material cost and the process flexibility that satisfy these characteristics.

Next, the relationship between the film thickness of the stress relaxation layer and the wafer stress and α ray will be described. FIG. 18 shows the relationship between the film thickness of the stress relaxation layer and the wafer stress.
As shown in FIG. 18, when the stress relaxation layer is applied and cured on a wafer having a diameter of 8 inches, when the film thickness becomes thicker than 150 μm, the wafer stress becomes large and the warp of the wafer becomes large. crack,
Peeling of the insulating film is likely to occur.

On the other hand, FIG. 19 shows the relationship between the thickness of the stress relaxation layer and the α dose transmitted through the stress relaxation layer. α rays are generated by the decay of uranium, thorium, etc. contained as impurities in the solder used for semiconductor devices,
It causes the malfunction of the transistor part. As shown in FIG. 19, when the thickness of the stress relaxation layer is thicker than 35 μm, α rays hardly penetrate, and the problem of malfunction due to α rays does not occur. On the contrary, when the thickness of the stress relaxation layer is thinner than 35 μm, α-rays are transmitted, so that malfunction due to α-rays easily occurs.

From these relationships, the thickness of the stress relaxation layer should be 3
To prevent α rays from reaching the circuit portion formed on the surface of the semiconductor element and to secure the connection reliability between the semiconductor device and the substrate on which the semiconductor device is mounted by setting the distance to 5 μm or more and 150 μm or less. You can
Depending on the configuration of the semiconductor device, there are a part that is easily affected by α-rays, for example, a memory cell 110 that is easily affected by a transistor malfunction and a part that is not easily affected by α-rays in the same element. Therefore, as shown in FIGS. 20 and 21, the stress relaxation layer is formed on the surface of the semiconductor element by setting the thickness of the stress relaxation layer to 35 μm or more and 150 μm or less for a portion that is particularly susceptible to α rays. It is possible to prevent the α ray from reaching the circuit portion. It should be noted that there is no problem from the viewpoint of α-ray shielding even if the thickness of the stress relaxation layer formed in the region less susceptible to α-rays is less than 35 μm. Therefore, for example, as shown in FIG. 21, the stress relaxation layer is formed thick in a region where α-ray shielding is required, and the stress relaxation layer is formed thin in other regions, and the average thickness of the entire stress relaxation layer is 35 μm or more. It can be 150 micrometers or less. When such a measure is taken, it is desirable that the semiconductor device be configured in consideration of the magnitude of thermal stress strain applied to each bump. In general, a thicker stress relaxation layer is more likely to be subjected to thermal stress strain as it goes to the outer periphery of the semiconductor device 13. Therefore, a transistor region that is easily affected by α rays is arranged on the outer periphery of the semiconductor device 13 and On the other hand, it is preferable that the region that is not easily affected is arranged near the center of the semiconductor device 13. For example, as shown in FIG. 38, the stress relaxation layer 5 may be thin near the center of the semiconductor device 13 and gradually thicker toward the outer periphery. In this case, the bump near the center has a larger connection height and a smaller connection angle than the other bumps, so that the stress relaxation function of the bump itself is increased and the stress relaxation function of the thinned stress relaxation layer 5 is increased. Has been replaced. In the case of the semiconductor device 13 having a region that is not affected by α rays at all, if the region that is not influenced by α rays is arranged near the center of the semiconductor device 13 as shown in FIG.
It is not necessary to form the stress relaxation layer 5 near the center of. Next, as another example, an example of a stress relaxation layer including fine particles having a composition different from that of the stress relaxation layer will be described.

The fine particles contained in the stress relaxation layer 5 described above are made of the same material as the stress relaxation layer 5 and have the same physical properties. By virtue of the fine particles dispersed in the stress relaxation layer, it is possible to have the viscoelastic properties required for printing.

However, in this structure, since the physical property values change abruptly at the boundary between the wafer and the stress relaxation layer 5, there is a possibility that thermal stress or the like concentrates on the boundary and the wiring is broken.

Therefore, in this embodiment, the characteristics of the stress relaxation layer 5 formed on the circuit formation surface of the wafer are made different in the thickness direction so that the characteristics of the stress relaxation layer on the front surface side of the wafer become close to the characteristics of the wafer. I chose

As a result, the difference in characteristics at the boundary between the upper surface of the wafer and the lower surface of the stress relaxation layer is reduced, and the discontinuity of the wiring provided on these and the tension, compression, and bending due to the expansion and contraction of the stress relaxation layer. It is possible to prevent disconnection of the wiring portion by preventing the stress of 1 from being applied to the wiring portion.

Further, the characteristics of the stress relaxation layer 5 on the wafer side are close to those of the wafer, and the characteristics of the substrate on which the semiconductor device is mounted are close to the characteristics of the substrate. It is also effective in improving the connection life of the connection part between the device and the substrate.

Here, the coefficient of thermal expansion or elastic modulus may be considered as a characteristic that gradually changes in the thickness direction of the stress relaxation layer 5. Then, as a specific means for changing the characteristics of the stress relaxation layer, as shown in FIG. 22, silica particles 102 that are insulating particles are mixed, and the silica particles 102 are mixed in the thickness direction of the stress relaxation layer 5. The coefficient of thermal expansion and elastic modulus are gradually changed by providing a quantity distribution. In a portion where a large amount of silica particles 102 are distributed, the coefficient of thermal expansion of the stress relaxation layer 5 is small and the elastic modulus is high. On the other hand, when the blending amount of the silica particles 102 decreases, the coefficient of thermal expansion increases and the elastic modulus decreases.

Also in the manufacturing process of the semiconductor device of this embodiment, the circuit formation on the wafer, the stress relaxation layer formation, the distribution of silica particles, the wiring formation on the stress relaxation layer, etc. are performed in the wafer state, thereby simplifying the whole process. It is possible to improve the life of the wiring part with less variation in manufacturing and manufacturing.

In this example, one type or two or more types of particles made of an inorganic material such as silica, alumina, and boron nitride, which are insulating particles for adjusting the elastic modulus and thermal expansion, are mixed in the stress relaxation layer 5, If necessary, particles made of an organic material such as polyimide or silicone may be appropriately mixed.

Further, in order to improve the adhesiveness with silica particles or various interfaces constituting the insulating resin layer, a coupling agent made of alkoxysilane, titanate or the like, or a thermoplastic resin or the like for improving the elongation at break or the breaking strength of the resin is improved. Compounding agents such as dyes and pigments for coloring the insulating resin layer to prevent malfunction of the circuit part formed on the wafer due to ultraviolet rays, etc., and curing accelerators for promoting the curing reaction of the resin layer, etc. Is also possible.

Stress relaxation layer 5 whose characteristics are changed in the thickness direction
As a method of forming the above, for example, a liquid stress relaxation layer 5 containing the above-mentioned materials is applied on the circuit surface of the wafer, and the stress relaxation layer 5 is heated and hardened. There is a method in which the insulating particles are gradually settled on the wafer side. If there is a distribution in the particle size of the silica particles,
The larger the particle size, the faster the settling, and the smaller the particle size, the harder the settling. When the stress relaxation layer is heat-cured with the wafer facing down, a distribution of characteristics is formed in the thickness direction of the stress relaxation layer. ..

As a method of controlling the concentration distribution of the silica particles blended in the stress relaxation layer 5 in the film thickness direction, the curing temperature and curing temperature profile of the insulating resin may be appropriately adjusted,
Compounding amount and type of curing accelerator to accelerate the progress of curing,
Alternatively, there is a method of appropriately blending a reaction inhibitor or the like for delaying curing, and a method of changing the particle size distribution of insulating particles such as silica particles.

The silica particles applicable to the present embodiment are those obtained by crushing fused and ingot-formed silica lumps, crushing the silica ingot, and then again heating and melting the silica particles to make them spherical, and further synthesized. Silica particles and the like are applicable. The particle size distribution and blending amount of the silica particles depend on the size, the thickness, the degree of integration, the thickness of the stress relaxation layer 5, the particle size of the particles and the type of the substrate to which the structure of this embodiment is applied. Various changes are possible.

When the stress relaxation layer 5 is formed by the printing method, depending on the printing method, it may be necessary to change the particle size distribution depending on the size of the mask to be applied.

The stress relaxation layer 5 need not be formed by printing once, but may be formed by printing at least twice as shown in FIG. Further, printing may be performed by changing the compounding amount of silica particles contained in each layer.

In this embodiment, since the physical properties of the portion where the wiring is formed do not change rapidly at the stage from the circuit portion of the wafer to the electrode provided on the stress relaxation layer, a large force is concentrated on a portion of the wiring. It is possible to prevent disconnection of the wiring.

Next, an example of an embodiment of the semiconductor device 13 in which the film thickness of the stress relaxation layer 5 immediately below the bump 1 existing near the periphery of the semiconductor device 13 is made thinner than that of other portions will be described with reference to FIG. . In this embodiment, the outermost bump 1a is
The height is lower by δ than the bump 1b on the inside.

As a method of reducing the film thickness of the stress relaxation layer 5 in the peripheral portion of the semiconductor device 13, the presence or absence of fine particles contained in the stress relaxation layer forming material such as a paste-like polyimide material, the shape and mixing of the particles. The printing speed, the plate separation speed, the printing conditions such as the number of times of printing, and the ratio of the solvent in the paste can be changed.

Generally, the bump 1a existing near the periphery of the semiconductor device 13 has a larger distortion than the other bumps 1b due to various loads after the semiconductor device 13 is connected to the circuit board 14. For example, since the semiconductor device 13 and the circuit board 14 have different linear expansion coefficients, when the temperature rises, the bumps 1a near the periphery of the semiconductor device 13 are more distorted. If this strain is large or if it repeatedly acts, the bump 1 from the periphery of the semiconductor device 13
a is easy to destroy.

When the thickness of the stress relaxation layer 5 is reduced near the periphery of the semiconductor device 13 as in the present embodiment, it becomes possible to control the shape of the bump 1 at the corresponding portion, and the bump 1 is connected to the circuit board 14. At this time, the bump 1 becomes a vertically long bump 1aa as shown in FIG. Since the volume of the vertical bump 1aa is the same as that of the other bumps 1, the contact angle between the bump 1 and the bump pad 3 and the contact angle between the bump 1 and the pad on the circuit board 14 are large. That is, in FIG. 25, α1> α2, β1> β
It becomes 2.

By increasing the contact angle, the stress concentration on the connecting portion between the bump and the pad is alleviated. In this way, the film thickness of the stress relaxation layer 5 is made thinner in the peripheral portion of the semiconductor device 13 where the bump pads 3 are formed than in the other portions, and the bumps 1 are formed to be vertically long. The connection reliability of can be improved. The cross-sectional shape of the stress relaxation layer 5 can be designed within the range in which the height of the bump 1 does not hinder the connection of the semiconductor device 13 to the circuit board 14.
Various things are possible.

The magnitude of δ is (1) the stress relaxation characteristics required for the vertically elongated bumps 1aa located at the outermost periphery, (2) the tolerance value of the bump height variation during the functional inspection of the semiconductor device 13, and (3) the semiconductor. It is determined in consideration of a bump height variation allowable value when the device 13 is connected to the circuit board 14, and the like. More specifically, the stress relaxation characteristic is obtained from the elastic modulus of the stress relaxation layer 5 and the size of the semiconductor device 13. On the other hand, regarding the variation at the time of function inspection and connection,
The allowable values of the solder balls and the stress relaxation layer 5 are calculated in consideration of their deformations. For example, in the function inspection, if the inspection jig is pressed from the top surface of the bump to deform the stress relaxation layer 5, it is possible to perform the function inspection in the state where there is substantially no bump height variation. Even if such an operation is performed, since the stress relaxation layer 5 has a considerably lower elastic modulus than the solder bump material, the deformation of the stress relaxation layer 5 takes priority over the deformation of the solder bump, and the solder bump is deformed. It will not be scratched. Therefore, even if the value of δ required from the stress relaxation characteristic becomes larger than the bump height variation required in the function inspection device, it may be within a range that can be dealt with by the deformation of the stress relaxation layer 5. . Further, since the stress relaxation material is an elastic body, its shape is restored after the inspection is completed, so that there is no particular problem when connecting to the substrate. Taking this into consideration, δ is effectively determined from the above (1) and (3). As described above, the stress relaxation characteristic is that the film thickness of the stress relaxation layer 5 is 35
Since a good result can be obtained in the range of ˜150 μm, δ = 150−35 = 115 μm from the stress relaxation characteristic. Further, the value of δ = 115 μm is substantially equal to the upper limit value allowed when connecting to the circuit board 14. Therefore, the value of δ is the upper limit in many cases of 115 μm.

Further, the structure of this embodiment can be applied to the case where the miniaturization of the semiconductor device is advanced and the bumps must be formed on the inclined portions of the stress relaxation layer due to the wiring of the semiconductor device. In FIG. 24, the thickness of the stress relaxation layer 5 is controlled in order to make the heights of the outermost bump 1a and the bump 1b one inside thereof different, but as another control method, the protective layer 8 may be used. There is also a method by adjusting the structure of. For example,
As shown in FIG. 40, the organic layer of the protective film 8 is not formed just under the outermost peripheral bump 1a, or is formed very thin, and the organic layer of the protective film 8 is formed thicker inside the bump 1b. There is a method. There is no problem in achieving the desired height difference δ by appropriately adjusting and controlling the thickness of the stress relaxation layer 5 and the organic layer thickness of the protective layer 8 as necessary.

Further, an external force is easily applied to the bumps located on the outermost periphery of the semiconductor device, which may cause cracks or the like in the solder. Therefore, some of the bumps located on the outermost periphery may be used as a cushioning member. . In this case, it is preferable that the bumps used as the cushioning members are not electrically connected to the aluminum pads 7 and are unnecessary for the electrical operation of the semiconductor device. As a result, it is possible to extend the period until breakage occurs in other bumps necessary for electrically operating the semiconductor device. For some bumps used as cushioning members, it is possible to further extend the time until the bump breaks by increasing the bump diameter. In the present embodiment, any known method may be used to increase the suitable bump diameter,
One particularly suitable method is to increase the bump land (pad) while keeping the solder volume itself the same as the other bumps. The larger the pad, the larger the connection diameter, while the volume of solder is the same as the others, which lowers the bump height.
When connected to the circuit board 14, the contact angle between the bump and the pad is increased, so that stress concentration at the contact point between the bump and the pad can be avoided. As the crack concentration in the solder slows down due to the lack of stress concentration, and the absolute value of the crack length up to fracture also increases due to the increase in the bump diameter, extending the period until bump fracture. Greatly contribute to.

Further, from the viewpoint of facilitating the design of the wiring lead-out of the circuit board for connecting the semiconductor device, it is desirable to dispose the power supply or ground line near the center of the semiconductor device. As a result, FIG. (A)
As shown in (b), the rewiring wiring 4 for connecting the aluminum pad 7 and the bump pad close to the aluminum pad is a signal line, and the rewiring wiring 4 for connecting the distant bump pad is a power supply or ground wire. It is desirable to use. In this case, the bump that is close to the aluminum pad may be located on the inclined portion of the stress relaxation layer 5. In addition, the power supply line or the ground line may be wider than the signal line.

Another embodiment of the semiconductor device is shown in FIG.
In this embodiment, the stress relaxation layer 5 is formed so as to extend over the adjacent semiconductor device 13 on the wafer 9 on which the semiconductor is formed. The aluminum pad 7, the bump pad 3, and the rewiring wiring 4 connecting these are designed so that the rewiring wiring 4 does not cross the boundary between the semiconductor device 13 and the adjacent semiconductor device 13. Has been done. The manufacturing process is basically the same as that described above, but there are differences after the seventh process.

When the semiconductor wafer is cut, it is necessary to cut the stress relaxation layer 5, but since the stress relaxation layer 5 is a low elastic material, a semiconductor which is mostly made of silicon and has different strength is formed. It is difficult to cut together with the wafer 9. Therefore, after the stress relaxation layer 5 is cut, the wafer 9 having the semiconductor formed thereon is diced. Hereinafter, description will be made with reference to FIG.

First, only the stress relaxation layer 5 is cut in the seventh improvement step. As a cutting method, it is preferable to use a rotary blade suitable for cutting the low elastic resin material. In addition to this, a carbon dioxide gas laser or sandblast can be used.

In the eighth improving step, a solder resist is applied to the entire surface as the surface protective film 6. As a coating method, printing using a mesh mask or curtain coating may be used in addition to the spin coating method. Also in order to apply the solder resist, it is desirable that the wall surface of the cut portion of the stress relaxation layer 5 in the seventh improvement step is not vertical but has an inverted V shape. By performing this coating after cutting the stress relaxation layer in the seventh improvement step, the stress relaxation layer 5 becomes a factor for peeling from the surface of the wafer 9 on which the semiconductor is formed, ions such as those causing deterioration of the performance of the semiconductor, etc. It is possible to provide a device that can reduce the intrusion of foreign matter and ensure durability and the like.

In the ninth improving step, the pattern of the surface protective film 6 is formed by carrying out photosensitive development. As a result, only the bump pad 3, the cut portion 24, and the periphery thereof are exposed from the surface protective film 6. Further, electroless gold plating is performed using the surface protective film 6 as a mask to deposit gold on the bump pads 3. In the examples, only gold plating is used, but palladium or platinum may be plated before gold plating, or tin plating may be performed after the gold plating is completed without any particular problem.

In the tenth improving step, the wafer 9 on which the semiconductor is formed by dicing is divided into the semiconductor devices 13. Note that dicing is generally performed using a rotary blade.

Through the above steps, the semiconductor device 13 including the step of cutting the stress relaxation layer 5 can be manufactured.

According to this embodiment, the stress relaxation layer 5 can be formed without any problem even when the semiconductor device 13 has a small outer dimension. Specifically, when the stress relaxation layer 5 is formed over two adjacent semiconductor devices, it is not necessary to change the film formation technique of the stress relaxation layer 5 even if the outer dimension is almost halved. Is manufactured by using the same print mask even if the size of the semiconductor device is changed by adjusting the shape and outer dimensions of the semiconductor device and the width and shape of the cut portion 24 that serves as a cutting margin when the semiconductor device 13 is separated from each other. In some cases, it is possible. Further, since the rewiring wiring 4 connects the aluminum pad 7 and the bump pad 3 through the inclined portion of the stress relaxation layer 5 as in the first embodiment, the rewiring wiring 4 also has a stress concentration portion. Flip-chip connections that do not exist and do not require underfill are possible.

The structure according to the present embodiment is particularly applicable to a semiconductor device having a pad laid out in the center portion of the semiconductor device, such as a DRAM.

Further, in the drawings of this embodiment, the stress relaxation layer 5 extending over the two adjacent semiconductor devices 13 is cut, but the slope for the redistribution wiring 4 to reach from the aluminum pad 7 to the bump pad 3 is formed. It is also possible to adopt a structure in which at least two or more semiconductor devices 13, for example, four stress-relieving layers 5 adjacent to each other are cut so that the stress relaxation layers 5 are cut as long as the portions exist. As a matter of course, the stress relaxation layer 5 may be formed by connecting the adjacent two rows and cut. In this case, since the manufacturing method allows positional deviation in the column direction, it can be applied to finer processing.

In each embodiment, for example, FIG.
As shown in, the corner portions of the stress relaxation layer 5 may be rounded. In the case of not rounding, defects in which air bubbles are entrapped are sometimes observed when the stress relaxation layer 5 is printed using a paste-like polyimide material. Moreover, the stress relaxation layer 5 is easily peeled from the corners. If air bubbles remain in the stress relaxation layer 5, the air bubbles will rupture when the semiconductor device 13 is heated and the rewiring wiring 4 will be broken. Therefore, it is desirable to round the corners of the pattern opening 18 of the printing metal mask used for forming the stress relaxation layer 5.

The stress relaxation layer 5 in each embodiment can be formed by printing and applying using a printing metal mask or a dispenser.

Further, not only the printing method, but also stamping, spraying using air or an inert gas, an ink jet method, attaching an uncured or semi-cured resin sheet, or any of these methods is appropriately used. It can be formed by combining them. When the stress relaxation layer is formed by the printing method, the inclination of the end portion of the printed portion is caused by the flow of the insulating layer at the end portion when the insulating material is printed and the print mask is removed, or during the heat curing process. It is formed. According to this method, it is possible to collectively form the stress relaxation layer and the end portion having the specific inclination for each wafer. On the other hand, when the stress relaxation layer is formed by stamping, the stress relaxation insulating material is applied to the stamping die and the shape of the stress relaxation layer is transferred onto the wafer, so that the shape of the end portion changes when the insulating material cures. It is possible to select a non-insulating material. In this case, the shape of the end portion is more likely to be constant than in the printing method. Further, in the method of spraying the insulating material using gas or the like, since a printing mask or a stamping die is not used, there is a degree of freedom in the shape when the stress relaxation layer is formed. It is possible to form a stress relaxation layer that is difficult to form with a mold. Further, as compared with the printing method and the stamping method, the thickness of the stress relaxation layer can be adjusted by adjusting the amount of spraying, and the range of the thickness adjustment becomes wider. The method of attaching a semi-cured or uncured resin sheet has a feature that a thick film stress relaxation layer can be formed and a sheet-shaped insulating resin is used in advance, so that the surface of the stress relaxation layer is excellent in flatness. It is possible to obtain a desired stress relaxation layer thickness and end inclination by combining these methods singly or as appropriate.

Next, another embodiment of the semiconductor device will be described. Figure 2
9 is a schematic cross-sectional view showing a state in which the semiconductor device is mounted on a substrate for converting the protruding electrodes, and FIG. It is a figure.

The projecting electrodes 1 formed on the semiconductor device 13 are mounted on the corresponding electrodes 120 on the substrate through a solder paste or flux, and the projecting electrodes are melted by a reflow furnace or the like to form the substrate 115 and the semiconductor. The device 13 is connected. The substrate on which the semiconductor device is mounted is an electrode 120 for mounting on a substrate used for various electronic devices on the back surface of the semiconductor element mounting surface and, if necessary, the protruding electrode 12
Has 1.

When the semiconductor device 13 is mounted on a substrate used in various electronic devices, it is necessary to heat and melt the protruding electrodes 121 provided on the substrate 115. In order to further improve the reliability of the mounting process and various tests, particularly the reliability of the drop impact test, the semiconductor device 1
3 and the substrate 115 are reinforced with a resin 118.

As the resin 118 filling the space between the semiconductor device 13 and the substrate 115, liquid epoxy resin, phenol resin, polyimide resin, silicone resin or the like used for general semiconductor encapsulation can be used. In order to adjust the coefficient of thermal expansion or elastic modulus of silica, one kind or two or more kinds of particles made of an inorganic material such as silica, alumina and boron nitride are mixed, and if necessary, resin such as silicone or thermoplastic resin, alkoxysilane or It is possible to add a coupling agent such as titanate, a colorant, a flame retardant for imparting flame retardancy, or a curing accelerator for promoting the curing reaction of the flame retardant aid resin layer.

In the present embodiment, even if the pitch of the projecting electrodes on the semiconductor device and the pitch of the electrodes of the substrate used in various electronic devices are different, various electronic devices can be used by interposing a predetermined substrate. It is possible to connect.

The same applies to the case of mounting on a circuit board used for general electronic equipment as in the case of mounting on a board to be a semiconductor device.

In the embodiments described so far, if necessary, for example, a low elastic material is used for the insulating layer of the semiconductor device, and an insulating layer having a thickness of 35 μm or more is formed, so that the connecting portion is formed. Can be prevented from being destroyed.
Further, the presence of the low-elasticity insulating layer makes it possible to significantly reduce the stress generated in the connection portion. For this reason,
The connection life of the semiconductor device is significantly improved.

When a thick insulating layer having a thickness of about 35 μm or more is adopted, the conventional wiring forming method cannot be applied. When a thick insulating layer is formed, since the material for forming the insulating layer has a high viscosity, the spin coating method results in an insulating layer containing bubbles, and thus does not function as an insulating layer. Even if a new thick film forming method is developed separately from this, the light transmittance decreases at a film thickness of 35 μm, so that the openings and the like of the insulating layer cannot be formed with high accuracy by exposure and development. . Even if this problem can be solved, the side wall of the opening of the insulating layer is almost vertical at about 80 degrees or more, and the height thereof is much larger than the wiring thickness, so that the metal wiring is formed on the side wall. It becomes difficult to be done. Even if it can be formed, since the bent portion of the metal wiring is formed at the boundary between the side wall and the upper layer, stress is likely to be concentrated at this location, and thus cracks are likely to propagate. Therefore, the connection life when connecting the circuit boards is shortened.

Therefore, it is preferable to form a thick film insulating layer by mask printing an insulating material containing fine particles as described above, and to make the shape of the opening of the insulating layer a gentle slope. As a result, the wiring on the insulating layer can be formed by the conventional method, and since there is no bent portion of the metal wiring where stress concentrates, the wiring is less likely to be broken.

[0109]

According to the present invention, that-out <br/> a semiconductor device capable of unnecessary flip chip connection underfill achieved.

[Brief description of drawings]

FIG. 1 is a partial cross-sectional view showing the structure of an embodiment of a semiconductor device of the present invention.

FIG. 2 is a plan view showing a state in which the semiconductor devices of this embodiment are continuously formed.

FIG. 3 is a view showing an example of a manufacturing process of a semiconductor device of the present invention (1)

FIG. 4 is a diagram showing an example of the manufacturing process of the semiconductor device of the present invention (2)

FIG. 5 is a diagram showing an example of the manufacturing process of the semiconductor device of the present invention (3)

FIG. 6 is a view showing a printing mask used for forming a stress relaxation layer of the present invention.

FIG. 7 is a diagram showing a process of printing a stress relaxation layer.

FIG. 8 is a diagram showing a plate separating process in which a print mask is lifted above a wafer.

FIG. 9 is a view showing a semiconductor device in which a stress relaxation layer is formed.

FIG. 10 is a view showing a state in which an exposure mask is brought into close contact with a resist.

FIG. 11 is a diagram showing an example of rewiring wiring.

FIG. 12 is a diagram showing another example of rewiring wiring.

FIG. 13 is a diagram showing insufficient development of an actual rewiring wiring pattern.

FIG. 14 is a diagram showing another example of rewiring wiring.

FIG. 15 is a diagram showing another example of rewiring wiring.

FIG. 16 is a diagram showing another example of rewiring wiring.

FIG. 17 is a diagram showing a semiconductor device which has been subjected to a seventh step in the present invention.

FIG. 18 is a diagram showing the relationship between the film thickness of the stress relaxation layer and stress.

FIG. 19 is a diagram showing the relationship between the film thickness of the stress relaxation layer and α rays.

FIG. 20 is a diagram showing an example of a structure of a semiconductor device of the present invention.

FIG. 21 is a diagram showing an example of the structure of a semiconductor device of the present invention.

FIG. 22 is a diagram showing an example of the structure of a semiconductor device of the present invention.

FIG. 23 is a diagram showing one embodiment of the structure of a semiconductor device of the present invention.

FIG. 24 is a diagram showing a semiconductor device in which the film thickness of the stress relaxation layer is partially reduced.

FIG. 25 is a diagram showing a state in which a semiconductor device in which the stress relaxation layer is partially thin is connected to a circuit board.

FIG. 26 is a diagram showing one embodiment of the structure of a semiconductor device of the present invention.

FIG. 27 is a view showing a state in which a stress relaxation layer is formed across a boundary between a semiconductor device and an adjacent semiconductor device.

FIG. 28 is a view showing a method of cutting the stress relaxation layer.

FIG. 29 is a diagram of an example in which a semiconductor device is mounted on a substrate.

FIG. 30 is a diagram of another embodiment in which a semiconductor device is mounted on a substrate.

FIG. 31 is a diagram showing a conventional semiconductor device.

FIG. 32 is a diagram showing a state in which a conventional semiconductor device is connected to a circuit board.

FIG. 33 is a diagram showing one embodiment of the structure of the semiconductor device of the present invention.

FIG. 34 is a view showing another embodiment of the structure of the semiconductor device of the present invention.

FIG. 35 is a view showing another embodiment of the structure of the semiconductor device of the present invention.

FIG. 36 is a view showing another embodiment of the structure of the semiconductor device of the present invention.

FIG. 37 is a diagram showing one embodiment of the structure of a semiconductor device of the present invention.

FIG. 38 is a view showing another embodiment of the structure of the semiconductor device of the present invention.

FIG. 39 is a view showing another embodiment of the structure of the semiconductor device of the present invention.

FIG. 40 is a view showing another embodiment of the structure of the semiconductor device of the present invention.

FIG. 41 is a diagram showing a relationship between a glass transition temperature and a linear expansion coefficient.

[Explanation of Codes] 1 ... Bump, 1aa ... Longitudinal bump, 2 ... Au plating, 3
... bump pads, 4 ... rewiring wiring, 5 ... stress relaxation layer,
6 ... Surface protective film, 7 ... Aluminum pad, 8 ... Protective film, 9 ...
Wafer on which semiconductor is formed, 10 ... Bump, 11 ... Metal wiring, 12 ... Insulating layer, 13 ... Semiconductor device, 14 ... Circuit board, 15 ... Underfill, 16 ... Feed film, 17 ... Reverse wiring pattern, 18 ... Connection part between aluminum pad and wiring, 19 ... Boundary between lower layer part, 20 ... Gap, 21 ... Exposure mask, 22 ... Resist, 23 ... Connection part with aluminum pad, 24 ... Cutting part, 25 ... Nickel alloy stencil,
26 ... Resin sheet, 27 ... Frame, 28 ... Pattern opening of print mask, 102 ... Silica particles, 110 ... Memory cell, 115 ... Substrate, 116 ... Electrode, 118 ... Resin, 12
0 ... Electrode, 121 ... Electrode

Front page continuation (72) Inventor's record Noriyuki 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa, Hitachi, Ltd., Institute of Industrial Science (72) Inventor Hiroyuki Hozoji 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Hitachi, Ltd. Manufacturing Engineering Laboratory (72) Inventor Shigeharu Kakuda 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Hitachi Production Engineering Laboratory (72) Inventor Naoya Isada 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Hitachi, Ltd., Production Technology Laboratory (72) Inventor En, Minagawa 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Hitachi, Ltd. Production Technology Laboratory, (72) Inventor Ichiro Yasue, 5-20-1, Kamimizumoto-cho, Kodaira-shi, Tokyo Issue Hitachi, Ltd. Semiconductor Group (72) Inventor Asao Nishimura 5-20-1, Joumizuhoncho, Kodaira-shi, Tokyo Hitachi Ltd. Semiconductor Group (72) Kenji Ujiie Gojomizucho, Kodaira-shi, Tokyo Chome 20 No. 1 Hitachi Ltd. Semiconductor Group (72) Inventor Akira Yajima 5-20-1, Kamisuihonmachi, Kodaira-shi, Tokyo Hitachi Ltd. Semiconductor Group (56) References JP-A-11-191572 (JP) , A) JP-A-9-252034 (JP, A) JP-A 8-293509 (JP, A) JP-A 11-312710 (JP, A) JP-A 11-54649 (JP, A) JP-A 11-191571 (JP, A) JP 2002-16179 (JP, A) JP 2002-16180 (JP, A) JP 2002-16178 (JP, A) JP 2002-16198 (JP, A) JP 2002-16190 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 23/29 H01L 21/56 H01L 21/60 311 H01L 23/12 501 H01L 23/31

Claims (22)

(57) [Claims] 1. A semiconductor element having a circuit electrode, and the semiconductor so that the circuit electrode of the semiconductor element is exposed.
A first insulating layer formed on the element, and a flat portion and an end thereof formed on the first insulating layer.
Second insulating layer having a slanted portion on the outer surface, and an external connection terminal formed on the flat portion of the second insulating layer
And formed on the flat and sloped portions of the second insulating layer.
And the external connection terminal and the circuit electrode of the semiconductor element
A wiring electrically connecting the second insulating layer and the third insulating layer formed on the wiring.
A semiconductor device having a second insulating layer , wherein the second insulating layer is the semiconductor device and the semiconductor device.
Is a layer that relieves the stress generated between the
And a semiconductor device characterized by containing particles.
Place 2. The semiconductor device according to claim 1, wherein The particles of the second insulating layer form the second insulating layer.
Adjust the viscosity of the insulating material and adjust the inclination of the second insulating layer.
A semiconductor device characterized by controlling the shape of an inclined portion. 3. The semiconductor device according to claim 1, wherein: The particles of the second insulating layer are dispersed in the second insulating layer.
And controlling the shape of the second insulating layer.
Semiconductor device. 4. The half according to any one of claims 1 to 3.
A conductor device, The second insulating layer is a mask having a plurality of openings formed therein.
Formed by printing an insulating material having the particles using
A semiconductor device characterized in that it is a layer. 5. The half according to any one of claims 1 to 3.
A conductor device, The second insulating layer has the particles using a mask
It is a layer formed by stencil printing an insulating material
A semiconductor device characterized by: 6. The half according to any one of claims 1 to 5.
A conductor device, The second insulating layer comprises a precursor of an insulating material, a solvent, and the insulating material.
Cure the insulating material containing the edge material and particles of the same material
A semiconductor device characterized in that it is a layer. 7. The half according to any one of claims 1 to 5.
A conductor device, The second insulating layer is composed of a polyimide precursor, a solvent, and a poly.
It is a layer obtained by curing an insulating material containing imide particles.
And a semiconductor device. 8. The half according to any one of claims 1 to 5.
A conductor device, The second insulating layer is a precursor of the first insulating material and a solvent
Particles of a second insulating material different from the first insulating material
Characterized by being a layer obtained by curing an insulating material containing
Semiconductor device. 9. The half according to any one of claims 1 to 5.
A conductor device, The second insulating layer contains polyimide particles.
And a semiconductor device. 10. The method according to any one of claims 1 to 5.
A semiconductor device, The second insulating layer is made of at least an amide imide resin,
Sterimide resin, ether imide resin, silicone resin
Particles of grease, acrylic resin, polyester resin
A semiconductor device comprising: 11. The method according to any one of claims 1 to 5.
A semiconductor device, The second insulating layer is at least silica, alumina, nitrogen.
Characterized by containing particles of any of the boride
Semiconductor device. 12. The method according to any one of claims 1 to 11.
A semiconductor device of The average particle size of the particles contained in the second insulating layer is 1
To 2 micrometer semiconductor
apparatus. 13. The method according to any one of claims 1 to 12.
A semiconductor device of The maximum particle size of the particles contained in the second insulating layer is 1
Semiconductor device characterized by being 0 micrometer
Place 14. The semiconductor device according to claim 11.
hand, In the thickness direction of the second insulating layer, the second insulating layer
The particle size of the particles contained in the layer is near the semiconductor element.
Larger, smaller with increasing distance from the semiconductor element
A semiconductor device characterized in that 15. The method according to any one of claims 1 to 14.
A semiconductor device of The thickness of the second insulating layer is about 35 micrometers or
150 micrometers, from the external connection terminal
Preventing α rays generated from reaching the semiconductor element
A semiconductor device characterized by the above. 16. A method of manufacturing a semiconductor device, comprising: Firstly, on the wafer so that the circuit electrodes of the wafer are exposed.
A first step of forming an insulating layer of The semiconductor device and the semiconductor device on the first insulating layer.
Has a function to relieve the stress generated between the board and
Second having a flat part and an inclined part at its end
A second step of forming an insulating layer of The wafer is placed on the sloped portion and the flat portion of the second insulating layer.
The third process to form the wiring drawn from the circuit electrode
And The external connection terminal electrically connected to the wiring is the second
Has a fourth step of forming on the flat portion of the insulating layer of In the second step, a mask having a plurality of openings is formed.
The insulating material having particles is printed by using
Manufacturing method of semiconductor device characterized by forming insulating layer
Law. 17. A method of manufacturing a semiconductor device, comprising: Firstly, on the wafer so that the circuit electrodes of the wafer are exposed.
A first step of forming an insulating layer of The semiconductor device and the semiconductor device on the first insulating layer.
Has a function to relieve the stress generated between the board and
Second having a flat part and an inclined part at its end
A second step of forming an insulating layer of The wafer is placed on the sloped portion and the flat portion of the second insulating layer.
The third process to form the wiring drawn from the circuit electrode
And The external connection terminal electrically connected to the wiring is the second
Has a fourth step of forming on the flat portion of the insulating layer of In the second step, the insulating material having particles using a mask is used.
Stencil printing material to form the second insulating layer
A method of manufacturing a semiconductor device, comprising: 18. The semiconductor device according to claim 16 or 17.
A method of manufacturing a device, In the second step, the particles increase the viscosity of the insulating material.
To adjust and control the shape of the slope of the second insulating layer.
A method of manufacturing a semiconductor device, comprising: 19. The method according to any one of claims 16 to 18.
A method of manufacturing a semiconductor device according to claim 1, In the second step, the insulating material is used as the insulating material.
The precursor of the edge material, the solvent, and the same material as the insulating material.
Printing a paste-like insulating material containing particles
Manufacture of a semiconductor device characterized by forming a second insulating layer
Build method. 20. The method according to any one of claims 16 to 18.
A method of manufacturing a semiconductor device according to claim 1, In the second step, the insulating material is poly
Paste containing imide precursor, solvent and polyimide particles
-Shaped insulating material is printed to form the second insulating layer To do
And a method for manufacturing a semiconductor device. 21. The method according to any one of claims 16 to 18.
A method of manufacturing a semiconductor device according to claim 1, In the second step, as the insulating material, the first
Insulating material precursor and solvent different from the first insulating material
A paste-like insulating material containing particles of the second insulating material
Printing to form the second insulating layer
Manufacturing method of semiconductor device. 22. The method according to any one of claims 16 to 20.
A method of manufacturing a semiconductor device according to claim 1, In the second step, as the insulating material, thixo
Particles having a tropic index of 2 to 3
By printing an insulating material containing a mixture of
A method of manufacturing a semiconductor device, comprising: