JP3399456B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flip chip
The structure and manufacturing method of a semiconductor device for the purpose of continuation.
You. 2. Description of the Related Art Many semiconductor devices have a laminated structure.
In many cases, an insulating layer is disposed between the layers.
An opening is provided in this insulating layer, and the opening is
Through the wiring to connect the lower layer terminals and the upper layer terminals.
Has been established. [0003] The following method is adopted as a method of forming an insulating layer.
Have been. That is, the photosensitive insulating material is placed on the semiconductor device.
Coating by spin coating, exposure and development
This forms an opening in the insulating layer. Also, the lower terminal
The metal wiring connecting the terminal with the upper layer terminal is made of the second photosensitive material
Material is applied to the upper layer of the insulating layer, and then exposed and developed.
To form a mask, plating and sputtering
Insulation layer by using processes such as
A metal wiring connecting the lower terminal and the upper layer is formed. trout
After the photosensitive insulating material used as the
Remove it. [0004] By the above-described steps, the edge under the insulating layer is formed.
Wiring for connecting the element and the upper layer can be formed. like this
FIG. 3 is a partial cross-sectional view of a semiconductor device formed by various processes.
It is shown in FIG. In the figure, the aluminum pad 7 is the insulating layer 1
2 Terminals on lower layer, bump pad 3 on insulating layer
It is a layer terminal. And the wafer on which the semiconductor is formed
The insulating layer 12 formed on the aluminum pad 7 is
Is provided with an opening. Also, aluminum pad 7
To the bump pads 3 in the upper layer of the insulating layer 12
11 are formed. The bump 10 has a bump 10
Are formed. In addition, like this, the aluminum pad 7
Forming the wiring from the bump pad 3 to the
being called. In this case, the thickness of the insulating layer 12 is made of metal.
The thickness is almost equal to the thickness of the wiring 11. [0005] The semiconductor device manufactured through such a process.
Mounted on a circuit board such as a printed wiring board and connected
One type of connection is flip-chip connection. FIG.
1 is a cross-sectional view of a semiconductor device connected by flip chip.
The connection between the semiconductor device 13 and the circuit board 14
The bumps 10 provided on the terminals 13 are melted on the circuit board.
It is realized by solidifying again after melting. Semiconductor equipment
The gap between the device 13 and the circuit board 14 is filled with a highly rigid resin.
Have been. This resin is called an underfill 15.
It has the effect of reinforcing the connection. Underfill
Japanese Patent Application Laid-Open (JP-A) No. 11-1 discloses an example of the implemented flip chip connection.
No. 11,768. [0006] However, the above-mentioned prior art
The technology has the following problems. First, the gap between the semiconductor device and the circuit board is
There is a difficulty in the resin supply method. In other words, the gap is generally
Method of supplying resin to a gap of 0.3 mm or less
As a method, a method utilizing a capillary phenomenon has been adopted. I
However, the resin material for underfill is made of high-viscosity liquid
Because it is fat, it takes time to embed it in the gap, and
Are likely to remain. Second, it is difficult to remove the semiconductor device.
That is, the semiconductor device connected to the circuit board is defective.
If the semiconductor device is removed from the circuit board,
The cured underfill material remains on the circuit board after removal.
If it is difficult to recycle the circuit board because it will remain on the board
The problem exists. To solve the first and second problems
The semiconductor device without the underfill
It is desirable to connect to the board. However, under
The fill is caused by the heat generated when using the completed electrical products.
To prevent breakage of the connection due to distortion in the connection
If not, semiconductors
The problem is that the connection life of the device becomes extremely short.
Occurs. Also, flip chip that does not require underfill
For forming solder bumps on a semiconductor device that enables connection
Of the impurities contained in the solder bumps
Generates α-rays, leading to malfunction of the transistor section.
May cause. An object of the present invention is to eliminate the need for underfill.
Realizing semiconductor devices that enable flip-chip connection
It is in. The present invention achieves the above object.
In order to do so, it is structured as claimed.
You. Thus, on a desired insulating layer (thick film insulating layer),
The above object is achieved by forming wiring. example
For example, if a low elastic material is used for the insulating layer of the semiconductor device, and
The connection part is formed by forming an insulating layer with a thickness of 35 microns or more.
Can be prevented from being destroyed. Also, a low elasticity insulating layer
Greatly reduces the stress generated at the connection.
It becomes possible. This allows connection of semiconductor devices
Life is greatly improved. Also, make the insulating layer a predetermined thickness.
In this way, stress generated on the wafer etc. is alleviated.
Therefore, unnecessary α-rays can be blocked. In addition, it is said that it is about 35 micrometers or more.
If a thick insulating layer is used, the conventional wiring
Hard to apply. In other words, when forming a thick insulating layer,
Since the material for forming the edge layer has a high viscosity, the spin coating method
Then, it becomes an insulating layer containing bubbles, and as an insulating layer
Function will be lost. Apart from this, a new
Even if a thick film formation method is developed,
In the case of exposure development,
It is difficult to pattern the openings of the insulating layer with high precision.
It is difficult. Even if this problem can be solved,
The side wall of the part is approximately vertical of about 80 degrees or more, and
Because the height is much larger than the wiring thickness,
It becomes difficult for metal wiring to be formed on the side wall. You can even form
The metal wiring at the boundary between the side wall and the upper layer.
Since a bend is formed, stress tends to concentrate at this location
Therefore, cracks are easily developed. For this reason, the circuit board
The connection life during connection is shortened. Therefore, for example, an insulating material containing fine particles is used.
The thick insulating layer is formed by mask printing the material.
The shape of the opening of the insulating layer should be a gentle slope
Therefore, wiring on the insulating layer can be formed by the conventional method,
And there is no bent part of metal wiring where stress is concentrated
Therefore, disconnection of the wiring hardly occurs. The characteristics of the thick insulating layer
Properties in the thickness direction. For example, the characteristics of a thick insulating layer
On the semiconductor element side, it is close to the semiconductor element, and on the electrode side, these
Close to the characteristics of the substrate on which it is mounted. As a result,
Make sure that stress is not concentrated on the wiring formed on the
Reliability can be further improved. In other words,
The layer can be suppressed. In this specification, this thickness
The film insulating layer is described as a stress relaxation layer. DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of the present invention will be described.
This will be described with reference to the drawings. In all figures, the same
Since one symbol indicates the same part, duplicate description is omitted.
In some cases, and for ease of explanation,
The dimensional ratio has been changed from the actual one. First, the structure of the semiconductor device according to the present embodiment will be described.
explain about. Many semiconductor devices per wafer
Are manufactured in a lump, but in the following,
For the sake of clarity, some of them will be described. FIG. 1 shows this embodiment.
2 is a partial cross-sectional view of the semiconductor device 13 of FIG. The wafer 9 on which the semiconductor circuit is formed is:
Way that has completed the previous process in the semiconductor manufacturing process
C, which is divided into many semiconductor devices 13 before being cut
It is. Each semiconductor device 13 has an external connection terminal, for example,
An aluminum pad 7 is formed. This aluminum pad 7
In the conventional semiconductor device 13, QFP (Quad
Semiconductor package such as Flat Package)
If you want to use a semiconductor package,
Used to achieve continuity with the external terminals of the
You. The surface of the semiconductor device 13 on which the semiconductor circuit is formed,
On the aluminum pad 7 and in the area where a large number of semiconductors are formed
Cutting when the wafer 9 is cut into chip-shaped semiconductor devices 13
Except for the cut portion 24 and its surroundings, the
You. The protective film 8 has a thickness of 1 to 10 micrometers.
Insulating resin made of inorganic material of a certain degree or organic material
Insulating resin consisting of This protective film 8 has a thickness
Made of inorganic material of about 1 to 10 micrometers
Insulating film alone or organic material on top of the inorganic insulating film
Using a composite film in which organic insulating films
You. When this composite film is used, the organic film is a photosensitive resin.
It is desirable to use materials. In this embodiment, the protective film 8
As an example of a photosensitive material suitable as an organic film, a photosensitive material may be used.
Liimide, photosensitive benzocyclobutene, photosensitive polyben
And zuoxazole. This embodiment is not limited to this.
Well-known inorganic material, organic material or as a protective film
These composite membranes can be used. For example, as an inorganic film,
SiN or SiO2 can be used. The organic film is an inorganic film
Of course, it may be formed to cover almost the entire surface of
However, as shown in FIG.
34 may be formed only in the region shown in FIG.
As shown in the figure,
It may be done. Thus, the area of the organic film is limited.
The wafer due to the internal stress of the protective film 8
9 warpage is reduced,
This is advantageous in terms of focusing at the time of exposure. This implementation
In the example, the region near the aluminum pad 7 is the aluminum pad.
Area up to a maximum distance of 1 mm from the end of
You. 33 and 34, the periphery of the aluminum pad 7 is shown.
Organic film is formed in a continuous area, but individual aluminum
It may be formed in an independent area for each pad.
No. Specifically, for example, the region is as shown in FIG. Figure
Which of the configurations shown in FIGS.
The pattern accuracy of the photosensitive resin used for the film,
It is determined in consideration of the force and the element characteristics of the semiconductor device.
To give an example of the element characteristics here, the semiconductor device
Of each active cell inside the device
Energy barrier level has fluctuated
It refers to On the protective film 8, a thickness of 35 to 150
The chromium stress relaxation layer 5 is selectively formed.
You. The thickness of the stress relaxation layer depends on the size of the semiconductor element and the stress relaxation.
It depends on the elastic modulus of the sum layer, the thickness of the semiconductor element, etc.
Although it is not possible to determine the
Is approximately 150 to 750 micrometers,
Consists of a conductor element and a stress relaxation layer formed on its surface
Perform stress simulation experiments with bimetal models
However, the required thickness of the stress relaxation layer is 10 to 200 mm.
It is desirable to use a micrometer, more preferably 35 to 1
This test was conducted because it was found to be 50 micrometers.
The example was formed in this film thickness range. This is the thickness of the semiconductor device.
Equivalent to a thickness of about 1/20 to 1/5
You. When the film thickness is smaller than 35 micrometers,
The desired stress relaxation cannot be obtained, and the film thickness is 150
When the thickness of the stress relaxation layer 5 itself exceeds the thickness of the micrometer,
Wafer warpage occurs due to internal stress
Out of focus in the exposure process and hand in the wiring formation process
Ring defects are likely to occur, reducing productivity
There is a problem. The stress relaxation layer 5 is formed of a semiconductor wafer 9
A much lower modulus of elasticity, e.g.
With a resin material having an elastic modulus of GPa to 10 GPa
Is formed. Stress relaxation with an elastic modulus in this range
If it is a sum layer, we can provide a reliable semiconductor device
it can. That is, if the elastic modulus is less than 0.1 GPa,
In the case of a force relaxation layer, it is necessary to support the weight of the semiconductor device itself.
It is difficult to use it as a semiconductor device.
The problem of instability is likely to occur. On the other hand, 10GPa
If a stress relaxation layer with an elastic modulus exceeding
Wafer warpage due to internal stress of layer 5 itself
Occurs, defocus in the exposure process, wiring formation process, etc.
Handling troubles etc. easily occur,
Even the risk of cracking the wafer
is there. The edge portion of the stress relaxation layer 5 has a slope,
Is about 5 to 30%. Tilt below 5%
In the case of an oblique angle, the inclination becomes too long to obtain a desired film thickness.
Absent. For example, a thickness of 100
To be more than 3mm horizontal
A distance is required, and when the left and right edges are combined, almost 7 mm
Without the rim, the desired film thickness cannot be obtained.
You. On the other hand, when the inclination angle is more than 30%, in terms of the horizontal distance,
There is no problem, but conversely, sufficient step coverage
There is a high risk that a ledge cannot be obtained. Especially plating resist
Process merge in exposure and development and development process
No special skills or skills are required. further
When the inclination angle is large, the so-called stress concentration effect works.
As a result, stress concentrates on the edge, and as a result,
The wiring 4 for rewiring tends to be broken at the
This may require special contrivance in the wiring structure.
You. In the case of FIG.
50 micrometer membrane at chromometer horizontal distance
Because of the thickness, the average slope is 10%. Rewiring
Wiring 4 is formed of a conductor such as copper.
Electrodes on the surfaces of the pad 7 and the stress relieving layer 5, for example, bumps
The pad 3 is connected. On the bump pad 3,
Gold plating 2 is provided to prevent oxidation of bump pad 3.
You may ask. The surface of the semiconductor device 13 has bump pads 3 and
And a wafer 9 on which a large number of semiconductors are formed
Except for the cutting portion 24 when cutting into the device 13, the surface protective film
6 is covered. The protective film 8 and the stress relaxation layer are formed by the surface protective film 6.
5 is completely covered and sealed,
The protective film 8 and the stress relaxation from the surface of the formed wafer 9
Prevents the sum layer 5 from peeling off, leading to deterioration of semiconductor performance.
Intrusion of foreign substances such as ions that occur can be reduced. Also,
The protective film 8, the stress relaxation layer 5, and the surface protective film 6 are all cut off.
The semiconductor device 13 is cut because it is retracted from the cut portion 24.
No damage on separation. The surface protective film 6 has an electric insulating property.
Various resin materials can be used. Shape pattern
It is preferable to use photosensitive material
But, for example, it supported high-precision printing such as inkjet
A film may be formed by printing using a material. Other, car
The insulating film is solid by an inexpensive coating method such as ten coating.
After formation, use photolithography process to
A resist is formed and patterned.
Etching the above insulating film using
The film may be formed through a process called stripping. like this
As the material, various materials can be used in this embodiment.
However, there are several examples: (1) Acrylic as photosensitive material
Modified photosensitive epoxy resin, photosensitive polyimide resin,
(2) Polyamideimide as inkjet printing material
Resin, polyimide resin, (3)
Triazole resin, modified melamine resin, polyimide resin
Fats and the like are preferably used. More about photosensitive materials
Specifically, as an inexpensive photosensitive resin material,
Solder Resists Suitable for Solder Board Manufacturing Process
And used for surface covers of flexible printed circuit boards
Photosensitive polyimide is suitably used as the surface protective film 6.
Is done. On the other hand, as a solid film forming material, for example, Toray
Photo Nice TM of Co., Ltd. is suitable. Note that
In the example, a solder resist was used. Bump pad 3
The bump 1 is formed thereon. This bump 1
Generally, it is formed of a solder material. Here bump
1 is an external connection terminal. FIG. 2 shows a semiconductor device 13 shown in FIG.
The state that is continuously formed on the wafer
The bumps 1 shown in FIG. In FIG.
The area indicated by the hatching is the surface protection film 6.
It is a distant. Also, the stress relaxation layer 5 is a rectangle with rounded corners.
Each semiconductor device is formed in a state where it is formed in a shape.
Between the semiconductor devices 13 during the separation of each semiconductor device 13
Is present. The cutting margin is, for example, the surface
10 to 100 micrometers from the end of the protective film 6
It is desirable to be located. If shorter than 10 micrometers
Easy to induce chipping when separating each semiconductor device
Tend to be longer than 100 micrometers
Then, the effective area usable as a semiconductor element decreases.
Therefore, in order to improve the yield of the semiconductor device 13,
In this embodiment, the distance between the filter and the surface protective layer 6 is 10 to 10
It is desirable to be located at 0 micrometer. In addition,
Although not shown in the lower layer of one end of the wiring 4 for rewiring,
An aluminum pad 7 is present. According to this semiconductor device structure, the stress relaxation layer
5 exists between the wiring 4 for rewiring and the wafer 9,
The conductor device 13 is connected on the circuit board 14 and operates.
To disperse the distortion caused by the heat received by the bumps 1
It becomes possible. Therefore, the semiconductor device 13 is
Even if it is mounted on the substrate 14, the underfill 15 can be performed.
It is possible to prolong the connection life. Also, stress
Since the relaxation layer 5 has a gentle slope,
There is a wiring bent portion which becomes a stress concentration portion in the middle of the wiring 4 for use.
Absent. The manufacturing process of the semiconductor device 13 in this embodiment
An example of the process will be described with reference to the drawings. First step according to FIG.
4 to 6 from FIG. 4
The seventh to ninth steps will be described with reference to FIG. What
In each of the figures, the semiconductor device according to the present embodiment is shown.
A part is taken so that the sectional structure of
FIG. First step: Aluminum pad 7 for external connection
About wafer 9 on which formed semiconductor is formed
Are manufactured in the same process as the conventional semiconductor device 13. Book
In the semiconductor device used in the embodiment, the material of the pad for external connection is used.
The quality was aluminum, but the external connection pads were copper.
It doesn't matter. In this embodiment, a wire is used as an external connection.
Since no bonding is used, the external connection pads
Need to consider bonding issues that are likely to occur
Because there is no. If the external connection pad is copper,
Improves electrical characteristics of semiconductor devices by reducing electrical resistance
It is desirable also from the viewpoint of. Second step: forming a protective film 8 if necessary
I do. The protective film 8 is used in a semiconductor manufacturing process using an inorganic material.
May be already formed in the so-called pre-process
And furthermore, using an organic material on an inorganic material
It may be formed. In this embodiment, the semiconductor process
Consisting of inorganic materials formed in the so-called pre-process
Insulating film, for example, silicon nitride, tetra
There is silicon dioxide formed by ethoxysilane, etc.
Or an organic material on the insulating film composed of these composite films.
A certain photosensitive polyimide is applied, and this is exposed, developed, and hardened.
The protective film 8 with a thickness of about 6 micrometers
Has formed. As a result, the way the semiconductor is formed
A protective film 8 is formed on c. In this embodiment, the protective film 8 is used.
The film thickness was 6 micrometers, but the required film thickness was
It varies depending on the type of semiconductor element, and the range is 1
To about 10 micrometers. Note that FIG.
As shown, the organic film covers almost the entire surface of the inorganic film.
33 to FIG. 3 to FIG.
As shown in FIG. 5, in the region near the aluminum pad 7
It may be formed only on the surface. Only inorganic materials
In the case of an insulating film, the thickness range is 3 micrometers or less.
It becomes. The photosensitive polyimide used in the examples of the present application
Besides, polybenzoxazole, polybenzocyclo
Uses butene, polyquinoline, polyphosphazene, etc.
it can. Third step: A paste-like polyimide material is applied.
Print and apply to the place where the force relaxation layer 5 is to be formed, and then apply
It is cured by heating. Thereby, the protective film 8
The force relaxing layer 5 is formed. Fourth step: Power supply for use in electroplating
After forming the film 16 by a method such as sputtering, the reverse
Turn 17 is formed using a photoresist. Fifth step: Reverse the feed film 16 and the wiring
Electroplating is performed using pattern 17 and wiring for rewiring is performed.
A line 4 and a bump pad 3 are formed. Also need
By repeating the electroplating in accordance with the
It has a layer structure. Sixth step: wiring of photoresist
Etch reverse pattern 17 and feed film 16 for electroplating
It is removed by a rolling process. Seventh step: Surface using solder resist
A protective film 6 is formed. And using this pattern
Electroless gold plating 2 is performed on the outermost surface of the bump pad 3. Eighth step: flux on bump pad 3
And solder balls, and heat the bumps.
The solder balls are connected to the pads 3 to form the bumps 1. Ninth step: Wafer 9 on which semiconductor is formed
Is cut into semiconductor devices 13 by wafer dicing technology
I do. In the following, the third to eighth steps are described.
Will be described in detail. First, the third step will be described. For printing
The mask to be used is a solder paste for the printed circuit board.
It has the same structure as the printing mask used in strike printing
Can be used. For example, as shown in FIG.
Stencil 25 made of metal alloy via resin sheet 26
It is not possible to use a metal mask attached to the frame 27.
come. The pattern opening 28 of the printing mask is
The paste spreads wet after printing
So, even if you make it smaller,
Good. As shown in FIG. 7, paste printing is performed using a printing mask.
And the pattern of the wafer 9 on which the semiconductor is formed
Make sure that the squeegee stays
The pattern opening 28 is moved by moving the
After filling, a printing mask is applied to the wafer on which the semiconductor is formed.
Printing is performed by raising relative to wafer 9.
Perform so-called contact printing. Note that here
The close contact between the wafer and the printing mask creates a gap between the two.
It doesn't necessarily mean eliminating it at all. On the wafer
Since the protective film 8 has already been partially formed,
It is practically difficult to attach the print mask to the
That's why. In this embodiment, the wafer and the printing mask
Mark such that the gap between them is 0 to 100 micrometers
Printing was performed under printing conditions. In addition, print with the first squeegee
Coating the entire squeegee surface of the mask with paste
Then, use a second squeegee to open the pattern of the printing mask.
Fill mouth 28 and remove excess paste. So
After that, a printing mask is applied to the wafer 9 on which the semiconductor is formed.
There is also a printing method that raises the relative height. Shown in FIG.
So that the print mask is raised relative to the wafer 9
When doing it, you may raise it vertically, but relatively
You may raise it while moving so that it may have an inclination angle. Inclination
Beveling allows the print mask to be a wafer
When leaving the plate, the plate separation angle becomes uniform in the wafer plane.
I'm sorry. Also, the print mask can be moved from one end of the wafer to the other.
Away from the edge of
The last moment of plate separation, which tends to be
In the area, it is also advantageous in terms of yield improvement.
You. Furthermore, multiple wafers can be connected using the same printing press.
When performing continuous printing, mask at appropriate timing.
It is advisable to insert a process of wiping the back of the plate. For example, a book
In the embodiment, when 10 sheets are continuously printed, once the back side of the mask
After cleaning, the eleventh sheet was printed.
The timing, number and method of cleaning the back of the mask
Depending on the viscosity, solids concentration, filler amount, etc.
Appropriate adjustment is required. The semiconductor on which the paste is subsequently printed and applied
Using a hot plate or heating furnace
The paste is hardened by stepwise heating
The formation of the sum layer 5 is completed. For forming the stress relaxation layer 5 used here
Is a paste-like polyimide.
It can be cured by heating after being printed and applied on top
I can do it. This paste-like polyimide is
Precursors and solvents for amides and a large number of poly
Consists of imide microparticles. As fine particles,
Physically, it has an average particle size of 1 to 2 micrometers.
Has a particle size distribution with a large particle size of about 10 micrometers
Fine particles were used. The poly used in this example
The imide precursor, when cured, becomes polyimide microparticles.
Since the same material is used, the paste-like polyimide cures
A uniform stress relaxation layer 5 made of one type of material
Will be formed. In this embodiment, a stress relaxation layer is formed.
Although polyimide was used as the material, in the present embodiment, polyimide was used.
In addition to amide, amide imide resin, ester imide resin, d
-Terimide resin, silicone resin, acrylic resin,
Use of ester resins, resins modified from these, etc.
Both are possible. When using resin other than polyimide
To impart compatibility to the polyimide microparticle surface
Treatment or with the polyimide microparticles
It is desired to modify the resin composition to improve affinity
Good. Of the resins listed above, having an imide bond
Resins such as polyimide, amide imide, ester
In imides, ether imides, etc.
The thermomechanical properties such as strength at high temperatures
Excellent, resulting in the formation of plating power supply films for wiring
Choice of method spreads. For example, high-temperature processing such as sputtering
It is possible to select a plating power supply film forming method that involves a process. Silicon
Resin, acrylic resin, polyester resin, amide
Imide, ester imide, ether imide, etc.
Thermo-mechanical properties for resins that have parts condensed by external bonds
Is slightly inferior, but is advantageous in terms of processability and resin price.
There is a case. For example, in polyesterimide resin, general
The curing temperature is lower than that of polyimide, so it is easy to handle. Book
In the examples, among these resins, device characteristics, price, heat
Use these resins as appropriate, taking into account the overall mechanical characteristics, etc.
Divide. In the paste-like polyimide, polyimide fine
Adjusting the viscoelastic properties of the material by dispersing small particles
Use pastes with excellent printability.
Rukoto can. By adjusting the composition of fine particles,
To control the thixotropic properties of the
Printing characteristics by combining with viscosity adjustment.
Can be improved. Also, the inclination angle of the stress relaxation layer 5
Can also be adjusted. Paste suitable for this embodiment
The thixotropic properties of were measured using a rotational viscometer
From the ratio of the viscosity at 1 rpm to the viscosity at 10 rpm
The so-called thixotropic index obtained is 2.0
To 3.0 is desirable. In addition, Thixo
The temperature dependence of the tropy index
If the thixotropy index is 2.0 to 3.0
Printing in a temperature range that results in
It is. The printed paste-like polyimide is hardened by heating.
After the conversion, a cross section as shown in FIG.
A stress relaxation layer 5 having a shape is formed. Mark like this
When the stress relieving layer 5 is formed by printing, the stress relieving layer 5
200 to 1000 micrometers from the edge
There may be a swelling part in the sword, but this swelling
For the location and presence / absence of the
Adjust the composition of the polyimide of various
By changing the matter, it becomes possible to control to some extent. In addition,
Various conditions related to printing in this case include metal mass
Thickness, squeegee speed, squeegee material, squeegee angle,
Squeegee pressure (printing pressure), plate release speed, wafer printing
Temperature, the humidity of the printing environment, and the like. Above swelling
Control of the height and shape of the part can be achieved by the above printing conditions
However, as another control method, the structure of the protective layer 8 is adjusted.
There is also a method. For example, as shown in FIG.
The region where the organic layer of the film 8 is formed is limited only to the vicinity of the pad 7.
Then, the stress relaxation layer corresponding to the upper part of the organic layer is raised.
It is easy to make it work. Further, as shown in FIG.
If the bulging portion is positively formed, the deflection of the wiring 4
Part can be formed, thereby
The structure is easy to absorb the stress that breaks, preventing disconnection more.
be able to. Specifically, the average thickness of the stress relaxation layer 5
On the other hand, up to about 25 micrometers, preferably 7
Bulge with a height of about 12 micrometers
Preferably, a minute is formed. Even at the top of this level
For example, it can be formed sufficiently by mask printing. For example this
The semi-cylindrical shape with a radius of 10 micrometers
Assuming that, the half-arc length of the bulge is (2 × 3.1
4 × 10 micrometers) /2=31.4 micrometers
And the redundant length of wiring is
31.4-10 = 21.4 micrometers, stress relaxation
42.8 microphones when one is formed on each side of the sum layer
Meter. Thus, the redundant portion is provided in the wiring 4.
Can be used for wiring structures and solder joints.
The thermal stress used is reduced, and
We can provide the structure. The required thickness of this bulge is
The thickness and elastic modulus of the stress relaxation layer 5 and the
Size, power consumption of semiconductor devices,
Experiments and simulations taking into account the physical properties of the circuit board 14
From the solution. For example, in this embodiment, the semiconductor element
13, the diagonal length of the semiconductor element 13 is L millimeters.
The difference between the coefficient of linear expansion of the
ppm / ° C, substrate mounting process of semiconductor element 13-operation
200 degrees Celsius maximum temperature range caused by ON / OFF during
Then, when the board mounted product is used in the actual usage environment, the wiring
The maximum amount of thermal deformation received is 15 (ppm / ° C.) × L / 2 (m
m) × 200 (° C.) = 0.015 × L mm
Become. Therefore, the redundant length required for the bulge is
It is considered that 0.002 x L millimeters is sufficient.
I got it. From this calculation, the bulge is approximated by a semi-cylindrical shape.
Therefore, in this embodiment, the height of the swelling portion is the stress relaxation.
L / 2000 to L / 500 mm relative to the average thickness of layer 5
It was made to fit within the range of about meters. The required thickness of the stress relaxation layer 5 is one mark.
If not formed by printing and heat curing, print and material
To obtain the required film thickness by repeating the curing of the material multiple times
Can be. For example, a pace of solid content concentration of 30 to 40%
Using a metal mask with a thickness of 65 micrometers
When used, the film thickness after curing in two printings is about 50
Micrometers can be obtained. And especially the circuit
When the semiconductor device 13 is connected to the substrate 14, distortion concentrates.
Applicable for bumps 1 located in easy-to-use locations
The thickness is increased by limiting only to the stress relaxation layer 5 where
By doing so, the concentration of distortion can be reduced. For this reason
The semiconductor is formed, for example, paste-like polyimide
Used for the first printing on the wafer 9
If you print multiple times using a different metal mask than
good. Further, as a second method, the structure of the protective layer 8 is adjusted.
To partially change the thickness of the stress relaxation layer
You can also. For example, as shown in FIG.
The area directly under the bump X where it is easy to concentrate is protected by an inorganic film
Use only layers, in other areas organic film over inorganic film
The composite layer formed with is used as a protective film. Of such a protective film
When a stress relaxation layer is formed on the
A gentle slope at the part A of the stress relaxation layer where there is no roller
A part is formed. Now, the thickness of the stress relaxation layer is 50 mic.
The elastic modulus is 1 GPa and the thickness of the organic film is 1
Suppose the elastic modulus is 3 GPa at 0 micrometers
The average elasticity of the part consisting of the organic protective film and the stress relaxation layer
The rate (GPa / micrometer) is (3 × 10 + 1 × 5
0) /60≒1.3, while the slope in the part A
Has an average elastic modulus of 1. Therefore, such a structure
The thermal stress of the stress relaxation layer is
Will be dispersed in the area where the protective film is formed.
Prevent breakage of bumps around thermal stress
be able to. In addition, fine particles are not necessarily contained in the stress relaxation layer.
No need to disperse fine particles in paste
Even if the minimum viscoelastic properties required for printing are ensured
I just need. However, do not disperse the fine particles in the paste
In this case, the margins for various printing conditions are extremely narrow.
Could be. Next, the fourth step will be described. In this embodiment
Is the wiring 4 for rewiring, two layers of copper electroplating and nickel electroplating
And Note that one end of the rewiring wiring 4 is connected to the bump pad 3.
May also be used. Here, both copper and nickel
Although the method of forming the conductor using the
It is also possible to use an abbreviation. First, a power supply film for performing electroplating
16 is formed on the entire surface of the semiconductor wafer. Here, evaporation
Also, electroless copper plating, CVD, etc. can be used.
However, the bonding strength between the protective layer 8 and the stress relaxation layer 5 is high.
It was decided to use a good sputter. As a pretreatment for sputtering
Between the bonding pad 7 and the conductor 4 for rewiring.
Sputter etching was performed in order to secure conduction.
As the sputtered film in this embodiment, chromium (75
No.) / Copper (0.5 micrometer) multilayer film
Was formed. The function of the chrome here is located above and below
To ensure the adhesion between the copper and the stress relaxation layer, etc.
The film thickness is desirably the minimum that maintains their adhesion.
As the chrome film thickness increases, the deposition time increases and the production efficiency increases.
In addition to the problem of lowering, the protective layer 8 and the stress relaxation layer 5
Is generated in the sputtering chamber for a long time.
Exposure to high-energy plasma
There is a danger that the material forming these layers will deteriorate.
You. The required film thickness is determined by sputter etching and sputtering.
It varies depending on the conditions of the
The maximum is about 0.5 micrometers. The book
Instead of the chromium film used in the examples, a titanium film or titanium /
A platinum film, tungsten, etc. can be substituted. Meanwhile, spa
The copper film thickness is determined by the copper electroplating and electrical
When performing nickel plating, the plating film thickness distribution
The minimum film thickness that does not occur is preferable.
Taking into account the amount of film loss caused by pickling
Determine the film thickness that does not induce thickness distribution. Sputtered copper thickness
Thicker than necessary, for example, 1 micrometer
If the thickness of the copper exceeds
In addition to the problem of reduced production efficiency, implemented in later processes
Etching for a long time when removing the feed film 16
Is inevitable, and as a result, the size of the rewiring wiring 4 is reduced.
Etching increases. In a simple calculation, one microphone
When etching the power supply film of
1 micrometer on each side and 2 micrometers on each side
Pitching occurs. In actual production, the etching film
Over-etching so that no residue remains
Is generally performed, so that
When etching the electrical film, the wiring is 5 micrometers
Side etching. Side edge
When the ringing becomes large in this way, the wiring resistance increases.
Or cause breaks easily,
It is easy to cause problems from a viewpoint. Therefore, the thickness of the sputtered copper
Is about 1 micrometer at the maximum. Next, using photolithography technology,
The reverse pattern 17 of the wiring 4 for rewiring is formed by using a resist.
Formed. Edge of the stress relaxation layer 5 indicated by B in FIG.
The resist film thickness at the part
The strike makes it thicker than other places. Because of this, resolution
In order to secure the degree, a negative type is preferable. Regis
In the case where a liquid resist is used,
A resist film is formed on the upper part of the slope of the edge portion of the
The thickness tends to be thin, and the resist thickness
It tends to be thick. Film thickness at upper slope and lower slope
Different resists under the same exposure and developing conditions
A wide development latitude is required for the polishing. Generally, membrane
The development latitude with respect to the thickness is more neat than that of the positive photosensitive resist.
In this embodiment, the negative type photosensitive resist is wide because the resist is wide.
Was used. Use a film resist.
When used, there is no heat difference between the upper and lower slopes.
Both negative and positive types can be used, but there are no slopes.
The actual optical path length becomes longer due to exposure
In this case as well, good results can be obtained by using the negative type.
And many. When the inclination of the edge of the stress relaxation layer 5 is large
Using a film resist with weak or bleaching characteristics
In this case, a negative type is particularly preferred. In this embodiment, FIG.
As shown in the figure, the exposure mask 21 and the resist 22 are in close contact.
Then, an exposure machine of a type having a gap 20 in a part was used.
The resolution limit of the exposure machine is that the exposure mask 21 and the resist
22 is about 10 micrometers
Was. According to our experimental results, the gap under the exposure mask 21
The relationship between the interval 20 and the wiring width to be resolved is as shown in Table 1.
Was. The values in Table 1 indicate the optical system of the exposure machine, the developing conditions,
Resist sensitivity, resist curing conditions, wiring width / interval
It changes with the ratio of Experimental results shown in Table 1
Is a value when the ratio of wiring width / wiring interval is 1.0. [Table 1] FIG. 11 shows the connection portion 23 with the aluminum pad and the bus.
The situation where the pump pad 3 is connected by the wiring 4 for rewiring
Show. In the case of the exposure apparatus used in this embodiment,
The gap below the exposure mask on the horizontal axis is the thickness of the stress relaxation layer.
And the thickness of the stress relaxation layer is, for example, 6
If it is 0 micrometers, the width of the wiring is 25 micrometers.
Can be resolved down to Therefore, the wiring of the signal line
Power or ground wire with a width of 25 micrometers
Wiring with a wiring width of 40 micrometers
Can also. The wiring of the signal line is 25 micrometers
It is also possible to make some of the signal lines thicker.
You. FIG. 12 shows that the stress relaxation layer 5 is located near the inclined portion.
The wiring 4 for rewiring shown in FIG. As mentioned above,
The resist film thickness becomes non-uniform in the vicinity of the edge of the relaxation layer 5
Is likely to cause insufficient development in that area.
there were. FIG. 13 shows the actual state at the edge of the stress relaxation layer 5.
This shows a state where an image shortage has occurred. In this embodiment,
By improving the wraparound of the developer as a countermeasure
Settled. More specifically, the wiring pattern shape
To change as shown in FIG. 14 or FIG.
It is a measure. FIG. 14 is a view showing the connection 23 with the aluminum pad.
The case where the wiring width is increased to near the top of the stress relaxation layer 5 is as follows:
FIG. 15 shows only the edge portion of the stress relaxation layer 5 having poor resolution.
The case where the wiring width is increased is shown. In addition, these FIG.
4 and the wiring width in FIG.
And the resolution characteristics shown in Table 1. Other solutions
Eliminate remaining development by extending development time
There is also a possible method. Also, light is diffracted on the mask surface.
This is caused by the existence of the gap 20 under the exposure mask 21.
As a result, resolution and pattern accuracy may be reduced.
You. As a solution to this phenomenon, (1)
Change of optical system, (2) improvement of resist bleaching property,
(3) Optimization of resist pre-bake conditions, (4) Multi-stage exposure
And light. About change of optical system of exposure machine
To give one example, the NA value is 0.0001 or more and 0.2
The following measures can be taken to use an exposure machine. here
It is not limited to the examples given in
Improve pattern resolution and accuracy by combining
can do. The edge of the stress relieving layer 5 has a stress on the wafer.
Stress caused by the difference in the physical property values of the relaxation layer 5 tends to concentrate.
Because of the structural characteristics of the
Making the wire thicker can effectively prevent disconnection
it can. Make sure that all wiring is the same thickness
It is not necessary, for example, as shown in FIG.
The width of the wiring may be changed between the line and the signal line. this
In general, power / gran
It is desirable to make the line thicker than the signal line. Signal line
When thick, this increases the capacitance component of the wiring
This is because it affects during high-speed operation. Conversely, power /
The effect that the power supply voltage is stabilized by thickening the ground line
Is more preferable because it can be expected. Therefore, illustrated
As for signal wiring, it is the part where stress concentrates
A thicker pattern around the edge to minimize damage
Power supply or ground wiring.
It is desirable to make the part uniformly thick. On the other hand, the stress relaxation layer
For the flat part where no is formed, the capacitance component of the wiring
In consideration of the influence of the above, the signal wiring is thinned. However, this
This depends on the type of semiconductor device and its wiring pattern.
Need to be considered. For example, semiconductor elements and their wiring
Depending on the pattern, if the thickness of the protective film 8 is increased,
Since it has a great effect on reducing the wiring capacity, the stress relaxation layer
I have to make the signal wiring thick in the flat part that is not formed
In this case, it is desirable to form the protective film 8 thick.
Specifically, if the wiring width is increased by 10%,
It is desirable to increase the thickness of the film 8 by about 10%.
On the other hand, the wiring width at the upper flat part of the stress relaxation layer is
It is limited by wiring density rather than volume. Sand
The number of wires that pass through the bump pad interval, the bump pad
Diameter, the alignment accuracy in the wiring formation process, etc.
The upper limit value of the wiring width in the upper flat part of the force relaxation layer is determined.
You. Specifically, as an example, the bump pad interval is 0.5
Mm, pad diameter 300 micrometers,
(500-300) /
(3 × 2-1) = 40 This calculation
As a result, in the present embodiment, the average wiring width / wiring interval = 40 my
It was a chromometer. The fifth step will be described. In this embodiment
, Copper plating was performed using a sulfuric acid acidic copper plating solution. Electric
Copper-copper plating is suitable for cleaning with surfactants, water, and diluted sulfuric acid.
After washing with water and water, the power supply film 16 is connected to the cathode.
Then, a copper plate containing phosphorus was connected to the anode to carry out the test. Subsequently, electro nickel plating is performed. What
Note, before electro nickel plating, cleaning with surfactant,
Water washing, washing with diluted sulfuric acid, and washing with water give good film quality.
A nickel-plated film tends to be easily obtained. Electric ni
Kel plating connects the power supply film 16 to the cathode, and
Was connected to the anode. Electric nickel suitable for this embodiment
Plating can be performed using any of the commonly used nickel plating baths.
Can be used in both watt bath and sulfamine bath
Good, but in this example, a watt bath
Operate under plating conditions adjusted so that stress is in the appropriate range.
became. The plating solution component of the sulfamine bath is lower than that of the watt bath.
It is expensive and tends to decompose slightly
Despite the drawback, film stress is easy to control. Meanwhile, watts
Baths generally have a high film stress, so thick film
The film stress (tensile stress) of
Increases the risk of cracks in the wiring layer
There are drawbacks. In this example, a watt bath was used,
Regardless of whether you use the Amin bath or the Watt bath,
Types and concentrations of additives (film stress inhibitors), plating
Model for finding the appropriate range of flow density and plating solution temperature
It is advisable to carry out the experiment beforehand. In this embodiment
Are properly controlled by controlling the film thickness to 10 micrometers or less.
Now, we need to find the conditions under which no cracks
It was carried out after. Note that the plating film stress is
It is one of the indices related to Kell's metal crystal orientation.
Control to suppress the growth of the solder diffusion layer
There is a need to. Under conditions where film stress is properly controlled
The plating film eutects a specific amount of trace components.
Become like For example, containing 0.001 to 0.05% sulfur
In the case of such a film, the content of a specific crystal orientation plane increases. Yo
More specifically, the orientation planes 111, 220, 200, 3
11, the total content is 50% or more. Electric nickel
The plating thickness depends on the type of solder used in the subsequent process and
Reflow conditions and product characteristics of semiconductor devices (mounting form)
To determine the optimum value. Specifically, solder reflow
Of solder and nickel formed during
Determined so that the thickness of the gold layer is greater than the thickness of the nickel plating
Just do it. The thickness of the above alloy layer depends on the concentration of tin in the solder.
The higher the temperature, the larger the higher the maximum reflow temperature.
It becomes. In this way, on the copper wiring as rewiring wiring
When a nickel layer is formed, the gap between the semiconductor device and the circuit board
The working thermal stress deforms the rewiring wiring, and then
When the stress is released, the rewiring wiring is
Can return to its pre-deformation shape due to its spring property. example
For example, thermal stress caused by the operation of semiconductor devices
The stress relief layer and the redistribution layer formed on it
The line wirings 4 are deformed in a state of being in close contact with each other. At this time
The deformation of the rewiring wiring is due to the swelling of the stress relaxation layer.
The redundant part of the rewiring is used
You. After that, the stress relief layer is released from thermal stress, etc.
When returning to the shape, when the rewiring wiring is only copper wiring
The copper wiring returns to the original wiring shape due to the spring property of the copper wiring itself.
Hateful. On the other hand, when a nickel layer is formed on copper wiring,
Rewiring wiring (copper wiring) due to the spring property of the nickel layer
Can easily return to its original shape. In addition, copper wiring
What is formed on the copper wiring is not limited to the nickel layer
It may be as springy as nickel layer
No. Also, instead of copper wiring, stretch wiring should be formed.
In this case, a nickel layer is not always necessary. In the sixth step, electrolytic copper plating and electric
After plating, the reverse pattern of the wiring
By removing the dist 17 and performing an etching process,
The formed power supply film 16 is removed. For copper etching,
There are types such as iron chloride and alkaline etching solution.
In the embodiment, an etchant containing sulfuric acid / hydrogen peroxide as a main component
Solution was used. Control is required if the etching time is not longer than 10 seconds
It is difficult from a practical point of view because it is difficult to control
If etching is performed for a long time, for example, over 5 minutes
In the case of etching, side etching is
There is also a problem that it becomes harder and the tact becomes longer
Therefore, the etching solution and etching conditions should
It is better to ask more. Of the power supply film 16 to be subsequently performed
For the etching of the chromium part, in this embodiment,
An etching solution containing potassium silicate and metasilicic acid as main components
Using. The electric nickel plating film is used as the power supply film 16.
Also functions as an etching resist when etching
ing. Therefore, nickel and copper, nickel and chromium
In consideration of the etching selectivity, the composition
It is preferable to determine the switching condition. For example, specifically
For example, sulfuric acid hydrogen peroxide
For the tinting agent, the sulfuric acid content is 50% or less at maximum,
More preferably, it is 15% or less. As a result, nickel
And etch copper with an etching selectivity of about 10 times
Wear. In the seventh step, the bump pad 3 and the cutting
The surface protective film 6 having an opening only in the portion 24 and its periphery is formed.
And then electroless gold plating
Gold was formed on the pad portion 3. Here, the surface protective film 6 is used.
Using a solder resist, which is
After coating the entire surface, it is exposed and developed to form a pattern.
To achieve. In addition, other than the solder resist,
Surface protective film using materials such as polyimide and polyimide for printing
6 can also be formed. Through the above steps
As a result, the surface protection film 6 can be used for the wiring 4 for rewiring,
This completely covers the layer 5, the protection film 8, and the like. others
Therefore, the surface protection film 6 includes the rewiring wiring 4, the stress relaxation layer 5,
Deterioration, peeling, and corrosion of the protective film 8 by irritants
Can be suppressed. Up to the seventh step, from the aluminum pad 7
The wiring 4 for rewiring up to the bump pad 3 and the bump pad 3
FIG. 17 and FIG.
And formed as shown in FIG. In the eighth step, the solder ball mounting device and the
The bump is formed using a flow furnace. That is,
With the use of a device that mounts on the bump pad 3
Mount a fixed amount of flux and solder balls. On this occasion,
Solder balls are bump pads due to the adhesive force of the flux
Temporarily fixed on top. Semiconductor wafer with solder balls
When the wafer is put into the reflow furnace, the solder balls
It melted and then solidified again, as shown in FIG.
The bump 1 is connected to the bump pad 3. Besides this
Using a printing machine to apply solder paste on bump pads 3
Print coating and reflow to form bumps 1
There is also a way to do it. Regardless of the method, the solder material is different
It is possible to select various things, at this time
Many of the solder materials available on the market can be used.
In addition, although the solder material is limited, plating technology
There is also a method of forming the bump 1 by using it. Also,
Bumps and conductive materials using balls with gold or copper as the core
Bumps formed using compounded resin may be used
No. The steps from the first step to the ninth step are performed.
With the stress relaxation layer 5 shown in FIG.
The rewiring wiring 4 is formed in approximately the same number of steps, and the rewiring wiring is formed.
Semiconductor with no bent part where stress concentrates in the middle of 4
The device 13 can be realized. Also use printing technology
Thick insulating layer without using exposure or development technology.
The stress relaxation layer 5 can be formed in a pattern.
The force relaxation layer 5 has a slope for forming the wiring 4 for rewiring.
can do. According to the present embodiment, underfill is performed.
Even if the semiconductor device 13 is flip-chip connected without
The connection reliability of the semiconductor device 13 is greatly improved. others
Therefore, according to the present embodiment, the underflow
Flip chip connection that does not use
It is clear that it will be possible to reduce the price of
Call In addition, since no underfill is performed,
The body device 13 can be removed. In other words, the circuit board
If the semiconductor device 13 connected to the
The body device 13 is removed from the circuit board and the circuit board is regenerated.
It is also possible to
The case can be reduced. Next, the material of the stress relaxation layer 5 according to the present embodiment
Will be described. The most preferred application in this embodiment
The material for forming the force relaxation layer 5 is a paste-like polyimide.
Modified amide imide resin, ester
Amide resin, ether imide resin, polyester resin,
It is possible to use modified silicone resin, modified acrylic resin, etc.
No. Among the above-listed resins, trees having an imide bond
Fats, such as polyimide, amide imide, ester imi
In imides, ether imides, etc.
The thermomechanical properties such as strength at high temperatures
Excellent, resulting in the formation of plating power supply films for wiring
Choice of method spreads. For example, high-temperature processing such as sputtering
It is possible to select a plating power supply film forming method that involves a process. Silicon
Resin, acrylic resin, polyester resin, amide
Imide, ester imide, ether imide, etc.
Thermo-mechanical properties for resins that have parts condensed by external bonds
Is slightly inferior, but is advantageous in terms of processability and resin price.
There is a case. For example, in polyesterimide resin, general
Since the curing temperature is lower than that of polyimide, it is easy to handle.
In the present embodiment, among these resins, device characteristics, price,
Considering thermo-mechanical properties, etc., these resins
Use them properly. The material for forming the stress relaxation layer 5 is, for example, an epoxy resin.
Resins such as xy, phenol, polyimide, and silicone
A single or a combination of two or more
Contains a coupling agent and colorant to improve adhesion
It is possible to use it. The modulus of elasticity of the stress relaxation layer 5 at room temperature
About 0.1 to 10.0 GPa is applicable
However, it is desirable that the elastic modulus is lower than that of general polyimide.
No. When the elastic modulus is less than 0.1 GPa and too small
Indicates the formation of the protruding electrodes described later and the function test of the semiconductor device.
When wiring is performed, the wiring part is easily deformed and problems such as disconnection may occur.
To be reminded. Further, the elastic modulus of the stress relaxation layer 5 is 10.0 G.
If it exceeds, sufficient stress reduction effect cannot be obtained,
Connection reliability decreases when the semiconductor device is mounted on a substrate
It is feared that. Further, the curing temperature of the material for the stress relaxation layer 5 is
It is desirable to use one from 100 ° C to 250 ° C.
No. If the curing temperature is lower than this,
It is difficult to control in
Wafer stress increases due to heat shrinkage during cooling
This is because there is a concern that the characteristics of the element may change. After curing
The stress relaxation layer is suitable for sputtering, plating, etching, etc.
Exposure to various processes, heat resistance, chemical resistance,
Characteristics such as solvent resistance are also required. Specifically, heat resistance
The glass transition temperature (Tg) exceeds 150 ° C and 400 ° C or less
Below, more preferably, Tg is 180 ° C.
As described above, the Tg is most preferably 200 ° C. or higher. FIG.
Is an experimental result showing the relationship between the glass transition temperature (Tg) and the coefficient of linear expansion.
It is a fruit. This indicates that the glass transition temperature (Tg) is 200 ° C or less.
If it is above, it can be seen that no crack has occurred. What
In addition, suppress the amount of deformation in various temperature treatments during the process
From the viewpoint, the linear expansion coefficient (α1) in the region below Tg is small.
Very preferred. Specifically, the closer to 3 ppm
No. In general, low elastic materials often have a large linear expansion coefficient.
Is the linear expansion coefficient of the material of the stress relaxation layer 5 suitable in this embodiment.
Desirably, the range is from 3 ppm to 300 ppm.
New More preferably in the range of 3 ppm to 200 ppm
And the most desirable linear expansion coefficient is 3 ppm to 150 pp.
m. On the other hand, the thermal decomposition temperature (Td) is about 300 ° C
It is desirable that this is the case. Tg and Td fall below these values
The thermal process in the process, such as sputtering or
Deformation, deterioration or decomposition of the resin occurs during the sputter etch process
There is a risk. In terms of chemical resistance, 30% sulfuric acid
24 hours or less in aqueous solution or 10% sodium hydroxide aqueous solution
The resin immersion such as discoloration and deformation due to the above immersion does not occur.
desirable. Solvent resistance includes solubility parameter (S
(P value) is desirably 8 to 20 (cal / cm3) 1/2.
The stress relief layer 5 transforms some components into the base resin
If the material is composed of
It is desirable to be within the range of the resolution parameter.
More specifically, the solubility parameter (SP value) is 8
Less than or more than 20 components are contained in more than 50% by weight.
Desirably not. These chemical resistance and resistance
Insufficient solvent properties limit applicable manufacturing processes
May be undesirable from the viewpoint of reducing manufacturing costs.
There is also. Realistically, a material code that satisfies these characteristics
After considering the cost and process freedom comprehensively,
It is good to determine the material for the relaxation layer 5. Subsequently, the thickness of the stress relaxation layer and the wafer stress
And the relationship between α rays. FIG. 18 shows the stress relaxation.
It shows the relationship between the thickness of the sum layer and the wafer stress.
As shown in FIG. 18, the stress relaxation layer has an 8-inch diameter.
150 micrometer when applied and cured
When the film thickness is thicker than that, the wafer stress increases,
Wafer warpage increases, wafer cracks,
Peeling of the insulating film or the like is likely to occur. On the other hand, FIG.
The relationship with the α dose transmitted through the force relaxation layer was shown. α rays
Is contained as an impurity in the solder used for semiconductor devices.
Generated by the collapse of uranium and thorium
This causes a malfunction of the transistor section. As shown in FIG.
As described above, the thickness of the stress relaxation layer is less than 35 micrometers.
When the thickness increases, almost no alpha rays are transmitted, and malfunctions due to alpha rays
No problem arises. Conversely, from 35 micrometers
When the thickness of the force relaxation layer is reduced, α-rays are transmitted,
It can be understood that a malfunction due to is likely to occur. From these relationships, the thickness of the stress relaxation layer is set to 3
5 micrometers or more and 150 micrometers or less
By this, the circuit part formed on the surface of the semiconductor element
To prevent α-rays from reaching the semiconductor device.
Connection reliability with the mounted substrate can be ensured.
Note that, depending on the configuration of the semiconductor device, α rays
Susceptible parts, such as transistor malfunction
Memory cells 110 that are susceptible to
There are difficult parts. Therefore, it is particularly affected by α-rays.
As shown in Figs.
The thickness of the relaxation layer is more than 35 micrometers and 150 microphones
Meters or less, the shape
To prevent alpha rays from reaching the circuit part
it can. In addition, it is formed in a region that is hardly affected by α rays.
The thickness of the stress relief layer should be less than 35 micrometers
However, there is no problem from the viewpoint of α-ray shielding. So, for example
For example, as shown in FIG.
Make the sum layer thick, and make the stress relaxation layer thin in other areas.
To form an average stress relief layer having an average thickness of 35 μm.
Torr to 150 micrometers
You. When applying such a device, it is necessary to cover each bump.
The configuration of a semiconductor device considering the magnitude of thermal stress strain
Is desirable. Generally goes to the outer periphery of the semiconductor device 13
More likely to undergo thermal stress strain and require a thicker stress relief layer
Transistis that is susceptible to α-rays
Is arranged on the outer periphery of the semiconductor device 13 so that the
An area that is not easily affected is located near the center of the semiconductor device 13.
Should be placed. For example, as shown in FIG.
The thickness of the layer 5 is small near the center of the semiconductor device 13,
It is also possible to get thicker as you go. This place
In this case, the bump near the center has a higher connection height than the other bumps.
As the connection angle decreases as the size increases, the bump
The thinner stress relief function has increased its stress relaxation function
It replaces the stress relief function of layer 5. The effect of α-rays
In the case of a semiconductor device 13 having a region that does not receive any
Is a half of an area not affected by α rays as shown in FIG.
If it is arranged near the center of the conductor device 13, the semiconductor device 13
It is not necessary to form the stress relaxation layer 5 in the vicinity of the center.
No. Next, as another embodiment, the composition is different from that of the stress relaxation layer.
Examples of the stress relaxation layer containing fine particles will be described.
You. Fine particles contained in the above-described stress relaxation layer 5
Is the same material as the stress relaxation layer 5 and has the same physical properties.
You. Necessary for printing due to dispersion of fine particles in the stress relaxation layer
Viscoelastic properties. However, in this structure, the wafer and the stress relaxation
Thermal stress, etc., due to sudden changes in physical properties at the boundary with the sum layer 5
However, there is a possibility that wiring may be
You. Therefore, in this embodiment, the circuit type of the wafer is
The characteristics of the stress relaxation layer 5 formed on the surface
The characteristics of the stress relaxation layer on the wafer surface side
It was made to be close to the characteristic. Thus, the upper surface of the wafer and the lower part of the stress relaxation layer
Reduce the difference in properties at the boundary of the surface, and
Discontinuous force on the provided wiring or expansion and contraction of the stress relaxation layer
Do not apply tension, compression, or bending stress to the wiring.
By doing so, the disconnection of the wiring portion can be prevented. Further, the characteristics of the stress relaxation layer 5 on the wafer side
Is close to the wafer, and the substrate side on which the semiconductor device is mounted is
By approaching the characteristics of the substrate of FIG.
Not only wiring but also connection between the semiconductor device and the connection portion of the substrate
It is also effective for extending the life. Here, the stress relaxation layer 5 changes gradually in the thickness direction.
Characteristics such as thermal expansion coefficient or elastic modulus are considered.
Can be Then, a specific method of changing the characteristics of the stress relaxation layer
As shown in FIG.
In the thickness direction of the stress relaxation layer 5
Has a distribution of the amount of silica particles 102 added to it, and has a coefficient of thermal expansion
And gradually change the elastic modulus. Many silica particles 102
In the distributed part, the thermal expansion coefficient of the stress relaxation layer 5 is small.
The modulus of elasticity increases. On the other hand, blending of silica particles 102
As the amount decreases, the coefficient of thermal expansion increases and the elastic modulus decreases.
Become. Manufacturing process of the semiconductor device in this embodiment
Also, circuit formation on wafer, stress relaxation layer formation, silica particles
Distribution of silicon, formation of wiring on stress relaxation layer, etc. in wafer state
By doing so, simplification of the overall process and manufacturing variations
And the like, and the life of the wiring portion can be improved. In this embodiment, the modulus of elasticity and heat
Insulating particles to control expansion, silica and aluminum
One kind of particles made of inorganic materials such as boron and boron nitride
Or two or more types, and if necessary, polyimide or
Even if particles made of an organic material such as silicone are appropriately compounded.
Good. Further, the silica particles and the insulating resin layer are formed.
To improve the adhesion to various interfaces.
Coupling agents such as tantalate, elongation at break of resin
Modifiers such as thermoplastics to improve the breaking strength,
Prevents malfunctions of the circuit section formed on c due to ultraviolet rays etc.
Dyes and pigments to color the insulating resin layer
Incorporates a curing accelerator, etc. to accelerate the curing reaction of the layer
It is also possible. The stress relaxation layer 5 whose characteristics are changed in the thickness direction
As a method of forming, for example, the materials described above are blended
Liquid stress relaxation layer 5 is applied on the circuit surface of the wafer
Then, during the process of heating and curing this stress relaxation layer 5,
Insulating particles made of silica etc. are gradually settled on the wafer side
There is a method. If there is a distribution in the particle size of the silica particles,
Larger particles have faster sedimentation and smaller particles.
The lower the stress, the harder it is to settle.
When heat curing is performed, the distribution of characteristics in the thickness direction of the stress relaxation layer
Is formed. Film of silica particles blended in stress relaxation layer 5
As a method of controlling the concentration distribution in the thickness direction, insulating resin
The curing temperature and curing temperature profile of the
The amount and type of curing accelerator for accelerating the progress of curing,
Alternatively, appropriately add a reaction inhibitor etc. to delay curing
The particle size distribution of insulating particles such as silica particles
There is a method. The silica particles applicable to the present embodiment are:
Crushed ingot of lumps of silica,
After crushing Caingot, heat and melt the silica particles again
Applicable to spherical and synthetic silica particles
Noh. This particle size distribution and the amount of silica particles
The size, thickness and integration of the semiconductor device to which the example structure is applied
Degree, the thickness of the stress relaxation layer 5, the particle size of the particles,
Various changes can be made depending on the type. In the case where the stress relaxation layer 5 is formed by a printing method,
The size of the applied mask, depending on the printing method.
However, it may be necessary to change the particle size distribution.
You. The stress relaxation layer 5 is formed by one printing.
Need not be performed at least twice, as shown in FIG.
It may be formed by the above printing. In addition, each layer
Printing may be performed with different amounts of silica particles contained.
No. In this embodiment, the stress from the circuit portion of the wafer
Wiring is formed at the stage of reaching the electrode provided on the relaxation layer
Since the physical properties of the part do not change rapidly,
Power is not concentrated, and the disconnection of the wiring can be prevented.
You. Next, the semiconductor device 13 exists near the periphery of the semiconductor device 13.
The thickness of the stress relaxation layer 5 immediately below the bump 1
An example of an embodiment of the thinned semiconductor device 13 will be described with reference to FIG.
Will be explained. In this embodiment, the outermost bump 1a is
The height is lower by δ than the bump 1b inside one of them.
Has become. Stress Relaxation in Peripheral Part of Semiconductor Device 13
As a method for reducing the thickness of the layer 5, a paste-like poly
Minutes contained in stress relaxation layer forming materials such as imide materials
Presence or absence of particles, particle shape and composition, printing speed, plate release speed
Printing conditions such as the degree of printing,
There are ways to change them. Generally, it exists near the periphery of the semiconductor device 13.
The semiconductor device 13 is connected to the circuit board 14 on the bump 1a.
After loading, the load is different from other bumps 1b etc.
An extra large distortion has occurred. For example, with the semiconductor device 13
Since the coefficient of linear expansion with the circuit board 14 is different,
The bump 1a closer to the periphery of the semiconductor device 13
Large distortion occurs. If this distortion is large or repeated
In the case where the bumps 1
a is easily broken. As in this embodiment, the periphery of the semiconductor device 13 is
It is possible to reduce the thickness of the stress relaxation layer 5 in the vicinity.
It is possible to control the shape of the bump 1 at the spot
When connected to the circuit board 14, the bump 1 is shown in FIG.
The vertical bump 1aa as described above is obtained. Such a vertical bar
In the pump 1aa, the volume itself is the same as the other bumps 1.
Therefore, the contact angle between the bump 1 and the bump pad 3
Large contact angle between bump 1 and pad on circuit board 14
Become. That is, in FIG. 25, α1> α2, β1> β
It becomes 2. As the contact angle increases, bumps and
Stress concentration at the connection with the
You. As described above, the thickness of the stress relaxation layer 5 is
Other parts about the bump pad 3 formation location in the peripheral part
By making it thinner and making the shape of the bump 1 vertically long,
To improve the connection reliability between the body device 13 and the circuit board 14
I can do it. The sectional shape of the stress relaxation layer 5 is
When the height of the step 1 is in contact with the circuit board 14 of the semiconductor device 13,
It is possible to design within a range that does not hinder the subsequent
Various things can be considered. The magnitude of δ is as follows: (1) The vertical position at the outermost periphery
Stress relaxation characteristics required for long bump 1aa, (2) semiconductor
Bump height variation during function test of body device 13
(3) Connection of the semiconductor device 13 to the circuit board 14
Determined by taking into account the allowable value of bump height variation at the time of continuation
I do. More specifically, the stress relaxation characteristics described above
Calculated from the elastic modulus of the force relaxation layer 5 and the size of the semiconductor device 13.
You. On the other hand, regarding the variation at the time of functional inspection and connection,
Considering the deformation of the solder balls and the stress relaxation layer 5,
Find these tolerances. For example, the function test is on the top of the bump
Press the inspection jig to deform the stress relaxation layer 5
If there is no bump height variation,
Function test. Performed such an operation
However, the stress relieving layer 5 has a lower phase than the solder bump material.
Due to the low elastic modulus, stress rather than solder bump deformation
Deformation of the relaxation layer 5 occurs preferentially, and scratches on the solder bumps
There is no sticking. Therefore, from the stress relaxation property
The required value of δ is
Even if it becomes larger than the pump height variation,
As long as it can be accommodated by the deformation of the sum layer 5,
Absent. In addition, since the stress relaxation material is an elastic body,
The shape is restored after completion, so special connection is
No problem. Considering this, in effect,
Δ is determined from (1) and (3). Previous
As described above, the stress relaxation property is such that the thickness of the stress relaxation layer 5 is 35.
Good results with ~ 150 micrometers
From the stress relaxation characteristics, δ = 150−35 = 115
It becomes a chrome meter. Also, δ = 115 micrometer
Is allowed when connecting to the circuit board 14.
It is almost equal to the upper limit. Therefore, the value of δ is 115
In most cases, this is the upper limit. Further, the structure of this embodiment is similar to that of the semiconductor device.
Due to the progress of miniaturization, due to the wiring of the semiconductor device, the stress relaxation layer
Suitable when bumps must be formed on the slope
it can. In FIG. 24, the outermost bump 1a and its
Stress to make difference in height with bump 1b inside one
Although the thickness of the relaxation layer 5 is controlled, other control methods and
Then, there is a method by adjusting the structure of the protective layer 8. For example,
As shown in FIG. 40, protection is provided immediately below the outermost peripheral bump 1a.
Do not form the organic layer of the film 8 or make it very thin
In addition, the organic layer of the protective film 8 is formed inside the bump 1b.
Is formed thicker. Stress, if necessary
The thickness of the relaxation layer 5 and the thickness of the organic layer of the protective layer 8 are appropriately adjusted.
It is not possible to achieve the desired height difference δ by controlling
No problem. A van located at the outermost periphery of the semiconductor device
When soldering is easily affected by external forces and solder cracks, etc.
Some of the outermost bumps
May be used as a buffer member. In this case, the cushioning member
Electrically connected to the aluminum pad 7
Not necessary for the semiconductor device to operate electrically
It is desirable that This allows the semiconductor device to be powered
Other bumps required for pneumatic operation break
You can extend the period until you do. The buffer
For some bumps used as materials, increase the bump diameter.
To extend the time until the bump breaks.
Can be done. In this embodiment, the preferred bump diameter is increased.
Any known and commonly used method may be used,
To illustrate one particularly preferred method, the volume of the solder itself is
Keep the bump land (pack)
C). Making pads bigger
Increases the connection diameter, while the solder volume remains the same.
The bump height is lower due to the
Contact angle between bump and pad when connected to circuit board 14
Increases the stress concentration on the contact point between the bump and the pad.
Can be avoided. Solder by eliminating stress concentration
Crack progress in the inside and the bump diameter increases.
Breakage of crack length until breakage
Since the log value itself is also large, the bumps go up to the step
Will greatly contribute to the extension of the period. Further, the arrangement of the circuit board for connecting the semiconductor device is
Think from the perspective of facilitating the design of line drawers
And a power or ground line near the center of the semiconductor device.
It is desirable to place it as a result, as a result, FIG.
From the aluminum pad 7 and the aluminum pad as shown in FIG.
The wiring 4 for rewiring connecting the bump pads with a short distance of
As the signal line, the wiring for the most wiring connecting distant bump pads
Line 4 is preferably used as a power or ground line.
No. In this case, the bumps that are closer to the aluminum pad
It may be located on the inclined part of the stress relaxation layer 5. In addition,
Make the source or ground line wider than the signal line.
You may do it. FIG. 27 shows another embodiment of the semiconductor device.
In this embodiment, the stress relaxation layer 5 is formed as a wafer on which a semiconductor is formed.
Formed over the next semiconductor device 13 on the wafer 9
are doing. Aluminum pad 7, bump pad 3, and
The wiring 4 for rewiring connecting them is half the wiring 4 for rewiring.
Crossing the boundary between the conductor device 13 and the adjacent semiconductor device 13
The design is devised so that there is no such thing. Manufacturing
The process is basically the same as that already described,
There is a difference after seven steps. When cutting a semiconductor wafer, the stress is relaxed.
Although it is necessary to cut the sum layer 5, the stress relaxation layer 5 is made of a low elastic material.
Material, most of which are made of silicon and have different strengths
Batch cutting with the wafer 9 on which the semiconductor is formed
Is difficult. Therefore, first, the cutting of the stress relaxation layer 5
Then, the wafer 9 on which the semiconductor is formed is
To This will be described below with reference to FIG. First, in the seventh improvement step, only the stress relaxation layer 5
Disconnect. Cutting method includes cutting low elastic resin material
It is better to use a rotary blade suitable for In addition to carbonic acid
Gas laser or sandblasting can be used
You. In the eighth improvement step, the surface protection film 6
Then, a solder resist is applied on the entire surface. The application method
In addition to spin coating, a mesh-shaped mask
Printing or curtain coating may be used. Solder cash register
Stress relief in the seventh improvement process to apply the strike
The wall surface of the cut portion of layer 5 is not vertical but inverted V-shaped
It is desirable to do so. This coating is the seventh
By performing after cutting the stress relaxation layer in the good process, the stress
The relaxing layer 5 is located on the surface of the wafer 9 on which the semiconductor is formed.
It may cause peeling or degrade semiconductor performance.
Intrusion of foreign substances such as ions can be reduced, ensuring durability etc.
Device can be provided. In the ninth improvement step, photosensitive development is performed.
Thus, a pattern of the surface protection film 6 is formed. This
Only the bump pad 3 and the cutting portion 24 and the periphery thereof
It is exposed from the surface protection film 6. Also, the surface protective film 6 is
Electroless gold plating on the bump pad 3
A gold film is formed. In the examples, only gold plating was used.
But palladium or platinum plating before gold plating
It does not matter if tin plating is performed after gold plating.
There is no particular problem. In the tenth improvement step, dicing is performed.
The wafer 9 on which the semiconductor is formed by the
To divide. Generally, dicing is performed using a rotary blade.
Done. Through the above steps, the stress relaxing layer 5 is cut.
Of the semiconductor device 13 including the steps of FIG. According to the present embodiment, the outer shape of the semiconductor device 13
Even if the size is small, the stress relaxation layer 5 is formed without any problem.
It becomes possible. Specifically, two adjacent semiconductors
When forming the stress relaxation layer 5 over the device,
Even if the shape size is almost halved, the film forming technology of the stress relaxation layer 5
There is no need to change, the shape, external dimensions and
A cut margin for separating the semiconductor devices 13 from each other
By adjusting the width and shape of the cut portion 24, the size of the semiconductor device can be increased.
Manufacture using the same print mask even if it changes
It may even be possible. Also, the rewiring wiring 4 is
As in the case of the first embodiment, aluminum is passed through the inclined portion of the stress relaxation layer 5.
Because pad 7 and bump pad 3 are connected,
There is no stress concentration part in the wire 4
Unnecessary flip chip connection becomes possible. The structure according to the present embodiment is particularly suitable for semiconductors.
Semiconductor with pads laid out in the center of the device
Applicable to devices such as DRAM. In the drawings in the present embodiment, two adjacent
Of the stress relaxation layer 5 extending over the semiconductor device 13 of FIG.
However, the wiring 4 for rewiring is changed from the aluminum pad 7 to the bump pad.
At least as long as there is a slope to reach 3
Two or more semiconductor devices 13, for example, four adjacent to each other
Of the connected stress relaxation layer 5 for the semiconductor device of FIG.
It is also possible to adopt such a structure. Of course
Then, the stress relaxation layers 5 connected in two adjacent rows are formed.
And cut it. In this case,
Because it is a manufacturing method that can tolerate misalignment, it can be used for finer processing
Can also be applied. In each embodiment, for example, FIG.
It is recommended that the corners of the stress relaxation layer 5 be rounded as shown in FIG.
No. If not rounded, paste-like polyimide material
When printing the stress relaxation layer 5 using
Good is sometimes observed. Further, the stress relaxation layer 5 is peeled off from the corner.
Easy to release. When bubbles remain in the stress relaxation layer 5, a half
When the conductor device 13 is heated, the air bubbles burst, and
Failures such as breakage of the wire 4 occur. Therefore, the stress
Putter of metal mask for printing used to form relaxation layer 5
It is desirable that the corner of the opening 18 be rounded. The stress relaxation layer 5 in each embodiment is marked with a mark.
Print and apply using a printing metal mask or dispenser
Can be achieved. In addition to the printing method,
Blow, air or inert gas
Jet method, uncured or semi-cured resin sheet
Or by applying these methods.
They can be formed by appropriately combining them. Stress relaxation layer
When forming by the printing method, the inclination of the end of the printing part is
When printing and removing the print mask, or heat curing
In the process, the flow of the insulating layer occurs at the end, and the slope of the end
Is formed. In this method, the stress relaxation layer and the
And edges with specific inclination can be created at once
It is. On the other hand, when forming a stress relaxation layer by stamping,
If necessary, apply an insulating material to relieve stress on the stamping mold.
Insulation material to transfer the shape of the stress relaxation layer onto the wafer
Insulation material that does not change the shape of the edge during curing can be selected
It works. In this case, the shape of the edge is constant compared to the printing method
There is a feature that it is easy to become. In addition, insulating materials such as gas
In the method of spraying with a
Since no pumping mold is used, the shape when forming the stress relaxation layer
The degree of freedom is high and if the nozzle shape is selected appropriately,
Shape of stress relaxation layer that is difficult to form with a screen or stamping mold
Is possible. In addition, printing and stamping methods
In comparison, the thickness of the stress relaxation layer can be adjusted by adjusting the spray amount
The range of thickness adjustment is also widened. Semi-cured or uncured
In the method of attaching a resin sheet, a thick film stress relaxation layer
It is possible to use a sheet-shaped insulating resin in advance.
As a result, the surface of the stress relaxation layer has excellent flatness.
You. To combine these methods singly or as appropriate
It is possible to obtain more desired stress relaxation layer thickness and edge inclination
It becomes. Next, another embodiment of the semiconductor device will be described. FIG.
9 is mounted on a substrate for converting a bump electrode of a semiconductor device
FIG. 30 is a schematic cross-sectional view showing a state in which
The gap between the substrate 13 and the substrate on which it is mounted is sealed with a resin 118.
FIG. 4 is a schematic cross-sectional view showing a state in which the cover is folded. The protrusion-like electrode 1 formed on the semiconductor device 13 is
Solder paste on the corresponding electrode 120 on the substrate
Is mounted via flux, etc.
By melting the protruding electrodes, the substrate 115 and the semiconductor device 13
Make a connection. The substrate on which the semiconductor device is mounted is a semiconductor element
Mount on the substrate used for various electronic devices on the back of the mounting surface
120 and, if necessary, the protruding electrode 12
One. The semiconductor device 13 is used for various electronic devices.
When mounted on a substrate, the protruding electrodes provided on the substrate 115
It is necessary to heat and melt 121. These mounting processes
And reliability in various tests, especially for drop impact tests.
Semiconductor device 1 in order to further improve the reliability
3 and a substrate 115 reinforced with a resin 118.
You. The space between the semiconductor device 13 and the substrate 115 is filled.
The resin 118 is a liquid-state resin used for general semiconductor sealing.
Epoxy resin, phenol resin, polyimide resin, silicon
Cone resin etc. can be used, and thermal expansion coefficient of sealing resin
Silica, alumina, boron nitride to adjust the modulus of elasticity
One or more particles made of inorganic materials such as
Blend, if necessary, silicone or thermoplastic resin, etc.
Cup made of resin, alkoxysilane, titanate, etc.
Ring agent, colorant, flame retardant for imparting flame retardancy,
Acceleration of curing for accelerating curing reaction of flame retardant auxiliary resin layer
It is possible to mix agents and the like. In this embodiment, the protruding electrodes on the semiconductor device
Pitch and substrate electrode used in various electronic devices
Even if the pitch is different,
Thus, connection to various electronic devices becomes possible. The same as mounting on a substrate to be a semiconductor device.
To mount on a circuit board used for general electronic equipment.
The same applies to the case. According to the present invention, no underfill is required.
Semiconductor device that enables simple flip-chip connection
It is.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a partial cross-sectional view showing a structure of an embodiment of a semiconductor device of the present invention. FIG. 2 is a plan view showing a state in which the semiconductor device of this embodiment is continuously formed. FIG. 3 is a diagram (1) showing an example of a manufacturing process of a semiconductor device of the present invention; FIG. 4 is a diagram (2) showing an example of a manufacturing process of a semiconductor device of the present invention; FIG. 3 shows an example of the manufacturing process of the device. FIG. 6 shows a printing mask used for forming the stress relaxation layer of the present invention. FIG. 7 shows a process of printing the stress relaxation layer. FIG. 8 is a view showing a plate separation process in which a print mask is raised from a wafer. FIG. 9 is a view showing a semiconductor device on which a stress relaxation layer is formed. FIG. FIG. 11 shows an example of rewiring wiring. FIG. 12 shows another example of rewiring wiring. FIG. 13 is a diagram showing insufficient development of the actual rewiring wiring pattern. FIG. 14 is a diagram showing another example of the rewiring wiring. FIG. 15 is another example of the rewiring wiring. FIG. 16 is a view showing another example of the wiring for rewiring. FIG. 17 is a view showing a semiconductor device which has gone through the seventh step in the present invention. FIG. 19 is a diagram showing the relationship between the thickness of the stress relaxation layer and α rays. FIG. 20 is a diagram showing one embodiment of the structure of the semiconductor device of the present invention. FIG. FIG. 22 shows an embodiment of the structure of the semiconductor device. FIG. 22 shows an embodiment of the structure of the semiconductor device of the present invention. FIG. 23 shows an embodiment of the structure of the semiconductor device of the present invention. FIG. 25 is a diagram showing a semiconductor device in which the thickness of a stress relaxation layer is partially reduced. FIG. 26 is a diagram showing a state in which a body device is connected to a circuit board. FIG. 26 is a diagram showing one embodiment of the structure of the semiconductor device of the present invention. FIG. FIG. 28 illustrates a method of cutting the stress relaxation layer. FIG. 29 illustrates an embodiment in which a semiconductor device is mounted on a substrate. FIG. 30 illustrates mounting of a semiconductor device on a substrate. FIG. 31 shows a conventional semiconductor device. FIG. 32 shows a state in which the conventional semiconductor device is connected to a circuit board. FIG. 33 shows the structure of the semiconductor device of the present invention. FIG. 34 is a diagram showing another embodiment of the structure of the semiconductor device of the present invention. FIG. 35 is a diagram showing another embodiment of the structure of the semiconductor device of the present invention. FIG. 37 shows another embodiment of the structure of the semiconductor device of the present invention. FIG. 37 shows the semiconductor device of the present invention. FIG. 38 is a diagram showing another embodiment of the structure of the semiconductor device of the present invention. FIG. 39 is a diagram showing another embodiment of the structure of the semiconductor device of the present invention. 40 is a view showing another embodiment of the structure of the semiconductor device of the present invention. FIG. 41 is a view showing the relationship between the glass transition temperature and the linear expansion coefficient. [Description of References] 1. Bump, 1aa. 2 ... Au plating, 3
... Bump pads, 4 ... Rewiring wiring, 5 ... Stress relaxation layers,
6 ... surface protective film, 7 ... aluminum pad, 8 ... protective film, 9 ...
Semiconductor-formed wafer, 10 bump, 11 metal wiring, 12 insulating layer, 13 semiconductor device, 14 circuit board, 15 underfill, 16 power supply film, 17 reverse pattern of wiring, 18 ... Connection portion between aluminum pad and wiring, 19: boundary between lower layer portion, 20: gap, 21: exposure mask, 22: resist, 23: connection portion with aluminum pad, 24: cut portion, 25: stencil made of nickel alloy,
26 ... resin sheet, 27 ... frame, 28 ... pattern opening of print mask, 102 ... silica particles, 110 ... memory cell, 115 ... substrate, 116 ... electrode, 118 ... resin, 12
0 ... electrode, 121 ... electrode

────────────────────────────────────────────────── ─── Continued on the front page (51) Int.Cl. ⁷ Identification code FI H01L 23/29 H01L 23/30 B 23/31 (72) Inventor Noriyuki 292 Yoshidacho, Totsuka-ku, Yokohama-shi, Kanagawa Hitachi, Ltd. Production Technology Laboratory (72) Inventor Hiroyuki Hozoji 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Hitachi, Ltd. Production Technology Laboratory (72) Shigeharu Tsunoda 292, Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa, Inc. Hitachi, Ltd. Production Technology Research Laboratory (72) Inventor Naoya Isada Kanagawa Prefecture, Yokohama City, Totsuka-ku, Yokohama 292, Yoshida-cho, Ltd. (72) Inventor Minagawa Yen Kanagawa Prefecture, Yokohama City, Totsuka-ku, Yokohama 292, Japan Stock (72) Inventor Ichiro Yasuo, Hitachi, Ltd. 5-2-1, Josuihoncho, Kodaira-shi, Tokyo Stock Company Hitachi, Ltd. Semiconductor Group (72) Inventor Asao Nishimura 5--20-1, Josuihoncho, Kodaira-shi, Tokyo Tokyo, Japan Inventor (72) Inventor Kenji Ujiya 5--20, Josuihoncho, Kodaira-shi, Tokyo No. 1 Within Hitachi, Ltd. Semiconductor Group (72) Inventor Akira Yajima 5-20-1, Kamimizuhonmachi, Kodaira-shi, Tokyo Within Hitachi, Ltd. Semiconductor Group (56) References JP-A-11-191571 (JP) JP-A-2000-1664761 (JP, A) JP-A-7-202362 (JP, A) JP-A-11-274365 (JP, A) JP-A-11-191572 (JP, A) JP-A-11 JP-A-147950 (JP, A) JP-A-10-242333 (JP, A) JP-A-8-274243 (JP, A) JP-A-9-199635 (JP, A) JP-A 2001-118956 (JP, A) Dictionary of Electronics Packaging Technology Glossary, Industrial Research Institute, Ltd., January 20, 1992, First Edition, First Edition, Page 103, see "Screen Printing" (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/312-21/318 H01L 21/32 H01L 21/47-21/475 H01L 21/60 H01L 23/12-23/15

Claims (1)

(57) Claims 1. A semiconductor element and an insulating material printed on the semiconductor element using a mask.
An insulating layer having an inclined portion formed as described above, an external connection terminal formed on the insulating layer, and an external connection terminal formed on the insulating layer, and
Wiring for electrically connecting the circuit electrodes of the body element, and the thickness of the insulating layer is 35 μm to 150 μm.
Chrome, the slope of the insulating layer and the thickness of the insulating layer.
Near the boundary of the flat part where the
A semi-conductive material characterized by having a high bulge portion
Body device. 2. A semiconductor device, an electrode pad formed on the semiconductor device, and a region on the semiconductor device but not covering the pad.
Formed by printing insulating material on the area using a mask
An insulating layer having an inclined portion, an external connection terminal formed on the insulating layer, and an electrical connection between the pad and the external connection terminal.
Has a wiring formed on the insulating layer, and the thickness of the insulating layer is 35 μm to 150 μm.
Chrome, the slope of the insulating layer and the thickness of the insulating layer.
Near the boundary of the flat part where the
A semi-conductive material characterized by having a high bulge portion
Body device. 3. The semiconductor device according to claim 1, wherein
The insulating layer has particles.
apparatus. 4. The semiconductor device according to claim 3, wherein
The particles spread and distribute in the insulating layer, and change the shape of the insulating layer.
A semiconductor device characterized by controlling. 5. The half of any one of claims 1 to 4,
A conductor device, wherein the particles are made of the same material as the insulating material forming the insulating layer.
A semiconductor device characterized by the following. 6. The half of any one of claims 1 to 4.
A conductor device, wherein the diameter of the particles is 10 micrometers or less.
Semiconductor device. 7. The half of any one of claims 1 to 4,
A conductor device, wherein the thickness of the insulating layer is 1/20 to 1 of the thickness of the semiconductor element.
/ 5. 8. The half of any one of claims 1 to 4,
A conductor device, wherein an inclination of an inclined portion of the insulating layer is inclined with respect to a circuit surface of the semiconductor element.
5% to 30%. 9. The half of any one of claims 1 to 4
A conductor device, wherein an elastic modulus of the insulating layer is 0.1 GPa to 10 GPa.
A semiconductor device characterized by the above-mentioned. 10. The method according to claim 1, wherein:
A semiconductor device, wherein the insulating layer has a curing temperature of 100 to 250 degrees Celsius.
The material according to claim 1, wherein the material is made of a material.
4. The semiconductor device according to 3. 11. The method according to claim 1, wherein
A semiconductor device, wherein the insulating layer has a glass transition temperature of 150 to 400 degrees Celsius.
A semiconductor device, characterized in that: 13. The method according to claim 1, wherein
A semiconductor device, wherein a thermal decomposition temperature of the insulating layer is 300 to 450 degrees Celsius.
Semiconductors and wherein the Rukoto. 14. The method according to claim 1, wherein
A semiconductor device, wherein the insulating layer is at least polyimide, polyamide,
Made of midimide, epoxy, or silicone
A semiconductor device characterized by being performed. 15. A method of manufacturing a semiconductor device , wherein an insulating material is formed on a wafer so that circuit electrodes of the wafer are exposed.
The material is printed using a mask and has a thickness of 35 micrometer.
Forming an insulating layer that is between Torr and 150 micrometers.
A first step, from the circuit electrode of the wafer to the inclined portion and the flat portion of the insulating layer.
A second step of forming a wiring, and an external connection terminal electrically connected to the wiring and the circuit electrode.
A third step of forming a mask on the insulating layer, wherein the printing step includes a squeegee in a diagonal direction of the opening of the mask.
To print the insulating material to form the insulating layer.
A method of manufacturing a semiconductor device. 16. A method of manufacturing a semiconductor device , wherein an insulating material is provided on a wafer so that circuit electrodes of the wafer are exposed.
The material is printed using a mask and has a thickness of 35 micrometer.
Forming an insulating layer that is between Torr and 150 micrometers.
A first step, from the circuit electrode of the wafer to the inclined portion and the flat portion of the insulating layer.
A second step of forming a wiring, and an external connection terminal electrically connected to the wiring and the circuit electrode.
A third step of forming a mask on the insulating layer, wherein in the printing step, a pair is formed from the top with respect to the opening of the mask.
Move the squeegee to the opposite vertex and print the insulating material
Forming the insulating layer by performing
Production method. 17. The semiconductor device according to claim 15, wherein
A method for manufacturing a semiconductor device , wherein the insulating material has particles.
Manufacturing method. 18. A method for manufacturing a semiconductor device according to claim 17.
The particles are made of the same material as the insulating material forming the insulating layer.
A method of manufacturing a semiconductor device, comprising: