JP3447584B2 - Successive approximation type analog / digital converter - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a successive approximation A / D converter equipped with a test mode for measuring input leakage characteristics and the like, and more particularly to a successive approximation A / D converter with a shortened measurement time.
Regarding the converter.

[0002]

2. Description of the Related Art Conventionally, successive approximation type A / D converters have been used as analog / digital (A / D) converters. FIG. 7 is a block diagram showing a conventional successive approximation A / D converter.

In the conventional successive approximation A / D converter, switches T10 to T17 are provided on the input signal lines for transmitting the analog input signals AN10 to AN17, respectively. A channel selector 13 is connected to the switches T10 to T17.
Output analog output terminal selection signals SL10 to SL17 to the switches T10 to T17. The channel selector 13 has a channel designation signal SLN1.
Is entered.

Further, the respective input signal lines are commonly connected and connected to the sample hold circuit 12. The sample-hold circuit 12 is provided with a capacitor CT1 whose one electrode is grounded and a switch TT1 for switching between conduction / non-conduction between the capacitor CT1 and the input signal line.
It should be noted that the sample and hold circuit 12 has an input signal ANI.
N1 is input. Analog input terminal selection signal SL10
When any of SL1 to SL17 is effective, any of the corresponding analog input signals AN10 to AN17 becomes the input signal ANIN1. In addition, the switch TT1 has
The sampling signal SMP1 is input.

Further, the conventional successive approximation A / D converter is connected with the comparator 11 connected to the capacitor CT1 in the sample hold circuit 12. Comparator 11
Receives the output of the sample and hold circuit 12 and the reference voltage, and when the switch TT1 is effective, the input signal ANIN1 is transmitted to the capacitor CT1 and the comparator 11.

[0006] The conventional successive approximation type A configured as described above
The operation of the / D converter will be described. FIG. 8 is a flowchart showing the operation of the conventional successive approximation A / D converter.

In the conventional successive approximation type A / D converter, first, the channel designation signal SLN1 is input to the channel selector 13, and any one of the analog input terminal selection signals SL10 to SL17 is selected and made effective. (Step S21). When any one of the analog input terminal selection signals SL10 to SL17 becomes valid, any one of the corresponding switches T10 to T17 becomes valid, and the corresponding analog input signal AN10 to AN.
Any one of 17 becomes the input signal ANIN1.

After that, A / D conversion is started (step S22).

Next, it waits for the timing at which the sampling signal SMP1 becomes valid (step S23).

When the sampling signal SMP1 becomes valid, the switch TT1 becomes valid. Then, the input leak characteristic in the sample hold circuit 12 or the like is measured (step S24).

After that, it is judged whether or not the measurement object is changed (step S25).
Returning to step 21, the channel is selected.

[0012]

However, the channel is selected for the measurement of the input leak characteristic in the sample hold circuit 12 of the analog input terminal in the conventional successive approximation type A / D converter configured as described above. However, there is a problem in that it takes a long time to measure the input leakage characteristic because a step of stopping the clock in synchronization with the sampling timing is required.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a successive approximation type A / D converter capable of shortening the measurement time of the input leak characteristic.

[0014]

A successive approximation type analog-to-digital converter according to the present invention has multiple test modes.
In the heavy-duty successive approximation type analog / digital converter,
A plurality of analog input terminals, selection means for selecting at least one from among a constantly plurality of said analog terminal during a test mode as an object of testing, the A selected
The analog signal transmitted through the analog terminal is
Sample hold circuit to hold and this sample hole
Comparing the analog signal held in the drive circuit with the reference voltage
And a comparator that outputs the result to a register,
The sample and hold circuit has a reference to one electrode.
A potential is applied and the analog signal is applied to the other electrode.
Generated based on the clock signal and the capacitor
The sampling signal is always input and the test mode
The test mode signal is input when switching to the
Logical sum of the sampling signal and the test mode signal
To the output of this mode switching circuit and the mode switching circuit
The selected analog input terminal based on the
Switch to high impedance state
And a switch for changing the mode
To the analog signal transmitted via the selected analog terminal.
A log signal is applied to the capacitor and this selected
It is characterized in that the input leak characteristic of the analog terminal is measured .

In the present invention, since at least one of the plurality of analog terminals is always selected as a test target during the test mode by the selecting means, the conventional channel is selected and matched with the sampling timing. There is no need for the process of stopping the clock. Therefore, the time for measuring the input leak characteristic such as the leak current is shortened.

[0016]

[0017]

Further, the selection means includes a plurality of input terminal switches connected between each of the analog input terminals and the mode changeover switch, and a plurality of the input terminal switches being turned on and off. And a channel selector that switches between states.

Furthermore, the test mode signal is also input to the channel selector,
When the test mode signal is input,
The input terminal switch can be turned on .

[0020]

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION A successive approximation A / D converter according to an embodiment of the present invention will be specifically described below with reference to the accompanying drawings. 1 is a block diagram showing a successive approximation A / D converter according to a first embodiment of the present invention.

In the successive approximation A / D converter according to the first embodiment, switches T0 to T7 are provided on the input signal lines connected to the input terminals to which the analog input signals AN0 to AN7 are input. There is. Switches T0 to T
A channel selector 3 is connected to 7 and analog input terminal selection signals SL0 to SL7 are output from the channel selector 3 to the switches T0 to T7, respectively.
The channel selector 3 receives the channel designation signal SLN and the test mode signal SLT.

The respective input signal lines are commonly connected and connected to the sample hold circuit 2. The sample-hold circuit 2 has a capacitor C whose one electrode is grounded.
T, a switch TT for switching between conduction and non-conduction between the capacitor CT and the input signal line, and a mode switching circuit MO which is an OR circuit connected to the switch TT are provided. Switch TT by mode switching circuit MO
Is switched between the on state and the off state. The input signal ANIN is input to the sample hold circuit 2 . When any of the analog input terminal selection signals SL0 to SL7 is valid, the corresponding analog input signal AN
Any one of 0 to AN7 becomes the input signal ANIN. In addition, the mode switching circuit MO has a sampling signal SMP.
And the test mode signal SLT is input.

Further, the successive approximation A / D converter according to the present embodiment is connected with the comparator 1 connected to the capacitor CT side of the switch TT in the sample hold circuit 2. The comparator 1 receives the output of the sample hold circuit 2 and the reference voltage, and when the mode switching circuit MO and the switch TT are valid, the input signal ANIN is transmitted to the capacitor CT and the comparator 1.

Next, the operation of the successive approximation A / D converter of the first embodiment constructed as described above will be explained.
FIG. 2 is a flowchart showing the operation of the successive approximation A / D converter according to the first embodiment of the present invention. FIG. 3 is a block diagram showing the successive approximation A / D converter according to the first embodiment when the test mode signal SLT becomes valid.

In this embodiment, the sampling signal S
When the MP is valid and the channel designation signal SLN is input to the channel selector 3, the test mode signal SLT
Is enabled (step S1). Test mode signal SL
When T becomes valid, all of the analog input terminal selection signals SL0 to SL7 output from the channel selector 3 become valid at the same time as shown in FIG.
T is also valid.

Then, the analog signal is input only to the input terminals whose input leak characteristics are to be measured, and the other seven input terminals are all set to the high impedance (HiZ) state, and the input leak characteristics such as the leak current are measured. Yes (step S2).

Thereafter, it is judged whether or not the measurement object is changed (step S3), and if it is changed, the step S1 is performed.
Return to and select a channel.

As described above, in this embodiment, when the test mode signal SLT is enabled, all the analog input signals AN0 to AN7 are simultaneously transmitted to the capacitor CT, so that the channel is selected and the sampling timing is set. The step of stopping the clock is also unnecessary. Therefore, the time for measuring the input leak characteristic such as the leak current in the sample hold circuit 2 of the analog input terminal is shortened.

Next, a second embodiment of the present invention will be described. In the second embodiment, the test mode signal is not input to the channel selector. FIG. 4 is a block diagram showing a successive approximation A / D converter according to the second embodiment of the present invention. It should be noted that in the second embodiment shown in FIG.
The same components as those of the first embodiment shown in FIG. 11 are designated by the same reference numerals, and detailed description thereof will be omitted.

Although the channel selector 4 connected to the switches T0 to T7 is provided in the second embodiment, the test mode signal SLT is not input to the channel selector 4 as described above. Other configurations in the second embodiment are similar to those in the first embodiment.

Next, the operation of the successive approximation type A / D converter of the second embodiment constructed as described above will be explained. FIG. 5 is a flowchart showing the operation of the successive approximation A / D converter according to the second embodiment of the present invention. 6 shows the analog input terminal selection signal SL0 and the test mode signal S.
It is a block diagram which shows the successive approximation type A / D converter which concerns on 2nd Example when LT becomes effective.

In this embodiment, first, the channel designation signal SLN is input to the channel selector 4, and any one of the analog input terminal selection signals SL0 to SL7 is selected and validated (step S11). When any one of the analog input terminal selection signals SL0 to SL7 becomes valid, any one of the corresponding switches T0 to T7 becomes valid, and any one of the corresponding analog input terminal selection signals AN0 to AN7 becomes an input signal. ANI
N.

Next, the test mode signal SLT is validated (step S12). When the test mode signal SLT becomes valid, the switch TT becomes valid. For example, when the analog input terminal selection signal SL0 and the analog input terminal selection signal SLT become valid, as shown in FIG. 6, the analog input signal AN0 becomes the input signal ANIN of the sample hold circuit 2 and is transmitted to the capacitor CT. It That is, the input terminal to which the analog input signal AN0 is input is selected as the measurement target of the input leak characteristic.

Then, the input leak characteristic such as the leak current in the sample hold circuit 2 is measured (step S13).

After that, it is judged whether or not the measurement object is changed (step S14).
Returning to 11, the channel is selected.

In the present embodiment, it is possible to measure the leak characteristic in the sample hold circuit 2 of the analog input terminal only for the terminal designated by the channel designation signal SLN. As a result, a step of designating the channel is required, but it is effective in that the off-leakage characteristic of the terminal not designated can be measured.

[0038]

As described in detail above, according to the present invention,
In the test mode, a selection means for constantly selecting at least one from a plurality of analog terminals to be tested is provided.
Since set only by that can as <br/> Engineering that selects the conventional such channels stop clock in accordance with the timing of sampling was not required, to reduce the time of input leakage characteristic measurement such as leakage current .

[Brief description of drawings]

FIG. 1 is a successive approximation A / D according to a first embodiment of the present invention.
It is a block diagram which shows a converter.

FIG. 2 is a successive approximation A / D according to the first embodiment of the present invention.
It is a flowchart which shows operation | movement of a converter.

FIG. 3 is a block diagram showing a successive approximation A / D converter according to a first embodiment when a test mode signal SLT becomes valid.

FIG. 4 is a successive approximation A / D according to a second embodiment of the present invention.
It is a block diagram which shows a converter.

FIG. 5 is a successive approximation A / D according to a second embodiment of the present invention.
It is a flowchart which shows operation | movement of a converter.

FIG. 6 is a block diagram showing a successive approximation A / D converter according to a second embodiment when an analog input terminal selection signal SL0 and a test mode signal SLT are valid.

FIG. 7 is a block diagram showing a conventional successive approximation A / D converter.

FIG. 8 is a flowchart showing the operation of a conventional successive approximation A / D converter.

[Explanation of symbols]

1, 11; comparators 2, 12; sample and hold circuits 3, 4, 13; channel selector MO; mode switching circuits T0, T1, T7, T10, T11, T17, TT, T
T1; switches AN0, AN1, AN7, AN10, AN11, AN1
7: Analog input signals SL0, SL1, SL7, SL10, SL11, SL1
7; analog input terminal selection signals SLN, SLN1; channel designation signals SMP, SMP1; sampling signal SLT; test mode signals ANIN, ANIN1; input signals CT, CT1; capacitors

─────────────────────────────────────────────────── --- Continuation of the front page (56) References JP-A-9-27750 (JP, A) JP-A-3-198428 (JP, A) JP-A-55-82540 (JP, A) JP-A-6- 120826 (JP, A) JP 1-135321 (JP, A) JP 10-135832 (JP, A) JP 8-77789 (JP, A) JP 7-264071 (JP, A) Unexamined Japanese Patent Publication No. 4-129332 (JP, A) SHO 61-149491 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03M 1/00-1/88

Claims (3)

(57) [Claims] 1. A multiple successive approximation type analog-to-digital converter having a test mode, wherein a plurality of analog input terminals and at least one of the plurality of analog terminals are constantly tested during a test mode. selecting means for selecting as a target, through the analog terminals that are selected
Hold the analog signal transmitted by
Held by the sample and hold circuit.
The analog signal is compared with a reference voltage and the result is
A comparator for outputting to a register,
The pull-hold circuit has a reference potential applied to one electrode.
Capacitor to which the analog signal is applied to the other electrode
And the sampling signal generated based on the clock signal.
Signal is always input and switches to the test mode
When the test mode signal is input, the sampling signal
And a mode switch that outputs the logical sum of the test mode signal and
Switching circuit and the selection based on the output of this mode switching circuit.
Connect the selected analog input terminal to the capacitor
Mode switching to switch between high impedance and high impedance
Switch for, and has been selected in the test mode
The analog signal transmitted through the analog terminal is
Of the selected analog terminal applied to the capacitor
A successive approximation type analog-to-digital converter characterized in that input leak characteristics are measured . 2. The selection means comprises a plurality of input terminal switches connected between each of the analog input terminals and the mode switching switch, and a plurality of the input terminal switches being turned on and off. successive approximation analog / digital converter according to claim 1, characterized in that it comprises a channel selector for switching between the state, the. 3. The test mode signal is also input to the channel selector, and the channel selector
All the input terminals when a test mode signal is input
The child switch is turned on.
2. The successive approximation type analog / digital converter described in 2 .