JPH03198428A - A/d converter - Google Patents

Abstract

PURPOSE:To optimize the resolution in A/D conversion in accordance with a system to be measured by generating plural reference voltages from the voltage applied to a reference power supply terminal and selecting one of them as the internal reference voltage by a mode register. CONSTITUTION:An external reference voltage VREF is applied to a reference power terminal 12, and one of voltages VA to VD at respective taps of a resistance array 205 is supplied to a voltage follower 23 through one of transfer gates 201 to 204 driven by outputs 211 to 214 from a mode register 21. The voltage follower 23 supplies an internal reference voltage VR to the output by impedance conversion. This internal reference voltage VR can freely be changed by a CPU 11. Thus, the resolution of conversion is optimized in accordance with various conversion objects.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an A/D converter, and more particularly to an A/D converter that is built in a one-chip microcomputer and controls switching of a reference power source.

[Conventional technology]

Conventionally, an A/D converter built into this type of one-chip microcomputer performs A/D conversion using one reference voltage.

FIG. 4 is a circuit diagram of an A/D converter showing an example of such a conventional A/D converter.

As shown in FIG. 4, in the conventional A/D converter, an analog input voltage VIN input to an analog input terminal 1 is sampled by a sample-and-hold circuit 2 and supplied to one input of a comparator 3. The other input of the comparator 3 is supplied with the output voltage of the D/A converter 6 whose maximum value is the external reference voltage (reference voltage) v02 input to the reference power supply terminal 12, and the sample & hold circuit 2
The comparator 3 compares the magnitude relationship with the output voltage. The digital output 4 of the comparator 3 is determined one bit at a time starting from the most significant bit (MSB) of the comparison register 5, and the process is repeated up to the least significant bit (LSB). D/A that takes the output cuff of the final comparison register 5 as input
The output voltage of the converter 6 approaches the analog input voltage VIH as the conversion progresses toward the LSB side. These sample and hold circuits2. The comparator 3 and the sequential comparison register 5 are controlled by outputs 131 to 133 of the control circuit 13, respectively, and an interrupt signal (
INT) 134 is generated. The digital value of the instant comparison register 5 when the interrupt signal 134 is generated is taken into the conversion result register 8.

On the other hand, the CPU II receives this interrupt signal (I) from the control circuit 13.
NT) 134 and recognizes that one A/D conversion has been completed, the CPU II generates a read signal 9 and takes in the digital value of the conversion result register 8 via the data bus 10.

[Problem to be solved by the invention]

The conventional A/D converter described above has only one reference power supply terminal, so even if the voltage range of the analog input voltage changes, the resolution of A/D conversion cannot be optimized. There is.

For example, in an 8-bit A/D converter, if the analog input voltage VrN ranges from 0 to 5 V, and if the external reference voltage VREF is 5 V, then the resolution of the A/D converter is 5 V. /2"=19.5mV. However, the range of analog input voltage is Ov~4v.
When performing A/D conversion on a conversion target, VRBA is 5v
As it is, its resolution is 19.5 mV, which is the same as above. Therefore, to optimize the resolution, VRB should be set to 4
As for (2), it is necessary to increase the resolution to 4'V/2'=15.6mV.

In this way, in the conventional A/D converter, the reference voltage is fixed to one type, so there is a drawback that the resolution cannot be optimized in accordance with various conversion targets. On the other hand, in order to optimize the resolution, if the voltage VRRF supplied to the reference power supply terminal is made variable externally, the cost of the entire system using an L-chip microcomputer with a built-in A/D converter becomes high.
There is a drawback that it becomes

An object of the present invention is to provide an A/D converter that can optimize the conversion resolution according to the various conversion targets.

[Means to solve the problem]

The A/D converter of the present invention includes means for generating a plurality of reference voltages having the reference voltage as a maximum value from a reference voltage supplied to a reference power supply terminal, and a means for generating a plurality of reference voltages having a maximum value of the reference voltage, and selectively selecting any one of the plurality of reference voltages. and means for supplying the same.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an A/D converter showing a first embodiment of the present invention.

As shown in FIG. 1, the basic A/D conversion operation of this embodiment is similar to the operation of the conventional example described above, and the analog input voltage VIH input from the analog input terminal 1 is /N) is input to 2. Under the control of the output 131 of the control circuit 13, the sample and hold circuit 2 is initially in a sampling state and inputs vrN. Thereafter, during conversion, the S/H circuit 2 enters a hold state and works to hold VfN. The comparator 3 receives the held analog human power VIH and the output voltage of the D/A converter 6, which uses the internal reference voltage 8 as a reference voltage. That is, depending on the magnitude relationship, the output 4 of the comparator 3 is compared and determined bit by bit in order from the MSB of the instant comparison register 5, and this is repeated until LSH is determined. Since the output of the final comparison register 5 becomes the input to the D/A converter 6, first set the output value of the D/A converter 6 to the value of A in internal reference voltage 8. , and thereafter, as the conversion progresses from the MSB side to the LSB side, the output voltage of the D/A converter 6 approaches the analog human power VIH. The comparator 3 and the final comparison register 5 are controlled by the outputs 132 and 133 of the conversion control circuit 13, respectively, and an interrupt signal (INT) 134 is output when the conversion is completed.
occurs. The contents of the instant comparison register 5 (containing the digital value of the conversion result) when this interrupt signal (INT) 134 is generated are taken into the conversion result register 8.

On the other hand, the CPU II, informed of the end of the conversion by the interrupt signal (INT) 134, outputs the read signal 9 and takes in the contents of the conversion result register 8 via the data bus 10.

In the above conversion operation, the internal reference voltage VR is supplied by the reference voltage selection circuit 20 and the voltage follower 23. That is, an external reference voltage V□2 is applied to the reference power supply terminal 12, and the voltages VA, v of each tap of the resistor array 205 are applied to the reference power supply terminal 12.
,,vc,VD(VRIIP"VA>VB>VC>VD
>0V) (7) is supplied to the voltage follower 23 via any one of the transfer gates 201 to 204 driven by the outputs 211 to 214 from the mode register 21. This voltage follower 2
3 converts the impedance and supplies the internal reference voltage v8 to the output.

For example, if only 212 of the outputs 211 to 214 of the mode register 21 becomes high level, only the transfer gate 202 becomes conductive, and becomes Vn''VB.

In this way, data can be written to and read from the conversion result register 8 via the data bus 10 by the control signal 22 from the CPU 1l to the mode register 21, so that the internal reference voltage vR is
It can be freely changed by I.

FIG. 2 is a circuit diagram of an A/D converter showing a second embodiment of the present invention, and FIG. 3 is a timing diagram of various signals for explaining the conversion operation in FIG. 2.

As shown in FIG. 2, the basic A/D conversion operation of this embodiment is similar to that of the first embodiment described above, but in this embodiment, four multiplexed analog input terminals are used. 101 to 104. It also has a timing generation circuit 24 whose control is defined by the output 215 of the mode register 21.
4, analog input terminals 101 to 104 become 1.
It is selected sequentially for each conversion (so-called scan mode). Furthermore, the reference voltage selection circuit 20 is switched in conjunction with this scan mode, and each analog human power VrN+
The internal reference voltage VR for each ~VrN4 is automatically set.

In the operation of the A/D converter, as shown in FIG. 3, first, the CPU II sends out a control signal 22 to set data in the mode register 21 via the data bus 10. Now, the modes are outputs 105, 2111106, 212, 107, and 213 of the timing generation circuit 24.
．． It is assumed that signals of the same phase are generated at 108 and 214, respectively.

First, in the first conversion, the outputs 105 and 211 of the timing generation circuit 24 become high level, and the transfer gate 109 of the analog input selection circuit 100 becomes conductive, so that the analog input voltage V[Nl of the analog input terminal 101 becomes Selected as a target for A/D conversion. Also,
Transfer gate 2 of reference voltage selection circuit 20
01 becomes conductive, and vA (=vO, ) becomes the internal reference voltage v8. That is, in the first conversion, the analog input voltage vrN+ is A/D converted using the reference voltage vA as the full scale. The operation in which the interrupt signal (IJT) 134 is generated at the end of the conversion and the conversion value is taken into the conversion result register 8 is the same as in the first embodiment described above.

Similarly, in the second, third, and fourth conversions, the output signals of the timing generation circuit 24 are 106 and 2, respectively.
The level becomes high in the order of 12.107, 213.108, and 214. Therefore, the transfer gates 110 to 112 of the analog input selection circuit 100 become conductive in order, and the inputs vrN2 of the analog input terminals 102 to 104
r V INS rVIN4 is sequentially selected as a conversion target. At the same time, the transfer gates 202 to 204 of the reference voltage selection circuit 20 are sequentially turned on, and Va, Vo, and VD are sequentially selected as the internal reference voltage VR. Therefore, in the second conversion, the analog input voltage Vnu is set to the reference voltage VB at full scale, and in the third conversion, the analog input voltage Vnu is set to V□9. But ■. and full scale, and in the fourth conversion, VIN4 was converted with VD as full scale.

In this embodiment, four types of voltages can be selected as the internal reference voltage using the mode register 21, but there is no particular limit to this number, and the mode register 21
It is clear that the number of voltage types can be set as many as determined by the bit width of 1.

〔Effect of the invention〕

As explained above, the A/D converter of the present invention has a means for generating a plurality of reference voltages from a voltage applied to a reference power supply terminal, and a mode register to internally generate one of the plurality of reference voltages. By providing a means to select as a reference voltage,
It is now possible to freely change the reference voltage,
This has the effect that the resolution in A/D conversion can be optimized depending on the system to be measured. Furthermore, the A/D converter of the present invention eliminates the need for control to vary the voltage supplied to the reference power supply terminal depending on the system under test even in an application system using a one-chip microcomputer that incorporates the A/D converter. This has the effect of significantly reducing the overall cost.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of an A/D converter showing a first embodiment of the present invention, Fig. 2 is a circuit diagram of an A/D converter showing a second embodiment of the invention, and Fig. 3 is a circuit diagram of an A/D converter showing a second embodiment of the invention. FIG. 2 is a timing diagram of various signals for explaining the conversion operation, and FIG. 4 is a circuit diagram of a conventional A/D converter. 1.101~104... Analog input terminal, 2
...Sample & hold circuit, 3...
Comparator, 5...Final comparison register, 6...
...D/A converter, 8... Conversion result register,
11...CPU, 12...Reference power supply terminal, 20...Reference voltage selection circuit, 21...Mode register, 23...
- Voltage follower, 24...timing generation circuit, 100...analog input selection circuit.

Claims (1)

[Claims] In an A/D converter built into a one-chip microcomputer, means for generating a plurality of reference voltages having the reference voltage as a maximum value from a reference voltage supplied to a reference power supply terminal; An A/D converter comprising means for selectively supplying one of the two.