JP3441388B2 - Synchronous circuit and semiconductor memory device using the same - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous circuit applied to, for example, a semiconductor integrated circuit, and more particularly to a SAD (Sy
The present invention relates to a phase shift synchronizing circuit that shifts the phase of an output clock signal with respect to an input clock signal by using a nchronous Adjustable Delay).

[0002]

2. Description of the Related Art In a semiconductor integrated circuit such as a synchronous DRAM, it is necessary to synchronize a clock signal inside the chip with a clock signal supplied from outside the chip. In this case, if the clock signal supplied from the outside of the chip is received by the input buffer circuit and distributed to a plurality of inside the chip, it becomes difficult to synchronize each clock signal due to the delay due to the buffer circuit and wiring. . In order to avoid this, a synchronization circuit that synchronizes the clock signals with each other is provided.

As this kind of synchronizing circuit, for example, T. Sa
eki, et al. "A 2.5ns Clock Access 250MHz 256Mb SDR
AM with a Synchronous Mirror Delay, "ISSCC Digest
of Technical Papers, pp.374-375, Feb., 1996 "", SMD (Synchronous Mirror Delay) disclosed, and Japanese Patent Application No. 8-100976, STBD (Sync.
SAD methods including hronous traced backward delay) are known.

FIG. 27 shows a well-known SAD type synchronizing circuit. This SAD type synchronizing circuit is an input buffer circuit (IB) that receives an external clock signal CK,
Delay monitor (DLM), first delay line (DL1),
A second delay line (DL2), the input buffer circuit (I.
According to the output signal of B), the first and second delay lines (DL
1, a controller (CONT) for controlling DL2), and a second
Of the delay line (DL2) is supplied to the output buffer circuit (OB). The first and second delay lines (DL1, DL2) have a plurality of unit delay elements (DL) (not shown) connected in series.

FIG. 28 shows signals of the respective parts of FIG. The synchronization circuit delays the output signal of the input buffer circuit (IB) and outputs 2τ from the external clock signal CK.
(Τ: cycle of external clock signal CK) A delayed internal clock signal CK ′ is generated. That is, the input buffer circuit (IB) receives D1 from the external clock signal CK having the period τ.
A signal CLK delayed by only is generated, and this signal CLK is delayed by A by a delay monitor (DLM) and supplied to the first delay line (DL1). First delay line (DL
The signal supplied to 1) is propagated through the first delay line (DL1) by τ-A until the next pulse of the signal CLK is supplied to the control unit (CONT), and further, the second signal. Only τ-A is propagated by the delay line (DL2). The output signal Dout of the second delay line (DL2) is output via the output buffer circuit (OB) having the delay amount of D2, so that the internal clock signal CK ′ is generated. Therefore, when A = D1 + D2, the delay of the internal clock signal CK ′ with respect to the external clock signal CK is D1 + A + 2 (τ−A) + D2 = 2τ. Therefore, the internal clock signal CK 'is synchronized with the external clock signal CK. Since the SAD method has a high synchronization speed, it is applied to various circuits.

FIG. 29 shows the SAD type synchronous circuit as a D circuit.
It shows a case where it is applied to an input / output circuit of a DR (Double Data Rate) memory device. The first selection circuit 210a has four
The parallel / serial conversion circuit outputs the bit data D1 to D4 as 1-bit data in response to the selection signals SL1 to SL4. The second selection circuit 210b outputs 1-bit data in response to the selection signals SL1 to SL4. The serial / parallel conversion circuit outputs 4-bit data D1 to D4. The output terminal of the first selection circuit 210a is connected to the input / output pad 21 via the output buffer circuit 210c.
0d, and the input terminal of the second selection circuit 210b is connected to the input / output pad 21 via the input buffer circuit 210e.
It is connected to 0d.

FIG. 30 shows the first and second selection circuits 21.
The selection signals SL1 to SL4 supplied to 0a and 210b are shown. External signals of these selection signals SL1 to SL4 are shifted by 90 ° and 270 °, and the cycle thereof is ½ of that of the external clock signal. To generate these selection signals SL1 to SL4, an internal clock signal Du and 270 obtained by shifting the external clock signal by 90 ° are used.
The shifted internal clock signal Dd is required.

FIG. 31 shows the internal clock signals Du and D.
An example of a circuit for generating the selection signals SL1 to SL4 by using d is shown. Each circuit that generates the selection signals SL1 to SL4 includes 1-bit counters 220a to 220d, and AND circuits 220e to 220h that take the logical product of the output signals of these counters 220a to 220d and the internal clock signals Du and Dd, respectively. It is configured.

As described above, in order to generate the selection signals SL1 to SL4, the logical product of the output signals of the 1-bit counters 220a to 220d and the internal clock signals Du and Dd may be obtained. Internal clock signal D
In order to have a sufficient margin with respect to u and Dd,
The count-up signal of the counter is the internal clock signal D
It is necessary that the phase precedes u and Dd by more than the delay of the counter. Therefore, the internal clock signal D
internal clock signal aDu whose phase precedes u, Dd,
aDd is generated, and these internal clock signals aDu and aD are generated.
The counter 220a uses d as a signal for counting up.
To 220d respectively.

FIG. 32 shows the operation of the circuit for generating the selection signal SL1. In this way, by operating the counter 220a using the internal clock signal aDu, it is possible to generate the selection signal SL1 in synchronization with the internal clock signal Du and having a half cycle of the internal clock signal aDu. Other selection signals SL2-SL4 are similarly generated.

Further, in order to capture the input / output (I / O) data shown in FIG. 30 with the maximum margin, it is preferable to capture at the center of the input / output data indicated by the broken line. For this purpose, the internal clock signal synchronized with the rising edge of the external clock signal (hereinafter referred to as Tu) and the internal clock signal synchronized with the falling edge of the external clock signal, that is, the external clock signal is shifted by 180 °. An internal clock signal (hereinafter called Td) is required.

33 (a) (b) and 34 (a)
(B) shows an SAD-type synchronizing circuit that generates the internal signals Du, Dd, Tu, and Td. FIG. 33
(A) shows a synchronizing circuit SAD1 for generating an internal clock signal Tu synchronized with the rising edge of the external clock signal, and FIG. 33 (b) shows an internal clock signal Td synchronized with the falling edge of the external clock signal. 34A shows a synchronous circuit SAD2, FIG. 34A shows a synchronous circuit SAD3 for generating an internal clock signal Du which is shifted by 90 ° with respect to an external clock signal, and FIG. The synchronous circuit SAD4 for generating the internal clock signal Dd is shown. The synchronous circuit SAD1 generates the internal clock signal Tu from the external clock signal CK, and the other synchronous circuits SAD2 to SAD4 respectively generate the internal clock signals Td, Du, Dd based on the internal clock signal Tu supplied from the synchronous circuit SAD1. To generate.

33 (a) (b) and 34 (a)
In (b), (IB) shows an input buffer circuit, and (OB) shows an output buffer circuit. DL
Reference numerals 1 and DL2 are first and second delay lines, respectively, and these first and second delay lines DL1 and DL2 are composed of a plurality of delay elements (not shown) connected in series. For convenience of explanation, the control unit for controlling the first and second delay lines is omitted. In the synchronization circuit SAD1, the first and second delay lines DL1 and DL2 have the same delay time,
In the synchronization circuit SAD2, the delay time of the second delay line DL2 has a delay time that is half that of the first delay line DL1. Further, in the synchronous circuit SAD3, the delay time of the second delay line DL2 has a delay time of 1/4 that of the first delay line DL1, and in the synchronous circuit SAD4, the delay time of the second delay line DL2 is It has a delay time of 3/4 that of one delay line DL1.

[0014]

The output buffer circuit (OB) 230 connected to the second delay line DL2 of the synchronous circuit SAD1 outputs the generated internal clock signal Tu to the synchronous circuits SAD2 to SAD4. To drive them without delay, the circuit becomes a circuit having a very large current capacity, and the circuit scale becomes significantly large.

The synchronous circuits SAD1 to SAD4 are also provided.
Since the second delay line DL2 has a different configuration, it is necessary to arrange a delay line corresponding to each synchronous circuit. Further, since the synchronous circuits SAD1 to SAD4 require as many as 19 input and output buffer circuits in total, there is a problem that the occupied area of the synchronous circuits SAD1 to SAD4 with respect to the chip increases and the power consumption increases. is doing.

In addition, the internal clock signals Du and D described above are used.
When generating the internal clock signals aDu and aDd that are in phase advance with respect to d, the internal clock signal aDu is one stage before the output buffer circuit 240 that outputs the internal clock signal Dd, as shown in FIG. It is output from the output buffer circuit 250. That is, it is configured as shown in FIG. However, the internal clock signal aD
As for u, the output buffer circuit 230 of FIG.
Since there is no output buffer circuit in the preceding stage, an output buffer circuit for newly generating the internal clock signal aDu needs to be provided in the preceding stage of the output buffer circuit 230. However, as shown in FIG.
When the output buffer circuit 260 that generates the internal clock signal aDu is provided in the preceding stage of 0, eight output buffer circuits are required to configure the delay monitor DLM. Therefore, since a total of 10 output buffer circuits are required only by the synchronization circuit SAD3, the area occupied by the chip increases and the power consumption increases. Moreover, 8
There is a problem in that the delay amount in the delay monitor DLM configured by the individual output buffer circuits is too large, and synchronization cannot be achieved at a high frequency where the delay amount is longer than the cycle of the clock signal.

The present invention has been made to solve the above problems, and an object of the present invention is to prevent an increase in occupied area in a chip, reduce power consumption, and achieve synchronization. An object of the present invention is to provide a synchronous circuit capable of widening the obtained frequency range and a semiconductor memory device using the synchronous circuit .

[0018]

According to the present invention, in order to solve the above-mentioned problems, a first clock signal is input and the first clock signal is input.
The second clock signal synchronized with the second clock signal and the third clock signal having a phase advanced from the second clock signal, and the third clock signal are supplied to the first synchronization circuit. 3rd clock signal
Phase from the clock signal and a second synchronization circuit for generating a fourth clock signal which is delayed a predetermined angle, said first
Of the synchronizing circuit of the input clock receiving the first clock signal.
Buffer circuit and a first delay line having a plurality of delay elements
A second delay line having a plurality of delay elements;
A controller for controlling the first and second delay lines, and the second delay
Delay the line output signal and output the third clock signal
A first output buffer circuit, and the first output buffer
The third clock signal output from the circuit
Second output buffer for outputting the second clock signal
Circuit and an input buffer connected to the first delay line.
Circuit delay time and the first and second output buffer circuits
A first delay monitor having a delay time that is the sum of the delay times
The second synchronization circuit includes a plurality of delay elements.
A third delay line having a plurality of delay elements and a plurality of delay elements,
A fourth delay line having a shorter delay time than the third delay line
A control unit for controlling the third and fourth delay lines;
Delaying the output signal of the fourth delay line to obtain the fourth clock signal;
The third output buffer circuit that outputs the signal and the output end
The third delay line connected to the third delay line and supplied to the input end.
3 clock signal delay time and the third output buffer
A second delay having a delay time that is the sum of the delay times of the circuits
A monitor.

[0019]

[0020]

The ratio of the delay times of the third delay line and the fourth delay line is different from the ratio of the delay time of the second delay monitor and the delay time of the third output buffer circuit,
A fourth clock output from the third output buffer circuit.
The clock signal is delayed in phase from the second clock signal .

The third delay line has m delay elements connected to each other, and the fourth delay element has m delay elements, of which n delay elements are They are connected to each other and the mn delay elements are short-circuited.

Further, the present invention is synchronized with the input clock signal has a plurality of synchronizing circuits which the input clock signal in phase to produce a different output clock signal, said plurality of synchronization
First and second delay lines are provided for the circuit, and the first delay line is provided.
Delay line has m delay elements, and the second delay line
Has m delay elements, of which n delay elements are included.
The children are connected to each other to form a second delay element group, and m−
a third delay element in which the n delay elements are connected to each other
A first delay element group, and the first delay element group comprises the plurality of synchronization circuits.
And the second and third delay elements are shared by the respective synchronous circuits.
Connected to.

[0024] The first delay line constitutes the fourth delay group the m delay the delay element Cormorants <br/> Chi of n element are connected to each other, m-n-number of The delay elements are connected to each other to form a fifth delay element group, and the fourth and fifth delay element groups are connected to the respective synchronizing circuits .

The second delay line has m delay elements, among which n delay elements are connected to each other to form a third delay element group, and mn delay elements are provided. The elements are connected to each other to form a fourth delay element group, and the third and fourth delay element groups are shared by the plurality of synchronization circuits.

Further, according to the present invention, the first clock signal is input, the second clock signal synchronized with the first clock signal and having a phase shifted from the first clock signal, and the second clock signal. A synchronizing circuit for outputting a third clock signal having a phase different from that of the signal, and the synchronizing circuit comprises:
A first delay line having m delay elements connected to each other; a first delay element group having m delay elements of which n delay elements are connected to each other; −
A second delay line having a second delay element group in which n delay elements are connected to each other, a control unit for controlling the first and second delay lines, and the first delay element group A first output buffer circuit that delays the output signal of the second delay element group to generate the second clock signal, and a second output buffer circuit that delays the output signal of the second delay element group to generate the third clock signal. An output buffer circuit and a delay monitor connected to the first delay line and having a delay time of a sum of a delay time of the first clock signal and a delay time of the first output buffer circuit are provided. There is.

[0027]

[0028]

Further, according to the present invention, there is provided a first input buffer circuit having a plurality of clock signals and a plurality of delay elements.
Delay line, a second delay line having a delay amount different from that of the first delay line, a control unit for controlling the first and second delay lines, and an output signal of the second delay line. A plurality of output buffer circuits that output first and second clock signals having different delay amounts, an input end connected to the input buffer circuit, and an output end connected to the first delay line. A delay monitor having a delay amount different from the sum of the delay amount of the buffer circuit and the delay amount of the output buffer circuit is provided.

The delay amount of the first delay line is m, the delay amount of the second delay line is n, and the phase of the second clock signal is advanced by k output buffers from the first clock signal. , The number of output buffer circuits is k + 1.
And the number of the input buffer circuits is 2n− (k +
1). Further, according to the present invention, a generation circuit for generating a clock signal and a phase for generating a plurality of internal clock signals which are supplied with the clock signal generated by the generation circuit and have different phases from the clock signal according to the clock signal The phase shift synchronization circuit includes a shift synchronization circuit and a memory device connected to the phase shift synchronization circuit and accessed according to a plurality of internal clock signals supplied from the phase shift synchronization circuit. A second clock signal synchronized with the first clock signal and a third clock signal having a phase advanced from the second clock signal, 3 clock signals are supplied and synchronized with the third clock signal, and the phase is located from the third clock signal.
And a second synchronization circuit for generating a fourth clock signal which constant angular lag, the first synchronization circuit, the first click
An input buffer circuit that receives the lock signal and multiple delay elements
A first delay line having a child and a first delay line having a plurality of delay elements.
Control for controlling the second delay line and the first and second delay lines
And an output signal of the second delay line,
A first output buffer circuit for outputting the clock signal of
The third output from the first output buffer circuit
A clock signal is supplied and the second clock signal is output
Connecting the second output buffer circuit and the first delay line
And the delay time of the input buffer circuit and the first and second delay times.
Has a delay time that is the sum of the delay time of the output buffer circuit of
A first delay monitor, and the second synchronization circuit
The path includes a third delay line having a plurality of delay elements and a plurality of delay lines.
A delay element, and a delay time shorter than that of the third delay line
Controls the fourth delay line having and the third and fourth delay lines
And a control unit for delaying the output signal of the fourth delay line,
Third output buffer for outputting the fourth clock signal
A circuit and an output terminal connected to the third delay line, and an input terminal
The delay time of the third clock signal supplied to
The delay time of the sum of the delay time of the third output buffer circuit and
And a second delay monitor having the same.

[0031]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIGS. 1A, 1B and 2A, 2B.
Shows a first embodiment of the present invention. The first embodiment shows a SAD type synchronizing circuit for generating the internal signals Du, Dd, Tu and Td. Figure 1
(A) is an internal clock signal Tu synchronized with the rising of the external clock signal CK, and this internal clock signal Tu
A synchronous circuit SAD1 for generating an internal clock signal aTu with a more advanced phase is shown. FIG. 1B shows a synchronizing circuit SAD2 for generating the internal clock signal Td synchronized with the fall of the external clock signal.
FIG. 2A shows an internal clock signal Du which is shifted by 90 ° with respect to the external clock signal, and a synchronization circuit SAD3 for generating an internal clock signal aDu whose phase is advanced from the internal clock signal Du. FIG. 2B shows an internal clock signal Dd shifted by 270 ° from the external clock signal,
Also, there is shown a synchronizing circuit SAD4 for generating an internal clock signal aDd whose phase is advanced from the internal clock signal Dd.

The synchronizing circuit SAD1 is connected to the external clock signal CK.
The internal clock signal Tu is generated from the other synchronous circuit SA
D2 and SAD4 are based on the internal clock signal Tu supplied from the synchronization circuit SAD1
d, Dd, and aDd are generated respectively. Further, the synchronization circuit SAD3 uses the internal clock signals Du and aD based on the internal clock signal aTu supplied from the synchronization circuit SAD1.
Generate u respectively.

1A and 1B and FIGS. 2A and 2B, (IB) indicates an input buffer circuit, and (O.
B) shows an output buffer circuit. The input buffer circuit and the output buffer circuit are configured by, for example, at least one inverter circuit connected in series, a differential amplifier, or the like. DL1 and DL2 are first and second delay lines, respectively, and these first and second delay lines D
L1 and DL2 are composed of a plurality of delay elements (not shown) connected in series. For convenience of explanation, the first and second
The control unit for controlling the delay line is omitted.

In the synchronizing circuit SAD1, the first and second delay lines DL1 and DL2 have the same delay time,
In the synchronization circuit SAD2, the delay time of the second delay line DL2 has a delay time that is half that of the first delay line DL1. Further, in the synchronous circuit SAD3, the delay time of the second delay line DL2 has a delay time of 1/4 that of the first delay line DL1, and in the synchronous circuit SAD4, the delay time of the second delay line DL2 is It has a delay time of 3/4 that of one delay line DL1.

In the synchronizing circuit SAD1 shown in FIG. 1A, the external clock signal CK is input to the input buffer circuit 10a,
10b and output buffer circuits 10c and 10d
Of the delay line DL1. The signal CLK output from the input buffer circuit 10a is the first and second signals.
Is supplied to a control unit (not shown) that controls the delay lines DL1 and DL2. Output buffer circuits 10e and 10f are connected in series to the output terminal of the second delay line DL2.
The internal clock signal T is output from the output buffer circuit 10f.
u is output, and the output buffer circuit 10e outputs an internal clock signal aTu that is one phase ahead of the internal clock signal Tu by one output buffer circuit. The delay monitor DLM is configured by the input buffer circuit 10b and the output buffer circuits 10c and 10d so that the delay time is equal to the total delay time of the input buffer circuit 10a and the output buffer circuits 10e and 10f.

In the synchronous circuit SAD2 shown in FIG. 1B, the internal clock signal Tu supplied from the synchronous circuit SAD1 is supplied to the first delay line DL1 via the output buffer circuits 11a and 11b, and It is supplied to a control unit (not shown) that controls the first and second delay lines DL1 and DL2. The output buffer circuits 11a and 11b form a delay monitor DLM. The output terminal of the output buffer circuit 11c is connected to the output terminal of the second delay line DL2, and the internal clock signal Td is output from the output terminal of the output buffer circuit 11c.

In the synchronizing circuit SAD3 shown in FIG. 2A, the internal clock signal aTu supplied from the synchronizing circuit SAD1 is supplied to the first delay line DL1 via the output buffer circuits 12a to 12d, and 1st and 2nd
Is supplied to a control unit (not shown) that controls the delay lines DL1 and DL2. The output buffer circuits 12a to 12d form a delay monitor DLM. Output buffer circuits 12e and 12f are provided at the output terminals of the second delay line DL2.
Are connected in series. The output buffer circuit 12f outputs an internal clock signal Du, and the output buffer circuit 12e outputs an internal clock signal aDu that is one phase ahead of the internal clock signal Du in output buffer circuit.

In the synchronizing circuit SAD4 shown in FIG. 2B, the internal clock signal Tu supplied from the synchronizing circuit SAD1 is supplied to the first delay line DL1 via the output buffer circuits 13a to 13d, and It is supplied to a control unit (not shown) that controls the first and second delay lines DL1 and DL2. The output buffer circuits 13a to 13d form a delay monitor DLM. Output buffer circuits 13e to 13g are connected in series to the output terminal of the second delay line DL2. The output from the buffer circuit 13g outputs the internal clock signal Dd, the internal clock signal aDd advanced output buffer circuit one stage phase than the internal clock signal Dd is output from the output buffer circuit 1 3 f.

In the first embodiment, the synchronizing circuit SA
An internal clock signal aTu whose phase is advanced from that of the internal clock signal Tu supplied from the synchronization circuit SAD1 is input to D3. This synchronizing circuit SAD3 is based on the internal clock signal aTu,
° Generate the phase-shifted internal clock signal aDu,
This internal clock signal aDu is output to the output buffer circuit 12f.
Internal clock signal D whose phase is shifted by 90 ° from the internal clock signal Tu by delaying by 1 clock
is generating u.

According to the first embodiment described above, the synchronization circuit SA
In D1, in order to generate an internal clock signal ATU, the output buffer circuit increase two synchronous circuit SA
In D3, the conventional synchronous circuit SAD3 shown in FIG.
It is possible to reduce the number of output buffer circuits by four as compared with. Therefore, the total number of buffer circuits of the synchronous circuits SAD1 to SAD4 can be reduced, so that the increase of the area occupied by the chip can be prevented and the power consumption can be reduced.

Further, in the synchronizing circuit SAD3, the number of buffer circuits constituting the delay monitor DLM can be reduced from eight in the past to four, so that the delay monitor DLM can be used.
It is possible to reduce the delay amount of the signal at. Therefore, it is possible to synchronize with a high-frequency clock signal, and there is an advantage that the range in which synchronization can be taken can be expanded. (Second Embodiment) Next, a second embodiment of the present invention will be described.

In the first embodiment, the case where the number of output buffer circuits of the synchronizing circuit SAD3 for phase shifting by 90 ° is reduced is shown, but in the second embodiment, the output is made in the general phase shift synchronizing circuit. A case of reducing the number of buffer circuits will be described.

FIGS. 3A and 3B are the premise of the second embodiment, for example, 360 / m with respect to the external clock signal CK.
° (where m is an integer) shifted internal clock signal D
A synchronous circuit for generating x is shown.

In the synchronizing circuit SAD1 shown in FIG. 3A, the external clock signal CK is input to the input buffer circuit 31a,
It is supplied to the first delay line DL1 via 31b and the output buffer circuit 31c. The input buffer circuit 31b and the output buffer circuit 31c constitute a delay monitor DLM. Further, the signal CLK output from the input buffer circuit 31a is the first and second delay lines DL1 and DL.
2 is supplied to a control unit (not shown) that controls the control unit 2. An output buffer circuit 31d is provided at the output terminal of the second delay line DL2.
Are connected, and the internal clock signal Tu is output from the output buffer circuit 31d.

In the synchronizing circuit SAD2 shown in FIG. 3B, the internal clock signal Tu supplied from the synchronizing circuit SAD1 is m output buffer circuits 32-1 to 32-m.
The signal is supplied to the first delay line DL1 via the and via a control unit (not shown) that controls the first and second delay lines DL1 and DL2. Output buffer circuit 32-1
˜32-m constitutes a delay monitor DLM. An output buffer circuit 3 is provided at the output end of the second delay line DL2.
The input terminal of 2n is connected to this output buffer circuit 32n.
The internal clock signal Dx is output from the output terminal of the. The second delay line DL2 of the synchronization circuit SAD2 is the first delay line DL.
It has a delay time of 1 / m.

In the synchronizing circuit SAD2, when the internal clock signal aDx whose phase is advanced by one clock buffer from the internal clock signal Dx is required, the internal clock signal aDx is output from the output buffer circuit one stage before the output buffer circuit 32n. It may be taken out, but the circuit shown in FIG. 3B does not have such an output buffer circuit.

This is solved by the circuit shown in FIGS. 4A and 4B. Since the internal clock signal aDx is generated as shown in FIG. 4B, the output buffer circuit 32n is generated.
The output buffer circuit 32o is connected in series with the. With such a configuration, the internal clock signal aDx can be generated. However, in the case of this circuit, the number of buffer circuits forming the delay monitor DLM is 2m, which is twice the number of buffer circuits shown in FIG. 3B. Therefore, the area and power consumption are significantly increased, and the characteristics for high frequency signals deteriorate.

Therefore, in the second embodiment, as shown in FIG.
As shown in (b), the input signal of the synchronization circuit SAD2 is
Similar to the first embodiment, the internal clock signal aTu has a phase advanced from that of the internal clock signal Tu.

The synchronizing circuit SAD1 shown in FIG. 5A is similar to the output buffer circuits 31e and 31f in the circuit shown in FIG.
Has been added. That is, the output buffer circuit 31d
The output buffer circuit 31e is connected to the preceding stage, and the output buffer circuit 31f is added to the delay monitor DLM. The output buffer circuit 31d outputs the internal clock signal Tu, and the output buffer circuit 10e outputs the internal clock signal aTu.

In the synchronizing circuit SAD2 shown in FIG. 5B, the internal clock signal aTu supplied from the synchronizing circuit SAD1 is m output buffer circuits 32-1 to 32-.
is supplied to the first delay line DL1 via m, and
It is supplied to a control unit (not shown) that controls the first and second delay lines DL1 and DL2. The output buffer circuit 32-
1-32 to m form a delay monitor DLM.
The second delay line DL2 is 1 / m of the first delay line DL1.
Has a delay time of. Output buffer circuits 32o and 32n are connected in series to the output terminal of the second delay line DL2. The internal clock signal Dx is output from the output end of the output buffer circuit 32n, and the output buffer circuit 32o is output.
An internal clock signal aDx whose phase is advanced by one buffer from the internal clock signal Dx is output from the output terminal of the.

According to the second embodiment, the synchronization circuit SA
The input signal of D2 is the internal clock signal aTu which is in advance of the phase of the internal clock signal Tu output from the synchronization circuit SAD1. Therefore, the number of output buffer circuits forming the delay monitor DLM of the synchronization circuit SAD2 is m.
The number of output buffer circuits can be increased and the number of output buffer circuits can be prevented from increasing.

Further, in the synchronizing circuit SAD1, the number of output buffer circuits is increased by two as compared with the circuit shown in FIG. 4A, but in the synchronizing circuit SAD2, FIG.
Since the number of circuits can be reduced by m as compared with the circuit shown in (1), it is possible to significantly suppress an increase in chip occupying area and power consumption. Moreover, when the delay amount of the 2m output buffer circuits in the circuit shown in FIG. 4B is too large for the cycle of the required operating frequency, the circuit configuration of this embodiment is effective. (Third Embodiment) Next, a third embodiment of the present invention will be described. In the second embodiment, the internal clock signal D
The case has been described where the internal clock signal aDx whose phase is advanced by one output buffer circuit with respect to x is generated. In this embodiment, 360 × with respect to the external clock signal CK
When the internal clock signal Dy shifted by (n / m) ° (where m and n are integers) is generated, the internal clock signal D
A case will be described in which the internal clock signal aDy whose phase is advanced by k stages of the buffer circuit (where k ≧ n) from y is generated.

FIGS. 6A and 6B show a general synchronizing circuit which is a premise of the third embodiment. The configuration of the synchronization circuit SAD1 shown in FIG. 6A is as shown in FIG.
It is similar to (a). The synchronization circuit SAD shown in FIG.
2, the internal clock signal Tu supplied from the synchronizing circuit SAD1 is m output buffer circuits 34-1 to 34-3.
It is supplied to the first delay line DL1 via 4-m and is also supplied to a control unit (not shown) that controls the first and second delay lines DL1 and DL2. Output buffer circuit 3
4-1 to 34-m form a delay monitor DLM. N output buffer circuits 34-1 to 34-n are connected in series to the output terminal of the second delay line DL2, and the internal clock signal Dy is output from the output terminal of the output buffer circuit 34-n. The second delay line D of the synchronization circuit SAD2
L2 has a delay time of n / m of the first delay line DL1.

In the synchronizing circuit SAD2 shown in FIG. 6B, even if an attempt is made to generate the internal clock signal aDy whose phase is advanced by k stages of the output buffer circuit from the internal clock signal Dy, the second delay line DL2 is provided. Since only n output buffer circuits are connected, only a signal advanced by (n-1) stages can be generated. Second delay line DL2
The number of output buffer circuits connected to is from n to (k +
When the number is increased to 1), it is necessary to increase the number of output buffer circuits forming the delay monitor DLM to m × {(k + 1) / n}. When m × {(k + 1) / n} is not an integer, it is multiplied by i as shown in Expression (1) so that it becomes an integer.

M × {(k + 1) / n} × i (where i is an integer) (1) and the number of output buffer circuits connected to the second delay line DL2 is also as shown in equation (2). need to be multiplied by i.

(K + 1) × i (2) Therefore, the total number of output buffer circuits is significantly increased from m + n to m × {(k + 1) / n} × i + (k + 1) × i.

For example, 360 × with respect to the external clock signal
(4/9) = 80 In the case of generating an internal clock signal whose phase is shifted, if an internal clock signal advanced by four stages in the buffer circuit is to be generated, m = 9, n =
4, k = 4, and if i = 4 for integerization, from the formula (1), the delay monitor DLM requires 45 output buffer circuits, and the output buffer connected to the second delay line DL2. From the equation (2), 20 circuits are required. Therefore, the total number of input buffer circuits and output buffer circuits required to form the synchronous circuits SAD1 and SAD2 is as large as 69, which increases the chip occupying area and significantly increases the power consumption. .

Therefore, in the third embodiment of the present invention, as shown in FIG.
As shown in (a) and (b), the synchronous circuit SAD1 generates an internal clock signal aTu that is phase advanced from the internal clock signal Tu by k stages of the buffer circuit, and outputs the synchronous circuit SAD1.
AD2 generates internal clock signals Dy and aDy based on this internal clock signal aTu.

That is, as shown in FIG. 7A, in the synchronizing circuit SAD1, the external clock signal CK is input through the input buffer circuits 31a, 31b and k + 1 output buffer circuits 35-1 to 35-k + 1 to the first circuit. Delay line DL1
Is supplied to. The input buffer circuit 31b and the output buffer circuits 35-1 to 35-k + 1 are delay monitor DLs.
Makes up M. Further, the input buffer circuit 31a
A signal CLK output from the first and second delay lines D
It is supplied to a control unit (not shown) that controls L1 and DL2. An output buffer circuit 36 and k output buffer circuits 37-1 to 37-are provided at the output terminal of the second delay line DL2.
k are connected in series. The output buffer circuit 37-k outputs the internal clock signal Tu, and the output buffer circuit 36 outputs the internal clock signal Tu.
Outputs an internal clock signal aTu whose phase is advanced by k buffer circuits from the internal clock signal Tu.

In the synchronizing circuit SAD2 shown in FIG. 7B, the internal clock signal aTu supplied from the synchronizing circuit SAD1 is m output buffer circuits 38-1 to 38-.
is supplied to the first delay line DL1 via m, and
It is supplied to a control unit (not shown) that controls the first and second delay lines DL1 and DL2. Output buffer circuit 38-
1 to 38-m form a delay monitor DLM.
The second delay line DL2 is n / m of the first delay line DL1.
Has a delay time of. The n output buffer circuits 39-connected in series are connected to the output terminal of the second delay line DL2.
1 to 39-n and k output buffer circuits 40-1 to 40-k connected in series are sequentially connected. The internal clock signal Dy is output from the output terminal of the output buffer circuit 40-k, and the internal clock signal aDy that is advanced in phase by k buffer circuits from the internal clock signal Dy is output from the output buffer circuit 39-n. .

According to the third embodiment, the synchronizing circuit SA
At D1, an internal clock signal aTu whose phase is advanced by k stages of the buffer circuit from the internal clock signal Tu is generated,
In the synchronizing circuit SAD2, an internal clock signal aDy whose phase is shifted by 360 × (n / m) ° is generated from the internal clock signal aTu, and the internal clock signal aDy is generated.
The internal clock signal Dy is generated by delaying Dy by k stages of the buffer circuit. Here, the synchronization circuit SAD
1, the input buffer circuit that constitutes the delay monitor,
The number of output buffer circuits is 2 to k shown in FIG.
It has increased to +2. However, the number of output buffer circuits forming the delay monitor of the synchronizing circuit SAD2 is as shown in FIG.
7 (b) is m × {(k + 1) / n} × i, whereas FIG. 7 (b) has m. Therefore, the synchronization circuit S
The total number of input buffer circuits and output buffer circuits of AD1 and the synchronizing circuit SAD2 can be reduced.

When the internal clock signal shifted by 80 ° with respect to the external clock signal described with reference to FIGS. 6A and 6B is generated, the internal clock signal aDy whose phase is advanced by four stages of the buffer circuit is generated ( m = 9, n =
4, k = 4), the synchronous circuit SAD1 shown in FIG. 7A can be configured by 2+ (k + 1) + 1 + k = 12 input buffer circuits and output buffer circuits.
The synchronous circuit SAD2 shown in FIG. 7B can be configured by an output buffer circuit in which the sum of m, n, and k is 9 + 4 + 4 = 17. Therefore, in the case of the configuration of the third embodiment,
Compared with the configuration shown in FIGS. 6A and 6B, the area occupied by the chip can be significantly reduced and the power consumption can be reduced.

Moreover, the delay monitor of the synchronizing circuit SAD2 requires 45 output buffer circuits in the case of FIG. 6B, whereas m = 9 outputs in the case of FIG. 7B. It can be composed of a buffer circuit. Therefore, it has an advantage that it can operate reliably even at high frequencies. (Fourth Embodiment) Next, a fourth embodiment of the present invention will be described.

For example, if the phase of the external clock signal is 360 ×
S for generating (n / m) ° shifted internal clock signal
The first AD synchronous circuit and 360 × {(m−n) /
If there is a second synchronous circuit of the SAD system that generates an internal clock signal that is shifted by m} °, the delay lines of the first and second synchronous circuits are configured as follows.

FIG. 8 shows the configuration of a delay line applied to a conventional first synchronizing circuit for shifting the phase of an external clock signal by 90 °, for example. For example, four unit delay elements (DL) 41-1 to 41-4 are connected to each other and the first delay line DL1 is connected to the control unit 43.
On the other hand, the second delay line DL2 includes one unit delay element 42-1 of the four unit delay elements 42-1 to 42-4.
4 are used, and the remaining unit delay elements 42-1 to 42-
3 is short-circuited. That is, these unit delay elements 4
The delay times of 2-1 to 42-3 are set to zero.

FIG. 9 shows the configuration of a delay line applied to a conventional second synchronizing circuit that shifts the phase by 270 ° with respect to an external clock signal, for example. First delay line DL
1 is, for example, four unit delay elements (DL) 41-1 to 4-4.
1-4 are connected to each other and to the controller 43. In contrast, three unit delay elements 42-2～42-4 of the second delay line DL2 is four unit delay elements 42-1 to 42-4 are used, the remaining delay units 42
-1 is short-circuited. That is, this unit delay element 4
The delay time of 2-1 is zero.

8 and 9, in the actual layout, since the delay time of each unit delay element is the same, the unit delay elements constituting the first delay line DL1 and the second delay line DL2 are arranged. The size of the unit delay elements constituting the same was the same, and the space occupied by the short-circuited elements was not used effectively. For this reason, useless space is generated.

Therefore, in the fourth embodiment, for example, a first synchronizing circuit for generating an internal clock signal obtained by shifting the phase of the external clock signal by 360 × (n / m) ° and 360 ×
If there is a second synchronizing circuit that generates an {(m−n) / m} ° shifted internal clock signal, the delay lines of the first and second synchronizing circuits are merged to save space. ing.

That is, as shown in FIG. 10, each of the first and second delay lines DL1 and DL2 is composed of m unit delay elements. The unit delay elements 51-1 to 51-m forming the first delay line DL1 are connected to each other and to the control unit 53. The first delay line DL1 is shared by, for example, the first and second synchronizing circuits.

On the other hand, of the m unit delay elements forming the second delay line DL2, n unit delay elements 52-1 to 52-1 are provided.
52-n are connected to each other and to the controller 53. These unit delay elements 52-1 to 52-n
Is, for example, the phase of the external clock signal is 360 × (n /
m) Used for the first synchronizing circuit which generates the internal clock signal shifted by °. The remaining m−n unit delay elements 52-n + 1 to 52-m are connected to each other and to the control unit 53. These unit delay elements 52
-N + 1 to 52-m are used, for example, in a second synchronizing circuit which generates an internal clock signal obtained by shifting the phase of the external clock signal by 360 × {(m−n) / m} °.

FIG. 11 specifically shows FIG. 10, for example, a first synchronizing circuit 270 for generating an internal clock signal obtained by shifting the phase of the external clock signal by 90 °, and 270.
The delay line is shown when there is a second synchronizing circuit that generates a shifted internal clock signal.

That is, as shown in FIG. 11, each of the first and second delay lines DL1 and DL2 is composed of four unit delay elements. The unit delay elements 61-1 to 61-4 forming the first delay line DL1 are connected to each other and to the control unit 63. The first delay line DL1 is shared by, for example, the first and second synchronizing circuits.

On the other hand, out of the four unit delay elements constituting the second delay line DL2, one unit delay element 62-4 is connected to the control section 63 and used for the first synchronizing circuit.
The unit delay elements 62-1 to 62-3 are connected to each other and also to the control unit 63, and are used for the second synchronization circuit.

FIG. 12 schematically shows the circuit pattern of the second delay line DL2. Unit delay elements 62-1-6
2-3 are connected to each other at the contact portion CT,
One end of each of the unit delay elements 62-1 and 62-3 has a wiring L1,
It is connected to L2. In addition, wirings L3 and L4 are connected to the unit delay element 62-4. These wirings L1
L4 is arranged above the unit delay elements 62-1 to 62-4.

According to the fourth embodiment, the first and second delay lines DL1 and DL2 are shared by the first and second synchronizing circuits. Therefore, the area of the delay line can be reduced.
Furthermore, the first delay line DL1 can be reduced by sharing the first delay line DL1 provided in each of the first and second synchronization circuits with the first and second synchronization circuits. Therefore, power consumption can be reduced.

FIG. 13 shows a case where the fourth embodiment is applied to the first embodiment, for example, and the delay lines of the synchronous circuits SAD3 and SAD4 shown in FIGS. There is. Since the synchronization circuits SAD1 and SAD2 are the same as those in FIGS. 1A and 1B, they are omitted.

In FIG. 13, the same parts as those in FIGS. 2A and 2B are designated by the same reference numerals. Second delay line DL2
Has two outputs, a 90 ° shift output and a 270 ° shift output. The output buffer circuits 12e and 12f are connected in series to the 90 ° shift output terminal, the internal clock signal Du is output from the output buffer circuit 12f, and the internal clock signal D is output from the output buffer circuit 12e.
An internal clock signal aDu whose phase is advanced by one stage from the buffer circuit is output from u.

Output buffer circuits 13e, 13f, 13h and 13g are serially connected in this order to the 270 ° shift output terminal. The synchronization circuit SAD shown in FIG.
4, the output buffer circuit 13h is connected one stage more because the input signal of the delay monitor DLM is shown in FIG.
This is because in the case of (b), it is the internal clock signal Tu, whereas in the case of FIG. 13, the internal clock signal aTu advanced by one stage of the buffer circuit is input. By adding the output buffer circuit 13h, the output buffer circuit 13g outputs the internal clock signal Dd, and the output buffer circuit 13h outputs the internal clock signal aDd which is one phase ahead of the internal clock signal Dd in phase by one buffer circuit. .

According to the circuit configuration shown in FIG. 13, the first delay line DL1 is shared by the synchronous circuits SAD3 and SAD4, and the second delay line DL2 is divided into the synchronous circuits SAD3 and SAD3.
It is used by SAD4. Moreover, the synchronization circuit SAD
3, the delay monitor DLM is shared by the SAD 4, so that the circuit configuration can be significantly reduced and the power consumption can be reduced.

In the fourth embodiment, the second delay line is set to 3
For 60 × (n / m) ° shift and 360 × {(m−n)
Although the description has been given of the case of dividing into two for the shift of / m} °, the present invention is not limited to this and it is also possible to divide into three or more. For example, 360 × (n1 / m) °
For shift, 360 × (n2 / m) ° For shift, 360 ×
It is possible to divide and use the second delay line, such as for (n3 / m) ° shifts. That is, n1 + n2
If the relationship of + n3≤m is satisfied, the delay line can be shared. (Fifth Embodiment) Next, a fifth embodiment of the present invention will be described.

FIGS. 14A and 14B show the fifth embodiment. In the above-described fourth embodiment, the case where at least two delay lines in which the delay amount of the second delay line DL2 is smaller than that of the first delay line DL1 is combined has been shown. That is, although the case where the second delay line DL2 is divided and used has been described, this embodiment will explain the case where the first delay line DL1 is divided and used.

FIG. 14A shows a case where at least two delay lines in which the delay amount of the first delay line DL1 is smaller than that of the second delay line DL2 are combined.

FIG. 14B shows the first delay line DL.
1, the second delay line DL2 has a small delay amount, and the second delay line DL2 has a small delay amount, and the first delay line DL1 has a small delay amount. It shows the case of fusing.

According to the fifth embodiment, the area of the delay line can be reduced and the power consumption can be suppressed as in the fourth embodiment. Moreover, it becomes possible to configure an optimum delay line according to various delay amounts. (Sixth Embodiment) Next, a sixth embodiment of the present invention will be described. When configuring a delay line having a required delay amount, an error may occur in the delay amount depending on the arrangement of the unit delay elements forming the delay line. In the sixth embodiment, an arrangement of delay lines that can minimize this error will be described.

FIG. 15 shows an arrangement of delay lines for shifting the clock signal by 90 ° in the SAD type synchronous circuit. In this case, as in FIG. 8, the first delay line D
L1 is, for example, four unit delay elements (DL) 71-1 to
71-4 are connected to each other and to the control unit 73. On the other hand, in the second delay line DL2, only one unit delay element 72-4 of the four unit delay elements 72-1 to 72-4 is used, and the remaining unit delay elements 72-
1 to 72-3 are short-circuited. Clock signal 90 °
When shifting, the configuration of the second delay line DL2 is as shown in FIG.
However, it is not limited to the case where only the unit delay element 72-4 is used. That is, the position where the unit delay line is provided in the second delay line DL2 is not limited to the position shown in FIG.

FIGS. 16A, 16B and 16C show the second delay line DL when the clock signal is shifted by 90 °.
The modification of No. 2 is shown. In this way, the unit delay element 7
9 to clock signals by using 2-1 to 72-3, respectively.
It can be shifted by 0 °. There are four types of positions at which the unit delay lines are arranged in the second delay line DL2.

17 (a) (b) and 18 (a) (b)
16A and 16B respectively show changes in the position and delay amount of the unit delay element in the second delay line DL2 shown in FIGS. 15 and 16A, 16B, and 16C. That is, FIG. 17A shows the case where the position of the unit delay element is shown in FIG.
16B shows the case where the position of the unit delay element is shown in FIG. 18A shows the case where the position of the unit delay element is shown in FIG. 16B, and FIG. 18B shows the case where the position of the unit delay element is shown in FIG. 16C. The delay amount of the second delay line DL2 is 1 of the delay amount of the first delay line DL1.
Ideally, the delay amount is / 4, but since the delay amount of the second delay line DL2 is discrete, an error occurs between the ideal delay amount and the actual delay amount. Since this error directly becomes an absolute error of the output signal, it is important to minimize this error.

In the case shown in FIGS. 17 (a) and 18 (b),
If the delay amount u of the unit delay element (DL) is, for example, 0.4 ns, the maximum error Emax between the ideal delay amount and the actual delay amount is, for example, 0.3 ns.
In the case of (b) and FIG. 18 (a), the maximum error Emax between the ideal delay amount and the actual delay amount is, for example, 0.2 ns.
Is.

17 (a) (b) and 18 (a) (b)
As can be seen from the above, the error shown in FIGS. 16A and 16B has the smallest error, and the error shown in FIGS. 15 and 16C has the largest error. The maximum error Emax is shown in FIG.
As shown in FIGS. 16A and 16B, FIG.
In the case of the configuration shown in (b), it is 1/2 u ( u is the delay amount of the unit delay element). If the delay amount u of the unit delay element (DL) is 0.4 ns, for example, it will be 0.2 ns. On the other hand, in the case of the configuration shown in FIG. 15 and FIG.
4u = 0.3 ns. That is, FIG. 16 of the present embodiment.
In the case of the configuration shown in (a) and (b), FIG. 15 and FIG.
It has an advantage that the error is smaller than that of the configuration shown in FIG.

Generally, the clock signal is 360 × (n /
In the case of a delay line applied to a SAD type synchronous circuit that shifts by m) °, a first delay line DL1 configured by m unit delay elements is provided for a first delay line DL1 configured by n unit delay elements. Two delay lines DL2 are arranged, but this arrangement is important. That is, the delay amount of the second delay line may be arranged so as to be closest to the ideal straight line of n / m, and the delay amount m of the first delay line DL1 and the delay amount of the second delay line DL2 With respect to the amount n, the total number y of the second delay lines DL2 up to the point corresponding to the x-th stage of the unit delay element of the first delay line DL1 is closest to (n / m) × x. So it is important to arrange.

Further, in the first delay line DL1 consisting of m unit delay elements and the second delay line DL2 consisting of n unit delay elements, the unit delay elements constituting the second delay line DL2 are Further arrangement methods are possible.

FIG. 19 shows the first method, in which n unit delay elements adjacent to the second delay line DL2 are continuously arranged.

On the other hand, FIG. 20 shows an arrangement method according to the sixth embodiment, showing a case where n unit delay elements are arranged separately.

FIG. 21 shows the error between the ideal delay amount and the actual delay amount when the unit delay elements are continuously arranged as shown in FIG. 19, and FIG. 22 shows the error as shown in FIG. The error between the ideal delay amount and the actual delay amount when the unit delay elements are discretely arranged is shown. Figure 2
As can be seen from FIG. 1 and FIG. 22, when the unit delay elements are continuously arranged, the maximum error Emax becomes very large,
The maximum error Emax can be reduced when the unit delay elements are discretely arranged according to the sixth embodiment.

In the case of the sixth embodiment, the arrangement of the unit delay element closest to the ideal straight line can be obtained by drawing as shown in FIG. 22, but it can also be obtained by a mathematical expression. The calculation method using mathematical formulas will be described below.

FIG. 23 shows the central portion CP of FIG. 22 extracted. When the first delay line DL1 is composed of m unit delay elements and the second delay line DL2 is composed of n unit delay elements, an ideal delay amount and an actual delay amount are obtained. And becomes like this.

Focusing on the k-th (k = 1, 2, 3, ... N) unit delay element part, (k−1) × m / n and k × m
If the unit delay element is arranged at the position closest to (2k−1) × (m / n) / 2, which is the midpoint of / n, the error becomes the smallest. As shown in FIG. 23, when there is a unit delay element at the A-th integer, the implementation delay amount increases by A-
The position is 1/2, and this A-1 / 2 is (2k-
1) The position closest to (m / n) / 2 may be used. For example, in the case of m = 4 and n = 1, A = 2 and 3 are obtained as A that is closest to A-1 / 2 in 2. 2 for A
Either of 3 and 3 is acceptable. It should be noted that when arranging the unit delay elements in the second delay line DL2, it is difficult to arrange all the unit delay elements in the positions that match the above equation, and some of them do not match the above equation. There is no problem if the error is within the allowable range.

As described above, according to the sixth embodiment, the unit delay element forming the second delay line can be arranged at the position having the smallest error from the ideal delay amount. Therefore, the absolute error of the output clock signal output from the delay line can be reduced.

In the sixth embodiment, the second delay line D
Although the arrangement of the unit delay elements forming L2 has been described, it is also possible to apply the sixth embodiment to the arrangement of the unit delay elements forming the first delay line DL1. (Seventh Embodiment) Next, a seventh embodiment of the present invention will be described. In the second embodiment, the synchronization circuits SAD1 and SA
Use D2 to set the phase of the external clock signal to 360 × (n /
m) ° shifted internal clock signal was generated. On the other hand, in the seventh embodiment, the external clock signal
A SAD type synchronous circuit for generating an internal clock signal shifted by 60 × (n / m) ° will be described.

FIG. 24 shows the SA that is the premise of the seventh embodiment.
The D-system synchronizing circuit is shown. In FIG. 24, the external clock signal CK has n input buffer circuits 81-1 to 81-1.
81-n, m-number of the input buffer circuit 82-1～8 2 -
It is supplied to the first delay line DL1 through m and m output buffer circuits 83-1 to 83-m. The input buffer circuit 82-1~8 2 -m, and the output buffer circuit 8
3-1 to 83-m form a delay monitor DLM. In addition, the signal CLK output from the input buffer circuit 81-n is the first and second delay lines DL1 and DL2.
Is supplied to a control unit (not shown) that controls the. The second
N output buffer circuits 8 are provided at the output terminals of the delay line DL2 of
4-1 to 84-n are connected in series, and the internal clock signal Dz is output from the output buffer circuit 84-n. The delay amount of the second delay line DL2 is equal to the first delay line DL1.
The delay amount is set to n / m.

In the above synchronizing circuit, when the internal clock signal aDz whose phase is advanced by k stages of the buffer circuit from the internal clock signal Dz is to be generated, the second delay line DL is used.
If it is attempted to solve the problem by adding (k + 1) output buffer circuits to the second output terminal, the number of input buffer circuits and output buffer circuits that form the delay monitor also increases, as described in the third embodiment. It is necessary to increase the number, and the total number of buffer circuits becomes huge.

Therefore, in the seventh embodiment, when k ≧ n, but 2n ≧ k, if the delay amounts of the input buffer circuit and the output buffer circuit are the same, the number of input buffer circuits is By subtracting from n shown in 24,
The number of output buffer circuits is increased from n to k + 1 so that the total number of buffer circuits can be reduced.

That is, as shown in FIG. 25, the external clock signal CK is received by 2n- (k + 1) input buffer circuits 81-1 to 81-2n- (k + 1). That is, the number of input buffer circuits is changed from n in FIG. 24 to 2n- (k +
1) Reduce to individual pieces. On the other hand, the second delay line DL2
(K + 1) output buffer circuits 84-1 to 84-k
Connect +1. That is, the output buffer circuit is shown in FIG.
The number is increased from n shown in 4 to (k + 1).

The number of input buffer circuits is changed from n to 2n−
By reducing the number to (k + 1), the output signal at the n-th stage of the output buffer circuit advances by the buffer circuit k + 1-n stages from the internal clock signal Dz output from the output buffer circuit 84-n shown in FIG. It will be. However, the final output of the circuit shown in FIG. 25 is delayed by the buffer circuit k + 1−n stages from the nth stage. Therefore, (k +
1-n)-(k + 1-n) = 0, and synchronization is achieved.

According to the seventh embodiment described above, the number of input buffer circuits that receive the external clock signal is reduced, and the number of output buffer circuits that output the internal clock signal is increased. I try not to change the number of circuits. Therefore, it is possible to reduce the total number of buffer circuits and directly output 360 × from the external clock signal.
An internal clock signal shifted by (n / m) ° can be generated.

In the seventh embodiment, the delay times of the input buffer circuit and the output buffer circuit are the same, but the delay time reduced in the input buffer circuit and the delay time increased in the output buffer circuit are the same. For example,
The number of input buffer circuits and output buffer circuits need not be the same.

In the first to third embodiments, the synchronizing circuit SAD1 generates the internal clock signal synchronized with the external clock signal. However, if the driving capability of the external clock signal is large, the synchronizing circuit SAD1 is It can be omitted.

Further, in each of the above embodiments, the external clock signal is received by the SAD type synchronous circuit, but the present invention is not limited to this, and for example, a buffer circuit composed of a plurality of inverter circuits connected in series is used. be able to. Moreover, if the phase margin of the buffer circuit composed of this inverter circuit is within the allowable range, the synchronizing circuit S
AD1 is not needed.

In addition to SAD, for example, PLL (Phase
When a high-precision buffer circuit including a Locked Loop (DL) circuit, a DLL (Delayed Locked Loop) circuit, etc. is used and the output signal from the buffer circuit is phase-shifted, the synchronizing circuit SAD1 is not necessary.

Further, although the external clock signal is used as the input signal of the synchronizing circuit SAD, it is not limited to this.

That is, FIG. 26 shows an example of a semiconductor integrated circuit device to which the present invention is applied. As shown in FIG. 26, for example, the DDR memory device 1 is mounted on the chip 100.
In the case of a semiconductor integrated circuit device in which 01 and the processor 102 are mounted together, the clock signal generation circuit 10 in the chip 100
A clock signal is generated in 3, and this clock signal is SAD
It may be supplied to the synchronous circuit 104 of the system.

Further, although the output signal of each synchronizing circuit SDA has been described as the internal clock signal used in the chip, the output signal is not limited to this and may be output to the outside of the chip.

Further, each of the above-mentioned embodiments may be used alone, or may be used in combination as appropriate.

Besides, the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications can be made without departing from the spirit of the invention.

[0115]

As described above in detail, according to the present invention,
While preventing an increase in the occupied area in the chip,
A synchronous circuit capable of reducing power consumption and widening a frequency range in which synchronization can be achieved, and a semiconductor using the same.
A storage device can be provided.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a synchronization circuit according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram showing a synchronization circuit according to the first embodiment of the present invention.

FIG. 3 is a configuration diagram showing a synchronization circuit which is a premise of the second embodiment.

FIG. 4 is a configuration diagram showing a synchronization circuit which is a premise of the second embodiment.

FIG. 5 is a configuration diagram showing a synchronizing circuit according to a second embodiment of the present invention.

FIG. 6 is a configuration diagram showing a general synchronizing circuit which is a premise of the third embodiment.

FIG. 7 is a configuration diagram showing a synchronization circuit according to a third embodiment of the present invention.

FIG. 8 is a configuration diagram showing a delay line applied to a conventional synchronizing circuit.

FIG. 9 is a configuration diagram showing another example of a delay line applied to a conventional synchronizing circuit.

FIG. 10 is a configuration diagram showing a delay line of a synchronizing circuit according to a fourth embodiment of the present invention.

11 is a configuration diagram specifically showing FIG.

12 is a plan view schematically showing a circuit pattern of a second delay line DL2 shown in FIG.

FIG. 13 is a configuration diagram showing a case where a fourth embodiment is applied to the first embodiment.

FIG. 14 illustrates a fifth embodiment of the present invention and is a configuration diagram showing an arrangement of unit delay elements.

FIG. 15 is a configuration diagram showing an arrangement of unit delay elements.

16 shows a sixth embodiment of the present invention, and FIG.
5 is a configuration diagram showing an arrangement of unit delay elements different from that of FIG.

FIG. 17 is a diagram showing the relationship between the placement of unit delay elements and the error.

FIG. 18 is a diagram showing a relationship between an arrangement of unit delay elements and an error.

FIG. 19 is a configuration diagram showing an arrangement of general unit delay elements.

20 shows a sixth embodiment of the present invention, and FIG.
9 is a configuration diagram showing an arrangement of unit delay elements different from FIG.

FIG. 21 is a diagram showing an error between the ideal delay amount and the actual delay amount in FIG.

22 is a diagram showing an error between an ideal delay amount and an actual delay amount according to the sixth embodiment of the present invention shown in FIG.

23 is a diagram showing the central portion CP of FIG. 22 taken out and showing a method of arranging the unit delay elements.

FIG. 24 is a configuration diagram showing a SAD type synchronization circuit which is a premise of the seventh embodiment.

FIG. 25 is a configuration diagram showing a SAD type synchronizing circuit according to a seventh embodiment of the present invention.

FIG. 26 is a configuration diagram showing an example of a semiconductor integrated circuit device to which the present invention is applied.

FIG. 27 is a configuration diagram showing a conventional SAD-type synchronization circuit.

28 is a timing chart shown for explaining the operation of FIG. 27. FIG.

FIG. 29 is a configuration diagram showing an input / output circuit of a DDR memory device.

FIG. 30 is a timing chart showing the operation of FIG. 29.

31 is a circuit diagram showing a circuit for generating a selection signal applied to the circuit shown in FIG.

32 is a timing chart showing an operation of a part of the circuit shown in FIG. 31. FIG.

FIG. 33 is a configuration diagram showing a conventional SAD-type synchronization circuit.

FIG. 34 is a configuration diagram showing a conventional SAD-type synchronization circuit.

FIG. 35 is a configuration diagram showing a conventional SAD-type synchronization circuit.

[Explanation of symbols]

SAD1 to SAD4 ... Synchronous circuit, DL1, DL2 ... First and second delay lines, 10a, 11a, 11b ... Input buffer circuit (I.
B), 10c, 10d, 10e, 10f ... Output buffer circuit (OB), 11a to 11c, 12a to 12d ... Output buffer circuit (OB), 13a to 13f ... Output buffer circuit (OB), 31a, 31b ... Input buffer circuit (IB), 31c to 31f, 32-1 to 32-m, 32n, 32o
Output buffer circuit (OB), 33-1 to 32-m, 34-1 to 34-n Output buffer circuit (OB), 35-1 to 35k + 1, 36, 37-1 to 37 -K ...
Output buffer circuit (OB), 38-1 to 38-m, 39-1 to 39-n, 40-1 to
40-k ... Output buffer circuit (OB), 81-1 to 81-n, 82-1 to 82-n ... Input buffer circuit (IB), 51-1 to 51-m, 52-1 52-n, 52-n +
1-52-m ... Unit delay element, 61-1 to 61-4, 62-1 to 62-4 ... Unit delay element, 71-1 to 71-4, 72-1 to 72-4 ... Unit delay element, 63, 73 ... Control unit.

Continuation of the front page (56) Reference JP-A-10-69326 (JP, A) JP-A-10-335994 (JP, A) JP-A-10-303713 (JP, A) JP-A-11-110062 (JP , A) JP-A-10-285017 (JP, A) JP-A-10-285004 (JP, A) JP-A-10-145347 (JP, A) JP-A-8-237091 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G06F 1/10 G11C 11/407 H03L 7/00

Claims (14)

(57) [Claims] 1. A first clock signal is input, and a first clock signal is output, and a second clock signal synchronized with the first clock signal and a third clock signal with a phase advanced from the second clock signal are output. And a third clock signal supplied thereto, synchronized with the third clock signal, and having a predetermined phase from the third clock signal.
And a second synchronization circuit for generating a fourth clock signal which is delayed time, the first synchronization circuit includes an input buffer circuit receiving said first clock signal, first having a plurality of delay elements One delay line, a second delay line having a plurality of delay elements, a control unit for controlling the first and second delay lines, an output signal of the second delay line is delayed, and Three black
A first output buffer circuit that outputs a clock signal, and the third output buffer circuit that outputs the first output buffer circuit.
A clock signal is supplied and the second clock signal is output
A second output buffer circuit, and a delay of the input buffer circuit connected to the first delay line.
Time and the delay time of the first and second output buffer circuits
A first delay monitor having a sum delay time of
And, the second synchronization circuit includes a third delay line having a plurality of delay elements, a plurality of delay elements, a short delay from the third delay line
A fourth delay line having a time, a control unit for controlling the third and fourth delay lines, an output signal of the fourth delay line is delayed , and a fourth delay line is output.
Output buffer circuit for outputting a clock signal and an output terminal connected to the third delay line and supplied to an input terminal.
Delay time of the third clock signal and the third output
The delay time of the sum of the delay time of the force buffer circuit
Synchronization characterized by having two delay monitors
circuit. 2. The ratio of the delay times of the third delay line and the fourth delay line is different from the ratio of the delay time of the second delay monitor and the delay time of the third output buffer circuit. , A fourth output from the third output buffer circuit
The phase of the clock signal is later than that of the second clock signal.
Synchronization circuit according to claim 1, characterized in that it is. 3. The third delay line is m connected to each other.
Number of the delay elements, the fourth delay element has m of the delay elements, n of the delay elements are connected to each other, and mn of the delay elements are short-circuited. The synchronous circuit according to claim 2 , wherein 4. The fourth clock signal is the first clock signal.
The phase should be 90 ° shifted with respect to the clock signal.
The synchronous circuit according to claim 1, wherein: 5. The fourth clock signal is the first clock signal.
The phase is 360 / m ° to the clock signal (however, m is
Integer) shifted.
Synchronous circuit. 6. A plurality of synchronization circuits that generate an output clock signal that is synchronized with an input clock signal and has a phase different from that of the input clock signal .
First and second delay lines are provided, the first delay line has m delay elements , and the second delay line is provided .
Delay line has m delay elements, of which n
The delay elements are connected to each other to form a second delay element group.
And the mn delay elements are connected to each other to generate a third
A delay element group, wherein the first delay element group includes the plurality of delay element groups.
Shared by the synchronous circuit of the second delay element and the second delay element of the third delay element.
A synchronous circuit characterized by being connected to a synchronous circuit. Wherein said first delay line constitutes the fourth delay group <br/> out n pieces of the delay elements of the m delay element is connected to each other, m-n pieces 7. The synchronous circuit according to claim 6 , wherein said delay elements are connected to each other to form a fifth delay element group, and these fourth and fifth delay element groups are connected to each of said synchronous circuits. . 8. The third delay element group is composed of delay elements that are not adjacent to each other.
7. The synchronizing circuit according to 7 . 9. A second clock signal which is input with the first clock signal, is synchronized with the first clock signal, is phase-shifted from the first clock signal, and has a different phase from the second clock signal. And a first delay line having m delay elements connected to each other, and the m delay elements, of which: a second delay line having a first delay element group in which n delay elements are connected to each other, and a second delay element group in which mn delay elements are connected to each other; A control unit for controlling the first and second delay lines; a first output buffer circuit for delaying an output signal of the first delay element group to generate the second clock signal; and a second delay The third clock signal for delaying the output signal of the element group, A second output buffer circuit for generating a delay having a delay time which is a sum of a delay time of the first clock signal and a delay time of the first output buffer circuit, the delay time being connected to the first delay line. A synchronous circuit comprising a monitor. 10. A plurality of input buffer circuits for receiving a clock signal, a first delay line having a plurality of delay elements, a second delay line having a delay amount different from that of the first delay line, and the first delay line. A control unit for controlling the second delay line, a plurality of output buffer circuits for delaying the output signal of the second delay line and outputting first and second clock signals having different delay amounts, and an input terminal Is connected to the input buffer circuit, the output end is connected to the first delay line, and a delay monitor having a delay amount different from the sum of the delay amount of the input buffer circuit and the delay amount of the output buffer circuit is provided. and the delay amount of the first delay line is m, the delay amount of the second delay line
Is n, and the second clock signal is the first clock
When the phase is advanced by k output buffers from the signal
And the number of the output buffer circuits is k + 1,
The number of input buffer circuits is 2n- (k + 1)
A synchronous circuit characterized by. 11. The synchronizing circuit according to claim 10, wherein the delay monitor is composed of m input buffer circuits and m output buffer circuits. 12. A generation circuit for generating a clock signal, and a phase shift for supplying a clock signal generated by the generation circuit and for generating a plurality of internal clock signals having different phases from the clock signal according to the clock signal. A phase shift synchronization circuit; and a memory device connected to the phase shift synchronization circuit and accessed according to a plurality of internal clock signals supplied from the phase shift synchronization circuit. clock signal is input, a first synchronization circuit for outputting the first second clock signal and the third clock signal is advanced in phase than the second clock signal synchronized with the clock signal, the third Clock signal is supplied to the third clock signal, and the phase of the third clock signal is a predetermined angle.
And a second synchronization circuit for generating a fourth clock signal which is delayed time, the first synchronization circuit includes an input buffer circuit receiving said first clock signal, first having a plurality of delay elements One delay line, a second delay line having a plurality of delay elements, a control unit for controlling the first and second delay lines, an output signal of the second delay line is delayed, and Three black
A first output buffer circuit that outputs a clock signal, and the third output buffer circuit that outputs the first output buffer circuit.
A clock signal is supplied and the second clock signal is output
A second output buffer circuit, and a delay of the input buffer circuit connected to the first delay line.
Time and the delay time of the first and second output buffer circuits
A first delay monitor having a sum delay time of
And, the second synchronization circuit includes a third delay line having a plurality of delay elements, a plurality of delay elements, a short delay from the third delay line
A fourth delay line having a time, a control unit for controlling the third and fourth delay lines, an output signal of the fourth delay line is delayed , and a fourth delay line is output.
Output buffer circuit for outputting a clock signal and an output terminal connected to the third delay line and supplied to an input terminal.
Delay time of the third clock signal and the third output
The delay time of the sum of the delay time of the force buffer circuit
A semiconductor monitor having two delay monitors
Body memory. 13. The ratio of the delay times of the third delay line and the fourth delay line is the delay time of the second delay monitor and the delay times of the third and fourth output buffer circuits. Different from the ratio , output from the third output buffer circuit
The fourth clock signal is higher than the second clock signal.
13. The semiconductor memory device according to claim 12 , wherein the phases are delayed . 14. The third delay line has m delay elements connected to each other, and the fourth delay element has m delay elements, of which n delays are included. 14. The semiconductor memory device according to claim 13 , wherein elements are connected to each other, and the mn delay elements are short-circuited.