JP2008090598A - Memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make a non-standard device such as an FPGA which is not suitable for a standard value relating to required output delay coexist with a standarid device on the same bus. <P>SOLUTION: This storage device is provided with: standard devices 2 and 3; non-standard device 4; and a controller 1 for generating a first read clock #1; and a delay control part 47 for receiving the first read clock #1, and for supplying it to the nonstandard device 4, and for generating a second read clock #2 by delaying the first read clock #1 according to the output delay time in the nonstandard device 4, and for supplying the second read clock #2 to standard devices 2 and 3. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a storage device, and relates to a technique suitable for a storage device using, for example, a memory device capable of high-speed operation such as QDR SRAM conforming to a QDR (Quad Data Rate) system.

In recent years, the transmission speed of communication devices has increased with the spread of the Internet and the like. Therefore, a communication device that requires high-speed transmission requires a device such as a memory that can operate at high speed. As a conventional memory capable of high-speed operation, a DDR (Double Data Rate) type memory (DDR SRAM) and a QDR (Quad Data Rate) type memory (QDR SRAM) are known.
Here, DDR SRAM captures address signals and control signals from the processor and bus controller in the SRAM in synchronization with the system clock, and synchronizes both the rising and falling edges of the clock, making it easier than before. Thus, a double transfer rate is realized. QDR SRAM further separates the data input and data output, operates both in DDR, and simultaneously performs reading and writing, thereby transferring twice as much as the DDR method (4 times the conventional method). The rate is realized.

Although there is no direct technical relevance to these DDR schemes and QDR schemes, as a known clock timing adjustment technique, for example, there is a technique proposed in Patent Document 1 below.
That is, Patent Document 1 describes the comparison between a comparison clock and a reference clock using a loopback wiring for the purpose of enabling stable data transmission and reception at the time of writing and reading even when there is a wiring length delay. There is a disclosure of a method for adjusting the phase of a read clock in a DLL (Delay Locked Loop) circuit so that the phase difference becomes zero.
JP 2000-293429 A

  By the way, in general, devices that can be connected to a processor or bus controller (hereinafter collectively referred to as “controller”) conforming to the QDR system are QDR standard devices such as QDR SRAM, LA-1 [NPF (Network Processing Forum Look-Aside] standard) is limited to ASIC (Application Specific Integrated Circuit) and the like. The reason is that since the A / C characteristics required by the controller are very critical, the requirements cannot be satisfied unless the device is designed on the assumption of QDR connection.

  11 and 12 show an example of the prior art. FIG. 11 shows a configuration when the controller 101 performs access control (write / read control) for QDR SRAMs 102 and 103 connected in multiple stages (series) via a QDR bus (write data bus, read data bus, etc.). 11 shows a configuration when the controller 101 performs access control to a single ASIC 104 via the QDR bus. In these FIGS. 11 and 12, reference numeral 202 denotes a transmission path (such as write data, write address, and control signal). Write data bus), 201 represents a write clock transmission path (write clock line), 203 represents a read data transmission path (read data bus), and 204 represents a read clock transmission path (read clock line). Yes.

  That is, in the configuration shown in FIG. 11, write data is supplied from the output port “K” of the controller 101 to the QDR SRAM 102 from the output port “A / D / CNT”. Writing to the QDR SRAM 102 or transfer to the QDR SRAM 103 is executed, and writing of write data to the QDR SRAM 103 is executed according to the transferred write clock.

On the other hand, a read clock is output from the output port “CO” of the controller 101, and this is given in the order of the QDR SRAMs 103 and 102, whereby data reading from the QDR SRAMs 103 and 102 is sequentially executed, and the input port “ Read data is input to “DIN”, and a read clock is input to the input port “CIN”.
In the configuration shown in FIG. 12 as well, write data is supplied from the output port “K” of the controller 101 to the ASIC 104 and write data is output from the output port “A / D / CNT” to the ASIC 104. Is written to the ASIC 104. Further, when a read clock is applied to the ASIC 104 from the output port “CO” of the controller 101, data reading from the ASIC 104 is executed, and read data is read from the input port “DIN” of the controller 101 to the input port “CIN”. Each clock is input.

  As described above, in the general QDR circuit configuration, with respect to the connection of the clock output from the controller 101, the write clock is matched with the connection order of the address lines and write data, and the read clock is the reverse of the write clock. By doing this, the propagation delay on the printed board between the clock and the other signal lines becomes the same with respect to the data traveling direction, and the data fetch timing can be unified. Note that the write clock and the read clock can be controlled independently, and the output timing of the read data can be adjusted by the input phase of the read clock.

  By the way, as described above, QDR is a technique for improving the data transfer speed by separating both the data input port and the output port and using both edges of the clock. Therefore, the required A / C characteristic is critical. That is, in a general QDR SRAM, when the write clock and the read clock have the same phase, the data output timing (latency) at the time of reading is 1.5 clocks (TCO is 0 to 500 ps) from taking in the address and read clock. It is later (see arrow 110 in FIGS. 11, 12 and 13). TCO represents a delay time from a clock edge to data output.

  However, the above idea in the read cycle is based on the premise that the output delay of each device constituting the circuit satisfies the QDR standard (such a device is hereinafter referred to as a QDR standard device), and is on the QDR bus. If even one device with a large (or small) delay (non-QDR standard device) exists, the data capture timing on the controller 101 side cannot be fixed, and this is not established. The reason why the device connected to the controller 101 is limited to a specific device is that it is necessary to satisfy this output delay in addition to the QDR protocol.

  Therefore, even when a general-purpose device such as an FPGA (Field Programmable Gate Array) is originally used for a portion where a QDR standard device such as an ASIC should be used, the output delay of 1.5 clocks (TCO is 0 to 500 ps) described above. Satisfaction is very difficult to achieve even if the circuit configuration inside the FPGA is optimized by using a high-speed FPGA product (which is naturally expensive).

That is, in the case of a circuit configuration in which only a general-purpose device such as an FPGA exists on the same QDR bus, the data fetch timing on the controller 101 side may be adjusted in accordance with the output delay of the general-purpose device. If different devices are mixed, it cannot be realized only by the setting on the controller 101 side and cannot be realized.
For example, assuming that a QDR standard device such as QDR SRAMs 102 and 103 and a general-purpose device (non-QDR standard device) such as FPGA 105 are mixed on the QDR bus as shown in FIG. As shown in FIG. 4, the controller 101 does not satisfy the standard that the delay time from fetching the address and read clock to the read data output in the non-QDR device 105 is 1.5 clocks (TCO is 0 to 500 ps). Data cannot be read.

By the way, if a 150 MHz clock is used, it is necessary to output data in phase with the read clock (0 phase) in 10 ns from the address fetch. If this is 200 MHz, an output delay time of 7.5 ns is required. It will be.
Note that the technique (clock phase control circuit) of Patent Document 1 can only absorb the clock phase shift caused by the wiring length delay due to the presence of the folded wiring. Even if this technique is applied to the QDR technique, The output timings of the data (read data) output from the QDR standard device and the general-purpose device such as the FPGA cannot coincide with each other or fall within the QDR standard.

  The present invention was devised in view of such problems, and enables general-purpose devices (non-standard devices) such as FPGAs that do not conform to the standard value related to required output delay to coexist with standard devices on the same bus. With the goal.

In order to achieve the above object, the present invention is characterized by using the following storage device. That is,
(1) The storage device of the present invention outputs a read data to the data bus within a specified output delay time after receiving the read clock, and outputs the read data to the data bus after receiving the read clock. A non-standard device that exceeds the output delay time by the time, a controller that generates a first read clock, a first read clock from the controller that is supplied to the non-standard device, and the first And a delay control unit that generates a second read clock that is delayed according to the output delay time of the non-standard device and supplies the read clock to the standard device.

(2) Here, the storage device may further include a setting register for setting a delay amount of the first read clock in the delay control unit.
(3) Whether the controller can normally receive the read data output from the standard device and the non-standard device from the data bus while changing the setting of the delay amount for the setting register. A delay amount setting control unit that confirms and optimizes the delay amount may be provided.

(4) Further, in the present storage device, a plurality of the standard devices are connected in series via the data bus, and the delay control unit generates the plurality of second read clocks to generate the standards. You may comprise so that it may supply separately as a read clock of a device.
(5) In addition, the delay control unit sets the delay amount of each second read clock so as to absorb the delay amount generated according to the difference between the wiring length of the second read clock and the wiring length of the data bus. It may be configured to adjust individually.

According to the present invention, at least one of the following effects or advantages can be obtained.
(1) Since the read clock supplied from the controller to the nonstandard device is delayed by the delay control unit according to the excess time of the output delay time of the nonstandard device and supplied to the standard device, The read data output timing (phase) can be matched. Therefore, a standard device and a nonstandard device can be used together. As a result, a general-purpose device such as an FPGA that can be easily changed in circuit as compared with a standard device can be applied, and flexible circuit design and reduction in manufacturing cost can be achieved.

(2) Also, by providing the setting register, the output phase of the second read clock can be changed (adjusted) at any time.
(3) Further, while changing the setting from the delay amount setting control unit, confirm whether or not the read data output from the standard device and the non-standard device can be normally received from the data bus, Since the delay amount can be optimized, it is possible to always perform normal access to each device.

(4) If the second read clock is individually connected to each device, it is possible to eliminate the influence of the lead clock waveform breakage caused by reflection, which greatly contributes to the stability and reliability of the product. Is possible.
(5) Further, by individually adjusting the delay amount of each second read clock, the delay amount generated according to the difference between the wiring length of the second read clock and the wiring length of the data bus is absorbed. Therefore, the read clock line length can be optimized (minimized). Therefore, it is possible to more effectively remove the influence of the lead clock waveform breakage due to reflection, and it is possible to greatly contribute to the stability and reliability of the product.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention is not limited to the following embodiments, and it goes without saying that various modifications can be made without departing from the spirit of the present invention.
[A] Outline
In a configuration in which a QDR standard device such as QDR SRAM and an ASIC coexist on the same bus, if it is necessary to add a function to the part that should originally be an ASIC or to implement a completely different function, it is usually an ASIC. However, if a general-purpose device such as an FPGA can be used here, the development period can be shortened and functions can be added flexibly because of the characteristics of general-purpose devices (QDR non-standard (non-standard) devices). It becomes possible.

However, as described above, the latency and the delay amount of a general-purpose device such as an FPGA in the read cycle are relatively large. Therefore, even if the circuit inside the general-purpose device is optimized to the maximum, the same configuration as in the case of the ASIC is used. The requirements of the standard cannot be satisfied.
Therefore, in the present embodiment, the data output of the QDR standard device is delayed by manipulating the read clock for the QDR standard device such as QDR SRAM, that is, intentionally delaying by, for example, a DLL circuit, and the respective output phases. Adjust. As a result, it is possible to eliminate a delay portion of data output during a read cycle of a general-purpose device such as an FPGA, and it is possible to apply a general-purpose device such as an FPGA to a portion that should originally be a QDR standard device such as an ASIC. .

  Specifically, the read clock supplied to the QDR standard device such as QDR SRAM is delayed by the output delay excess of the general-purpose device such as FPGA (time exceeding 1.5 clock) using the DLL circuit. By combining them, it is possible to make the clock and data phases seen on the QDR bus controller side the same without depending on the device that has performed the read access.

[B] Description of First Embodiment FIG. 1 is a block diagram showing a configuration of a QDR-compliant storage device (QDR bus connection configuration) according to the first embodiment of the present invention. The storage device shown in FIG. QDR bus controller 1 and QDR standard device (standard device), that is, QDR memory (QDR SRAM) that outputs read data within a specified output delay time (QDR standard value) of 1.5 clock + TCO after receiving a read clock ) 2, 3 and non-QDR standard devices, that is, general-purpose devices 4 such as FPGAs (hereinafter referred to as FPGA 4) that exceed the QDR standard value after receiving a read clock and outputting read data, From the side closer to the QDR bus controller 1, the devices 2, 3, 4 are arranged in the order of the QDR memory 2, 3, FPGA 4, the data bus and clock line They are connected to each other through.

  That is, in FIG. 1, reference numeral 11 is a transmission path (write clock line) for a write clock (K), and reference numeral 12 is a transmission path (write data bus) for write data (including a write address and a control signal, the same applies hereinafter). Reference numeral 13 represents a read data transmission path (read data bus), and reference numeral 14 (14a, 14b) represents a read clock transmission path (read clock line). The data buses 12 and 13 and the clock lines 11 and 14 are wired so that the read clock and read data travel directions (the left direction in FIG. 1) are the same. Has been.

  However, the data buses 12 and 13 and the clock lines 11 and 14 are wired only between the QDR bus controller 1 and the devices 2, 3 and 4, and pass through the devices as shown in FIG. The portion is not a physical wiring, but merely represents a clock and data transmission path. In FIG. 1, the transmission paths 11, 12, 13, and 14 are partially bent in the middle (for example, in the QDR memories 2 and 3, etc.) for write / read clock and write / read data. Expresses the required output delay. Further, the dotted arrow 15 indicates that “1.5 clock (latency) + TCO” from when the QDR memories 2 and 3 receive the read clock supplied from the FPGA 4 to when the read data is actually output to the read data bus 13. The time (output delay) is required.

  Here, the QDR bus controller (hereinafter also simply referred to as “controller” 1 outputs a write clock from the output port “K” to the write clock line 11 and also according to the write clock from the output port “A / D / CNT”. By outputting write data to the write data bus 12, write processing to the internal memories and registers of the QDR memories 2 and 3 and FPGA 4 is executed, while read clock # 1 is output from the output port “CO” to the read clock line 14a. At the same time, the read clock # 2 and read data via the read clock line 14b and the read data bus 13 are received at the input ports "CIN" and "DIN", respectively, so that the read processing for the QDR memories 2, 3 and FPGA 4 is executed It has the function to do.

  The QDR memories 2 and 3 store and transfer write data from the write data bus 12 according to the write clock (K) from the controller 1, respectively, while data according to the read clock # 2 input from the read clock line 14b. And reading the read data to the read data bus 13, and outputting (transferring) the input read clock # 2 to the read clock line 14b on the output side.

  The FPGA 4 stores the write data from the write data bus 12 in accordance with the write clock (K) from the controller 1, while reading out data in accordance with the read clock # 1 input from the controller 1 (read clock line 14a). The read data is output to the read data bus 13 and the input read clock # 1 is delayed by the internal DLL circuit 47 and output to the read clock line 14b as the read clock # 2.

  That is, the FPGA 4 of this example delays the read clock # 1 (CO) from the controller 1 by the read data output delay of the FPGA 4 by the DLL circuit 47 and supplies it to the QDR memories 2 and 3 as shown in FIG. By using the read clock # 2 (CIN), the read data output timing (phase) of the QDR standard devices 2 and 3 and the non-QDR standard device (FPGA) 4 can be matched. . As a result, even if the non-QDR standard device 4 is mixed with the QDR standard devices 2 and 3, it apparently operates in conformity with the QDR standard. In FIG. 2, the presence of the pattern delay is ignored.

  Therefore, specifically, in the FPGA 4 of this example, when focusing on its main part, for example, as shown in FIG. 3, DLL setting units 41 and 46, DLL circuits 42 and 47, flip-flop (FF) circuits 43, 45, An internal memory (register, etc.) 44 is provided. In FIG. 3, reference numeral 48 represents a buffer. Further, the components other than the DLL circuit 47 are collectively shown as an internal memory / control unit 40 in FIG.

  Here, each of the DLL circuits 42 and 47 locks the input clock phase and generates an output clock delayed by a fixed time by the clock phase shift circuit. The DLL circuits 42 and 47 may use existing DLL circuits in the FPGA 4. Specifically, the DLL circuit (delay control unit) 47 supplies the read data output clock (Clk-C) supplied to the FF 45 from the read clock # 1 (CO) supplied from the controller 1 and the QDR standard devices 2 and 3. The read clock # 2 (CIN) to be supplied is generated, and the DLL circuit 42 controls the internal clock for address fetching (Clk-A) and the internal memory 44 from the write clock (K) for fetching the address. For generating a clock (Clk-B). The fixed delay times of the DLL circuits 42 and 47 are set by the DLL setting units 41 and 46 and are defined in the circuit data generation process stage of the FPGA 4.

  The FF 43 takes in the read address input (A) for the internal memory 44 in accordance with the address take-in internal clock (Clk-A) from the DLL circuit 42 and supplies it to the internal memory 44. In accordance with the control clock (Clk-B) from the DLL circuit 42, the data written in the storage area indicated by the read address from the FF 43 is output as read data.

The FF 45 takes in the read data output from the internal memory 44 in accordance with the read data output clock (Clk-C) from the DLL circuit 47 and outputs it to the read data bus 13.
The operation of the internal memory 44 in the read cycle and the adjustment method of the DLL circuits 42 and 47 in the FPGA 4 configured as described above will be described below with reference to the time chart shown in FIG.

  (S1) First, as shown in (1) and (2) of FIG. 4, read by the clock (Clk-A) generated by the DLL circuit 42 with the rising edge of the write clock (K) for taking in the address as a reference. Capture address input (A). The phase of the clock (Clk-A) is set to the minus side (fastening direction) to a position where the setup time of the FF 43 can be satisfied, thereby realizing fast address fetching.

(S2) Similarly, as shown in (3), (4), and (5) of FIG. 4, the clock (Clk-B) generated by the delay by the DLL circuit 42 with the rising edge of the write clock (K) as a reference. The read address is input to the internal memory 44. The clock (Clk-B) is adjusted to a position satisfying (wiring delay to the internal memory 44) + (setup time of the internal memory 44).
(S3) As shown in (6), (7), and (8) of FIG. 4, a clock (delayed and generated by the DLL circuit 42 with reference to the rising edge of the read clock # 1 (CO) supplied from the controller 1 ( Clk-C) fetches the read data output from the internal memory 44 and outputs the read data from the FPGA 4. Normally, a synchronous method using another read clock is used for data output from the internal memory 44. However, an asynchronous method is adopted in order to speed up the data output, and the clock (Clk is set at a position that satisfies the setup time of the FF 45. -C) is adjusted.

  (S4) As shown in (9) and (10) of FIG. 4, the phase of the read clock # 2 (CIN) to be supplied from the DLL circuit 47 to the QDR memories 2 and 3 is the FF 45 and its output side buffer 48. Is adjusted so that the time from the fall of the read clock # 2 to the data output satisfies the TCO (0 to 500 ps) standard. This adjustment is performed by setting the DLL circuit 47 from the DLL setting unit 46.

  Here, as shown in FIG. 3, the DLL circuit 47 of this example has a number (here, four) of clock phase shift circuits (tap delay circuits) 471-1 to 471 corresponding to the number of clocks that can be generated. -4 and selectors 472-1 to 472-4 respectively corresponding to the clock phase shift circuit 471-i (i = 1 to 4), and the clock phase shift circuit 471-i steps the input clock in stages. A plurality of clocks having different phases are generated by phase shifting, and one of them is selected and output by the selector 472-i according to the setting from the DLL setting unit 46, so that a clock obtained by delaying the input clock by a required amount can be up to four. The system can be generated and output.

  In this example, as can be seen from FIG. 3, two of the four systems are used, that is, the clock (Clk-C) is set by the combination of the clock phase shift circuit 471-1 and the selector 472-1. The read clock (CIN) is generated by the combination of the clock phase shift circuit 471-2 and the selector 472-2. Note that the remaining two systems (the set of the clock phase shift circuit 471-3 and the selector 472-3 and the set of the clock phase shift circuit 471-4 and the selector 472-4) are both unused in this embodiment. (Used in the second embodiment to be described later).

  More specifically, the clock phase shift circuit 471-i has the ability to phase shift the input clock in units of 9 (deg) when one clock cycle is 360 (deg), for example, as shown in FIG. , The adjustment tap value X = t / {(1 / f) /, where t (seconds) is the time to be delayed and f (Hz) is the frequency of the read clock 1. (360/9)}.

Therefore, for example, when the frequency of the read clock # 1 that is the input clock to the phase shift circuit 471-2 is 150 MHz and it is necessary to output the read clock # 2 delayed by about 1000 ps,
X = (1000 × 10 ¹² ) / {(1/150 × 10 ⁶ ) / (360/9)} = 6
Thus, the selector 472-2 only has to select and output a clock that has received a phase shift amount of 6 taps by the clock phase shift circuit 471-2.

  As described above, according to the present embodiment, the read clock # 1 (CO) supplied from the controller 1 to the FPGA 4 is delayed by the output delay of the FPGA 4 by the DLL circuit 47 and supplied to the QDR memories 2 and 3. By setting the clock # 2 (CIN), the read data output timing (phase) of the QDR standard devices 2 and 3 and the non-QDR standard device (FPGA) 4 can be matched. It becomes possible to use the device 4 outside the QDR standard together.

  Accordingly, since the FPGA can be applied as the non-QDR standard device 4, the feature of the FPGA 4 that the circuit can be changed relatively easily can be used, and flexible circuit design, reduction in manufacturing cost, and the like can be achieved. . In recent device development, since the development period is very short, it is very common to develop a prototype in advance with FPGA4 and realize cost reduction by implementing ASIC for the part that can be shipped. . Whether or not the FPGA 4 can be used is an extremely important factor that affects not only the sales of the product but also the existence itself, and the effect is immeasurable only by that point.

(B1) Description of Modification Note that the FPGA 4 described above relates to a clock phase shift amount (that is, DLL delay amount) with respect to the DLL setting unit 46 (41) shown in FIG. A DLL setting register 50 for providing setting information can be provided. In FIG. 6, the parts denoted by the same reference numerals as those described above represent the same or similar parts as those already described, and the internal memory / control unit 40 shown in FIG. Notation is omitted.

By providing the DLL setting register 50, the output phase of the read clock # 2 can be changed (adjusted) at any time.
Then, the setting of the DLL delay amount for the DLL setting register 50 can be automatically performed via the control bus 51 by the software 10 of the controller 1 as shown in FIG.

That is, first, the software 10
(S21) An appropriate initial value is set in the DLL setting register 50 as the DLL delay amount of the FPGA 4,
(S22) The write clock and the write data are actually given to the FPGA 4, and the read clock # 1 is given to execute the write process and the read process to check whether or not the read data can be normally received. .

(S23) As a result, if the read data cannot be received normally, the software 10 resets the DLL delay amount shifted by a predetermined amount from the initial value in the DLL setting register 50.
(S24) The software 10 repeatedly executes the processes of S22 and S23 until the read data can be normally received, and confirms the setting range of the DLL delay amount that allows normal access,
(S25) Finally, the DLL delay amount is set in the DLL setting register 50 so as to be the center of the set width.

That is, whether or not the software 10 of this example can normally receive the read data output from the QDR memories 2 and 3 and the FPGA 4 from the read data bus 13 while changing the setting of the DLL delay amount for the DLL setting register 50. The function as a delay amount setting control unit that optimizes the DLL delay amount is confirmed.
Thus, by setting the DLL delay amount and performing the write / read check from the software 10, the controller 1 can optimize the DLL delay amount by which the read data can be normally received. 1 can always perform normal access to each device 2, 3, 4.

[C] Description of Second Embodiment FIG. 8 is a block diagram showing the configuration of a QDR-compliant storage device (QDR bus connection configuration) according to the second embodiment of the present invention. The storage device shown in FIG. 1 includes a controller 1, QDR memories (QDR SRAMs) 2 and 3, and an FPGA 4, which are the same as or similar to those described above (however, the internal memory / control unit 40 is shown in the figure). Although not shown), all four clock outputs of the DLL circuit 47 described above with reference to FIG. # 2 can be given.

  That is, for example, the output (read clock # 2) of the selector 472-2 shown in FIG. 3 is connected to the read clock input of the QDR memory 3 by the read clock line 14 (14b), and the output (read clock # 3) of the selector 472-3 is connected. ) Is connected to the read clock input of the QDR memory 2 via the read clock line 14 (14c), and the output (read clock # 4) of the selector 472-4 is connected to the input port “CIN” of the controller 1 via the read clock line 14 (14d). Connect to. Note that the output of the selector 472-1 (internal clock (Clk-C)) is supplied to the FF 45 as in the first embodiment.

  However, the read clock lines 14b to 14d are wired so as to have the same length as the corresponding read data bus. That is, the read clock line 14b for the read clock # 2 is wired so as to be the same length as the read data bus 13 between the FPGA4-QDR memories 3, and the read clock line 14c for the read clock # 3 is connected to the FPGA4-QDR. The read clock bus 14d for the read clock # 4 is wired between the memories 3 and the FPGA4-QDR memory 2 so as to have the same length as the total of the read data buses 13, and is connected between the FPGA4-QDR memories 3 and the FPGA4-QDR memories. 2 and between the QDR memory 2 and the controller 1 are wired so as to have the same length as the total of the read data bus 13.

Thereby, even if the delay amount (phase shift amount) of the read clocks # 2, # 3, and # 4 with respect to the read clock # 1 is the same, the controller 1 normally accesses the devices 2, 3, and 4. be able to.
In this example, the read clocks # 1, # 2, # 3, and # 4 are individually connected (one-to-one) to the devices 4, 3, 2, and 1, so that the first embodiment As compared with the first embodiment, it is possible to eliminate the influence of the lead clock waveform cracking due to reflection, and greatly contribute to the stability and reliability of the product. It is.

In this example, the read clocks # 1 to # 4 are generated by a single DLL circuit 47, but a plurality of individually or partially shared DLL circuits are prepared so that equivalent clocks can be generated. (The same applies to the following modifications).
(C1) Description of Modified Example In the read clock independent wiring configuration described above with reference to FIG. 8, the delay amount of each read clock # 2, # 3, # 4 generated by the DLL circuit 47 is individually set by the DLL setting unit 46. By adjusting, it is possible to optimize the wiring length of the read clocks # 2, # 3, and # 4.

That is, each of the read clock lines 14b to 14d is wired with the shortest length, and the delay due to the difference from the wiring length of the corresponding read data bus 13 is the delay amount in the DLL circuit 47 as read clocks # 2 and # 3. , # 4 (that is, tap outputs selected by the selectors 472-2, 472-3, and 472-4 shown in FIG. 3 are individually set).
For example, the delay amount of the read clock # 2 is set by setting the delay due to the wiring length difference between the FPGA4-QDR memory 3 and the read data bus 13 together with the TCO delay of the FPGA 4, and the delay amount of the read clock # 3 is The delay due to the wiring length difference between the FPGA4-QDR memory 3 and between the FPGA4-QDR memory 2 and the read data bus 13 is set together with the TCO delay of the FPGA 4, and the delay amount of the read clock # 4 is set to the FPGA4- The delay due to the wiring length difference between the read data bus 13 between the QDR memories 3, between the FPGA 4 -QDR memory 2 and between the QDR memory 2 and the controller 1 is set together with the TCO delay of the FPGA 4.

  Thus, the read clock line length is not equal to the read data bus length as in the second embodiment, but the read clock line is made the shortest, and the wiring length difference due to this is absorbed by the DLL circuit 47. By adjusting the phase in this manner, the read clock line length can be optimized (minimized). Therefore, as compared with the second embodiment described above, it is possible to more effectively remove the influence of the waveform crack of the read clock due to reflection, which can greatly contribute to the stability and reliability of the product. is there.

In the second embodiment described above and its modifications, the setting register 50 may be provided as in the modifications (FIGS. 6 and 7) of the first embodiment. It is also possible to apply settings and write / read checks.
[D] Others In each of the first and second embodiments and the modifications described above, the DLL circuit 47 is built in the FPGA 4, but may be provided outside the FPGA 4, for example, as shown in FIG. . However, since it is necessary to delay the read clock # 2 supplied to the QDR memories 2 and 3 with respect to the read clock # 1 to the FPGA 4, at least the read clock # 1 output from the FPGA 4 is used as the QDR standard device 3 (2). Need to be delayed before feeding.

In the above-described embodiment, the case where the two QDR standard devices 2 and 3 exist between the controller 1 and the FPGA 4 is illustrated, but of course, one or three or more may exist. The same effects as above can be obtained.
[E] Appendix (Appendix 1)
A standard device that outputs read data to the data bus within the specified output delay time after receiving the read clock, and
A non-standard device that exceeds the output delay time from receiving a read clock to outputting read data to the data bus;
A controller for generating a first read clock;
The first read clock is received from the controller and supplied to the non-standard device, and a second read clock is generated by delaying the first read clock according to the output delay time in the non-standard device. And a delay control unit for supplying the standard device.

(Appendix 2)
The storage device according to appendix 1, further comprising a setting register for setting a delay amount of the first read clock in the delay control unit.
(Appendix 3)
The controller
While changing the setting of the delay amount for the setting register, it is confirmed whether or not the read data output from the standard device and the non-standard device can be normally received from the data bus, and the optimum delay amount is determined. The storage device according to appendix 2, further comprising a delay amount setting control unit for performing the conversion.

(Appendix 4)
A plurality of the standard devices are connected in series via the data bus,
The delay control unit
The storage device according to appendix 1, wherein a plurality of the second read clocks are generated and individually supplied as read clocks for the standard devices.

(Appendix 5)
The delay control unit
The delay amount of each of the second read clocks is individually adjusted to absorb the delay amount generated according to the difference between the wiring length of the second read clock and the wiring length of the data bus. The storage device according to appendix 4, which is characterized.

(Appendix 6)
6. The storage device according to any one of appendices 1 to 5, wherein the delay control unit is provided in the non-standard device.
(Appendix 7)
6. The storage device according to any one of appendices 1 to 5, wherein the delay control unit is provided outside the non-standard device.

1 is a block diagram showing a configuration of a storage device (QDR bus connection configuration) compliant with QDR according to a first embodiment of the present invention. FIG. 3 is a time chart for explaining an operation during a read cycle of the storage device shown in FIG. 1. FIG. 2 is a block diagram illustrating a configuration of a general-purpose device (around a DLL circuit) illustrated in FIG. 1. 4 is a time chart for explaining an operation during a read cycle of the general-purpose device shown in FIG. 3. 4 is a time chart for explaining a delay adjustment method of the DLL circuit shown in FIG. 3. It is a block diagram which shows the modification of the memory | storage device shown in FIG. It is a block diagram which shows the modification of the memory | storage device shown in FIG. It is a block diagram which shows the structure of the memory | storage device (QDR bus connection structure) based on QDR which concerns on 2nd Embodiment of this invention. It is a block diagram which shows the modification of the memory | storage device shown in FIG. FIG. 10 is a block diagram illustrating a modification of the storage device illustrated in FIGS. 1 and 6 to 9. It is a block diagram which shows the structure of the memory | storage device based on the conventional QDR. It is a block diagram which shows the structure of the memory | storage device based on the conventional QDR. 13 is a time chart for explaining an operation during a read cycle of the storage device shown in FIGS. 11 and 12; It is a block diagram which shows the structure of a memory | storage device in order to demonstrate the subject of a prior art. 15 is a time chart for explaining an operation during a read cycle in the configuration shown in FIG.

Explanation of symbols

1 QDR bus controller 2, 3 QDR SRAM (QDR standard device: standard device)
4 FPGA (non-QDR standard device)
10 Software (Delay amount setting control unit)
11 Write clock line (transmission path)
12 Write data bus (transmission path)
13 Read data bus (transmission path)
14, 14a, 14b, 14c, 14d Read clock line (transmission path)
40 internal memory / control unit 41, 46 DLL setting unit 42, 47 DLL circuit 471-1 to 471-4 clock phase shift circuit (tap delay circuit)
472-1 to 472-4 selector 43, 45 FF circuit 48 buffer 50 DLL setting register 51 control bus

Claims (5)

A standard device that outputs read data to the data bus within the specified output delay time after receiving the read clock, and
A non-standard device that exceeds the output delay time from receiving a read clock to outputting read data to the data bus;
A controller for generating a first read clock;
The first read clock is received from the controller and supplied to the non-standard device, and a second read clock is generated by delaying the first read clock according to the output delay time in the non-standard device. And a delay control unit for supplying the standard device.   2. The storage device according to claim 1, further comprising a setting register for setting a delay amount of the first read clock in the delay control unit. The controller
While changing the setting of the delay amount for the setting register, it is confirmed whether or not the read data output from the standard device and the non-standard device can be normally received from the data bus, and the optimum delay amount is determined. 3. The storage device according to claim 2, further comprising a delay amount setting control unit for performing the conversion. A plurality of the standard devices are connected in series via the data bus,
The delay control unit
The storage device according to claim 1, wherein the storage device is configured to generate a plurality of the second read clocks and individually supply the second read clocks as the read clocks of the standard devices. The delay control unit
The delay amount of each of the second read clocks is individually adjusted to absorb the delay amount generated according to the difference between the wiring length of the second read clock and the wiring length of the data bus. The storage device according to claim 4, wherein the storage device is characterized.

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