JP2006331190A - Clock control circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To facilitate delay time adjustments by optimizing a clock tree in a clock control circuit for LSI integrating test circuits. <P>SOLUTION: The clock control circuit comprises a system register 21, a memory 22, a scan bypass register 23 and a BIST register 24. Clocks supplied to the registers are selected by a single multiplexer 11. Clock lines for transmitting the clocks to the registers are bundled into a single clock line 30. The multiplexer 11 comprises a first input terminal P1 to which a BIST clock is applied in a BIST mode and a scan clock is applied in a scan mode, and a second terminal P2 to which a system clock is applied. The multiplexer 11 is controlled by the output of an OR circuit 12 into which a BIST mode signal and a scan mode signal are input. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a clock control circuit, and more particularly to an LSI clock control circuit incorporating a test circuit.

  Recent LSIs have built-in test circuits such as a scan test circuit and a BIST circuit, thereby enabling a test for finding a faulty part of a logic circuit or a memory circuit. A scan test circuit is a circuit in which flip-flop circuits are arranged corresponding to each logic circuit in an LSI, and a plurality of flip-flop circuits are connected in a chain to form a shift register, which is taken into each flip-flop. The logic circuit is tested by performing a shift operation for shifting the data one after another and a capture operation for fetching the output of each logic circuit into each flip-flop. The BIST circuit is a circuit that enables a self-diagnosis test of the memory. BIST is an abbreviation for Built-In-Self-Test.

  In an LSI incorporating such a test circuit, system mode (normal LSI operation mode), scan mode (test operation mode for each logic circuit, mainly system registers), BIST mode (test for memory) In order to guarantee each operation mode (operation mode), it is necessary to supply a necessary clock by the clock control circuit via the clock line.

  FIG. 2 is a diagram showing a conventional clock control circuit in an LSI incorporating such a test circuit. Four registers, a system register 21, a memory 22, a scan bypass register 23, and a BIST register 24 necessary for each of the three operation modes are prepared.

  The system register 21 is a normal register used in the system. The scan bypass register 23 is a register for bypassing (bypassing) the memory 22 that becomes a barrier in the scan mode.

  It is necessary to selectively supply clocks to necessary registers for each operation mode. That is, as shown in FIG. 3, in the system mode, the system clock is supplied to the clock input terminals of the system register 21 and the memory 22. In the scan mode, a scan clock is supplied to the system register 21, the scan bypass register 23, and the BIST register. The scan clock is a clock for performing the aforementioned shift operation. In the BIST mode, it is necessary to supply a BIST clock to the memory 22 and the BIST register 24.

  For this purpose, in the clock control circuit of FIG. 2, two multiplexers (selectors) 51 and 52 and two clock lines 61 and 62 are used. In the system mode, the logical values of the BIST mode signal and the scan mode signal are both “0”, and the multiplexer 51 selects and outputs the system clock. Then, the system clock is supplied to the system register 21 and the memory 22 via the clock line 61, and normal LSI operation is performed.

  In the scan mode, since the logical value of the BIST mode signal is set to “0” and the logical value of the scan mode signal is set to “1”, the multiplexer 51 selects and outputs the scan clock. Then, the scan clock is supplied to the system register 21, the scan bypass register 23, and the BIST register 24 to test whether or not each of the registers 21, 23, 24 operates correctly.

In the BIST mode, since the logical value of the BIST mode signal is set to “1” and the logical value of the scan mode signal is set to “0”, the multiplexer 52 selects and outputs the BIST clock. Then, the BIST clock is supplied to the memory 22 and the BIST register 24 to test whether the memory 22 operates correctly. The following patent documents are listed as related technical documents.
JP 2001-59856 A

  By the way, in each operation mode, in order to operate the register supplied with the clock selected by the multiplexer (selector) in synchronization with the clock, it is necessary to align the arrival times of the clocks. For example, in the system mode, the system clock needs to reach the system register 21 and the memory 22 simultaneously. In other words, it is necessary to align the delay time of the clock from the clock source to the clock input terminal of the register and memory. This is the same in other operation modes. For this purpose, a delay buffer is inserted into the clock line to adjust the clock delay time.

  However, in the clock control circuit of FIG. 2, since two multiplexers (selectors) 51 and 52 and two clock lines 61 and 62 are used, such a delay time adjustment work becomes complicated. was there.

  Therefore, the clock control circuit of the present invention is a clock control circuit that supplies necessary clocks to the system register, the memory, the scan bypass register, and the BIST register, and the scan clock according to the BIST mode signal and the scan mode signal. A multiplexer that selects and outputs one of the BIST clock and the system clock, and a single clock line that is connected to the output of the multiplexer and transmits the clock selected by the multiplexer. The clock selected from the clock line is supplied to the system register, memory, scan bypass register, and BIST register.

  According to the clock control circuit of the present invention, the clock line is simplified and the clock tree is optimized, so that the adjustment work of the delay time of the complicated clock line is simplified. In addition, since the number of delay buffers inserted in the clock line is reduced, the chip area is reduced and the power consumption is also reduced. In addition, since the delay time of the system clock and the BIST clock can be made equal, the memory test at the actual operation speed (system operation speed) can be performed in the BIST mode.

  Hereinafter, a clock control circuit according to an embodiment of the present invention will be described with reference to the drawings.

  The clock control circuit includes a system register 21, a memory 22, a scan bypass register 23, and a BIST register 24. In addition, whether or not the clocks output from the multiplexer 11 are selected and supplied to the registers 21, 23, 24 and the memory 22 according to each operation mode, or is required according to each operation mode. A control circuit 25 for selecting the correct registers and memories is connected. In FIG. 1, the control circuit 25 is connected after each register and memory. However, the arrangement position of the control circuit 25 is not particularly limited.

  Corresponding to the above-described three operation modes (system mode, scan mode, and BIST mode), the system clock, scan clock, and BIST clock are supplied to the corresponding registers. These three clocks are selected by one multiplexer 11, and the clock lines that transmit these clocks to the corresponding registers are combined into one clock line 30.

  The multiplexer 11 includes a first input terminal P1 to which a BIST clock is applied in the BIST mode, a scan clock is applied in the scan mode, and a second input terminal P2 to which a system clock is applied. The multiplexer 11 is controlled by the output of the OR circuit 12 to which the BIST mode signal and the scan mode signal are input.

  The relationship between each operation mode and the register is the same as in FIG. That is, in the system mode, the logical values of the BIST mode signal and the scan mode signal are both set to “0”. The output of the OR circuit 12 is “0”. At this time, the multiplexer 11 selects the system clock applied to the second terminal P 2 and outputs it to the clock line 30. Then, the system clock is supplied to the system register 21 and the memory 22 via the clock line 30, and normal LSI operation is performed.

  Although the system clock can be supplied to other registers (scan bypass register 23 and BIST register 24), the control circuit 25 selects the system register 21 and the memory 22 necessary for system operation, and relates to the test circuit. Since the scan bypass register 23 and the BIST register 24 are not operating, there is no influence. It is also possible to select the system clock supplied to each register by the control circuit 25 and supply the clock only to the system register 21 and the memory 22.

  In the scan mode, the logical value of the BIST mode signal is set to “0”, and the logical value of the scan mode signal is set to “1”. The output of the OR circuit 12 is “1”. Then, the multiplexer 11 selects a clock applied to the first terminal P1. Therefore, at this time, if a scan clock is applied to the first terminal P1, the scan clock is supplied to the system register 21, the scan bypass register 23, and the BIST register 24 through the multiplexer 11, and each of the registers 21, 23, 24 is supplied. Is tested for proper operation.

  Although the scan clock can be supplied to the memory 22 as well, the control circuit 25 applies the scan clock only to the registers 21, 23 and 24 (registers necessary for the scan mode operation) except the memory 22 in the same manner as described above. Even if it is supplied or supplied to the memory 22, it is controlled so as not to affect the operation in the scan mode.

  In the BIST mode, the logical value of the BIST mode signal is set to “1”, and the logical value of the scan mode signal is set to “0”. The output of the OR circuit 12 is “1”. Then, the multiplexer 11 selects a clock applied to the first input terminal P1. Therefore, at this time, if the BIST clock is applied to the first input terminal P1, the BIST clock is supplied to the memory 22 and the BIST register 24 to test whether the memory 22 operates correctly. Similarly to the above, the BIST clock can be supplied to the system register 21 and the scan bypass register 23, but the control circuit 25 allows the BIST register 24 and the memory 22 (except for the system register 21 and the scan bypass register 23). Even if the BIST clock is supplied only to the registers and memories necessary for the BIST mode operation or supplied to the system register 21 and the scan bypass register 23, the resists 21 and 23 do not operate, and the BIST mode It is controlled so as not to affect the operation.

  For example, four delay buffers 40A, 40B, 40C, and 40D are inserted into the clock line 30 in order to adjust the delay times of the scan clock, the BIST clock, and the system clock. As a result, in each operation mode, the time for the clock to reach the registers 21, 23, 24 and the clock input terminal of the memory 22 is aligned, and the registers 21, 23, 24, and the memory 22 are synchronized with the clock. It becomes possible to operate.

  As described above, according to the clock control circuit of the present embodiment, the clock lines 30 are combined into one and the clock tree is optimized, so that the complicated adjustment work of the delay time of the clock line is not required. Further, since the number of delay buffers inserted in the clock line 30 is also reduced, the chip area is reduced and the power consumption is also reduced. In addition, since the delay time of the system clock and the BIST clock can be made equal, the memory test at the actual operation speed (system operation speed) can be performed in the BIST mode.

1 is a circuit diagram of a clock control circuit according to an embodiment of the present invention. It is a circuit diagram which shows the detail of the clock control circuit of a prior art example. It is a figure which shows the relationship between each operation mode and a required register.

Explanation of symbols

11 Multiplexer 12 OR circuit 21 System register
22 Memory 23 Scan bypass register
24 BIST register 25 Control circuit 30 Clock line 40A, 40B, 40C, 40D Delay buffer 51, 52 Multiplexer P1 First input terminal P2 Second input terminal 61, 62 Clock line

Claims (5)

A clock control circuit for supplying necessary clocks to a system register, a memory, a scan bypass register, and a BIST register,
One multiplexer that selects and outputs one of a scan clock, a BIST clock, and a system clock according to the BIST mode signal and the scan mode signal;
A single clock line connected to the output of the multiplexer and carrying a clock selected by the multiplexer;
A clock control circuit for supplying a clock selected from the clock line to the system register, memory, scan bypass register, and BIST register. 2. The multiplexer according to claim 1, further comprising a first input terminal to which a BIST clock is applied in the BIST mode, a scan clock is applied in the scan mode, and a second terminal to which a system clock is applied. The clock control circuit described. 3. The clock control circuit according to claim 1, wherein a delay buffer for adjusting a delay time of the scan clock, BIST clock, and system clock is inserted in the clock line. The system register, the memory, the scan bypass register, and the BIST register are connected to a control circuit for selecting a register and a memory necessary for the operation according to each operation mode of the system mode, the scan mode, and the BIST mode. The clock control circuit according to claim 1. The system register, the memory, the scan bypass register, and the BIST register select the clock output from the multiplexer, and the registers and memory necessary for the operation according to each operation mode of the system mode, the scan mode, and the BIST mode 4. The clock control circuit according to claim 1, further comprising a control circuit that supplies a clock only to the clock.

Images