CN111366842A - Chip mass production test system and method - Google Patents
Chip mass production test system and method Download PDFInfo
- Publication number
- CN111366842A CN111366842A CN202010158178.4A CN202010158178A CN111366842A CN 111366842 A CN111366842 A CN 111366842A CN 202010158178 A CN202010158178 A CN 202010158178A CN 111366842 A CN111366842 A CN 111366842A
- Authority
- CN
- China
- Prior art keywords
- mode
- selector
- memory
- test
- self
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318577—AC testing, e.g. current testing, burn-in
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The invention discloses a chip mass production test system, which comprises: the device comprises a first function register, a first selector, a memory, a second selector, a second function register, a bypass register and a controller; the output end of the first functional register is connected with the first input end of the first selector; the output end of the first selector is respectively connected with the input ends of the memory and the bypass register; the output end of the bypass register is connected with the second input end of the second selector; the output end of the memory is respectively connected with the first input end of the second functional register and the input end of the controller; the input end of the second register is connected with the output end of the second selector; the output end of the controller is connected with the first input end of the first selector, and the input end of the controller is connected with the output end of the memory. The chip mass production test system provided by the invention can enable the built-in self test and the low-speed scanning of the chip to run independently and parallelly, and is beneficial to improving the efficiency of chip mass production aging test.
Description
Technical Field
The invention relates to the technical field of chip testing, in particular to a system and a method for testing mass production of chips.
Background
Today, with the vigorous development of integrated circuits, the application of highly integrated large-scale integrated circuit chips is more and more extensive, and the quality and durability of the chips themselves are more and more emphasized by the users, the design manufacturers and the manufacturers. Therefore, Design For Test/DFT (Design For Test) is also becoming a subject of chip Design requiring careful consideration and implementation. The conventional chip usually includes a data Input/Output unit (Input, Output Cell/IO for short), a Standard Cell library (Standard Cell/STD for short), an embedded Memory (Memory Cell), and an Analog IP module (Analog IP). The DFT also has a corresponding test strategy scheme for different kinds of digital logic units. The most common DFT is SCAN Chain Test (SCAN Chain), which inserts controllable and observable SCAN chains into all digital sequential units, and then uses an Automatic Test Pattern Generation (ATPG) method to detect digital logic.
In the existing chip test system, the general DFT design sequence is MBIST, SCAN, and BSD. Firstly, inserting an MBIST logic, and increasing the read-write test logic of the memory in an MBIST mode; then, a scan chain is inserted, whether the existing logic is the MBIST logic or not is not needed to be distinguished, and the existing logic is generally included in a scan range to obtain better test coverage rate; and finally, inserting the part for testing IO by the BSD, wherein the BSD has read-write control on all IO, and the part is inserted finally and cannot be scanned by SCAN logic, so that the control logic of the IO cannot be damaged.
With the existing chip test system, the following problems exist:
the chip cannot be comprehensively tested in the single mode, so that the efficiency of chip testing cannot be improved.
Disclosure of Invention
The embodiment of the invention provides a chip mass production test system and a chip mass production test method, which can enable the built-in self test and the low-speed scanning of a chip to run independently in parallel, so that the chip can be tested in a whole plane, and the efficiency of the chip mass production test can be improved.
In order to achieve the above object, in one aspect, an embodiment of the present invention provides a system for testing mass production of chips, including: the device comprises a first function register, a first selector, a memory, a second selector, a second function register, a bypass register and a controller;
the output end of the first functional register is connected with the first input end of the first selector; the output end of the first selector is respectively connected with the memory and the input end of the bypass register;
the output end of the bypass register is connected with the second input end of the second selector;
the output end of the memory is respectively connected with the first input end of the second functional register and the input end of the controller; the input end of the second register is connected with the output end of the second selector;
the output end of the controller is connected with the first input end of the first selector, and the input end of the controller is connected with the output end of the memory.
Further, the first selector is used for selecting whether the working mode is a memory self-test mode; the second selector is used for selecting whether the working mode is the bypass mode or not.
In another aspect, another embodiment of the present invention provides a method for testing mass production of chips, which is suitable for the system for testing mass production of chips, and includes:
controlling the memory built-in self-test control logic to insert a scan chain into the first functional register, and logic of the scan chain not including the self-test control logic;
the first selector receives a memory self-test mode signal sent by the controller, and the first selector selects a signal input end as the first functional register or the self-test control logic according to the memory self-test mode signal;
when the signal input end is the first functional register, identifying a scan chain working mode in the first functional register through a clock system control logic; the working modes of the scan chain comprise a low-speed working mode and a high-speed working mode;
if the working mode is identified to be a low-speed scanning mode, controlling the self-testing mode of the memory to be 0 and controlling the bypass mode to be 1 through the clock control logic, and carrying out low-speed scanning on a chip to be tested;
if the working mode is identified to be the high-speed scanning mode, controlling the self-testing mode of the memory to be 0 and controlling the bypass mode to be 0 through the clock control logic, and scanning the chip to be tested at a high speed;
and when the signal input end is the self-test control logic, controlling the self-test mode of the memory to be 1 and controlling the bypass mode to be 0 through the clock control logic, and carrying out self-test on the chip to be tested.
Further, the method also comprises the steps of controlling a memory self-test mode to be 1 and controlling a bypass mode to be 1 through the clock control logic, and simultaneously carrying out low-speed scanning and self-test on the chip to be tested.
Further, the controlling the memory self-test mode to be 1 and the controlling the bypass mode to be 0 by the clock control logic specifically includes:
controlling the first selector to select the memory self-test mode to be 1 by the clock control logic, and controlling the second selector to select the bypass mode to be 0 by the clock control logic.
Further, the controlling the memory self-test mode to be 0 and the controlling the bypass mode to be 0 by the clock control logic specifically includes:
controlling the first selector to select the memory self-test mode to be 0 by the clock control logic, and controlling the second selector to select the bypass mode to be 0 by the clock control logic.
Further, the controlling the memory self-test mode to be 0 and the controlling the bypass mode to be 1 by the clock control logic specifically includes:
controlling the first selector to select the memory self-test mode to be 0 by the clock control logic, and controlling the second selector to select the bypass mode to be 1 by the clock control logic.
Further, the controlling the memory self-test mode to be 1 and the controlling the bypass mode to be 1 by the clock control logic specifically includes:
controlling the first selector to select the memory self-test mode to be 1 by the clock control logic, and controlling the second selector to select the bypass mode to be 1 by the clock control logic.
The embodiment of the invention provides a chip mass production test system and a chip mass production test method, wherein a self-test control logic is built in a memory and a bypass register is arranged, whether a working mode is a memory self-test mode or not is selected by a first selector and whether the working mode is a bypass mode or not is selected by a second selector when a chip is tested, so that the built-in self-test and low-speed scanning of the chip can run independently and parallelly, the chip can be tested on the whole, and the efficiency of the chip mass production test is improved.
Drawings
FIG. 1 is a schematic structural diagram of a system for testing mass production of chips according to the present invention;
fig. 2 is a schematic flow chart of a method for testing mass production of chips according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Please refer to fig. 1:
a first embodiment of the invention.
The embodiment of the invention provides a chip mass production test system, which comprises: a first function register 3, a first selector 4, a memory 2, a second selector 5, a second function register 6, a bypass register 7 and a controller 1;
the output end of the first functional register 3 is connected with the first input end of the first selector 4; the output end of the first selector 4 is respectively connected with the input ends of the memory 2 and the bypass register 7;
the output end of the bypass register 7 is connected with the second input end of the second selector 5;
the output end of the memory 2 is respectively connected with the first input end of the second functional register 6 and the input end of the controller 1; the input end of the second register is connected with the output end of the second selector 5;
an output of the controller 1 is connected to a first input of the first selector 4 and an input of the controller 1 is connected to an output of the memory 2.
In the embodiment of the invention, whether the working mode is the memory self-test mode or not is selected by the first selector 4, and whether the working mode is the bypass test mode or not is selected by the second selector 5. Preferably, the low-speed scan path of the embodiment of the present invention is the first functional register 3-the bypass register 7-the second functional register 6; the high-speed scanning path is a first functional register 3-a memory 2-a second functional register 6; the self-test path is controller 1-first selector 4-memory 2-second selector 5. It can be understood that, in the embodiment of the present invention, the self-test path is completely isolated from the low-speed scan path on the data channel, so that the built-in self-test and the low-speed scan of the memory 2 can run completely and independently, and a reliable basis is provided for the burn-in test of the chip, thereby facilitating the reliability and stability of the chip test.
As a specific implementation manner of the embodiment of the present invention, the first selector 4 is configured to select whether the operation mode is a memory self-test mode; the second selector 5 is used to select whether the operating mode is the bypass mode.
In the embodiment of the present invention, the first input terminal of the first selector 4 is 0, and the second input terminal is 1; the first input terminal of the second selector 5 is 0 and the second input terminal is 1; the embodiment of the invention controls the first selector 4 and the second selector 5 to select different input ends through the clock control logic, thereby realizing the selection of different working modes, further realizing the low-speed scanning, high-speed scanning, self-testing and aging testing of the chip to be tested, and being beneficial to improving the comprehensiveness and the efficiency of the quantitative testing of the chip.
The embodiment of the invention has the following beneficial effects:
in the embodiment of the invention, whether the working mode is the memory self-test mode is selected by the first selector 4, and whether the working mode is the bypass test mode is selected by the second selector 5, the low-speed scanning path is the first functional register 3-the bypass register 7-the second functional register 6, the self-test path is the controller 1-the first selector 4-the memory 2-the second selector 5, and the self-test path can be completely isolated from the low-speed scanning path on the data channel, so that the built-in self-test and the low-speed scanning of the memory 2 can be completely and independently operated in parallel, a reliable basis is provided for the aging test of a chip, and the reliability and the stability of the chip test are improved; the high-speed scanning path of the embodiment of the invention is the first functional register 3, the memory 2 and the second functional register 6, the input and the output of the memory 2 are not excluded during high-speed scanning, the input of the memory 2 and the output of the memory 2 can be controlled and observed according to the generation of a time sequence test vector, and the input end and the output end of the memory 2 still keep high-speed reading and writing in the mode, so that the purpose of testing the port at-speed of the memory 2 is achieved. The embodiment of the invention can effectively solve the requirement that a high-efficiency vector is needed to test the defect of stuck-at in the low-speed scanning mode, and also solves the requirement that the transition defect of the input/output port of the memory 2 needs to be tested in the high-speed scanning mode, thereby being beneficial to improving the efficiency of chip testing.
Please refer to fig. 2:
a second embodiment of the invention.
The embodiment of the invention provides a chip mass production test method, which is suitable for the chip mass production test system and comprises the following steps:
s1, controlling the memory 2 to build in self-test control logic, inserting scan chain into the first functional register 3, and the logic of the scan chain does not include the self-test control logic;
in the embodiment of the invention, by excluding the self-test control logic from the logic of the scan chain, the logic control of the memory 2 in the scan test can be excluded when the test method is used for low-speed scanning, so that the generation efficiency and the test coverage rate of the low-speed scan test vector can be effectively improved, and the efficiency of the chip quantitative test can be effectively improved.
S2, the first selector 4 receives the memory self-test mode signal sent by the controller 1, and the first selector 4 selects the signal input end as the first functional register 3 or the self-test control logic according to the memory self-test mode signal;
in the embodiment of the invention, the controller 1 sends a memory self-test mode signal to the first selector 4 according to the self-test control logic, and the first selector 4 can select a signal input end as the first functional register 3 or the self-test control logic according to the memory self-test mode signal; if the first functional register 3 is selected as the signal input end, scanning the chip to be tested through a scan chain in the first functional register 3; and if the self-test control logic is selected as the signal input end, carrying out self-test on the chip to be tested through the self-test control logic.
S3, when the signal input end is the first functional register 3, identifying the scan chain working mode in the first functional register 3 through the clock system control logic; the working modes of the scan chain comprise a low-speed working mode and a high-speed working mode;
in the embodiment of the present invention, the scan chain operating mode in the first functional register 3 is identified by a clock system control logic, and the clock control logic system includes two signals, OCC _ BYPASS and OCC _ RESET, where the OCC _ BYPASS signal is used to control whether the system outputs a clock using the clock control logic, and is also used to control the scan chain operating mode to be a high-speed scan mode or a low-speed scan mode; OCC _ RESET is responsible for resetting the clocked logic system. The embodiment of the invention can control the working modes of the scan chain including high-speed scanning and low-speed scanning through the clock system control logic, thereby scanning the chip to be tested.
S4, if the working mode is identified to be the low-speed scanning mode, controlling the self-testing mode of the memory to be 0 and controlling the bypass mode to be 1 through the clock control logic, and carrying out low-speed scanning on the chip to be tested;
in the embodiment of the invention, the low-speed scanning path is a first functional register 3, a bypass register 7 and a second functional register 6.
S5, if the working mode is identified to be the high-speed scanning mode, controlling the self-testing mode of the memory to be 0 and controlling the bypass mode to be 0 through the clock control logic, and scanning the chip to be tested at a high speed;
in the embodiment of the invention, the high-speed scanning path is the first functional register 3-the memory 2-the second functional register 6. In the embodiment of the invention, the input and the output of the memory 2 are not excluded during high-speed scanning, the input of the memory 2 and the output of the observation memory 2 can be controlled according to the generation of the time sequence test vector, and the input end and the output end of the memory 2 still keep high-speed reading and writing in the mode, thereby achieving the purpose of testing the port at-speed of the memory 2. The embodiment of the invention can effectively solve the requirement that a high-efficiency vector is needed to test the defect of stuck-at in the low-speed scanning mode, and also solves the requirement that the transition defect of the input/output port of the memory 2 needs to be tested in the high-speed scanning mode, thereby being beneficial to improving the efficiency of chip testing.
And S6, when the signal input end is a self-test control logic, controlling the self-test mode of the memory to be 1 and controlling the bypass mode to be 0 through the clock control logic, and carrying out self-test on the chip to be tested.
In an embodiment of the present invention, the self-test path is controller 1-first selector 4-memory 2-second selector 5. It can be understood that, in the embodiment of the present invention, the self-test path is completely isolated from the low-speed scan path on the data channel, so that the built-in self-test and the low-speed scan of the memory 2 can run completely and independently, and a reliable basis is provided for the burn-in test of the chip, thereby facilitating the reliability and stability of the chip test.
As a specific implementation manner of the embodiment of the present invention, the test method further includes controlling the memory self-test mode to be 1 and the bypass mode to be 1 by the clock control logic, and performing low-speed scanning and self-test on the chip to be tested at the same time.
In the embodiment of the invention, the built-in self-test vector and the test vector of the low-speed scanning mode are respectively input into the chip from different chip pins, and the built-in self-test path and the low-speed scanning chain path of the memory 2 work simultaneously, so that the aim of running various logic units in the whole chip in parallel can be fulfilled. At this time, except some analog IP units are locked in a stable state, other input/output units (IO), Standard logic units (Standard cells) and Memory 2 units (Memory) are all in a running state, so that the aging speed and the aging effect of the chip to be tested can be effectively improved, and the efficiency of quantitative testing of the chip is improved.
As a specific implementation manner of the embodiment of the present invention, the self-test mode of the memory is controlled to be 1 and the bypass mode is controlled to be 0 by the clock control logic, which specifically includes:
the first selector 4 is controlled by the clock control logic to select the memory self-test mode to be 1 and the second selector 5 is controlled by the clock control logic to select the bypass mode to be 0.
As a specific implementation manner of the embodiment of the present invention, the self-test mode of the memory is controlled to be 0 by the clock control logic, and the bypass mode is controlled to be 0, specifically:
the first selector 4 is controlled by the clock control logic to select the memory self-test mode to 0 and the second selector 5 is controlled by the clock control logic to select the bypass mode to 0.
As a specific implementation manner of the embodiment of the present invention, the self-test mode of the memory is controlled to be 0 and the bypass mode is controlled to be 1 by the clock control logic, which specifically includes:
the first selector is controlled by the clock control logic to select the memory self-test mode to be 0, and the second selector is controlled by the clock control logic to select the bypass mode to be 1.
As a specific implementation manner of the embodiment of the present invention, the self-test mode of the memory is controlled to be 1 by the clock control logic, and the bypass mode is controlled to be 1, specifically:
the first selector 4 is controlled by the clock control logic to select the memory self-test mode to be 1 and the second selector 5 is controlled by the clock control logic to select the bypass mode to be 1.
The embodiment of the invention has the following beneficial effects:
according to the embodiment of the invention, the logic of the scan chain is excluded from the self-test control logic, so that the logic control of the memory 2 in the scan test can be excluded when the test method is used for low-speed scanning, the generation efficiency and the test coverage rate of the low-speed scan test vector can be effectively improved, and the efficiency of the chip quantitative test can be effectively improved; the embodiment of the invention identifies the scan chain working mode in the first functional register 3 through the clock system control logic, can scan the chip to be tested, and improves the test comprehensiveness of the chip; according to the embodiment of the invention, the memory 2 is used for self-building the controller 1 and the bypass register 7, the first selector 4 is used for selecting whether the working mode is the memory self-testing mode or not, and the second selector 5 is used for selecting whether the working mode is the bypass testing mode or not, so that the self-testing path can be completely isolated from the low-speed scanning path on the data channel, the built-in self-testing and the low-speed scanning of the memory 2 can be completely and independently operated in parallel, a reliable basis is provided for the aging test of a chip, and the reliability and the stability of the chip test can be improved; the embodiment of the invention does not exclude the input and the output of the memory 2 during high-speed scanning, can control the input of the memory 2 and observe the output of the memory 2 according to the generation of the time sequence test vector, and the input end and the output end of the memory 2 still keep high-speed reading and writing in the mode, thereby achieving the purpose of testing the port at-speed of the memory 2. The embodiment of the invention can effectively solve the requirement that a high-efficiency vector is needed to test the defect of stuck-at in the low-speed scanning mode, and also solves the requirement that the transition defect of the input/output port of the memory 2 needs to be tested in the high-speed scanning mode, thereby being beneficial to improving the efficiency of chip testing.
The foregoing is a preferred embodiment of the present invention, and it should be noted that it would be apparent to those skilled in the art that various modifications and enhancements can be made without departing from the principles of the invention, and such modifications and enhancements are also considered to be within the scope of the invention.
Claims (8)
1. A chip volume production test system, comprising: the device comprises a first function register, a first selector, a memory, a second selector, a second function register, a bypass register and a controller;
the output end of the first functional register is connected with the first input end of the first selector; the output end of the first selector is respectively connected with the memory and the input end of the bypass register;
the output end of the bypass register is connected with the second input end of the second selector;
the output end of the memory is respectively connected with the first input end of the second functional register and the input end of the controller; the input end of the second register is connected with the output end of the second selector;
the output end of the controller is connected with the first input end of the first selector, and the input end of the controller is connected with the output end of the memory.
2. The system for mass production testing of chips of claim 1, wherein the first selector is configured to select whether the operation mode is a memory self-test mode; the second selector is used for selecting whether the working mode is the bypass mode or not.
3. A mass production testing method for chips, which is applied to the mass production testing system for chips according to any one of claims 1 to 2, comprising:
controlling the memory built-in self-test control logic to insert a scan chain into the first functional register, and logic of the scan chain not including the self-test control logic;
the first selector receives a memory self-test mode signal sent by the controller, and the first selector selects a signal input end as the first functional register or the self-test control logic according to the memory self-test mode signal;
when the signal input end is the first functional register, identifying a scan chain working mode in the first functional register through a clock system control logic; the working modes of the scan chain comprise a low-speed working mode and a high-speed working mode;
if the working mode is identified to be a low-speed scanning mode, controlling the self-testing mode of the memory to be 0 and controlling the bypass mode to be 1 through the clock control logic, and carrying out low-speed scanning on a chip to be tested;
if the working mode is identified to be the high-speed scanning mode, controlling the self-testing mode of the memory to be 0 and controlling the bypass mode to be 0 through the clock control logic, and scanning the chip to be tested at a high speed;
and when the signal input end is the self-test control logic, controlling the self-test mode of the memory to be 1 and controlling the bypass mode to be 0 through the clock control logic, and carrying out self-test on the chip to be tested.
4. The method for testing mass production of chips as claimed in claim 3, further comprising controlling a memory self-test mode to be 1 and a bypass mode to be 1 by the clock control logic while performing low-speed scan and self-test on the chips to be tested.
5. The method for testing mass production of chips according to claim 3, wherein the memory self-test mode is controlled to be 1 and the bypass mode is controlled to be 0 by the clock control logic, specifically:
controlling the first selector to select the memory self-test mode to be 1 by the clock control logic, and controlling the second selector to select the bypass mode to be 0 by the clock control logic.
6. The method for testing mass production of chips according to claim 3, wherein the clock control logic controls the memory self-test mode to be 0 and controls the bypass mode to be 0, specifically:
controlling the first selector to select the memory self-test mode to be 0 by the clock control logic, and controlling the second selector to select the bypass mode to be 0 by the clock control logic.
7. The method for testing mass production of chips as claimed in claim 3, wherein the clock control logic controls the memory self-test mode to be 0 and the bypass mode to be 1, specifically:
controlling the first selector to select the memory self-test mode to be 0 by the clock control logic, and controlling the second selector to select the bypass mode to be 1 by the clock control logic.
8. The method for testing mass production of chips according to claim 4, wherein the memory self-test mode is controlled to be 1 and the bypass mode is controlled to be 1 by the clock control logic, specifically:
controlling the first selector to select the memory self-test mode to be 1 by the clock control logic, and controlling the second selector to select the bypass mode to be 1 by the clock control logic.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010158178.4A CN111366842B (en) | 2020-03-09 | 2020-03-09 | Chip mass production test method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010158178.4A CN111366842B (en) | 2020-03-09 | 2020-03-09 | Chip mass production test method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111366842A true CN111366842A (en) | 2020-07-03 |
| CN111366842B CN111366842B (en) | 2022-04-22 |
Family
ID=71208686
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010158178.4A Active CN111366842B (en) | 2020-03-09 | 2020-03-09 | Chip mass production test method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111366842B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112115664A (en) * | 2020-11-18 | 2020-12-22 | 北京滕华软件有限公司 | Multi-mode multi-clock domain chip integrated control system |
| CN112345925A (en) * | 2020-10-30 | 2021-02-09 | 上海兆芯集成电路有限公司 | Scan chain control circuit |
| CN113740710A (en) * | 2021-09-02 | 2021-12-03 | 展讯通信（上海）有限公司 | Output test circuit and chip |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20040036542A (en) * | 2002-10-25 | 2004-04-30 | 인터내셔널 비지네스 머신즈 코포레이션 | Testing logic and embedded memory in parallel |
| CN1534687A (en) * | 2002-12-16 | 2004-10-06 | 株式会社瑞萨科技 | Semiconductor integrated circuit device |
| JP2006331190A (en) * | 2005-05-27 | 2006-12-07 | Sanyo Electric Co Ltd | Clock control circuit |
| CN105572573A (en) * | 2014-10-30 | 2016-05-11 | 国际商业机器公司 | Scan chain for memory time sequence testing, scan chain construction method and corresponding device |
| CN108107867A (en) * | 2017-11-24 | 2018-06-01 | 中国人民解放军国防科技大学 | Method and device for realizing memory self-test controller of multiplexing system logic |
-
2020
- 2020-03-09 CN CN202010158178.4A patent/CN111366842B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20040036542A (en) * | 2002-10-25 | 2004-04-30 | 인터내셔널 비지네스 머신즈 코포레이션 | Testing logic and embedded memory in parallel |
| CN1534687A (en) * | 2002-12-16 | 2004-10-06 | 株式会社瑞萨科技 | Semiconductor integrated circuit device |
| JP2006331190A (en) * | 2005-05-27 | 2006-12-07 | Sanyo Electric Co Ltd | Clock control circuit |
| CN105572573A (en) * | 2014-10-30 | 2016-05-11 | 国际商业机器公司 | Scan chain for memory time sequence testing, scan chain construction method and corresponding device |
| CN108107867A (en) * | 2017-11-24 | 2018-06-01 | 中国人民解放军国防科技大学 | Method and device for realizing memory self-test controller of multiplexing system logic |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112345925A (en) * | 2020-10-30 | 2021-02-09 | 上海兆芯集成电路有限公司 | Scan chain control circuit |
| CN112345925B (en) * | 2020-10-30 | 2024-05-24 | 格兰菲智能科技有限公司 | Scan chain control circuit |
| CN112115664A (en) * | 2020-11-18 | 2020-12-22 | 北京滕华软件有限公司 | Multi-mode multi-clock domain chip integrated control system |
| CN113740710A (en) * | 2021-09-02 | 2021-12-03 | 展讯通信（上海）有限公司 | Output test circuit and chip |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111366842B (en) | 2022-04-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111366842B (en) | Chip mass production test method | |
| US6353905B1 (en) | Semiconductor integrated circuit and recording medium | |
| US6668347B1 (en) | Built-in self-testing for embedded memory | |
| US7269766B2 (en) | Method and apparatus for memory self testing | |
| US20040128596A1 (en) | Method and apparatus for testing embedded cores | |
| US7437645B2 (en) | Test circuit for semiconductor device | |
| US6826101B2 (en) | Semiconductor device and method for testing the same | |
| US7251757B2 (en) | Memory testing | |
| CN101515479B (en) | Method for increasing test coverage of scan chain and device thereof | |
| US20050204239A1 (en) | Method for testing semiconductor integrated circuit | |
| US7539912B2 (en) | Method and apparatus for testing a fully buffered memory module | |
| CN112562770B (en) | Semiconductor device with test circuit | |
| KR20020030537A (en) | Semiconductor device comprising built-in redundancy analysis circuit for testing and analyzing a plurality of memories simultaneously and analyzing method thereof | |
| US9805826B2 (en) | Method and apparatus for testing integrated circuit | |
| KR100295546B1 (en) | Semiconductor device testing apparatus | |
| JP2004510989A (en) | Test access port (TAP) controller system and method for debugging internal intermediate scan test failures | |
| EP0849678A2 (en) | A system and method for testing electronic devices | |
| US20060041807A1 (en) | Integrated circuit | |
| US6990619B1 (en) | System and method for automatically retargeting test vectors between different tester types | |
| US20140365838A1 (en) | Integrated circuit comprising test circuitry for testing fan-out paths of a test control primary input | |
| US7134058B2 (en) | Memory circuit scan arrangement | |
| US20060053356A1 (en) | Integrated circuit | |
| CN111292795B (en) | Built-in self-test system for memory | |
| US20080316846A1 (en) | Semiconductor memory device capable of storing data of various patterns and method of electrically testing the semiconductor memory device | |
| US20140281764A1 (en) | Data path memory test |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |