CN113740710A - Output test circuit and chip - Google Patents
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Abstract
The embodiment of the application provides an output test circuit and chip, and output test circuit includes: the test circuit comprises an input selector, a first register and a mode selector, wherein the first register is respectively connected with the input selector and the mode selector, and the input selector is also used for being connected with a pin to be tested. In the test circuit, a test signal can be input to the pin to be tested, a sampling signal of the pin to be tested can be sampled, and whether short circuit occurs between the pin to be tested and an adjacent pin can be determined according to the test signal and the sampling signal. Need not with the help of other test circuit, the test procedure is simple and convenient, and then has improved test circuit's efficiency of software testing.
Description
Technical Field
The application relates to the technical field of circuit testing, in particular to an output testing circuit and a chip.
Background
Various types of pins, e.g., input pins, output pins, are included in the chip. When the fault of the chip needs to be tested, the pin of the chip needs to be tested.
In the related art, a Boundary scan test circuit is usually used to test pins of a chip, a Boundary Scan Cell (BSC) may be added to each pin, a test signal is input to each pin to be tested through the Boundary scan cell, a sampling signal of the pin to be tested is output through the Boundary scan cell corresponding to the pin connected to the pin to be tested, and a test result is determined by comparing the test signal with the sampling signal.
However, in the related art, the sampling signal needs to be output by using the pins of other test circuits, and the test process is cumbersome, resulting in low efficiency of testing the chip.
Disclosure of Invention
The application relates to an output test circuit and a chip, wherein the output test circuit can test the fault of a single chip, and the test efficiency of the chip is improved.
In a first aspect, an embodiment of the present application provides an output test circuit, including: an input selector, a first register and a mode selector, the first register is connected with the input selector and the mode selector respectively, the input selector is also used for being connected with a pin to be tested, wherein,
the input selector is used for receiving a test signal and outputting the test signal to the first register when the output test circuit is in a first state;
the first register is used for outputting the test signal to the test processing unit and outputting the test signal to the pin to be tested through the mode selector when the output test circuit is in a second state;
the input selector is further configured to receive a sampling signal of the pin to be tested and output the sampling signal to the first register when the output test circuit is in a third state;
the first register is further configured to output the sampling signal to a test processing unit.
In one possible embodiment, the input selector comprises two signal inputs, a signal control and an output, wherein,
the first input end of the input selector is used for being connected with the pin to be tested;
a second input of the input selector is configured to receive the test signal;
the signal control end of the input selector is used for receiving a first control signal, and the first control signal is used for controlling the gating of the first input end of the input selector or the gating of the second input end of the input selector;
the output end of the input selector is used for being connected with the input end of the first register.
In a possible implementation, when the output test circuit is in the first state, the first control signal is used for controlling the gating of the second input end of the input selector;
when the output test circuit is in the third state, the first control signal is used for controlling the gating of the first input end of the input selector.
In a possible embodiment, the output test circuit further comprises a second register, an input of the second register being connected to an output of the first register, an output of the second register being connected to an input of the mode selector, wherein,
the second register is used for receiving the test signal from the first register when the test circuit is in the second state, and sending the test signal to the pin to be tested through the mode selector.
In one possible embodiment, the mode selector comprises two input terminals, a signal control terminal and an output terminal, wherein,
the first input end of the mode selector is used for being connected with a core processing unit on a chip where the output test circuit is located;
a second input end of the mode selector is connected with an output end of the second register;
the signal control end of the mode selector is used for receiving a second control signal, and the second control signal is used for controlling the gating of the first input end of the second mode selector or the gating of the second input end of the second mode selector;
the output end of the mode selector is used for being connected with the pin to be tested.
In a possible implementation manner, when the chip where the output test circuit is located is in a functional mode, the second control signal is used for controlling the gating of the first input end of the mode selector;
and when the chip where the output test circuit is located is in a test mode, the second control signal is used for controlling the gating of the second input end of the mode selector.
In a possible embodiment, the output test circuit further includes a switch unit, wherein the switch unit is connected to the first input terminal of the input selector, and the switch unit is further configured to be connected to the pin to be tested.
In one possible embodiment, the switching unit comprises two input terminals, a signal control terminal and an output terminal, wherein,
the first input end of the switch unit is used for being connected with a core processing unit on a chip where the output test circuit is located;
the second input end of the switch unit is used for being connected with the pin to be tested;
the signal control end of the switch unit is used for receiving a test control signal, and the test control signal is used for controlling the gating of the first input end of the switch unit or the gating of the second input end of the switch unit;
and the output end of the switch unit is connected with the first input end of the input selector.
In a possible implementation manner, when the output test circuit is in the third state, the test control signal is used for controlling the second input terminal of the switch unit to be gated.
In a second aspect, the present application further provides a chip, the chip includes a core processing unit, a plurality of first pins, a plurality of second pins, a test circuit corresponding to each first pin, and a test circuit corresponding to each second pin, the first pins are connected to an input terminal of the core processing unit, the second pins are connected to an output terminal of the core processing unit, wherein,
the test circuit corresponding to the second pin is the output test circuit of any one of the first aspect;
the core processing unit is respectively connected with each first pin and each second pin, and each first pin and each second pin are also connected with a corresponding test circuit;
and the test circuits corresponding to the adjacent pins in the plurality of first pins and the plurality of second pins are connected.
In a possible implementation manner, the chip further includes a test processing unit, the test processing unit is connected to each test circuit, and the test processing unit is configured to determine a test result of a pin corresponding to each test circuit according to a test signal and a sampling signal output by each test circuit.
In a possible implementation manner, the test circuit corresponding to the first pin includes: an input selector, a first register, a mode selector and a feedback circuit, the first register being connected with the input selector, the feedback circuit and the mode selector, respectively, the feedback circuit, the input selector and the mode selector further being configured to be connected with a first pin, wherein,
the input selector is used for receiving a test signal and outputting the test signal to the first register when the test circuit is in a first state;
the first register is used for outputting the test signal to the test processing unit and outputting the test signal to the first pin through the feedback circuit when the test circuit is in a second state;
the input selector is further configured to receive a sampling signal of the first pin and output the sampling signal to the first register when the test circuit is in a third state;
the first register is further configured to output the sampling signal to the test processing unit.
In one possible embodiment, the input selector comprises two signal inputs, a signal control and an output, wherein,
the first input end of the input selector is used for being connected with the first pin;
a second input of the input selector is configured to receive the test signal;
the signal control end of the input selector is used for receiving a first control signal, and the first control signal is used for controlling the gating of the first input end of the input selector or the gating of the second input end of the input selector;
the output end of the input selector is used for being connected with the input end of the first register.
In a possible implementation manner, when the test circuit corresponding to the first pin is in the first state, the first control signal is used for controlling the gating of the second input end of the input selector;
and when the test circuit corresponding to the first pin is in the third state, the first control signal is used for controlling the gating of the first input end of the input selector. In a possible implementation manner, in the test circuit corresponding to the first pin, the feedback circuit includes a second register and a switch unit, the second register is respectively connected with the first register and the switch unit, the switch unit is further connected with the first pin, wherein,
the second register is configured to receive the test signal from the first register and send the test signal to the first pin through the switch unit when the input test circuit is in the second state.
In a possible implementation manner, in the test circuit corresponding to the first pin, the switch unit is configured to receive a test control signal, wherein,
and when the test circuit corresponding to the first pin is in the second state, the test control signal is used for controlling the switch unit to be closed.
In a possible implementation manner, in the test circuit corresponding to the first pin, the switch unit is a tri-state buffer.
In one possible embodiment, in the test circuit corresponding to the first pin, the mode selector includes two input terminals, a signal control terminal and an output terminal, wherein,
a first input end of the mode selector is used for being connected with the first pin;
a second input end of the mode selector is connected with an output end of the second register;
the signal control end of the mode selector is used for receiving a second control signal, and the second control signal is used for controlling the gating of the first input end of the first mode selector or the gating of the second input end of the first mode selector;
and the output end of the first mode selector is used for being connected with a core processing unit on a chip where the input test circuit is positioned.
In a possible implementation manner, when the chip where the test circuit corresponding to the first pin is located is in a functional mode, the second control signal is used for controlling the first input terminal of the first mode selector to be gated;
and when the chip where the test circuit corresponding to the first pin is located is in a test mode, the second control signal is used for controlling the gating of the second input end of the first mode selector.
An output test circuit and chip that this application embodiment provided, this output test circuit includes: the test circuit comprises an input selector, a first register and a mode selector, wherein the first register is respectively connected with the input selector and the mode selector, and the input selector is also used for being connected with a pin to be tested. The output test circuit can output the test signal and the sampling signal without outputting the sampling signal by other test circuits, the test process is simple and convenient, and the test efficiency of the test circuit is improved.
Drawings
Fig. 1 is a schematic view of an application scenario provided in an embodiment of the present application;
FIG. 2 is a schematic diagram of an internal circuit of a boundary stripe scan cell in the related art;
FIG. 3 is a diagram illustrating a short test of adjacent second pins in the related art;
fig. 4 is a first schematic structural diagram of a test circuit according to an embodiment of the present disclosure;
fig. 5 is a second schematic structural diagram of a test circuit according to an embodiment of the present disclosure;
fig. 6 is a schematic structural diagram of a test circuit according to an embodiment of the present disclosure;
fig. 7 is a schematic structural diagram of a test circuit according to an embodiment of the present disclosure;
FIG. 8 is a schematic diagram illustrating the testing of a single chip for adjacent pin failure;
fig. 9 is a schematic diagram of the positions of the BGA chip pins.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
For ease of understanding, an application scenario to which the embodiment of the present application is applied is described below with reference to fig. 1.
Fig. 1 is a schematic view of an application scenario provided in an embodiment of the present application. Referring to fig. 1, the chip may include a plurality of pins, a plurality of BSCs, a core processing unit, a bypass register, an instruction register, and a Test Access Port (TAP) controller, wherein the plurality of BSCs may constitute a boundary scan register.
The pins can be divided into a first pin and a second pin according to the positions of the pins. The first pin refers to a pin for receiving a signal, for example, the pins located on the left side and the upper side of the chip in fig. 1 are the first pins. The second pin is a pin for outputting a signal, for example, the pin located on the right side of the chip in fig. 1 is the second pin.
Each pin corresponds to a BSC, and the BSCs can be divided into an input BSC and an output BSC according to the difference between the BSC and the pin positions. The input BSC refers to a BSC receiving a signal from the first pin, and for example, BSCs located on the left side and the upper side of the chip in fig. 1 are input BSCs. The output BSC is the BSC that directs the output signal to the second pin, e.g., the BSC on the right side of the chip in fig. 1 is the output BSC.
A chip supporting boundary scan testing needs to have a Joint Test Action Group (JTAG) interface. The standard JTAG interface includes 4 pins, and names and functions of the 4 pins are shown in table 1:
TABLE 1
The core processing unit may be a core logic module of the chip.
The bypass register provides a shortest path from the TDI pin to the TDO pin. The bypass register is used for shortening the scanning path and bypassing the data register which does not need to be tested so as to reduce unnecessary scanning time.
The instruction register is used for storing a test instruction input from a TDI pin, sending various operation codes to data registers such as a boundary scan register and a bypass register after the instruction is decoded, and determining the working mode of boundary scan test.
Data may be input to the boundary scan register through the TDI pin and data in the boundary scan register may be output through the TDO pin. Under the action of TCK, the test signal input from TDI pin can move and scan in boundary scan unit in boundary scan register. The boundary scan register may be used by a tester to test the connections of external pins or to capture internal data while the chip is running.
The TAP controller may be controlled by the TMS signal, the TAP controller having a state machine of 16 states (e.g., update data states, sample data states, etc.). And on the rising edge of the TCK, the TAP controller controls the boundary scan test operation in the chip by using the TMS pin and controls the boundary scan test circuit to perform state conversion at the same time.
The chip has a functional mode and a test mode. When the chip is in a functional mode, the BSC connects the input pin and the output pin with the core processing unit. When the chip is in a test mode, the BSC accesses the TDI pin to input a test signal under different states, and the test signal is output from the TDO pin through a scanning test path. Whether the chip has a fault can be detected by comparing the input test signal with the output test signal.
For ease of understanding, the internal circuit of the boundary scan cell will be described below with reference to fig. 2.
Fig. 2 is a schematic diagram of an internal circuit of an output boundary stripe scan cell in the related art. Referring to fig. 2, an input selector 201, a first register 202, a second register 203, and a mode selector 204 are included.
When the chip is in functional mode, the mode selector 204 gates "0" and the signal from the core processing unit enters from the PI and is output from the PO to the second pin directly through the mode selector 204. The signal output from the PO may be input as a PI to a boundary scan cell on another chip.
When the chip is in a test mode, the mode selector 204 gates '1', and the conducting circuit paths of the BSC internal circuits are different in different test states:
when the BSC internal circuit is in a test data introduction state, the input selector 201 gates "1", a test signal enters from the SI, passes through the input selector 201, is stored in the first register 202, and is output from the SO, and the test signal output from the SO passes through the scan test path and is output from the TDO pin.
When the BSC internal circuit is in the update data state, the test signal stored in the first register 202 is shifted out to the second register 203, and is output from the second register 203 to the pin through the mode selector 204.
When the BSC internal circuit is in a sampling data state, the input selector 201 gates "0", a signal of the pin is captured as a sampling signal, the sampling signal passes through the input selector 201, is stored in the first register 202, is output from the SO, passes through the scan test path, and is output from the TDO pin.
In the related art, if a fault such as a short circuit exists in an adjacent pin, a sampling signal needs to be output by using a boundary scan test path of another chip. The manner of testing the adjacent second pin for short circuit in the related art is described below with reference to fig. 3.
Fig. 3 is a schematic diagram illustrating a short test of adjacent second pins in the related art. Referring to fig. 3, the chip 301 and the chip 302 are included. The operation of testing whether pin a and pin B are shorted is as follows:
in the test data import state, a high level "1" is configured to the first register of the BSC1, and "1" is output from SO to the SI of the BSC3, and the SI of the BSC3 outputs "1" from the TDO pin of the chip 302 through the scan test path. Meanwhile, the first register of BSC2 is configured with a low level "0", and "0" is output from SO to the SI of BSC4, and the SI of BSC4 is output from TDO pin of chip 2 "0" through scan test path.
In updating the data state, the "1" stored in the first register in BSC1 is shifted out to the second register and output from the second register, through the mode selector, to pin C. At the same time, the "0" of the first register stored in BSC2 is shifted out to the second register and output from the second register, through the mode selector, to pin D.
In the sampling data state, the level value of the pin C (or pin D) is captured, stored in the first register through the input selector in the BSC3 (or BSC4), and output from the SO of the BSC3 (or BSC4), and output from the TDO pin of the chip 302 through the scan test path.
If the level values of the pin C and the pin D output from the TDO pin of the chip 302 are "0" or "1" at the same time, it indicates that the pin a and the pin B are short-circuited.
The above-mentioned method for testing the short circuit of the adjacent pins has at least the following technical problems:
1. the scan test path of the chip 301 cannot test the short circuit of the adjacent pins in the chip 301, and the test needs to be performed by using scan test circuits of other chips or other test equipment, so that the test steps are complicated, and the test efficiency is low.
2. If one of the shorted adjacent pins is an input pin and the other is an output pin, the detection may not be possible, resulting in low detection accuracy.
3. If the pin C and the pin D are not on the same chip, although the voltage of the pin C and the pin D due to the short circuit is the same, the output level value of the pin C may be "1" and the output level value of the pin D may be "0", which results in low test accuracy.
To the various technical problems that exist, this application provides an output test circuit, can make output test circuit output test signal and sampling signal through increase short circuit test path in output test circuit, need not to export sampling signal with the help of other test circuit, and the test procedure is simple and convenient, and then has improved test circuit's efficiency of software testing.
The technical means shown in the present application will be described in detail below with reference to specific examples. It should be noted that the following embodiments may exist independently or may be combined with each other, and details of the same or similar concepts or processes are not repeated in different embodiments.
Fig. 4 is a first schematic structural diagram of an output test circuit according to an embodiment of the present disclosure. Referring to fig. 4, the output test circuit 40 includes an input selector 401, a first register 402 and a mode selector 403, the first register 402 is connected to the input selector 401 and the mode selector 403, respectively, and the input selector 401 is further used for being connected to a pin to be tested.
The output test circuit shown in the embodiment of the present application may be an internal circuit of the output BSC.
Alternatively, the input selector 401 may receive a signal and output the signal to the first register 402. For example, when the output test circuit is in the first state, the input selector 401 receives a test signal and outputs the test signal to the first register 402; or, when the output test circuit is in the third state, the input selector 401 receives the sampling signal of the pin to be tested, and outputs the sampling signal to the first register 402; alternatively, the input selector 401 may also receive signals from a core processing unit in the chip when the chip on which the output test circuit is located is in the internal logic test mode.
Specifically, the input selector 401 may include two signal input terminals, a signal control terminal, and an output terminal. A first input end of the input selector 401 is configured to receive a sampling signal of a pin to be tested; the second input end is used for receiving a test signal; the signal control end is used for receiving a first control signal; the output is for connection to an input of the first register 402.
The input selector 401 may be a multiplexer, such as a one-out-of-two selector, a one-out-of-three selector, or the like.
The first control signal is used to control the gating of the first input terminal or the gating of the second input terminal of the input selector 401. For example, when the output test circuit is in the first state, the first control signal is used to control the second input terminal of the input selector 401 to be gated; when the output test circuit is in the third state, the first control signal is used to control the gating of the first input terminal of the input selector 401.
The first register 402 may be a shift register, and input and output of signals may be determined by a clock control signal.
The first register 402 may be used to output signals. For example, when the output test circuit is in the first state, the first register 402 is used to output a test signal to the test processing unit; or, when the output test circuit is in the second state, the first register 402 outputs a test signal to the pin to be tested through the mode selector 403; alternatively, the first register 402 is used to sample signals to the test processing unit when the output test circuit is in the third state.
The first state may be a test data import state, the second state may be an update data state, and the third state may be a sample data state.
The test processing unit may be located inside the chip or outside the chip.
Next, the operation of the output test circuit will be described.
When the chip is in the functional mode, the mode selector 403 controls the signal from the core processing unit where the chip is located to be directly transmitted from the PI to the PO, and output from the PO to the pin to be tested.
When the chip is in the test mode, the PI is disconnected from the core processing unit where the chip is located, the mode selector 403 controls the scan test path to be conducted, and the conducted circuit paths of the output test circuit are different and specific in different test states:
when the test circuit is in the first state (test data importing state), the input selector 401 receives the test signal and outputs the test signal to the first register 402, and the first register 402 stores the test signal and outputs the test signal to the test processing unit (not shown).
When the test circuit is in the second state (update data state), the first register 402 outputs a test signal to the pin to be tested through the mode selector 403.
When the test circuit is in the third state (sampling data state), the input selector 401 receives a sampling signal from the pin to be tested and outputs the sampling signal to the first register 402, so that the first register 402 outputs the sampling signal to the test processing unit.
In the test process, a plurality of test circuits are usually tested at the same time, and the test signals (low level "0" or high level "1") inputted to two adjacent test circuits are different. For example, if the pin 1 and the pin 2 are adjacent to each other, the test signals output to the pin 1 and the pin 2 are different. If there is a short between pin 1 and pin 2, the sampled signals at pin 1 and pin 2 are the same. If there is no short circuit between pin 1 and pin 2, the sampled signals at pin 1 and pin 2 are different. Correspondingly, if the test processing unit determines that the test signals corresponding to the pin 1 and the pin 2 are different and the sampling signals corresponding to the pin 1 and the pin 2 are the same, it may be determined that the pin 1 and the pin 2 are short-circuited.
In the test circuit, a test signal can be input to the pin to be tested, a sampling signal of the pin to be tested can be sampled, and whether short circuit occurs between the pin to be tested and an adjacent pin can be determined according to the test signal and the sampling signal. Need not with the help of other test circuit, the test procedure is simple and convenient, and then has improved test circuit's efficiency of software testing.
In the embodiment of fig. 4, the output test circuit will be further described below with reference to the embodiment shown in fig. 5.
Fig. 5 is a second schematic structural diagram of an output test circuit according to an embodiment of the present disclosure. Referring to fig. 5, based on fig. 4, the output test circuit 40 further includes a second register 404, an input terminal of the second register 404 is connected to the output terminal of the first register 402, and an output terminal of the second register 404 is connected to the input terminal of the mode selector.
The second register 404 is used for receiving the test signal from the first register 402 and sending the test signal to the pin to be tested through the mode selector 403 when the output test circuit 40 is in the second state.
The mode selector 403 includes two input terminals, a signal control terminal and an output terminal, wherein a first input terminal is used for connecting with a core processing unit on a chip where the output test circuit 40 is located; a second input terminal is connected to the output terminal of the second register 404; the signal control terminal is configured to receive a second control signal, where the second control signal is used to control the gating of the first input terminal of the mode selector 403 or the gating of the second input terminal of the mode selector; the output of the mode selector 403 is used to connect with the pin to be tested.
Next, the operation of the test circuit will be described.
When the chip is in the functional mode, the second control signal controls the first input terminal of the mode selector 403 to be gated, and the signal from the on-chip core processing unit is directly transmitted from the PI to the PO and is output from the PO to the pin to be tested.
When the chip is in the test mode, the second control signal controls the second input terminal of the mode selector 403 to be gated, and the conducted circuit paths of the output test circuit are different in different test states, specifically:
in the first state (test data importing state), the working process of the circuit in the first state is the same as that of the test circuit in the embodiment shown in fig. 4, and is not described herein again.
In the second state (update data state), the first register 402 outputs a test signal to the pin to be tested through the second register 404 and the mode selector 403.
In the third state (sampling data state), the working process of the circuit in the third state is the same as that of the test circuit in the embodiment shown in fig. 4, and is not described herein again.
In the output test circuit, a test signal can be input to the pin to be tested, a sampling signal of the pin to be tested can be sampled, and whether short circuit occurs between the pin to be tested and an adjacent pin can be determined according to the test signal and the sampling signal. Need not with the help of other test circuit, the test procedure is simple and convenient, and then has improved test circuit's efficiency of software testing.
In the embodiment of fig. 5, the output test circuit will be further described below with reference to the embodiment shown in fig. 6.
Fig. 6 is a third schematic structural diagram of an output test circuit according to an embodiment of the present disclosure. Referring to fig. 6, based on fig. 5, the output test circuit 40 further includes a switch unit 405, the switch unit 405 is connected to the first input terminal of the input selector 401, and the switch unit 405 is further configured to be connected to a pin to be tested.
The switch unit 405 is configured to receive a test control signal, and when the output test circuit is in a third state, the test control signal controls the switch unit to turn on the short-circuit test path. The switch unit 405 may be a tri-state buffer, a multiplexer (e.g., a two-out-of-one selector, a three-out-of-one selector). If the switch unit 405 is a multiplexer, the switch unit may also be connected to the core processing unit on the chip where the output test circuit 40 is located.
Next, the operation of the test circuit will be described.
When the chip is in the functional mode, the working process of the output test circuit is the same as that of the test circuit in the embodiment shown in fig. 5, and is not described herein again.
When the chip is in the test mode, the second control signal controls the second input terminal of the mode selector 403 to be gated, and the conducted circuit paths of the output test circuit are different in different test states, specifically:
in the first state (test data importing state), the working process of the circuit in the first state is the same as that of the test circuit in the embodiment shown in fig. 4, and is not described herein again.
In the second state (the data update state), the working process of the circuit in the second state is the same as that of the test circuit in the embodiment shown in fig. 5, and is not described herein again.
In a third state (a sampling data state), the switching unit 405 receives a sampling signal from the pin to be tested, outputs the sampling signal to the selector 401, and outputs the sampling signal to the test processing unit through the first register 402.
In the output test circuit, a test signal can be input to the pin to be tested, a sampling signal of the pin to be tested can be sampled, and whether short circuit occurs between the pin to be tested and an adjacent pin can be determined according to the test signal and the sampling signal. Need not with the help of other test circuit, the test procedure is simple and convenient, and then has improved test circuit's efficiency of software testing. Meanwhile, by adding a short-circuit test path, an input circuit of the output test circuit is changed into a circuit which can not only input but also output.
Fig. 7 is a fourth schematic structural diagram of an output test circuit according to an embodiment of the present disclosure. Referring to fig. 7, based on fig. 6, the input selector 401, the switch unit 405, and the mode selector 403 may be alternative selectors, where the first input terminal is "0" and the second output terminal is 1.
The switch unit 405 includes two input terminals, a signal control terminal and an output terminal, wherein a first input terminal is used for connecting with a core processing unit on a chip where the output test circuit 40 is located; the second input end is used for being connected with a pin to be tested; the signal control terminal is used for receiving a test control signal, and the test control signal is used for controlling the gating of a first input terminal of the switch unit 405 or the gating of a second input terminal of the switch unit 405; the output terminal is for connection to a first input terminal of the input selector 401.
The operation and advantageous effects of the output test circuit in the embodiment shown in fig. 7 are similar to those in fig. 6, and are not described herein again.
On the basis of any of the above embodiments, the following describes a test procedure for determining whether there is a short-circuit fault in adjacent pins of a single chip by using a specific example shown in fig. 8.
FIG. 8 is a diagram illustrating a test for a failure of a second adjacent pin of a single chip. Referring to fig. 8, the test circuit includes a chip and an output test circuit.
The operation of testing whether pin 1 and pin 2 are shorted is as follows:
in the first state (test data lead-in state), the BSC1 configures a high level "1" to the first register of the test circuit and outputs "1" to the input selector of the BSC2 test circuit, and "1" is output from the TDO pin through the first register of the BSC2 test circuit. Meanwhile, the BSC2 test the first register of the circuit is configured with a low level "0", and outputs "0" from TDO.
In the second state (update data state), "1" stored in the first register in the BSC1 test circuit is shifted out to the second register and output from the second register through the mode selector to pin 1. At the same time, the "0" stored in the first register in the BSC2 test circuit is shifted out to the second register and output from the second register, through the mode selector, to pin 2.
In the third state (sampled data state), the level value of pin 1 is captured, stored in the first register through the switching unit and the input selector in the BSC1 test circuit, and output from the first register to the first register of the BSC2 test circuit, and the level value of pin 1 is output from the TDO pin. Meanwhile, the level value of the pin 2 is captured, stored in the first register through the switching unit and the input selector in the BSC2 test circuit, and output from the first register to the TDO pin.
And comparing the level value of the pin 1 and the level value of the pin 2 output by the TDO with the configured level values, and if the level value of the pin 1 and the level value of the pin 2 output by the TDO are simultaneously '0' or '1' in the third state, indicating that the pin 1 and the pin 2 are short-circuited.
In the test circuit, the test circuit can output the configured level value and can also collect and output the level value of the pin to be tested, other test circuits are not needed, the test process is simple and convenient, and the test efficiency of the test circuit is improved.
The application also provides a chip, which comprises a core processing unit, a plurality of first pins, a plurality of second pins, a test circuit corresponding to each first pin and a test circuit corresponding to each second pin, wherein the first pins are connected with the input end of the core processing unit, the second pins are connected with the output end of the core processing unit,
the test circuit corresponding to the second pin is the output test circuit in any of the above embodiments;
the core processing unit is respectively connected with each first pin and each second pin, and each first pin and each second pin are also connected with a corresponding test circuit;
and the test circuits corresponding to the adjacent pins in the plurality of first pins and the plurality of second pins are connected.
In a possible implementation manner, the chip further includes a test processing unit, the test processing unit is connected to each test circuit, and the test processing unit is configured to determine a test result of a pin corresponding to each test circuit according to the test signal and the sampling signal output by each test circuit.
In one possible embodiment, the test circuit corresponding to the first pin includes: the input selector, the first register, the mode selector and the feedback circuit, the first register is respectively connected with the input selector, the feedback circuit and the mode selector, the feedback circuit, the input selector and the mode selector are also used for being connected with the first pin, wherein,
the input selector is used for receiving the test signal and outputting the test signal to the first register when the test circuit is in a first state;
the first register is used for outputting a test signal to the test processing unit and outputting the test signal to the first pin through the feedback circuit when the test circuit is in a second state;
the input selector is also used for receiving the sampling signal of the first pin and outputting the sampling signal to the first register when the test circuit is in a third state;
the first register is also used for outputting the sampling signal to the test processing unit.
In one possible embodiment, the input selector comprises two signal inputs, a signal control and an output, wherein,
the first input end of the input selector is used for being connected with the first pin;
the second input end of the input selector is used for receiving a test signal;
the signal control end of the input selector is used for receiving a first control signal, and the first control signal is used for controlling the gating of the first input end of the input selector or the gating of the second input end of the input selector;
the output end of the input selector is used for being connected with the input end of the first register.
In a possible implementation manner, when the test circuit corresponding to the first pin is in the first state, the first control signal is used for controlling the gating of the second input end of the input selector;
when the test circuit corresponding to the first pin is in a third state, the first control signal is used for controlling the gating of the first input end of the input selector. In a possible embodiment, in the test circuit corresponding to the first pin, the feedback circuit includes a second register and a switch unit, the second register is respectively connected with the first register and the switch unit, the switch unit is further connected with the first pin, wherein,
the second register is used for receiving the test signal from the first register when the input test circuit is in a second state, and sending the test signal to the first pin through the switch unit.
In one possible embodiment, the switch unit is configured to receive a test control signal in the test circuit corresponding to the first pin, wherein,
and when the test circuit corresponding to the first pin is in a second state, the test control signal is used for controlling the switch unit to be closed.
In one possible embodiment, in the test circuit corresponding to the first pin, the switch unit is a tri-state buffer.
In one possible embodiment, the mode selector comprises two input terminals, a signal control terminal and an output terminal in the test circuit corresponding to the first pin, wherein,
the first input end of the mode selector is used for being connected with the first pin;
the second input end of the mode selector is connected with the output end of the second register;
the signal control end of the mode selector is used for receiving a second control signal, and the second control signal is used for controlling the gating of the first input end of the first mode selector or the gating of the second input end of the first mode selector;
the output end of the first mode selector is used for being connected with a core processing unit on a chip where the input test circuit is located.
In a possible implementation manner, when the chip where the test circuit corresponding to the first pin is located is in a functional mode, the second control signal is used for controlling the gating of the first input end of the first mode selector;
when the chip where the test circuit corresponding to the first pin is located is in the test mode, the second control signal is used for controlling the second input end of the first mode selector to be gated.
The chip can test the short-circuit fault of the pin of the chip, and other chips or test tools with test functions are not needed, so that the test cost is reduced; meanwhile, the testing process is simple and convenient, and the testing efficiency is improved.
On the basis of any of the above embodiments, a description will be given below of a test procedure for determining whether there is a short-circuit fault in a Ball Grid Array (BGA) chip by using a specific example shown in fig. 9.
Fig. 9 is a schematic diagram of the positions of the BGA chip pins. Please refer to fig. 9. If the BGA chip is to be tested for the presence of a fault, the first register in the BSC test circuit with the pin is configured with "010101 … …" in sequence according to the pin sequence shown in fig. 9, and then the first register in the BSC test circuit with the pin is configured with "101010 … …" in sequence, so as to perform two tests, with reference to the embodiment shown in fig. 8. Through two tests, whether the short circuit phenomenon exists in the horizontal direction and the vertical direction can be judged quickly.
Alternatively, the "1010 …" and "0101 …" are configured for each row (or each column) of the package array, and two tests can quickly determine whether there is a short circuit in the front and back diagonal directions.
Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the embodiments of the present invention, and are not limited thereto; although embodiments of the present invention have been described in detail with reference to the foregoing embodiments, those skilled in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the embodiments of the present invention.
Claims (12)
1. An output test circuit, comprising: an input selector, a first register and a mode selector, the first register is connected with the input selector and the mode selector respectively, the input selector is also used for being connected with a pin to be tested, wherein,
the input selector is used for receiving a test signal and outputting the test signal to the first register when the output test circuit is in a first state;
the first register is used for outputting the test signal to the test processing unit and outputting the test signal to the pin to be tested through the mode selector when the output test circuit is in a second state;
the input selector is further configured to receive a sampling signal of the pin to be tested and output the sampling signal to the first register when the output test circuit is in a third state;
the first register is further configured to output the sampling signal to a test processing unit.
2. The output test circuit of claim 1, wherein the input selector comprises two signal input terminals, a signal control terminal, and an output terminal, wherein,
the first input end of the input selector is used for being connected with the pin to be tested;
a second input of the input selector is configured to receive the test signal;
the signal control end of the input selector is used for receiving a first control signal, and the first control signal is used for controlling the gating of the first input end of the input selector or the gating of the second input end of the input selector;
the output end of the input selector is used for being connected with the input end of the first register.
3. The output test circuit of claim 2,
when the output test circuit is in the first state, the first control signal is used for controlling the gating of the second input end of the input selector;
when the output test circuit is in the third state, the first control signal is used for controlling the gating of the first input end of the input selector.
4. The output test circuit of any of claims 1-3, further comprising a second register having an input coupled to an output of the first register and an output coupled to an input of the mode selector, wherein,
the second register is used for receiving the test signal from the first register when the test circuit is in the second state, and sending the test signal to the pin to be tested through the mode selector.
5. The output test circuit of claim 4, wherein the mode selector comprises two input terminals, a signal control terminal, and an output terminal, wherein,
the first input end of the mode selector is used for being connected with a core processing unit on a chip where the output test circuit is located;
a second input end of the mode selector is connected with an output end of the second register;
the signal control end of the mode selector is used for receiving a second control signal, and the second control signal is used for controlling the gating of the first input end of the second mode selector or the gating of the second input end of the second mode selector;
the output end of the mode selector is used for being connected with the pin to be tested.
6. The output test circuit of claim 5,
when the chip where the output test circuit is located is in a functional mode, the second control signal is used for controlling the gating of the first input end of the mode selector;
and when the chip where the output test circuit is located is in a test mode, the second control signal is used for controlling the gating of the second input end of the mode selector.
7. The output test circuit of any of claims 1-6, further comprising a switch unit, wherein the switch unit is connected to the first input terminal of the input selector, and wherein the switch unit is further configured to be connected to the pin to be tested.
8. The output test circuit of claim 7, wherein the switching unit comprises two input terminals, a signal control terminal, and an output terminal, wherein,
the first input end of the switch unit is used for being connected with a core processing unit on a chip where the output test circuit is located;
the second input end of the switch unit is used for being connected with the pin to be tested;
the signal control end of the switch unit is used for receiving a test control signal, and the test control signal is used for controlling the gating of the first input end of the switch unit or the gating of the second input end of the switch unit;
and the output end of the switch unit is connected with the first input end of the input selector.
9. The output test circuit of claim 8, wherein the test control signal is configured to control the second input of the switch unit to be gated when the output test circuit is in the third state.
10. A chip, comprising a core processing unit, a plurality of first pins, a plurality of second pins, a test circuit corresponding to each first pin, and a test circuit corresponding to each second pin, wherein the first pins are connected to an input terminal of the core processing unit, the second pins are connected to an output terminal of the core processing unit, wherein,
the test circuit corresponding to the second pin is the output test circuit of any one of claims 1-9;
the core processing unit is respectively connected with each first pin and each second pin, and each first pin and each second pin are also connected with a corresponding test circuit;
and the test circuits corresponding to the adjacent pins in the plurality of first pins and the plurality of second pins are connected.
11. The chip according to claim 10, further comprising a test processing unit, wherein the test processing unit is connected to each test circuit, and the test processing unit is configured to determine a test result of the pin corresponding to each test circuit according to the test signal and the sampling signal output by each test circuit.
12. The chip of claim 11, wherein the test circuit corresponding to the first pin comprises: an input selector, a first register, a mode selector and a feedback circuit, the first register being connected with the input selector, the feedback circuit and the mode selector, respectively, the feedback circuit, the input selector and the mode selector further being configured to be connected with a first pin, wherein,
the input selector is used for receiving a test signal and outputting the test signal to the first register when the test circuit is in a first state;
the first register is used for outputting the test signal to the test processing unit and outputting the test signal to the first pin through the feedback circuit when the test circuit is in a second state;
the input selector is further configured to receive a sampling signal of the first pin and output the sampling signal to the first register when the test circuit is in a third state;
the first register is further configured to output the sampling signal to the test processing unit.
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