JPH06348363A - Clock signal distributing circuit - Google Patents

Abstract

PURPOSE:To provide a clock signal distributing circuit which can be easily designed for an integrated circuit and has the small clock skew. CONSTITUTION:A clock driver 11 which distributes the clock signals is subsidiarily connected to the circuit blocks 151-155 which has the same constitution. The block 151 includes the registers 101-104 which supply the input data to the corresponding logic circuits 121-124 respectively in response to the supply of clock signals, a delay circuit 141 which delays the clock signal supplied to the block 151, and a buffer 12 which supplies the delayed clock signal to the next circuit block. The circuit 141 synchronizes with the clock signal whose phase is shifted by a natural number multiple as much as a single clock cycle in regard of the delayed variable added to the buffer 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock signal distribution circuit, and particularly to a clock signal supplied to a plurality of registers in a circuit block incorporated in a semiconductor integrated circuit (IC) chip with a small skew and low power consumption. The present invention relates to a clock signal distribution circuit.

[0002]

2. Description of the Related Art A conventional clock signal distribution circuit for realizing a low skew of a clock signal is described in, for example, Japanese Patent Laid-Open No. 63-107316. Figure 10
According to this clock signal distribution circuit, the distribution clock bus 704 supplied from the clock driver 701 is D
Wiring is provided so as to surround the circuit blocks 702a and 702b such as FF or a plurality of circuit blocks 703a to 703i. The clock bus 704 is composed of a first layer wiring shown by a solid line and a second layer wiring shown by a dotted line. Each circuit block 702a and 702b and 703a
To 703i are connected to clock buses 704.
The clock signal is supplied to the wiring connected to the first wiring in the horizontal direction and the second wiring in the vertical direction. Since each wiring series is connected by the wiring 704 to the resistance component due to the wiring and the through hole and the capacitance component such as the wiring capacitance and the input capacitance of the block, the difference in the transmission time of the clock signal between the wiring series becomes small. , The variation of clock signal skew within the chip is reduced.

Further, another conventional example is disclosed in Japanese Patent Laid-Open No. 2-291.
There is a semiconductor device described in Japanese Patent Publication No. 13). Figure 1
1, the semiconductor device 711 has clock input terminals 712 and 720 and clock wirings 713 and 72.
1, flip-flops (FF) 714, 715, 72
2, and 723, high resistance wiring 716, 719, 72
4 and 725, low resistance wirings 717 and 718, and a capacitive element 726, and the flip-flops (FF) 714 and 715 connected to the clock input terminal 712 have a long clock wiring, the FF 714 increases the ratio of the low resistance wiring 717. In the FF 715 having a short wiring length, the ratio of the high resistance wiring 719 is increased and the resistance value of each clock wiring is adjusted to adjust the delay time of the clock signal between the FFs. Also, the FF7 connected to the clock input terminal 720
In FF722 and 723, the clock wiring 724 has a long high resistance wiring, whereas in the FF723, the clock wiring 725 has a short high resistance wiring. Therefore, a capacitive element 726 is added to the clock wiring 725 to provide a clock to the FF722 and 723. The delay time difference between the signal lines is reduced.

Another conventional example is the "IEEE 1992 C".
USTOM INTEGRATEDCIRCUITS
CONFERANCE, 28.3.1-28.3.4 "
It is described in. H-tree (H-tre)
Referring to FIG. 12, the clock signal distribution circuit having the structure e) has a clock driver, a plurality of buffers, and a plurality of registers arranged on the same layer, and the clock signal is distributed in order to equalize the wiring load and gate load of the buffer. The respective registers and the respective buffers are arranged so that the wirings of H-tree are arranged.

That is, the circuit block 6 in which the distribution numbers of the plurality of registers receiving the clock signal are different from each other
The circuit blocks 6801 to 6803 are provided with 801, 6802 and 6803 and a clock driver 6601, and the routing of the wiring with the buffers 6305, 6405 and 6521 is adjusted so that the wiring lengths from the clock driver 6601 are equal, and H- Dummy buffer 8406 for balancing the load of the tree configuration
8409 is added. The circuit block 6801
Is centered around the buffer 6305 to which the output signal of the clock driver 6601 is supplied and the buffers 6301 to 630.
4 are arranged in diagonal positions, and buffers 630 are provided.
The wiring to 5 is arranged in an H-tree shape with an equal wiring length. Further, each of the four registers centering on each of the buffers 6301 to 6304 is arranged in a diagonal position, and the connection with the buffers 6301 to 6304 is H with an equal wiring length.
-It is arranged in a tree shape. Circuit block 6802
Has the same configuration as the circuit block 6801 centering on the buffer 6405 to which the output signal of the clock driver 6601 is supplied, and the buffers 6405 and 6305, the buffer 64
01 and 6301, 6402 and 6302, 6403 and 63
03, and 6404 and 6304 correspond to each other, the description of the configuration will be omitted. In the circuit block 6803, four sets of circuit blocks having the same configuration as the circuit block 6802 are arranged at diagonal positions around a buffer 6521 to which the output signal of the clock driver 6601 is supplied, and a buffer 6505 serving as the center of these four blocks is provided. , 6
510, 6515, and 6520 are directly connected to each other in the form of an H-tree with the same wiring length as the buffer 6521. The buffers 6501, 6506, 6511, 6516, 6401 and the buffers 6502, 6507, 6512,
6517 and 6402 and buffers 6503 and 65
08, 6513, 6518, and 6403 and buffers 6504, 6509, 6514, 6519, and 6
Since 404 and 404 correspond to each other, the description of the configuration is omitted. In addition, for example, in order to reduce the block size of the circuit block 6801, the wiring may be bent and bent into a plurality of pulse wave shapes.

[0006]

The clock signal distribution circuit in the above-mentioned conventional IC chip has the following drawbacks. That is, in a configuration using a single clock driver, a skew occurs between the central portion near the clock driver and the peripheral portion far from the clock driver due to the delay of the clock signal. In order to reduce the wiring delay, it is necessary to increase the wiring cross-sectional area in order to reduce the wiring resistance of the clock signal line, which causes a delay, but the wiring capacitance increases. A larger clock driver is required to drive this increased wiring capacity, and power consumption also increases. For circuits using high-resistance wiring, low-resistance wiring, and capacitive elements, if the circuit scale becomes large, set the respective resistance and capacitance values according to the delay amount of each part over the entire chip. The degree of freedom becomes narrow. When a circuit arranged and wired in an H-tree is used, a fine design for aligning extra gates and wiring lengths for balancing loads in each layer is required, which complicates the design.

An object of the present invention is to solve the above-mentioned problems, and to provide a clock signal distribution circuit suitable for incorporation in an IC chip which is easy to design, with low skew between clock signals and low power consumption. Especially.

[0008]

A feature of the present invention is to provide a clock signal distribution circuit for supplying a clock signal from a clock input buffer to a plurality of registers in a circuit block arranged on a semiconductor integrated circuit. A delayed clock signal obtained by delaying the phase of the clock signal by a natural number multiple of the clock signal period is supplied to each of the plurality of registers of the plurality of circuit blocks in accordance with the arrangement distance from.

The delay circuit comprises a phase locked loop circuit to which the clock signal and the delayed clock signal supplied to the terminal register arranged in the circuit block are supplied, and the phase locked loop is the phase locked loop circuit. H- is a combination of H-shaped arrangements, each of which is arranged in a unit block having a plurality of circuit blocks and in which distribution of the clock signal supplied to each of the phase locked loops is combined.
The phase-locked loop may be arranged and wired so as to have a tree shape.

Further, the plurality of unit blocks are divided into a plurality of layers, the phase-locked loop is provided for each layer, and the distribution of the delayed clock signal supplied to each of the phase-locked loops is distributed in the H-tree form. Arrangement and wiring of the phase-locked loop are performed so that at least two unit blocks having different distribution states of the registers are arranged in the same hierarchy, and the phase-locked loop is provided for each unit block. The distribution of the clock signal supplied to each of the phase locked loops is the H-
The phase-locked loops may be arranged and wired so as to have a tree shape, or one or both of them may be combined.

[0011]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of a clock distribution circuit of the present invention, and FIG. 2 is a waveform diagram for explaining the operation of this embodiment.

Referring to FIG. 1, in the clock distribution circuit of the first embodiment, a clock driver 11 for distributing a clock signal and circuit blocks 151 to 155 are connected in cascade, and the circuit block 151 responds to the supply of the clock signal. Registers 101 to 104 for supplying input data to the corresponding logic circuits 121 to 124, respectively, and a block 15
Delay circuit 14 for delaying the clock signal supplied to
1 and its delayed signal are distributed in the block by the buffer 12. The circuit blocks 152 to 154 have the same configuration as the circuit block 151, and the registers 101 to 104 are assigned to 105 to 108, 109 to 112, and 113 to 116, respectively.
The logic circuits 121 to 124 are 125 to 128 and 129 to 1
32, 133-136, the delay circuit 141 has 142-1.
Since the buffer 12 corresponds to the buffers 13 to 15 in FIG.

The logic circuits 121 to 124 respectively supply the output data to the registers 105 to 108 of the block 152 of the next stage, and the buffer 12 the registers 105 to 105 of the next stage.
The delayed clock signal is supplied to 108 and the delay circuit 142, respectively. Hereinafter, since the circuit blocks 152 to 154 also have the same connection circuit, the description thereof will be omitted. Further, in the circuit block 155, the registers 117 to 120 have the register 1
Corresponding to 01 to 104, the output data of the preceding stage is received and output to a predetermined circuit.

According to this clock signal distribution circuit, the delay circuit 141 is designed so that the delay amount combined with the buffer 12 is one cycle delay with respect to the phase of the clock signal supplied from the clock driver 11. There is. Further, the delay circuits 142 to 144 are designed so that a delay of one cycle can be obtained with respect to the phase of the clock signal delayed in the preceding stage to which they are input. Therefore, each circuit block is synchronized with the signal whose phase is delayed by a natural multiple of the phase of the clock signal supplied from the clock driver 11 (t1 to t3 in FIG. 2). Therefore, at the time of designing, the skew can be realized by reducing the clock signal distribution range between the registers in the circuit block as much as possible, so that the design complexity can be reduced.

3 (a), (b), (c) and (d)
Referring to FIG. 3, delay circuits 141a and 141b shown in these figures are block diagrams of circuits that realize the delay circuit 141 of the present embodiment. The delay circuit 141 shown in FIG.
FIG. 3A is a circuit diagram in which inverter circuits 21 to 24 are cascade-connected to each other, and FIG. 3B is a waveform diagram for explaining the operation. Referring to FIG. 3B, the inverter 21
The output A2 of the inverter 23 in which the input clock signal A1 is delayed by the odd-numbered inverters is normally rotated by the even-numbered inverters 24, and the output signal is the inverter 24.
Of the input clock signal A1 of the inverter 21 including the delay t1 of the inverter 12 and the delay t2 of the buffer 12.
The signal A3 is shifted by one cycle with respect to. That is, the number of inverter connection stages and the transistor size are set to clock 1
It is set so that a delay of one cycle can be obtained. Also,
The delay circuit 141b shown in FIG.
3 is a circuit diagram in which 33 is connected in an odd-numbered cascade, and FIG.
(D) is a waveform diagram for explaining the operation. Referring to FIG. 3D, the input clock signal A4 of the inverter 31 becomes the input signal A5 of the inverter 33 which is delayed by an even number of stages, and is further inverted by the inverter 33, so that the delay t3 of the inverter 33 is shown in FIG. Buffer 1
The delay amount including the delay t4 of 2 can be regarded as a signal A6 which is shifted by a half cycle with respect to the input clock signal of the inverter 31. That is, the number of connecting stages of the inverter circuit and the transistor size are set so that a delay of half a clock cycle can be obtained. These delay circuits 141a and 14
A desired delay amount is set using either 1b.

The clock signal distribution circuit of this embodiment and FIG.
Comparing the clock skew with the clock signal distribution circuit of the conventional example shown in, when distributing a clock signal using one clock driver 701 of this conventional example,
The larger the distribution area is, the larger the clock skew becomes, but according to the circuit of the present embodiment, the clock shift is minimized by minimizing the deviation of the clock signals between the registers arranged in each circuit block. The queue can be reduced.

FIG. 4A is a layout showing a clock signal distribution circuit of the second embodiment, and FIG. 4B is a phase locked loop (PLL; Phase L) used in this embodiment.
It is a block diagram of an ocked Loop). Also in FIG.
FIG. 4 is a waveform diagram for explaining the operation. Referring to FIG. 4A, the clock signal distribution circuit shown in this figure is a circuit using a PLL for the delay circuit 141 in the first embodiment, and a circuit having one PLL 401 to 416 inside. Blocks 431-446 and buffer 421
˜424 and a clock driver 425 are arranged and wired around the clock driver 425 in an H-tree shape. The clock signals supplied to these blocks are PLLs 401, 402, 405, and 406.
Is supplied from the buffer 421 to the PLL 403,
Buffer 422 for 404, 407, and 408
From the buffer 423 to the PLLs 409, 410, 413, and 414.
A buffer 424 supplies the signals to 11, 412, 415, and 416, and a buffer 425 supplies the buffers 421 to 424. The PLL 401 uses the output signal of the clock driver 425 as a reference clock signal and is provided at one input terminal thereof, and is provided at the end of the circuit block 431 to which the output signal of the PLL is supplied and has a large delay amount (not shown). Clock signals are connected to the other input terminals. PLL402 ~
416 is similarly connected.

Referring also to FIG. 5, the input clock signal B1 is delayed by the clock driver 425 for a time t1, and the delayed signal B2 is further buffered by the buffer 421.
PL as clock signal B3 delayed by time t2 at
It is supplied to L401 and becomes the reference clock signal. The reference clock signal B3 and the clock signal B4 of a register (not shown) arranged at the end of the circuit block 431 and having a large delay amount are phase-compared by the PLL 401 to synchronize with the phase of the reference clock signal B3. Be done.
Therefore, only the distribution of the reference clock signal is H-tr.
The circuit blocks 431 to 44 are arranged by arranging them in an ee shape and arranging and wiring so that skew is not generated under an equal load.
It is possible to distribute the clock signal synchronized with the phase shifted by 6 by a natural number multiple of the clock cycle with high accuracy.

FIG. 6 is a layout diagram showing a clock signal distribution circuit of the third embodiment, and FIG. 7 is a waveform diagram for explaining its operation. Referring to FIG. 6, the clock signal distribution circuit shown in FIG. 6 includes circuit blocks 546 and 5 of the first hierarchy.
35 and a clock driver 521, the first layer circuit block 546 has a PLL 516 and second layer circuit blocks 540 and 545. The second level circuit block 540 includes a PLL 510 and circuit blocks 536 to 536.
539 and the circuit blocks 536 to 539 respectively have PLLs 506 to 509. Similarly, circuit block 5
45 includes a PLL 515 and circuit blocks 541 to 544, and the circuit blocks 541 to 544 are the PLL 51.
1 to 514. Further, the other first-level circuit block 535 includes the PLL 505 and the circuit blocks 531 to 534.
And circuit blocks 531 to 534 have PLL5.
01 to 504. The PLL 516 of the first layer receives the reference clock signal from the clock driver 521 at one input terminal thereof and supplies it to the PLLs 510 and 515, and also supplies this signal to the PLLs 510 and 515.
Is supplied to the other input terminal of the PLL 516 from either one of the input terminals. The output signal of PLL510 is PL
The signal is supplied as a reference signal to one of the input terminals of L506 to 509, and this signal is supplied to the other input terminal of the PLL510 from one of the input terminals of the PLL506 to 509. The output signals of the PLLs 506 to 509 are supplied to a register (not shown) in the circuit block, and this signal is supplied to the other input terminals of the PLLs 506 to 509 from the terminal ends of the registers. The circuit block 545 has a similar configuration, and the components 515 and 510, 511 and 50 are
6, 512 and 507, 513 and 508, and 514 and 509, respectively, correspond to each other and will not be described. Also,
The output signal of the clock driver 521 is supplied to the one input terminal of the PLL 505 of the circuit block 535 as a reference clock signal. The other configuration is the same as that of the circuit block 540, and the components 505 and 510, 501 are included.
And 506, 502 and 507, 503 and 508, and 5
Since 04 and 509 correspond to each other, description thereof will be omitted.
Further, the arrangement of each of these circuit blocks is such that each of the PLLs 501 to 516 has an H-tree centered on the clock driver 521.
It is arranged so as to be in a shape.

Referring to FIG. 7, input clock signal C1 of buffer 521 is delayed by time t1 in buffer 521, and this signal C2 is supplied to the input terminals of PLLs 505 and 516. This signal C2 and PLL 501-50
The respective input signals C3 of 4, 510 and 515 are respectively phase-compared and synchronized with the signal C2. Further input signal C
3 and the terminal signal C4 of the circuit blocks 531 to 534 are compared in phase and synchronized with the signal C3. Similarly, PLL 506 ~
509 and 511 to 514 to the input signal C5, the end signals C6 of the circuit blocks 536 to 539 and 541 to 544.
Synchronize with each other. Therefore, the circuit blocks 536-
The end signal C6 of 539 and 541 to 544 is the PLL 505.
And 516, respectively.

That is, when a delay circuit using a PLL is used, the design is facilitated by hierarchically forming an internal block of an IC to which a clock signal is supplied.
For example, circuit blocks 531 to 534, 536 to 53
If 9 and 541 to 544 are already designed and registered as macroblocks and are used, block 53
The clock design when designing 5 is blocks 531 to 5
It is only necessary to consider the supply to 34. Similarly, when designing block 540, the clock design is block 536.
˜539, the clock design when designing block 545 need only consider the supply to blocks 541-544, and the clock design when designing block 546 need only consider the supply to blocks 540 and 545, respectively. Therefore, the designed assets can be utilized and there is no need to consider the inside of these blocks. Further, even if the depths of the layers are different, a clock signal whose phase is shifted by a natural number times the clock period is always supplied, so that low skew is realized.

FIG. 8 is a layout diagram showing a clock signal distribution circuit of the fourth embodiment, and FIG. 9 is a waveform diagram for explaining its operation. Referring to FIG. 9, in the clock signal distribution circuit shown in this figure, a clock driver, a plurality of buffers, a plurality of registers and a plurality of PLLs are arranged on the same layer, and the wiring load and gate load of this buffer are made uniform. Therefore, the respective registers and the respective buffers are arranged so that the wiring of the clock signal has an H-tree arrangement. That is, the circuit block 68 in which the distribution states of the plurality of registers receiving the clock signal are different from each other
01, 6802 and 6803 and clock driver 6
601 and each circuit block 6801 to 6803,
Buffers 6305 and 640 connected respectively via PLLs 6701 to 6703 arranged in each block
5 and 6521 are arranged so that the wiring lengths from the clock driver 6601 are adjusted to be equal to each other. Other configurations are the same as those in FIG. 12 described in the related art, and therefore description thereof will be omitted.

Referring to FIG. 9, the clock driver 6
The input clock signal D1 of 601 is delayed by the time t1 in the buffer 6601 and this clock signal D2 is transferred to the PLL 6701.
To 6703 are supplied to one of the input terminals. PLL6
In the buffers 6305 and 640, the signals D3 delayed by a predetermined cycle in units of clocks 701 to 6703 are provided.
5 and 6521 are delayed by time t2, and the signal D4 is added to the buffer 6301, 6304, and 640.
1-6404, 6501-6504, 6506-650
9, 6511 to 6514, and 6516 to 6519 are further delayed by time t3 and supplied to each register. The signal D6 at the end of each of these circuit blocks 6801 to 6803 is PLL 6305, 6405, and 652.
The signal D2 is supplied to the other input terminal of 1 and the phase of the signal D2 is compared with that of the signal D2 to synchronize the phases of the signal D2 and the signal D6.

Comparing the circuit of this embodiment with the circuit of the conventional example shown in FIG. 12, the circuit shown in FIG. 12 has the same number of buffer stages up to the end to which the clock is distributed, and the load of the buffers at each stage is Uniformity is an essential condition for achieving low skew.

When the load blocks are not uniform as shown in FIG. 12, the dummy wiring or the dummy buffer 8 is used.
It is necessary to add 306 to 8308 and 8406 to 8408, which causes increase in power consumption and complexity of design. On the other hand, in the case of the present embodiment, it is sufficient to consider only the skew reduction in the circuit block, and the difference in the number of stages of the buffer between the circuit blocks or the difference in the buffer load in each layer can be ignored, which makes the design complicated. Can be significantly reduced.
Further, since the reference clock signal and the clock signal at the end of each block are synchronized by the PLL by shifting the phase by a natural multiple of the clock cycle, this occurs in the buffer due to variations in diffusion conditions during IC chip manufacturing. Clock skew can be reduced.

As described above, in order to reduce the clock skew in the circuit block as much as possible, the arrangement and wiring of each block is made into an H-tree structure, and the PLL is arranged to adjust the phase between each circuit block to a natural multiple of the clock cycle. Was used.

[0028]

As described above, the clock signal distribution circuit of the present invention divides a circuit block including a register and a logic circuit arranged on an IC chip into a plurality of blocks and supplies them to each circuit block. By supplying a clock signal having a phase delay that shifts the phase by a natural multiple of the clock signal period, the clock signal is supplied as a clock signal that is in phase synchronization with the clock signal output from the clock driver. Therefore, it is not necessary to distribute the same clock signal with low skew to the circuit blocks that require a clock on the entire IC chip. Therefore, when designing for low skew, each circuit block has a clock phase that is a natural multiple of the clock period. It is sufficient to design in consideration of delaying the delay time and low skew in a small circuit block, which can significantly reduce the design complexity and realize a clock signal distribution circuit for an IC having a small clock skew. . In addition, since there is no unnecessary wiring capacity for reducing skew and an increase in dummy buffer, low power consumption can be easily realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a waveform diagram for explaining the first embodiment.

FIG. 3A is a delay circuit 12 included in the first embodiment.
It is a block diagram of a. (B) is a waveform diagram for explaining the operation of the delay circuit 12a. FIG. 7C is a configuration diagram of the delay circuit 12b included in the first embodiment. (D) is a delay circuit 12b
3 is a waveform diagram for explaining the operation of FIG.

FIG. 4A is a block diagram showing a second embodiment of the present invention. (B) is a block diagram of a PLL used in the second embodiment.

FIG. 5 is a waveform diagram for explaining a second embodiment.

FIG. 6 is a block diagram showing a third embodiment of the present invention.

FIG. 7 is a waveform diagram for explaining a third embodiment.

FIG. 8 is a block diagram showing a fourth embodiment of the present invention.

FIG. 9 is a waveform chart for explaining a fourth embodiment.

FIG. 10 is a block diagram showing an example of a conventional clock signal distribution circuit.

FIG. 11 is a block diagram showing another example of a conventional clock signal distribution circuit.

FIG. 12 is a block diagram showing still another example of a conventional clock signal distribution circuit.

[Explanation of symbols]

11 clock driver 12-15, 421-425, 521, 6301-63
05,6401-6405 Buffers 21-24,31-33 Inverters 101-120 Registers 121-132 Logic circuits 141-144,141a, 141b Delay circuits 151-155,431-446,531-546,6
801 to 6803 circuit blocks 401 to 416, 501 to 516, 6701 to 6702
PLL

Claims (3)

[Claims] 1. A clock signal distribution circuit for supplying a clock signal from a clock input buffer to a plurality of registers in a circuit block arranged on a semiconductor integrated circuit,
The delayed clock signal obtained by delaying the phase of the clock signal by a natural number multiple of the clock signal period corresponding to the arrangement distance from the clock input buffer is supplied to each of the plurality of registers of the plurality of circuit blocks. Clock signal distribution circuit. 2. The delay circuit comprises a phase locked loop to which the clock signal and the delayed clock signal supplied to a terminal register arranged in the circuit block are supplied, and the phase locked loop is the circuit. The phase-locked loops are arranged in unit blocks each having a plurality of blocks, and the distribution of the clock signal supplied to each of the phase-locked loops is H-tree-shaped by combining H-shaped arrangements. 2. The clock signal distribution circuit according to claim 1, wherein the clock signal distribution circuit is arranged and wired. 3. The unit blocks are divided into a plurality of layers, the phase-locked loop is provided for each layer, and the distribution of the delayed clock signal supplied to each of the phase-locked loops is distributed in the H-tree shape. Arrangement and wiring of the phase-locked loop are performed so that at least two unit blocks having different distribution states of the registers are arranged in the same hierarchy, and the phase-locked loop is provided for each unit block. The arrangement and wiring of the phase-locked loop are performed such that the distribution of the clock signal supplied to the phase-locked loop is in the H-tree shape, and one or both of them are combined. The clock signal distribution circuit according to item 1.