JP3416040B2 - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP3416040B2
JP3416040B2 JP30880197A JP30880197A JP3416040B2 JP 3416040 B2 JP3416040 B2 JP 3416040B2 JP 30880197 A JP30880197 A JP 30880197A JP 30880197 A JP30880197 A JP 30880197A JP 3416040 B2 JP3416040 B2 JP 3416040B2
Authority
JP
Japan
Prior art keywords
bump
pad
semiconductor chip
chip
elliptical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP30880197A
Other languages
Japanese (ja)
Other versions
JPH11145199A (en
Inventor
秀彦 吉良
直樹 石川
俊二 馬場
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP30880197A priority Critical patent/JP3416040B2/en
Publication of JPH11145199A publication Critical patent/JPH11145199A/en
Application granted granted Critical
Publication of JP3416040B2 publication Critical patent/JP3416040B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
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    • H01L2224/05553—Shape in top view being rectangular
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/0554—External layer
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    • H01L2224/061—Disposition
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    • H01L2224/06131—Square or rectangular array being uniform, i.e. having a uniform pitch across the array
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    • H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06135—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
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    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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    • H05K1/111—Pads for surface mounting, e.g. lay-out
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Description

【発明の詳細な説明】 【０００１】 【発明の属する技術分野】本発明は半導体装置に係り、
特に外部接続端子として突起電極（バンプ）を有した半
導体装置に関する。近年、半導体装置の高密度化及び小
型化が急速な勢いで進んでおり、これに伴い半導体装置
に配設される外部接続端子数は増大し、よって外部接続
端子の端子間ピッチは狭ピッチ化する傾向にある。 【０００２】このため、半導体装置の外部接続端子とし
てバンプ（突起電極）を設けると共に、これを実装用基
板にフリップチップ実装する実装構造が提案されまた実
施されている。 【０００３】 【従来の技術】図８は、従来の半導体装置８（以下の説
明では、半導体装置として半導体チップを用いた例につ
いて説明する）を実装用基板２にフリップチップ実装し
た状態を示している。実装用基板２は、樹脂或いはセラ
ミック製の基板本体４の上面に配線６が所定のパターン
で形成されている。また、半導体チップ８は、図９に示
すように、チップ本体１２（基板）の回路形成面１４に
突起電極となる複数のバンプ１０（梨地で示す）が配設
されている。 【０００４】バンプ１０はスタッドバンプであり、ワイ
ヤボンディング技術を利用して形成されている。このバ
ンプ１０は、下段部１０ａと上段部１０ｂとを有した形
状とされており、特に下段部１０ａは略半球形状とされ
ている。前記のように、バンプ１０はチップ本体１２の
回路形成面１４に配設されるが、チップ本体１２のバン
プ形成位置にはパッド１６が形成されている。よって、
バンプ１０はパッド１６に接合されることにより、チッ
プ本体１２に接合された構成となる。 【０００５】このパッド１６の形状は、図９に示される
ように、バンプ１０の形状（即ち、下段部１０ａの略半
球形状）に対応するよう平面視した状態で円形状に形成
されていた。また、上記のようにパッド１６はバンプ１
０が接合されるものであるため、位置決め誤差及び取り
付け誤差等を考慮して、パッド１６の直径Ｗ１はバンプ
１０の径寸法Ｒ１に対して大きく設定されていた（Ｗ１
＞Ｒ１）。 【０００６】上記構成とされた半導体チップ８は、実装
用基板２にフリップチップ実装されるが、この実装状態
においてバンプ１０は導電性を有した接着剤２６により
配線６に固定される。これにより、半導体チップ８はフ
リップチップ実装用基板２に電気的及び機械的に接続さ
れた構成とされていた。ところで、半導体チップ８の高
密度化が近年程進んでいない従来では、半導体チップ８
のピン数は少なく、よって隣接するパッド１６間のピッ
チＰ１は広く取ることができた。 【０００７】よって、各パッド１６の面積（直径Ｗ１）
を大きくとることができ、これに伴いバンプ１０の形状
（径寸法Ｒ１）も大きくすることができた。このため、
バンプ１０をパッド１６に接合した時におけるバンプ１
０とパッド１６の接合面積を大きく取ることができ、よ
って接合力の強い信頼性の高い接合を行なうことができ
た。 【０００８】 【発明が解決しようとする課題】しかるに、近年の半導
体チップの急激な高密度化及び小型化に伴い、半導体チ
ップに設けられるピン数は増大する傾向にある。図１０
は、図９に示した半導体チップ８に対し、多ピン化が図
られた、従来の半導体チップ１８を示している。上記の
ように、半導体チップ１８が小型化しかつ多ピン化が図
られると、チップ本体１２に配設されるパッド２２の隣
接ピッチＰ２は、図９に示した半導体チップ８のパッド
１６間のピッチＰ１に比べて必然的に狭くなる（Ｐ２＜
Ｐ２）。 【０００９】また、隣接するパッド２２が干渉すること
は許されないため、上記のようにパッド間ピッチＰ２が
小さくなることにより各パッド２２の面積（直径Ｗ２）
も小さくなる。また、このように各パッド２２の面積
（直径Ｗ２）が小さくなることに伴い、バンプ２０の形
状（径寸法Ｒ２）も小さくせざるおえなくなる。このた
め、図１０に示す半導体チップ１８では、バンプ２０を
パッド２２に接合した際、バンプ２０とパッド２２との
接合面積は小さくなり、バンプ２０とパッド２２との間
における接合力は低下してしまう。よって、半導体チッ
プ１８は実装用基板２から離脱し易くなり、フリップチ
ップ実装の信頼性が低下してしまうという問題点があっ
た。 【００１０】本発明は上記の点に鑑みてなされたもので
あり、信頼性の高いフリップチップ実装を可能とした半
導体装置を提供することを目的とする。 【００１１】 【００１２】 【課題を解決するための手段】上記課題を解決するため
に本発明では、次の手段を講じたことを特徴とするもの
である。請求項１記載の発明では、複数のパッドを有す
ると共に、このパッド上に突起電極を配設した構成の半
導体装置において、前記突起電極を、平面視した状態に
おいて長円形状の半球部と該半球部上に形成される円柱
部とからなるスタッドバンプとすると共に前記パッドの
形状を矩形状とし、かつ、前記パッドの長手方向と前記
突起電極の長手方向とが一致するよう、前記突起電極を
前記パッドに配設したことを特徴とするものである。 【００１３】 【００１４】上記の各手段は、次のように作用する。請
求項１記載の発明によれば、突起電極を、平面視した状
態において長円形状の半球部と該半球部上に形成される
円柱部とからなるスタッドバンプとすると共にパッドの
形状を矩形状とし、かつパッドの長手方向と突起電極の
長手方向とが一致するよう突起電極をパッドに配設した
ことにより、隣接する突起電極を近接して配設すること
が可能となり、突起電極を高密度に配置することができ
る。 【００１５】また、長手方向に対しては突起電極は長く
形成することが可能であるため、上記のように隣接する
突起電極間の距離を短くしても、突起電極とパッドとの
接合面積は広くすることができ、よって突起電極とパッ
ドとの接合力を大きく維持させることができる。 【００１６】 【発明の実施の形態】次に、本発明の実施の形態につい
て図面と共に説明する。図１は、本発明の一実施例であ
る半導体装置（以下の説明では、半導体装置として半導
体チップ３０を用いた例について説明する）の部分拡大
図であり、図６は半導体チップ３０を実装用基板４６に
フリップチップ実装した状態を示している。 【００１７】半導体チップ３０は、いわゆるベアチップ
であり、例えばシリコン或いはガリウム−砒素よりなる
チップ本体３４（基板）の回路形成面３４に所定の回路
が形成されると共に、回路形成部分を囲繞するように複
数のパッド３８が形成されている。本実施例では、この
パッド３８の形状を矩形状（即ち、長方形状）としたこ
とを特徴の一つとしている。尚、以下この矩形状のパッ
ド３８を矩形状パッド３８と称する。 【００１８】このパッド３８の大きさは、短辺の長さＷ
Ｓ（短編長）が先に図１０を用いて説明した高密度化さ
れた半導体チップ１８のパッド径Ｗ２と略等しい寸法と
されている（ＷＳ≒Ｗ２）。これに対し長辺の長さＷＬ
（長辺長）は、半導体チップ１８のパッド径Ｗ２に比べ
て長い寸法に設定されている（ＷＬ＞Ｗ２）。また、各
パッド３８は、図１に示されるように、その長手方向が
互いに平行となるよう配設されている。これを換言すれ
ば、隣接する各パッド３８は、その長辺同志が互いに平
行に対向するよう列設されている。 【００１９】このように各パッド３８を列設させること
により、図中矢印Ｘ方向及び図中矢印Ｙ方向にパッド３
８を列設させる際、パッド３８を高密度に配設すること
ができる（即ち、単位長さ内に多数のパッド３８を配設
することができる）。これにより、半導体チップ３０が
高密度化及び多ピン化しても、これに容易に対応するこ
とが可能となる。 【００２０】続いて、上記構成とされたパッド３８に設
けられるバンプ３６（突起電極）について、図１に加え
図２乃至図５を用いて説明する。本実施例ではバンプ３
６としてスタッドバンプを採用しており、その形状を平
面視した状態において略長円形状に形成したことを特徴
とするものである（以下、このバンプ３６を長円形状バ
ンプ３６という）。即ち、図１乃至図３に示されるよう
に、長円形状バンプ３６は長手方向とこれに直交する方
向でその径寸法が異なっており、具体的には長径ＲＬと
短径ＲＳとを有した構成となっている（ＲＬ＞ＲＳ）。 【００２１】また、長円形状バンプ３６は、下段部３６
ａと上段部３６ｂとを有した形状とされており、下段部
３６ａが上記のように略長円形状とされており、その上
部に突設した上段部３６ｂは略円柱形状とされている。
即ち、本実施例に係る長円形状バンプ３６は、いわゆる
二段構造のバンプ形状とされている。この長円形状バン
プ３６は、チップ本体３２の回路形成面３４に配設され
るが、回路形成面３４の所定バンプ形成位置には、前記
した矩形状を有したした矩形状パッド３８が形成されて
いる。よって、図６に示されるように、半導体チップ３
０を実装用基板４６にフリップチップ実装した際、長円
形状バンプ３６は各矩形状パッド３８に接合され、これ
により半導体チップ３０と実装用基板４６は電気的に接
続された状態となる。 【００２２】このフリップチップ実装の際、長円形状バ
ンプ３６は導電性を有した接着剤４９により配線６に固
定される。上記のように、長円形状バンプ３６は下段部
３６ａと上段部３６ｂとを有した２段形状とされている
ため、接着剤４９の乗りがよく確実に半導体チップ３０
を実装用基板４６に電気的及び機械的に接続することが
できる。また、はんだを用いることなく半導体チップ３
０を実装用基板４６に搭載することができるため、鉛規
制に対しても対応することができる。 【００２３】ここで、長円形状バンプ３６と矩形状パッ
ド３８との接合構造に注目し、以下説明する。先ず、長
円形状バンプ３６と矩形状パッド３８の大きさに注目す
ると、本実施例では、長円形状バンプ３６の長径ＲＬは
矩形状パッド３８の長辺長ＷＬに対して若干小さく設定
されており（ＲＬ＜ＷＬ）、同様に長円形状バンプ３６
の短径ＲＳは矩形状パッド３８の短辺長ＷＳに対しても
若干小さく設定されている（ＲＳ＜ＷＳ）。 【００２４】この構成とすることにより、半導体チップ
３０を実装用基板４６にフリップチップ実装する際、位
置決め誤差及び取り付け誤差等が存在したとしても、確
実に半導体チップ３０を実装用基板４６に実装すること
が可能となる。次に、矩形状パッド３８に対する長円形
状バンプ３６の接合方向に注目する。前記のように、矩
形状パッド３８は矩形状とされており、また長円形状バ
ンプ３６は長円形状を有した形状とれさている。この長
円形状バンプ３６を矩形状パッド３８に接合する際、長
円形状バンプ３６の長手方向と矩形状パッド３８の長手
方向とが一致するよう接合される。 【００２５】このように長円形状バンプ３６を矩形状パ
ッド３８に接合することにより、隣接する長円形状バン
プ３６を近接して配設することが可能となり（即ち、バ
ンプ間ピッチを狭ピッチ化することができ）、よって長
円形状バンプ３６を高密度に配置することができる。従
って、半導体チップ３０が高密度化及び多ピン化して
も、これに十分に対応することができる。 【００２６】また、上記のように半導体チップ３０の高
密度化及び多ピン化に対応させるこためには、前記の長
手方向と直交する方向（即ち、図１に矢印Ｘ，Ｙで示す
方向）に長円形状バンプ３６及び矩形状パッド３８を狭
ピッチで配設することが重要である。これに対し長手方
向に関しては、これが直接に半導体チップ３０の高密度
化及び多ピン化に影響を与えないため、この長手方向に
は長円形状バンプ３６及び矩形状パッド３８を長く形成
することが可能である。即ち、長円形状バンプ３６の長
径ＲＬ及び矩形状パッド３８の長辺長ＷＬを長く形成し
ても、半導体チップ３０の高密度化及び多ピン化が妨げ
られるようなことはない。 【００２７】このため本実施例では、半導体チップ３０
の小型化の妨げとならない範囲において、長円形状バン
プ３６の長径ＲＬ及び矩形状パッド３８の長辺長ＷＬは
可能な限り長く形成した構成としている。この構成とす
るこにとより、半導体チップ３０を実装用基板４６に実
装した状態において、長円形状バンプ３６と矩形状パッ
ド３８の接合面積を大きく取ることができる。 【００２８】周知のように、バンプとパッドとの接合力
はバンプとパッドとの接合面積が増大する程強くなるた
め、上記した本実施例の構成とすることにより、隣接す
る長円形状バンプ３６のピッチＰ３を小さくしても、長
円形状バンプ３６と矩形状パッド３８との接合力を大き
く維持させることができ、よってフリップチップ実装の
信頼性を向上させることができる。 【００２９】続いて、上記した長円形状バンプ３６の形
成方法について、図４及び図５を用いて説明する。前記
したように、本実施例で用いている長円形状バンプ３６
は、スタッドバンプである。周知のように、一般的にス
タッドバンプはワイヤボンディング技術を利用して形成
される。本実施例における長円形状バンプ３６も、一般
に用いられいるスタッドバンプと同様にワイヤボンディ
ング技術を利用して形成することができる。 【００３０】以下、長円形状バンプ３６の具体的な形成
方法について説明する。ワイヤボンディング技術を長円
形状バンプ３６を形成するには、先ずワイヤボンディン
グ装置に設けられているキャピラリ４０を矩形状パッド
３８に押し当て、内部に挿通されたワイヤ（金線）４２
を矩形状パッド３８に超音波溶接する。この際、本実施
例では使用するキャピラリ４０に、予め下段用キャビテ
ィ部４４ａ及び上段用キャビティ部４４ｂを形成してお
く。下段用キャビティ部４４ａは略半楕円球形状を有し
た凹部であり、その長径及び短径は前記した長円形状バ
ンプ３６の長径ＲＬ及び短径ＲＳに対応するよう設定さ
れている。また、上段用キャビティ部４４ｂは、長円形
状バンプ３６の上段部３６ｂの形状に対応した円筒形状
とされている。 【００３１】よって、キャピラリ４０を矩形状パッド３
８に押し当て金線４２を矩形状パッド３８に超音波溶接
することにより、自動的に図２及び図３に示された長円
形状バンプ３６が形成される。即ち、従来から一般に用
いられているワイヤボンディング装置に配設されている
ワイヤボンディング用のキャピラリを、図４及び図５に
示されるキャピラリ４０に取り替えるのみで、本実施例
で用いる長円形状バンプ３６を形成することができる。 【００３２】これにより、半導体製造設備を大きく変更
することなく、かつ高いスループットで長円形状バンプ
３６を形成することができ、よって製造される半導体チ
ップ３０のコスト低減を図ることができる。次に、図１
乃至図６を用いて説明した半導体チップ３０の変形例に
ついて説明する。 【００３３】図７は、先に説明した半導体チップ３０の
変形例である半導体チップ５０を示している。尚、図７
において、図１乃至図６を用いて説明した半導体チップ
３０の構成と同一構成については同一符号を付して、そ
の説明を省略する。本変形例では、チップ本体３２に配
設される長円形状パッド５２及び矩形状パッド５４の夫
々の長手方向が、チップ本体３２の中心位置に対して放
射状に向くよう構成したことを特徴とするものである。
この構成とすることにより、半導体チップ５０を実装用
基板に実装した際の信頼性を向上させることができる。
以下、この理由について説明する。 【００３４】半導体チップ３０は、加熱することにより
熱膨張する。この際、チップ本体３２は図７に矢印で示
されるように放射状に熱膨張する。よって、半導体チッ
プ３０を実装用基板に実装した後に加熱処理が行なわれ
ると、各長円形状パッド５２にもチップ本体３２の中心
に対し放射方向に応力が印加されることとなる。ここ
で、長円形状パッド５２の剥離強さについて考察する
と、長円形状パッド５２の長手方向（図７に矢印Ａで示
す方向）に対する剥離強さは、長円形状パッド５２の長
手方向に直交する方向（図７に矢印Ｂで示す方向）に対
する剥離強さに対して強くなっている。 【００３５】よって本変形例のように、チップ本体３２
に配設される長円形状パッド５２及び矩形状パッド５４
の夫々の長手方向がチップ本体３２の中心位置に対して
放射方向に向くよう構成することにより、実装後におい
て半導体チップ３０に加熱処理が実施されても、チップ
本体３２の熱膨張方向に対し各長円形状パッド５２はそ
の剥離強さが大きくなっているため、半導体チップ３０
が実装用基板から離脱することを防止することができ
る。よって、本変形例の構成とすることにより、半導体
チップ５０を実装用基板に実装した際の信頼性を向上さ
せることが可能となる。 【００３６】尚、上記した実施例においては、半導体装
置としてベアチップ状態の半導体チップ３０，５０を例
に挙げて説明したが、本発明の適用はこれに限定される
ものではなく、例えばＢＧＡ(Ball Grid Array) 等のバ
ンプ（突起電極）を有した半導体装置に広く適用できる
ものである。また、上記した実施例では、長円形状バン
プ３６，５２をスタッドバンプとしワイヤボンディング
技術を用いて形成する方法を例に挙げて説明したが、長
円形状バンプはスタッドバンプに限定されるものではな
く、はんだバンプ等の他の構成のバンプを用いることも
可能である。また、その製造方法も、メッキ法，転写法
等の種々のバンプ形成方法を用いることも可能である。 【００３７】 【発明の効果】上述の如く本発明によれば、次に述べる
種々の効果を実現することができる。請求項１記載の発
明によれば、隣接する突起電極を近接して配設すること
が可能となり、突起電極を高密度に配置することができ
るため、半導体装置の小型化及び多ピン化に容易に対応
することができる。 【００３８】また、請求項２記載の発明によれば、隣接
する突起電極を近接して配設することが可能となり、突
起電極を高密度に配置することができる。また、長手方
向に対しては突起電極は長く形成することが可能である
ため、隣接する突起電極間の距離を短くしても突起電極
とパッドとの接合面積は広くすることができ、よって突
起電極とパッドとの接合力を大きく維持させることがで
きる。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
In particular, the present invention relates to a semiconductor device having a protruding electrode (bump) as an external connection terminal. In recent years, the density and miniaturization of semiconductor devices have been progressing at a rapid pace, and the number of external connection terminals arranged in the semiconductor device has increased accordingly, and the pitch between external connection terminals has been reduced. Tend to. For this reason, a mounting structure has been proposed and implemented in which a bump (protruding electrode) is provided as an external connection terminal of a semiconductor device and this is flip-chip mounted on a mounting substrate. FIG. 8 shows a state in which a conventional semiconductor device 8 (in the following description, an example using a semiconductor chip as a semiconductor device) is flip-chip mounted on a mounting substrate 2. I have. The mounting substrate 2 has a wiring 6 formed in a predetermined pattern on the upper surface of a resin or ceramic substrate main body 4. Further, as shown in FIG. 9, the semiconductor chip 8 is provided with a plurality of bumps 10 (shown in satin) serving as projecting electrodes on the circuit forming surface 14 of the chip body 12 (substrate). The bump 10 is a stud bump and is formed by using a wire bonding technique. The bump 10 has a shape having a lower portion 10a and an upper portion 10b. In particular, the lower portion 10a has a substantially hemispherical shape. As described above, the bumps 10 are provided on the circuit forming surface 14 of the chip body 12, and the pads 16 are formed at the bump forming positions of the chip body 12. Therefore,
The bump 10 is joined to the pad 16, so that the bump 10 is joined to the chip body 12. As shown in FIG. 9, the pad 16 has a circular shape in plan view corresponding to the shape of the bump 10 (ie, the substantially hemispherical shape of the lower portion 10a). As described above, the pad 16 is connected to the bump 1
0 is to be joined, so that the diameter W1 of the pad 16 is set to be larger than the diameter R1 of the bump 10 in consideration of a positioning error, a mounting error, and the like (W1).
> R1). The semiconductor chip 8 having the above configuration is flip-chip mounted on the mounting substrate 2. In this mounted state, the bumps 10 are fixed to the wiring 6 by a conductive adhesive 26. Thus, the semiconductor chip 8 is electrically and mechanically connected to the flip-chip mounting substrate 2. By the way, in the related art where the density of the semiconductor chip 8 has not been increased as recently,
And the pitch P1 between the adjacent pads 16 could be widened. Therefore, the area of each pad 16 (diameter W1)
And the shape (diameter dimension R1) of the bump 10 could be increased accordingly. For this reason,
Bump 1 when bump 10 is bonded to pad 16
The bonding area between the pad 0 and the pad 16 can be made large, so that a bonding with high bonding strength and high reliability can be performed. However, with the recent rapid increase in the density and miniaturization of semiconductor chips, the number of pins provided on the semiconductor chip tends to increase. FIG.
Shows a conventional semiconductor chip 18 in which the number of pins is increased with respect to the semiconductor chip 8 shown in FIG. As described above, when the size of the semiconductor chip 18 is reduced and the number of pins is increased, the adjacent pitch P2 of the pads 22 provided on the chip body 12 becomes the pitch between the pads 16 of the semiconductor chip 8 shown in FIG. Inevitably narrower than P1 (P2 <
P2). Further, since the interference between the adjacent pads 22 is not allowed, the area (diameter W2) of each pad 22 is reduced by reducing the pitch P2 between the pads as described above.
Is also smaller. Further, as the area (diameter W2) of each pad 22 becomes smaller, the shape (diameter dimension R2) of the bump 20 must be reduced. For this reason, in the semiconductor chip 18 shown in FIG. 10, when the bump 20 is bonded to the pad 22, the bonding area between the bump 20 and the pad 22 is reduced, and the bonding force between the bump 20 and the pad 22 is reduced. I will. Therefore, there is a problem that the semiconductor chip 18 is easily detached from the mounting substrate 2 and the reliability of flip-chip mounting is reduced. The present invention has been made in view of the above points, and has as its object to provide a semiconductor device which enables highly reliable flip-chip mounting. Means for Solving the Problems To solve the above problems
In the present invention, the following means are taken.
It is. In the first aspect of the present invention, which has a plurality of pads, the semiconductor device in which is disposed the projecting electrode on the pad, the projection electrode, hemispherical portions of the oval shape in a plan view and hemisphere A stud bump formed of a columnar portion formed on the portion, and the pad has a rectangular shape, and the projecting electrode is so formed that the longitudinal direction of the pad coincides with the longitudinal direction of the projecting electrode. It is characterized by being arranged on a pad. Each of the above-mentioned means operates as follows. According to the first aspect of the present invention, the protruding electrode is a stud bump composed of an elliptical hemispherical portion and a columnar portion formed on the hemispherical portion in a plan view, and the pad has a rectangular shape. In addition, since the protruding electrodes are arranged on the pad so that the longitudinal direction of the pad coincides with the longitudinal direction of the protruding electrode, adjacent protruding electrodes can be arranged close to each other, and the Can be arranged. Further, since the protruding electrodes can be formed longer in the longitudinal direction, even if the distance between the adjacent protruding electrodes is shortened as described above, the bonding area between the protruding electrodes and the pad is reduced. It can be widened, and thus the bonding strength between the protruding electrode and the pad can be kept large. Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a partially enlarged view of a semiconductor device according to an embodiment of the present invention (an example in which a semiconductor chip 30 is used as a semiconductor device will be described below). FIG. This shows a state where flip-chip mounting is performed on the substrate 46. The semiconductor chip 30 is a so-called bare chip. A predetermined circuit is formed on a circuit forming surface 34 of a chip body 34 (substrate) made of, for example, silicon or gallium-arsenic, and surrounds a circuit forming portion. A plurality of pads 38 are formed. The present embodiment is characterized in that the shape of the pad 38 is rectangular (that is, rectangular). Hereinafter, the rectangular pad 38 is referred to as a rectangular pad 38. The size of the pad 38 is the length W of the short side.
S (short stitch length) is approximately equal to the pad diameter W2 of the high-density semiconductor chip 18 described above with reference to FIG. 10 (WS ≒ W2). On the other hand, the long side length WL
(Long side length) is set to be longer than the pad diameter W2 of the semiconductor chip 18 (WL> W2). As shown in FIG. 1, the pads 38 are arranged so that their longitudinal directions are parallel to each other. In other words, adjacent pads 38 are arranged in a row such that their long sides face each other in parallel. By arranging the pads 38 in this manner, the pads 3 are arranged in the directions indicated by arrows X and Y in FIG.
When the rows 8 are arranged, the pads 38 can be arranged at a high density (that is, a large number of pads 38 can be arranged within a unit length). As a result, even if the semiconductor chip 30 has a higher density and a higher number of pins, it is possible to easily cope with this. Next, the bump 36 (protruding electrode) provided on the pad 38 having the above-described configuration will be described with reference to FIGS. 2 to 5 in addition to FIG. In this embodiment, the bump 3
A stud bump is adopted as 6 and is formed in a substantially elliptical shape when the shape is viewed in a plan view (hereinafter, this bump 36 is referred to as an elliptical bump 36). That is, as shown in FIGS. 1 to 3, the elliptical bump 36 has different diameters in the longitudinal direction and the direction perpendicular thereto, and specifically has a major diameter RL and a minor diameter RS. (RL> RS). The oval-shaped bump 36 is connected to the lower portion 36.
a and an upper portion 36b, the lower portion 36a has a substantially elliptical shape as described above, and the upper portion 36b projecting above the upper portion has a substantially cylindrical shape.
That is, the elliptical bump 36 according to the present embodiment has a so-called two-stage bump shape. The elliptical bump 36 is provided on the circuit forming surface 34 of the chip body 32, and a rectangular pad 38 having the above-described rectangular shape is formed at a predetermined bump forming position on the circuit forming surface 34. ing. Therefore, as shown in FIG.
When 0 is flip-chip mounted on the mounting substrate 46, the elliptical bumps 36 are bonded to the respective rectangular pads 38, whereby the semiconductor chip 30 and the mounting substrate 46 are electrically connected. At the time of flip-chip mounting, the elliptical bump 36 is fixed to the wiring 6 by an adhesive 49 having conductivity. As described above, the elliptical bump 36 has a two-stage shape having the lower portion 36a and the upper portion 36b.
Can be electrically and mechanically connected to the mounting substrate 46. Also, the semiconductor chip 3 can be used without using solder.
Since 0 can be mounted on the mounting substrate 46, it is possible to comply with the lead regulation. The following description focuses on the bonding structure between the elliptical bump 36 and the rectangular pad 38. First, focusing on the sizes of the oval bump 36 and the rectangular pad 38, in this embodiment, the major axis RL of the oval bump 36 is set to be slightly smaller than the major side length WL of the rectangular pad 38. Cage (RL <WL), similarly oval bump 36
Is set slightly smaller than the short side length WS of the rectangular pad 38 (RS <WS). With this configuration, when the semiconductor chip 30 is flip-chip mounted on the mounting substrate 46, the semiconductor chip 30 is reliably mounted on the mounting substrate 46 even if there are positioning errors and mounting errors. It becomes possible. Next, attention is paid to the bonding direction of the elliptical bump 36 to the rectangular pad 38. As described above, the rectangular pad 38 has a rectangular shape, and the oval bump 36 has an oval shape. When joining the elliptical bump 36 to the rectangular pad 38, the elliptical bump 36 is joined so that the longitudinal direction of the elliptical bump 36 matches the longitudinal direction of the rectangular pad 38. By bonding the elliptical bumps 36 to the rectangular pads 38 in this manner, adjacent elliptical bumps 36 can be arranged close to each other (that is, the pitch between the bumps can be reduced. Therefore, the elliptical bumps 36 can be arranged at a high density. Therefore, even if the semiconductor chip 30 has a higher density and a higher number of pins, it can sufficiently cope with this. In order to cope with the increase in the density and the number of pins of the semiconductor chip 30 as described above, a direction perpendicular to the longitudinal direction (ie, a direction indicated by arrows X and Y in FIG. 1). It is important to dispose the oval bumps 36 and the rectangular pads 38 at a narrow pitch. On the other hand, in the longitudinal direction, since this does not directly affect the increase in the density and the number of pins of the semiconductor chip 30, it is necessary to form the oval bumps 36 and the rectangular pads 38 long in the longitudinal direction. It is possible. That is, even if the long diameter RL of the oval-shaped bump 36 and the long side length WL of the rectangular pad 38 are made long, the increase in the density and the number of pins of the semiconductor chip 30 are not hindered. For this reason, in this embodiment, the semiconductor chip 30
The long diameter RL of the elliptical bump 36 and the long side length WL of the rectangular pad 38 are formed as long as possible without hindering the miniaturization of the device. With this configuration, it is possible to increase the bonding area between the elliptical bump 36 and the rectangular pad 38 when the semiconductor chip 30 is mounted on the mounting substrate 46. As is well known, the bonding strength between the bump and the pad increases as the bonding area between the bump and the pad increases. Even if the pitch P3 is reduced, the bonding force between the elliptical bump 36 and the rectangular pad 38 can be maintained large, and the reliability of flip chip mounting can be improved. Next, a method of forming the above-mentioned elliptical bump 36 will be described with reference to FIGS. As described above, the elliptical bump 36 used in this embodiment is used.
Is a stud bump. As is well known, stud bumps are generally formed using a wire bonding technique. The elliptical bump 36 in the present embodiment can also be formed by using a wire bonding technique, similarly to the commonly used stud bump. Hereinafter, a specific method of forming the oval bump 36 will be described. In order to form the elliptical bump 36 by the wire bonding technique, first, a capillary 40 provided in a wire bonding apparatus is pressed against a rectangular pad 38, and a wire (gold wire) 42 inserted inside is formed.
Is ultrasonically welded to the rectangular pad 38. At this time, in this embodiment, the lower cavity portion 44a and the upper cavity portion 44b are formed in advance in the capillary 40 used. The lower cavity portion 44a is a concave portion having a substantially semi-elliptical spherical shape, and its major axis and minor axis are set to correspond to the major axis RL and minor axis RS of the above-described elliptical bump 36. The upper cavity portion 44b has a cylindrical shape corresponding to the shape of the upper portion 36b of the oval bump 36. Therefore, the capillary 40 is connected to the rectangular pad 3
The elliptical bump 36 shown in FIGS. 2 and 3 is automatically formed by ultrasonically welding the gold wire 42 to the rectangular pad 38 at 8. That is, the capillary for wire bonding provided in the wire bonding apparatus generally used in the related art is simply replaced with the capillary 40 shown in FIGS. Can be formed. As a result, the elliptical bump 36 can be formed at a high throughput without largely changing the semiconductor manufacturing equipment, and the cost of the manufactured semiconductor chip 30 can be reduced. Next, FIG.
A modification of the semiconductor chip 30 described with reference to FIG. 6 will be described. FIG. 7 shows a semiconductor chip 50 which is a modification of the semiconductor chip 30 described above. Note that FIG.
In the figure, the same components as those of the semiconductor chip 30 described with reference to FIGS. 1 to 6 are denoted by the same reference numerals, and description thereof will be omitted. The present modification is characterized in that the longitudinal direction of each of the elliptical pad 52 and the rectangular pad 54 provided on the chip main body 32 is radially oriented with respect to the center position of the chip main body 32. Things.
With this configuration, the reliability when the semiconductor chip 50 is mounted on the mounting substrate can be improved.
Hereinafter, the reason will be described. The semiconductor chip 30 thermally expands when heated. At this time, the chip body 32 expands radially as indicated by arrows in FIG. Therefore, when the heat treatment is performed after the semiconductor chip 30 is mounted on the mounting substrate, a stress is also applied to each oval pad 52 in the radial direction with respect to the center of the chip body 32. Here, considering the peel strength of the oval pad 52, the peel strength of the oval pad 52 in the longitudinal direction (the direction indicated by the arrow A in FIG. 7) is orthogonal to the longitudinal direction of the oval pad 52. (The direction indicated by arrow B in FIG. 7). Therefore, as in this modification, the chip body 32
Oval pad 52 and rectangular pad 54 disposed on
Are configured so that the respective longitudinal directions are directed radially with respect to the center position of the chip body 32, so that even if heat treatment is performed on the semiconductor chip 30 after mounting, Since the peeling strength of the oval pad 52 is large, the semiconductor chip 30
Can be prevented from separating from the mounting substrate. Therefore, by adopting the configuration of the present modified example, it is possible to improve the reliability when the semiconductor chip 50 is mounted on the mounting substrate. In the above-described embodiment, the semiconductor devices 30 and 50 in a bare chip state have been described as examples of the semiconductor device. However, the application of the present invention is not limited to this. It can be widely applied to semiconductor devices having bumps (protruding electrodes) such as a Grid Array. Further, in the above-described embodiment, the method in which the oval bumps 36 and 52 are formed as stud bumps using the wire bonding technique has been described as an example. However, the oval bumps are not limited to the stud bumps. Instead, bumps having other configurations such as solder bumps can be used. Also, as the manufacturing method, various bump forming methods such as a plating method and a transfer method can be used. As described above, according to the present invention, the following various effects can be realized. According to the first aspect of the present invention, it is possible to arrange the adjacent protruding electrodes in close proximity, and to arrange the protruding electrodes at a high density, so that it is easy to reduce the size of the semiconductor device and increase the number of pins. Can be handled. Further, according to the second aspect of the present invention, it is possible to arrange the adjacent protruding electrodes close to each other, and it is possible to arrange the protruding electrodes at a high density. Further, since the protruding electrode can be formed longer in the longitudinal direction, the bonding area between the protruding electrode and the pad can be increased even if the distance between the adjacent protruding electrodes is shortened. The bonding strength between the electrode and the pad can be kept large.

【図面の簡単な説明】 【図１】本発明の一実施例である半導体チップの底面を
拡大して示す図である。 【図２】本発明の一実施例である半導体チップに設けら
れる長円形状バンプの正面図である。 【図３】本発明の一実施例である半導体チップに設けら
れる長円形状バンプの側面図である。 【図４】本発明の一実施例である半導体チップに設けら
れる長円形状バンプを形成する際に用いられるキャピラ
リの横断面図である。 【図５】本発明の一実施例である半導体チップに設けら
れる長円形状バンプを形成する際に用いられるキャピラ
リの縦断面図である。 【図６】本発明の一実施例である半導体チップが実装用
基板にフリップチップ実装された状態を示す図である。 【図７】本発明の変形例である半導体チップの底面を示
す図である。 【図８】従来の一例である半導体チップが実装用基板に
フリップチップ実装された状態を示す図である。 【図９】従来の一例である半導体チップの底面を拡大し
て示す図である（その１）。 【図１０】従来の一例である半導体チップの底面を拡大
して示す図である（その２）。 【符号の説明】 ３０，５０ 半導体チップ ３２ チップ本体 ３６，５２ 長円形状バンプ ３８，５４ 矩形状パッド ４０ キャピラリ ４２ 金線 ４４ キャビティ部 ４６ 実装用基板 ４７ 基板本体 ４８ 配線BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an enlarged view showing a bottom surface of a semiconductor chip according to one embodiment of the present invention. FIG. 2 is a front view of an elliptical bump provided on a semiconductor chip according to one embodiment of the present invention. FIG. 3 is a side view of an elliptical bump provided on a semiconductor chip according to one embodiment of the present invention. FIG. 4 is a cross-sectional view of a capillary used when forming an elliptical bump provided on a semiconductor chip according to one embodiment of the present invention. FIG. 5 is a longitudinal sectional view of a capillary used when forming an elliptical bump provided on a semiconductor chip according to one embodiment of the present invention. FIG. 6 is a diagram showing a state in which a semiconductor chip according to one embodiment of the present invention is flip-chip mounted on a mounting substrate. FIG. 7 is a diagram showing a bottom surface of a semiconductor chip which is a modification of the present invention. FIG. 8 is a view showing a state in which a semiconductor chip as an example of the related art is flip-chip mounted on a mounting substrate. FIG. 9 is an enlarged view of a bottom surface of a semiconductor chip as an example of the related art (part 1). FIG. 10 is an enlarged view showing a bottom surface of a semiconductor chip as an example of the related art (part 2). DESCRIPTION OF SYMBOLS 30, 50 Semiconductor chip 32 Chip main body 36, 52 Elliptical bump 38, 54 Rectangular pad 40 Capillary 42 Gold wire 44 Cavity 46 Mounting substrate 47 Substrate main body 48 Wiring

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平４−217325（ＪＰ，Ａ) 特開 平２−264435（ＪＰ，Ａ) 特開 平４−368130（ＪＰ，Ａ) 特開 平11−87418（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/60 H01L 21/92 ────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-4-217325 (JP, A) JP-A-2-264435 (JP, A) JP-A-4-368130 (JP, A) JP-A-11- 87418 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H01L 21/60 H01L 21/92

Claims (1)

(57)【特許請求の範囲】 【請求項１】 複数のパッドを有すると共に、該パッド
上に突起電極を配設した構成の半導体装置において、 前記突起電極を、平面視した状態において長円形状の半
球部と該半球部上に形成される円柱部とからなるスタッ
ドバンプとし、かつ、前記パッドの長手方向と前記突起
電極の長手方向とが一致するよう、前記突起電極を前記
パッドに配設した ことを特徴とする半導体装置。(57) [Claims] (1)A pad having a plurality of pads;
In a semiconductor device having a configuration in which a protruding electrode is provided on The protruding electrode has a semicircular shape in a plan view.
A stack consisting of a spherical portion and a cylindrical portion formed on the hemispherical portion.
A bump, and a longitudinal direction of the pad and the protrusion
The protruding electrodes are so arranged that the longitudinal direction of the electrodes coincide with each other.
Arranged on the pad A semiconductor device characterized by the above-mentioned.
JP30880197A 1997-11-11 1997-11-11 Semiconductor device Expired - Fee Related JP3416040B2 (en)

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JP3416040B2 true JP3416040B2 (en) 2003-06-16

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JP4601128B2 (en) * 2000-06-26 2010-12-22 株式会社光波 LED light source and manufacturing method thereof
JP2002009349A (en) * 2000-06-26 2002-01-11 Koha Co Ltd Surface emission led and its manufacturing method
JP3613167B2 (en) * 2000-10-12 2005-01-26 株式会社村田製作所 Pad electrode connection state inspection method
US6518675B2 (en) * 2000-12-29 2003-02-11 Samsung Electronics Co., Ltd. Wafer level package and method for manufacturing the same
JP3573150B2 (en) 2002-01-25 2004-10-06 セイコーエプソン株式会社 Semiconductor device and electro-optical device including the same
JP3863161B2 (en) 2004-01-20 2006-12-27 松下電器産業株式会社 Semiconductor device
JP5234239B2 (en) 2005-07-06 2013-07-10 セイコーエプソン株式会社 Semiconductor device
JP2007043071A (en) * 2005-07-06 2007-02-15 Seiko Epson Corp Semiconductor device
JP4605378B2 (en) 2005-07-13 2011-01-05 セイコーエプソン株式会社 Semiconductor device
JP2007027481A (en) * 2005-07-19 2007-02-01 Seiko Epson Corp Semiconductor device
JP4894999B2 (en) * 2005-11-25 2012-03-14 セイコーエプソン株式会社 Semiconductor device
US8624392B2 (en) 2011-06-03 2014-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Electrical connection for chip scale packaging
US8598691B2 (en) 2011-09-09 2013-12-03 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods of manufacturing and packaging thereof
US9548281B2 (en) 2011-10-07 2017-01-17 Taiwan Semiconductor Manufacturing Company, Ltd. Electrical connection for chip scale packaging
US8912668B2 (en) 2012-03-01 2014-12-16 Taiwan Semiconductor Manufacturing Company, Ltd. Electrical connections for chip scale packaging
US9196573B2 (en) 2012-07-31 2015-11-24 Taiwan Semiconductor Manufacturing Company, Ltd. Bump on pad (BOP) bonding structure
US9673161B2 (en) 2012-08-17 2017-06-06 Taiwan Semiconductor Manufacturing Company, Ltd. Bonded structures for package and substrate
US8829673B2 (en) 2012-08-17 2014-09-09 Taiwan Semiconductor Manufacturing Company, Ltd. Bonded structures for package and substrate
CN103594443B (en) * 2012-08-17 2017-04-12 台湾积体电路制造股份有限公司 Bonded structure for package and substrate

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