JP3410781B2 - Data transmission system - Google Patents
Data transmission systemInfo
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- JP3410781B2 JP3410781B2 JP25085993A JP25085993A JP3410781B2 JP 3410781 B2 JP3410781 B2 JP 3410781B2 JP 25085993 A JP25085993 A JP 25085993A JP 25085993 A JP25085993 A JP 25085993A JP 3410781 B2 JP3410781 B2 JP 3410781B2
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- Prior art keywords
- signal
- data
- equalization
- supplied
- detection
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- Dc Digital Transmission (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明はデータ伝送システムに係
り、特に、パーシャルレスポンス方式及び最尤復号を用
いたデータ伝送システムに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission system, and more particularly to a data transmission system using a partial response method and maximum likelihood decoding.
【０００２】近年、磁気ディスク装置の高密度化を図る
うえでパーシャルレスポンス（ＰＲ）方式及び最尤復号
（ＭＬＳＥ）等の信号処理技術が注目されており、特に
ＰＲ方式とＭＬＳＥとを組み合わせたＰＲＭＬ方式と呼
ばれる信号処理技術が注目されている。In recent years, signal processing techniques such as partial response (PR) system and maximum likelihood decoding (MLSE) have attracted attention in order to increase the density of magnetic disk devices, and in particular PRML in which the PR system and MLSE are combined. A signal processing technique called a method is drawing attention.
【０００３】また、一方、磁気ディスク装置を含むデー
タ伝送システムにおいては信号処理の高速化が求められ
ている。On the other hand, in a data transmission system including a magnetic disk device, high speed signal processing is required.
【０００４】[0004]
【従来の技術】図８にパーシャルレスポンス（ＰＲ：Pa
rcial Response）方式のクラス４と最尤検出（ＭＬＳ
Ｅ：Maximum Likelihood Sequence Estimation；ビタビ
検出）とを組み合わせた、ＰＲＭＬ方式と呼ばれるデー
タ伝送方式を用いた磁気ディスク装置の構成図を示す。
同図中、３１は磁気記録系を示す。2. Description of the Related Art FIG. 8 shows a partial response (PR: Pa
rcial response) class 4 and maximum likelihood detection (MLS)
FIG. 3 is a configuration diagram of a magnetic disk device using a data transmission method called PRML method in combination with E: Maximum Likelihood Sequence Estimation (Viterbi detection).
In the figure, 31 indicates a magnetic recording system.
【０００５】磁気記録系３１には入力信号が供給され、
磁気ディスク等に入力信号に応じた信号が記録され、そ
の再生信号は（１−Ｄ）なる等化と見なすことができ
る。このとき、Ｄは１ビットの遅延に相当する遅延演算
子を示す。An input signal is supplied to the magnetic recording system 31,
A signal corresponding to an input signal is recorded on a magnetic disk or the like, and the reproduction signal can be regarded as (1-D) equalization. At this time, D represents a delay operator corresponding to a 1-bit delay.
【０００６】ＰＲＭＬ方式では磁気記録系３１からの
（１−Ｄ）と見なおされる信号をまず、等化器３２に供
給する。等化器３２では供給された信号に対して（１＋
Ｄ）なる等化を実施する。In the PRML system, a signal from the magnetic recording system 31 which is re-considered as (1-D) is first supplied to the equalizer 32. In the equalizer 32, (1+
D) Perform equalization.
【０００７】ここで、磁気記録系３１で（１−Ｄ）、等
化器３２で（１＋Ｄ）なる等化が施されるため、等化器
３２の出力には再生信号に対して（１−Ｄ）（１＋Ｄ）
＝（１−Ｄ2 ）なる等化が実施されることになる。Since the magnetic recording system 31 equalizes (1-D) and the equalizer 32 equalizes (1 + D), the output of the equalizer 32 is (1-D) with respect to the reproduced signal. D) (1 + D)
= (1-D 2 ) equalization will be performed.
【０００８】等化器３２の出力は検出器３３に供給され
る。検出器３３は切換回路３４及び２系統の検出回路３
５，３６より構成される。切換回路３４は再生信号のビ
ット周期に応じて等化器３２より供給された信号を検出
回路３５，３６に交互に供給する。The output of the equalizer 32 is supplied to the detector 33. The detector 33 includes a switching circuit 34 and a two-system detection circuit 3.
It is composed of 5,36. The switching circuit 34 alternately supplies the signals supplied from the equalizer 32 to the detection circuits 35 and 36 in accordance with the bit period of the reproduced signal.
【０００９】検出回路３５，３６は供給された信号に対
して１／（１−Ｄ2 ）なる検出を実施する。The detection circuits 35 and 36 detect 1 / (1-D 2 ) of the supplied signal.
【００１０】図９にＰＲ方式の動作波形図を示す。ａ，
ｂは磁気記録系３１に供給される記録データ、ｃは磁気
記録系３１の出力データ、ｄは等化器３２の出力デー
タ、ｅ，ｆは切換回路３４の出力データ、ｇは検出器３
の出力データを示す。FIG. 9 shows an operation waveform diagram of the PR system. a,
b is the recording data supplied to the magnetic recording system 31, c is the output data of the magnetic recording system 31, d is the output data of the equalizer 32, e and f are the output data of the switching circuit 34, and g is the detector 3.
The output data of is shown.
【００１１】記録データａ，ｂは磁気記録系３１で（１
−Ｄ）によりデータｃとされる。等化器３２によりデー
タｃに（１＋Ｄ）なる等化が行なわれ、記録データａ，
ｂに対しては（１−Ｄ）（１＋Ｄ）＝（１−Ｄ2 ）なる
等化が実施されたことになる。このため、Ｄ2 なる２ビ
ットの遅延が生じ、切換回路３４による分割が可能とな
り、検出回路３５，３６で１ビット毎に交互に（１／
（１−Ｄ2 ））なる検出が行なわれ、検出回路３５，３
６の出力データを合成して出力することにより、データ
ｇに示すように記録データａを復元している。The recording data a and b are recorded in the magnetic recording system 31 (1
The data c is obtained by -D). The data c is equalized by (1 + D) by the equalizer 32, and the recording data a,
This means that the equalization of (1-D) (1 + D) = (1-D 2 ) is performed on b. For this reason, a delay of 2 bits D 2 occurs, and the division can be performed by the switching circuit 34, and the detection circuits 35 and 36 alternately (1 / bit by bit).
(1-D 2 )) is detected and the detection circuits 35, 3
By combining and outputting the output data of No. 6, the recording data a is restored as shown by the data g.
【００１２】また、図１０にＥＰＲＭＬ方式の磁気記録
再生系の構成図を示す。同図中、図８と同一構成部分に
は同一符号を付し、その説明は省略する。ＥＰＲＭＬ方
式ではＳＮ利得を向上するために等化器３２の後に（１
＋Ｄ）なる等化を行なう等化器４１を設け、記録データ
ａ，ｂに対して（１−Ｄ）（１＋Ｄ）（１＋Ｄ）＝（１
−Ｄ2 ）（１＋Ｄ）＝（１＋Ｄ−Ｄ2 ＋Ｄ3 ）なる等化
を実施、図９ｈに示すようなデータとする。FIG. 10 is a block diagram of a magnetic recording / reproducing system of the EPRML system. 8, those parts which are the same as those corresponding parts in FIG. 8 are designated by the same reference numerals, and a description thereof will be omitted. In the EPRML system, in order to improve the SN gain, (1
An equalizer 41 for equalizing + D) is provided, and (1-D) (1 + D) (1 + D) = (1
An equalization of −D 2 ) (1 + D) = (1 + D−D 2 + D 3 ) is performed to obtain data as shown in FIG. 9h.
【００１３】検出器４２では逆に〔１／（１＋Ｄ−Ｄ2
−Ｄ3 ）〕なる検出を行ない、図９ｇに示すように記録
データを復元する。On the contrary, in the detector 42, [1 / (1 + D-D 2
-D 3)] becomes performs detection to recover the recorded data as shown in FIG. 9g.
【００１４】[0014]
【発明が解決しようとする課題】しかるに、ＰＲＭＬ方
式の伝送システムではＳ／Ｎ利得があまり大きく取れな
いため、情報の高密度化には不利となる。However, since the S / N gain cannot be so large in the PRML type transmission system, it is disadvantageous for increasing the information density.
【００１５】また、従来のＥＰＲＭＬ方式の伝送システ
ムでは検出回路の処理が〔１／（１＋Ｄ−Ｄ2 −Ｄ3 ）
となり、奇数倍と偶数倍の遅延が混在するため、ＰＲＭ
Ｌ方式のように２系統に分割して処理することはでき
ず、従って、処理速度を上げることはできない等の問題
点があった。Further, processing of the detection circuit in the transmission system of a conventional EPRML scheme [1 / (1 + D-D 2 -D 3)
Therefore, since the delays of odd multiple and even multiple are mixed, PRM
Unlike the L system, it cannot be divided into two systems for processing, and therefore there is a problem that the processing speed cannot be increased.
【００１６】図１１にＭＲ（磁気抵抗効果型）ヘッドの
動作曲線（ρ(0-)−Ｈ特性）図を示す。ＭＲヘッドのρ
−Ｈ特性は図１１に示すようにリニアではないため、バ
イアス点により変動してしまう。例えばバイアス点ｈB
とした場合にはヘッド再生信号はバイアス、レベル上下
で非対称なものとなってしまう。一般に磁気記録系３１
内ではＭＲヘッドはＡＣカップリングされており、図１
２（Ａ）に示すＭＲヘッドで再生された信号は図１２
（Ｂ）に示すように０レベルがずれてしまう。FIG. 11 shows an operation curve (ρ (0-)- H characteristic) diagram of an MR (magnetoresistive effect) head. MR head ρ
Since the −H characteristic is not linear as shown in FIG. 11, it changes depending on the bias point. For example, bias point h B
In such a case, the head reproduction signal becomes asymmetrical between the bias and the level. Generally magnetic recording system 31
Inside, the MR head is AC-coupled.
The signal reproduced by the MR head shown in FIG.
As shown in (B), the 0 level shifts.
【００１７】０レベルがずれると正確な等化・検出でき
ないため、データの誤り率が増大してしまう。If the 0 level is deviated, accurate equalization / detection cannot be performed, and the data error rate increases.
【００１８】このように、磁気記録再生装置などにおい
ては、磁気記録再生系３１で磁気ヘッドの特性により誤
り率の劣化が生じてしまう等の問題点があった。As described above, in the magnetic recording / reproducing apparatus, there is a problem that the error rate is deteriorated in the magnetic recording / reproducing system 31 due to the characteristics of the magnetic head.
【００１９】本発明は上記の点に鑑みてなされたもので
高速に信号処理を行なえる伝送システムを提供すること
を目的とする。The present invention has been made in view of the above points, and an object of the present invention is to provide a transmission system capable of high-speed signal processing.
【００２０】[0020]
【課題を解決するための手段】図１に本発明の原理図を
示す。伝送路１には入力信号の情報が所定の周期毎に伝
送される。第１の等化手段２は伝送路上に設けられ、
（１−Ｄ）（１＋Ｄ）2〔Ｄ：１ビットの遅延演算子〕
なる等化を行なう。FIG. 1 shows the principle of the present invention. The information of the input signal is transmitted to the transmission line 1 every predetermined period. The first equalizing means 2 is provided on the transmission line,
(1-D) (1 + D) 2 [D: 1-bit delay operator]
Perform equalization.
【００２１】第２の等化手段３は伝送路１上に設けら
れ、（１−Ｄ）なる等化を行なう。The second equalizing means 3 is provided on the transmission line 1 and performs (1-D) equalization.
【００２２】切換手段４は伝送路１上の第１の等化手段
２及び第２の等化手段３の後に設けられ、第１の等化手
段２及び第２の等化手段３で等化された信号を２系統の
伝送路に所定の周期毎に交互に供給する。The switching means 4 is provided after the first equalization means 2 and the second equalization means 3 on the transmission line 1, and is equalized by the first equalization means 2 and the second equalization means 3. The generated signal is alternately supplied to the two transmission paths at predetermined intervals.
【００２３】第１の検出手段５は切換手段４から所定の
周期毎に交互に信号が供給される２系統の伝送路の一方
に設けられ切換手段４から供給される信号に対して〔１
／（１−２Ｄ2 ＋Ｄ4 ）なる検出を行なう。The first detecting means 5 is provided in one of the two transmission lines to which signals are alternately supplied from the switching means 4 at predetermined intervals, and the signal [1
/ (1-2D 2 + D 4 ) is detected.
【００２４】第２の検出手段６は切換手段４が所定の周
期毎に交互に信号が供給される２系統の伝送路の他方に
設けられ、切換手段４から供給される信号に対して〔１
／（１−２Ｄ2 ＋Ｄ4 ）なる検出を行なう。The second detecting means 6 is provided on the other side of the two transmission lines to which the switching means 4 is alternately supplied with a signal at predetermined intervals, and the signal supplied from the switching means 4 is [1.
/ (1-2D 2 + D 4 ) is detected.
【００２５】第１の検出手段５の出力信号と第２の検出
手段６の出力信号とを合成することにより入力信号が復
元される。The input signal is restored by synthesizing the output signal of the first detecting means 5 and the output signal of the second detecting means 6.
【００２６】[0026]
【作用】第１の等化手段で（１−Ｄ）（１＋Ｄ）2 に等
化された信号は第２の等化手段により（１−Ｄ）2 （１
＋Ｄ）2 ＝〔（１−Ｄ）（１＋Ｄ）〕2 ＝（１−Ｄ2 ）
2 ＝（１−２Ｄ2 ＋Ｄ4 ）に等化される。With the first equalizing means (1-D) (1 + D)2And so on
The equalized signal is (1-D) by the second equalizing means.2(1
+ D)2= [(1-D) (1 + D)]2= (1-D2)
2= (1-2D2+ DFour) Is equalized to.
【００２７】第１及び第２の等化手段により（１−２Ｄ
2 ＋Ｄ4 ）に等化された信号は切換手段４により所定周
期毎に交互に２系統の伝送路に供給される。By the first and second equalizing means (1-2D
The signal equalized to ( 2 + D 4 ) is alternately supplied to the two transmission lines at predetermined intervals by the switching means 4.
【００２８】一方の伝送路では第１の検出手段により
〔１／（１−２Ｄ2 ＋Ｄ4 ）〕なる検出が行なわれ、所
定周期おきに（１−２Ｄ2 ＋Ｄ4 ）〕に等化された信号
の復号が行なわれる。In one of the transmission lines, the detection [1 / (1-2D 2 + D 4 )] is performed by the first detection means and is equalized to (1-2D 2 + D 4 )] every predetermined period. The signal is decoded.
【００２９】また、他方の伝送路では第２の検出手段に
より〔１／（１−２Ｄ2 ＋Ｄ4 ）〕なる検出が行なわ
れ、所定周期おきに（１−２Ｄ2 ＋Ｄ4 ）〕に等化され
た信号の復号が行なわれる。Further, on the other hand the transmission path of the detection made [1 / (1-2D 2 + D 4 ) ] by the second detection means is performed, equalized to a predetermined period every (1-2D 2 + D 4)] The decoded signal is decoded.
【００３０】第１の検出手段と第２の検出手段とは信号
を所定周期おきに互いに補完していて、第１の検出手段
の出力と第２の検出手段との出力信号とを合成すること
により入力信号を復元できる。The first detecting means and the second detecting means complement each other with signals at predetermined intervals, and combine the output of the first detecting means and the output signal of the second detecting means. Can restore the input signal.
【００３１】（１−２Ｄ2 ＋Ｄ4 ）なる等化はＤ2 ，Ｄ
4 の偶数倍の遅延で実現できるため、信号を所定周期お
きに２系統の伝送路に分割して、入力信号の復号を行な
える。また、２系統で処理を行なうため、各系統の〔１
／（１−２Ｄ2 ＋Ｄ4 ）〕なる検出は所定の周期の２倍
の処理を行なえばよいことになる。The equalization of (1-2D 2 + D 4 ) is D 2 , D
Since it can be realized with a delay of an even multiple of 4 , the signal can be divided into two transmission lines at predetermined intervals and the input signal can be decoded. Also, since the processing is performed in two systems, [1 of each system
/ (1-2D 2 + D 4 )] can be detected by performing processing twice as long as a predetermined cycle.
【００３２】従って、処理時間の大きい〔１／（１−２
Ｄ2 ＋Ｄ4 ）〕の等化速度を１系統だけのものより２倍
高速化できるため、全体の処理速度を高速化できる。Therefore, the processing time is long [1 / (1-2
Since the equalization speed of D 2 + D 4 )] can be made twice as fast as that of only one system, the overall processing speed can be increased.
【００３３】[0033]
【実施例】図１に本発明の第１実施例の構成図を示す。
本実施例では磁気ディスク装置のＥＰＲＭＬ方式による
データ復号処理について説明する。同図中、１１は磁気
記録系を示す。磁気記録系１１には記録データが供給さ
れ、記録データに応じた情報が磁気ディスクに記録され
る。1 is a block diagram of the first embodiment of the present invention.
In this embodiment, a data decoding process by the EPRML system of the magnetic disk device will be described. In the figure, 11 indicates a magnetic recording system. Recording data is supplied to the magnetic recording system 11, and information corresponding to the recording data is recorded on the magnetic disk.
【００３４】磁気記録系１１では一般に磁気ディスクに
記録された情報の再生信号は元の記録データに対して
（１−Ｄ）なる等化と見なされる。（１−Ｄ）なる等化
はＤが１ビット分の遅延演算子を表わしており、現在供
給されているデータから１ビット前のデータを減算する
処理を示す。In the magnetic recording system 11, the reproduction signal of the information recorded on the magnetic disk is generally regarded as equalization (1-D) with respect to the original recording data. In the equalization of (1-D), D represents a delay operator for 1 bit, and indicates a process of subtracting 1 bit before data from the currently supplied data.
【００３５】磁気記録系１１で再生され（１−Ｄ）なる
等化が実施された信号はサンプリング用スイッチ手段１
２を介して等化器１３に供給される。等化器１３は磁気
記録系１１から供給された信号に（１＋Ｄ）2 なる等化
が実施される。（１＋Ｄ）2なる等化は（１＋Ｄ）なる
等化を２回実行した等化を表し、（１＋Ｄ）なる等化は
現在供給されているデータに１ビット前のデータを加算
する処理を示す。ここで、記録データには磁気記録系１
１で（１−Ｄ）、等化器１３で（１＋Ｄ）2 なる等化が
実施され、等化器１３の出力としては（１−Ｄ）（１＋
Ｄ）2 なる等化が実施されたことになる。The signal reproduced by the magnetic recording system 11 and equalized by (1-D) is the sampling switch means 1.
It is supplied to the equalizer 13 via 2. The equalizer 13 performs (1 + D) 2 equalization on the signal supplied from the magnetic recording system 11. (1 + D) 2 becomes equalized represents equalization executed twice equalization comprising (1 + D), shows a process of adding 1-bit data before the data are equalized currently supply comprising (1 + D). Here, the recording data includes the magnetic recording system 1
1 equals (1-D), and equalizer 13 equalizes (1 + D) 2 and the output of equalizer 13 is (1-D) (1+
D) 2 equalization has been implemented.
【００３６】等化器１３の出力データは次に等化器１４
に供給される。等化器１４は等化器１３から供給された
データに対して（１−Ｄ）なる等化を実施する。磁気記
録系１１，等化器１３，１４により記録データには（１
−Ｄ）2 （１＋Ｄ）2 ＝〔（１−Ｄ）（１＋Ｄ）〕2 ＝
（１−Ｄ2 ）2 ＝（１−２Ｄ2 ＋Ｄ4 ）なる等化が行な
われる。The output data of the equalizer 13 is then sent to the equalizer 14
Is supplied to. The equalizer 14 performs (1-D) equalization on the data supplied from the equalizer 13. The magnetic recording system 11 and the equalizers 13 and 14 add (1
-D) 2 (1 + D) 2 = [(1-D) (1 + D)] 2 =
An equalization of (1-D 2 ) 2 = (1-2D 2 + D 4 ) is performed.
【００３７】等化器１４の出力信号は検出器１５及びＰ
ＬＬ回路１６に供給される。検出器１５は等化器１４か
らの信号を復号して元の記録データを復元する。The output signal of the equalizer 14 is the detector 15 and P.
It is supplied to the LL circuit 16. The detector 15 decodes the signal from the equalizer 14 to restore the original recorded data.
【００３８】図３に検出器１５の構成図を示す。検出器
１５は切換手段１７，検出器１８，１９より構成され
る。切換手段１７は等化器１４から信号が供給され、供
給された信号をＰＬＬ回路１６からのクロックに応じて
検出器１８，１９に振り分ける。 ＰＬＬ回路１６は等
化器１４から供給された信号に基づいて、クロックの位
相を制御する。ＰＬＬ回路１６のクロックは磁気記録系
１１の出力信号と同期した周波数を有し、スイッチ手段
１２，等化器１３，１４，検出器１５に供給される。ス
イッチ手段１２はＰＬＬ回路１６からのクロックに応じ
てオン・オフし、磁気記録系１１の出力信号をサンプリ
ングし、等化器１３へ情報に応じた信号が供給されるよ
うに制御する。また、等化器１３，１４，検出器１５は
ＰＬＬ回路１６からのクロックに応じてデータの取り込
み遅延等が制御され、等化検出を実施する。FIG. 3 shows a block diagram of the detector 15. The detector 15 comprises a switching means 17 and detectors 18 and 19. The switching means 17 is supplied with a signal from the equalizer 14 and distributes the supplied signal to the detectors 18 and 19 according to the clock from the PLL circuit 16. The PLL circuit 16 controls the phase of the clock based on the signal supplied from the equalizer 14. The clock of the PLL circuit 16 has a frequency synchronized with the output signal of the magnetic recording system 11, and is supplied to the switch means 12, the equalizers 13 and 14, and the detector 15. The switch means 12 is turned on / off according to the clock from the PLL circuit 16, samples the output signal of the magnetic recording system 11, and controls the equalizer 13 to supply a signal according to the information. Further, the equalizers 13 and 14 and the detector 15 are controlled in data acquisition delay and the like according to the clock from the PLL circuit 16 to perform equalization detection.
【００３９】検出器１８，１９は共にＲＯＭ等で構成さ
れており、供給される信号波形に応じたデータのパター
ンにより出力データを決定し、供給された信号に対して
〔１／（１−２Ｄ2 ＋Ｄ4 ）〕なる検出が実施される構
成とされている。このとき、供給される信号波形が上下
のレベルで非対称となることを考慮して、上下レベルの
非対称な波形のパターンに対応して出力データを出力す
るようにデータを記憶されており、従って、上下レベル
の非対称な波形のデータでも確実に出力データが得ら
れ、誤り率を低減できる。Each of the detectors 18 and 19 is composed of a ROM or the like, and determines output data based on a data pattern corresponding to the supplied signal waveform, and [1 / (1-2D 2 + D 4 )] is performed. At this time, considering that the supplied signal waveform is asymmetrical at the upper and lower levels, the data is stored so as to output the output data corresponding to the asymmetrical waveform pattern at the upper and lower levels. It is possible to reliably obtain output data even with asymmetrical waveform data of upper and lower levels, and reduce the error rate.
【００４０】検出器１８，１９の出力データは入力デー
タに対して〔１／（１−２Ｄ2 ＋Ｄ 4 ）〕なる検出が施
されるため、（１−２Ｄ2 ＋Ｄ4 ）なる等化がなされる
たデータに対しては、（１−２Ｄ2 ＋Ｄ4 ）・〔１／
（１−２Ｄ2 ＋Ｄ4 ）〕＝１なる処理が実施される。こ
のとき、検出器１８と検出器１９とは１ビット毎に交互
に検出を行なうため、検出器１８，１９の夫々の出力は
１ビットおきの出力となる。従って、検出器１８，１９
の出力を合成して一つのデータとして出力することによ
り元の記録データが復元される。The output data of the detectors 18 and 19 are the input data.
[1 / (1-2D2+ D Four)]
Therefore, (1-2D2+ DFour) Is equalized
For the data that has been2+ DFour) ・ [1 /
(1-2D2+ DFour)] = 1 is performed. This
, The detector 18 and the detector 19 alternate every 1 bit.
In order to perform the detection, the outputs of the detectors 18 and 19 are
Output is every other bit. Therefore, the detectors 18, 19
By synthesizing the output of
The original recorded data is restored.
【００４１】図４に本発明の一実施例の動作波形図を示
す。同図中、ａは磁気記録系１１に供給される記録デー
タの数値による表示、ｂは記録データの波形図を示す。
記録データはａのハイレベルに相当する波形として磁気
記録系１１に供給される。FIG. 4 shows an operation waveform diagram of one embodiment of the present invention. In the figure, a is a numerical display of the recording data supplied to the magnetic recording system 11, and b is a waveform diagram of the recording data.
The recording data is supplied to the magnetic recording system 11 as a waveform corresponding to the high level of a.
【００４２】記録データｂは磁気記録系１１により（１
−Ｄ）なる等化が施されたものと見なすことができ、信
号Ｃとされる。信号Ｃにおいて、例えば時刻ｔ1 におけ
るデータ“１”は時刻ｔ1 におけるａのデータ“１”か
らその前の時刻ｔ0 のａのデータ“０”を減算したもの
であるから（１−０）で“１”とされる。また時刻ｔ 2
におけるデータ“１”は時刻ｔ2 でのａのデータ“０”
から時刻ｔ1 でのａのデータ“１”を減算したものであ
るから（０−１）で刻ｔ1 で“−１”とされる。以下、
同様な処理が行なわれ、図４に示される記録データａ，
ｂより信号Ｃが得られる。The recording data b is recorded by the magnetic recording system 11 as (1
-D) can be regarded as having been equalized,
Issue C. In the signal C, for example, time t1Oke
The data “1” is the time t1Is the data “1” of a in
Time t before that0Subtracting the data “0” of a
Therefore, it is set to "1" in (1-0). Also at time t 2
The data “1” in is at time t2"0" of data in a
From time t1Is the result of subtracting the data "1" of a in
Since it is (0-1), t1Is set to "-1". Less than,
Similar processing is performed, and the recording data a, shown in FIG.
The signal C is obtained from b.
【００４３】信号Ｃは等化器１３に供給される。等化器
１３では（１＋Ｄ）2 なる等化が実施され、信号ｈとさ
れる。信号ｈにおいて、時刻ｔ1 におけるデータ“１”
は時刻ｔ1 におけるｃのデータ“１”にその前の時刻ｔ
1 のｃのデータ“０”を加算する処理を２回実施するこ
とになるから１回目は（１＋０）で“１”，さらに２回
目で（１＋０）で“１”となる。時刻ｔ2 のデータは時
刻ｔ2 のｃのデータ“−１”にその前の時刻ｔ1 のデー
タ“１”を加算する処理を２回実施するから１回目で−
１＋１で“０”，２回目で０＋１で“１”となる。The signal C is supplied to the equalizer 13. In the equalizer 13, the equalization of (1 + D) 2 is carried out to obtain the signal h. Data “1” at time t 1 in signal h
Is the data “1” of c at the time t 1 and the previous time t
Since the process of adding the data "0" of c of 1 is performed twice, the first time becomes "1" at (1 + 0), and the second time becomes "1" at (1 + 0). Since the data is time t 2 carries out a process of adding the previous time t 1 of the data "1" to data "-1" of c at time t 2 2 times 1 time with -
It becomes "0" at 1 + 1 and becomes "1" at 0 + 1 at the second time.
【００４４】以下、同様な処理の結果図４ｈに実線で示
されるような信号が得られる。Thereafter, as a result of similar processing, a signal shown by a solid line in FIG. 4h is obtained.
【００４５】信号ｈは等化器１４に供給される。等化器
１４では磁気記録系１１で説明したのと同様な（１−
Ｄ）なる等化が実施され、図４に示される信号ｉとされ
る。信号ｉは切換手段１７により１ビット毎に検出器１
８，１９に交互に供給される。このため、検出器１８に
は例えば信号ｉのタイミングで信号が供給され、検出器
１９にはλのタイミングで信号が供給されるものとする
と、検出器１８に供給される信号は図４ｊに実線で示す
ような波形となり、また、検出器１９に供給される信号
は図４ｋに実線で示すような波形となる。The signal h is supplied to the equalizer 14. In the equalizer 14, the same (1-
D) equalization is carried out to obtain the signal i shown in FIG. The signal i is detected by the switching means 17 bit by bit in the detector 1
It is supplied alternately to 8 and 19. Therefore, the detector 18 signal is supplied at the timing of, for example, signal i, when the detector 19 shall signal is supplied at the timing of lambda, the signal supplied to the detector 18 in FIG. 4j The waveform shown by the solid line is obtained, and the signal supplied to the detector 19 has the waveform shown by the solid line in FIG. 4k.
【００４６】検出器１８では信号ｊに対して〔１／（１
−２Ｄ2 ＋Ｄ4 ）〕なる検出が実施され、検出器１９で
は信号ｋに対して〔１／（１−２Ｄ2 ＋Ｄ4 ）〕なる検
出が実施される。検出器１８の出力信号と検出器１９の
出力信号とを合成すると図４ｌに示すようなデータを
得、記録データａが復元される。図５に各方式の規格化
線密度に対するＳ／Ｎ利得特性図を示す。同図中、一点
鎖線はＰＲＭＬ方式、破線はＥＰＲＭＬ方式の特性を示
し、実線は本実施例の特性を示す。In the detector 18, [1 / (1
-2D 2 + D 4 )] is performed, and the detector 19 performs [1 / (1-2D 2 + D 4 )] on the signal k. When the output signal of the detector 18 and the output signal of the detector 19 are combined, data as shown in FIG. 4l is obtained, and the recorded data a is restored. FIG. 5 shows an S / N gain characteristic diagram with respect to the normalized linear density of each system. In the figure, the alternate long and short dash line shows the characteristics of the PRML system, the broken line shows the characteristics of the EPRML system, and the solid line shows the characteristics of this embodiment.
【００４７】図６に規格化線密度の説明図を示す。再生
波形（ローレンツ波形）の半分のレベルの幅が半値幅、
再生波形を再生するためのビットの周期がビット周期と
なる。規格化線密度は〔（半値幅）／（ビット周期）〕
により定義される。FIG. 6 shows an explanatory diagram of the normalized linear density. The half level width of the playback waveform (Lorentz waveform) is the half-value width,
The bit cycle for reproducing the reproduced waveform is the bit cycle. Normalized linear density is [(half width) / (bit period)]
Is defined by
【００４８】図６に示すように本実施例によれば、ＥＰ
ＲＭＬ方式により信号処理が行なえるため、ＰＲＭＬ方
式より高ＳＮ利得化が行なえると共にＰＲ方式同様に２
分割して検出できるため、高速処理が行なえる。According to this embodiment, as shown in FIG. 6, EP
Since the signal processing can be performed by the RML method, the SN gain can be increased as compared with the PRML method, and the same as in the PR method.
Since it can be detected by dividing it, high-speed processing can be performed.
【００４９】このように、本実施例によれば、検出器１
５が〔１／（１−２Ｄ2 ＋Ｄ4 ）〕なる検出となり、偶
数倍の遅延で実現できるため、検出器１８，１９に分割
でき、従って、１ビットおきの処理が行なえ、最も複雑
な処理を必要とする検出器１８，１９の処理を高速化が
実現できるため、全体の処理スピードを向上させること
ができる。As described above, according to this embodiment, the detector 1
5 is detected as [1 / (1-2D 2 + D 4 )] and can be realized with an even delay, so that it can be divided into detectors 18 and 19, and therefore, every other bit can be processed, and the most complicated processing can be performed. Since it is possible to speed up the processing of the detectors 18 and 19 that require the above, it is possible to improve the overall processing speed.
【００５０】また、本実施例によれば、等化器１４によ
り１−Ｄなる処理を施すため、本来の０レベルは確保し
つつも、上下レベルの非対称を補償できる。Further, according to this embodiment, since the equalizer 14 performs the processing of 1-D, it is possible to compensate the asymmetry of the upper and lower levels while ensuring the original 0 level.
【００５１】図７に０レベル補償動作説明図を示す。図
７（Ａ）は等化器１４に供給される信号、図７（Ｂ）は
出力信号を示す。FIG. 7 is a diagram for explaining the 0 level compensation operation. FIG. 7A shows a signal supplied to the equalizer 14, and FIG. 7B shows an output signal.
【００５２】等化器１４では（１−Ｄ）なる等化が実施
される。このため、時刻ｔ1 の信号レベルＬ2 は時刻ｔ
1 における信号レベルＬ1 ，時刻ｔ0 の信号レベルＬ1
を減じた値となり、０レベルはそのままで前後信号レベ
ルの非対称を平均化できる。The equalizer 14 performs equalization (1-D). Therefore, the signal level L 2 at time t 1 is
Signal level L 1 in 1, the signal level at time t 0 L 1
Is obtained by subtracting, and the asymmetry of the front and rear signal levels can be averaged while the 0 level remains unchanged.
【００５３】図８に本発明の第２実施例の構成図を示
す。同図中、図２と同一構成部分には同一符号を付し、
その説明は省略する。FIG. 8 shows a block diagram of the second embodiment of the present invention. In the figure, the same components as those in FIG.
The description is omitted.
【００５４】本実施例は等化器１４の後にトランスバー
サルフィルタ等の線形フィルタ４１を設けることによ
り、磁気記録系１１の再生信号の上下レベルの非対称の
影響を補正したものである。In this embodiment, a linear filter 41 such as a transversal filter is provided after the equalizer 14 to correct the influence of the asymmetry of the upper and lower levels of the reproduction signal of the magnetic recording system 11.
【００５５】本実施例によれば、第１実施例に比べ、さ
らに上下レベル非対称の影響を除去できる。According to this embodiment, the influence of the vertical level asymmetry can be further removed as compared with the first embodiment.
【００５６】[0056]
【発明の効果】上述の如く、本発明によれば、〔１／
（１−２Ｄ2 ＋Ｄ4 ）〕なる検出を２系統に分割して所
定の周期毎に交互に検出できるため、夫々の系統での検
出処理の負担を軽減でき、したがって、全体の処理速度
を上げることができるため、高速化が行なえる等の特長
を有する。As described above, according to the present invention, [1 /
(1-2D 2 + D 4 )] can be divided into two systems and can be detected alternately in every predetermined cycle, so the load of the detection process in each system can be reduced, and therefore the overall processing speed can be increased. Therefore, it has features such as high speed.
【図１】本発明の原理図である。FIG. 1 is a principle diagram of the present invention.
【図２】本発明の第１実施例の構成図である。FIG. 2 is a configuration diagram of a first embodiment of the present invention.
【図３】本発明の第１実施例の検出器の構成図である。FIG. 3 is a configuration diagram of a detector according to the first embodiment of the present invention.
【図４】本発明の第１実施例の動作波形図である。FIG. 4 is an operation waveform diagram of the first embodiment of the present invention.
【図５】本発明の第１実施例の動作特性図である。FIG. 5 is an operational characteristic diagram of the first embodiment of the present invention.
【図６】規格化線密度を説明するための図である。FIG. 6 is a diagram for explaining a normalized linear density.
【図７】本発明の第１実施例の波形補償動作説明図であ
る。FIG. 7 is an explanatory diagram of a waveform compensation operation according to the first embodiment of this invention.
【図８】本発明の第２実施例の構成図である。FIG. 8 is a configuration diagram of a second embodiment of the present invention.
【図９】ＰＲＭＬ方式の磁気記録再生系の構成図であ
る。FIG. 9 is a configuration diagram of a PRML type magnetic recording / reproducing system.
【図１０】ＰＲＭＬ方式の磁気記録再生系の動作波形図
である。FIG. 10 is an operation waveform diagram of a PRML type magnetic recording / reproducing system.
【図１１】ＥＰＲＭＬ方式の磁気記録再生系の構成図で
ある。FIG. 11 is a configuration diagram of an EPRML type magnetic recording / reproducing system.
【図１２】ＭＲヘッドの動作特性図である。FIG. 12 is an operating characteristic diagram of the MR head.
【図１３】０レベル補償動作説明図である。FIG. 13 is an explanatory diagram of 0 level compensation operation.
１ 伝送路 ２ 第１の等化手段 ３ 第２の等化手段 ４ 切換手段 ５ 第１の検出手段 ６ 第２の検出手段 １４ 等化器 ４１ 波形フィルタ 1 transmission line 2 First equalization means 3 Second equalization means 4 switching means 5 First detection means 6 Second detection means 14 Equalizer 41 Waveform filter
Claims (3)
送路（１）上に設けられ、（１−Ｄ）（１＋Ｄ）
2 〔Ｄ：所定周期の遅延演算子〕なる等化を行なう第１
の等化手段（２）を有するデータ伝送システムにおい
て、 前記伝送路（１）上に設けられ、（１−Ｄ）なる等化を
行なう第２の等化手段（３）と、 前記伝送路上の前記第１の等化手段（２）及び前記第２
の等化手段（３）の後に設けられ、前記第１の等化手段
（２）及び前記第２の等化手段（３）で等化された信号
を２系統の伝送路に前記所定の周期毎に交互に供給する
切換手段（４）と、 前記切換手段（４）から前記所定周期毎に交互に信号が
供給される前記２系統の伝送路の一方に設けられ、前記
切換手段（４）から供給される信号に対して、〔１／
（１−２Ｄ2 ＋Ｄ4 ）〕なる検出を行なう第１の検出手
段（５）と、 前記切換手段（４）から前記所定の周期毎に交互に信号
が供給される前記２系統の伝送路の他方に設けられ、前
記切換手段（４）から供給される信号に対して、〔１／
（１−２Ｄ2 ＋Ｄ4 ）〕なる検出を行なう第２の検出手
段（６）とを有し、 前記第１の検出手段（５）により検出された信号と前記
第２の検出手段（６）により検出された信号とを合成す
ることにより前記入力信号を復元することを特徴とする
データ伝送システム。1. A transmission path (1) which is transmitted at a predetermined cycle of an input signal, and is (1-D) (1 + D).
2 [D: Delay operator with predetermined period] First equalization
In the data transmission system having the equalizing means (2), the second equalizing means (3) provided on the transmission path (1) and performing the equalization (1-D), and the equalizing means (2) on the transmission path. The first equalizing means (2) and the second
Is provided after the equalizing means (3), and the signals equalized by the first equalizing means (2) and the second equalizing means (3) are transmitted to the two transmission lines in the predetermined cycle. Switching means (4) for alternately supplying each of the switching means and one of the transmission paths of the two systems to which signals are alternately supplied from the switching means (4) at the predetermined cycle, and the switching means (4) For the signal supplied from [1 /
(1-2D 2 + D 4 )] of the first detection means (5) for performing detection and the transmission paths of the two systems to which signals are alternately supplied from the switching means (4) at the predetermined cycle. For the signal supplied from the switching means (4) provided on the other side, [1 /
(1-2D 2 + D 4 )] and a second detection means (6) for performing the detection, the signal detected by the first detection means (5) and the second detection means (6). A data transmission system, characterized in that the input signal is restored by synthesizing with the signal detected by.
は上下レベルの非対称な波形に応じたパターンが記憶さ
れ、該パターンに応じたデータを変換し、等化を行なう
ことを特徴とする請求項１記載のデータ伝送システム。2. The first and second detecting means (5, 6)
The data transmission system according to claim 1, wherein a pattern corresponding to an asymmetrical waveform of the upper and lower levels is stored, and data corresponding to the pattern is converted to perform equalization.
の遅延演算子〕なる等化処理が行われたデータを伝送す
るデータ伝送システムであって、 前記データに（１−Ｄ）なる等化処理を行う処理手段
と、 前記処理手段により処理された信号の 上下レベルの非対
称を補正する線形フィルタを有することを特徴とするデ
ータ伝送システム。3.(1-D) (1 + D) Two [D: predetermined cycle
Of the delay operator] is transmitted
Data transmission system, Processing means for performing (1-D) equalization processing on the data
When, Of the signal processed by the processing means Upper and lower level unpaired
A digital filter characterized by having a linear filter for correcting
Data transmission system.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25085993A JP3410781B2 (en) | 1993-10-06 | 1993-10-06 | Data transmission system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25085993A JP3410781B2 (en) | 1993-10-06 | 1993-10-06 | Data transmission system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07107124A JPH07107124A (en) | 1995-04-21 |
| JP3410781B2 true JP3410781B2 (en) | 2003-05-26 |
Family
ID=17214076
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25085993A Expired - Fee Related JP3410781B2 (en) | 1993-10-06 | 1993-10-06 | Data transmission system |
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| Country | Link |
|---|---|
| JP (1) | JP3410781B2 (en) |
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| JPWO2003012789A1 (en) | 2001-07-27 | 2004-11-25 | 富士通株式会社 | Signal processing method, signal processing circuit and information recording / reproducing device |
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1993
- 1993-10-06 JP JP25085993A patent/JP3410781B2/en not_active Expired - Fee Related
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|---|---|
| JPH07107124A (en) | 1995-04-21 |
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