JP3397201B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP3397201B2 JP3397201B2 JP2000366693A JP2000366693A JP3397201B2 JP 3397201 B2 JP3397201 B2 JP 3397201B2 JP 2000366693 A JP2000366693 A JP 2000366693A JP 2000366693 A JP2000366693 A JP 2000366693A JP 3397201 B2 JP3397201 B2 JP 3397201B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- carrier
- semiconductor carrier
- semiconductor device
- semiconductor element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
Description
【発明の詳細な説明】Detailed Description of the Invention
【０００１】[0001]
【発明の属する技術分野】本発明は回路構成された半導
体キャリアに対して半導体素子がフェースダウンで実装
されたタイプの半導体装置に関するものであり、特にプ
リント基板と半導体装置との逆マウントを防止した半導
体装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device of a type in which a semiconductor element is mounted face down on a semiconductor carrier having a circuit structure, and in particular, reverse mounting of a printed circuit board and a semiconductor device is prevented. The present invention relates to a semiconductor device.
【０００２】[0002]
【従来の技術】近年、半導体素子を回路基板に実装する
方法として、フリップチップ実装工法を用いたパッケー
ジの検討がなされている。2. Description of the Related Art Recently, as a method for mounting a semiconductor element on a circuit board, a package using a flip chip mounting method has been studied.
【０００３】以下、従来の半導体装置について図面を参
照しながら説明する。図１０はチップサイズパッケージ
（ＣＳＰ）と呼ばれる従来の半導体装置の平面図、図１
１はその底面図、図１２は図１０のＡ−Ａ１線に沿った
断面図である。A conventional semiconductor device will be described below with reference to the drawings. FIG. 10 is a plan view of a conventional semiconductor device called a chip size package (CSP), FIG.
1 is a bottom view thereof, and FIG. 12 is a sectional view taken along the line AA1 of FIG.
【０００４】図示するように、表面の電極パッド１にＡ
ｕバンプ２の形成された半導体素子３が、フェースダウ
ン方式、すなわち表面側を下向きにして多層回路基板で
ある略正方形の半導体キャリア４に接合されている。半
導体キャリア４の上面には半導体素子３との導通のため
の複数の電極５が形成されており、電極５と半導体素子
３上に形成された二段形状のＡｕバンプ２とが導電性接
着剤６で接合されている。そして、接合された半導体素
子３と半導体キャリア４との間の隙間と、半導体素子３
の端部がエポキシ系封止樹脂７によって充填被覆されて
いる。半導体素子３の端部と半導体キャリア４にかかる
部分は、封止樹脂７のフィレット部である。また半導体
キャリア４上の電極５は、配線パターン８により半導体
キャリア４表面で引き回され、ビア９により半導体キャ
リア４の裏面の外部電極端子１０に導通されている。な
お、半導体キャリア４表面の配線パターン８は、ビア９
により積層基板である半導体キャリア４の内部で引き回
されて、図１１に示すように、半導体キャリア４の裏面
で外部電極端子１０の配列を構成する。As shown in FIG.
The semiconductor element 3 on which the u bump 2 is formed is bonded to the semiconductor carrier 4 having a substantially square shape, which is a multilayer circuit board, in a face-down method, that is, with the front surface side facing downward. A plurality of electrodes 5 for conduction with the semiconductor element 3 are formed on the upper surface of the semiconductor carrier 4, and the electrodes 5 and the two-stepped Au bumps 2 formed on the semiconductor element 3 are made of a conductive adhesive. It is joined at 6. The gap between the bonded semiconductor element 3 and the semiconductor carrier 4 and the semiconductor element 3
The end portion of is filled and covered with the epoxy sealing resin 7. The end portion of the semiconductor element 3 and the portion covering the semiconductor carrier 4 are fillet portions of the sealing resin 7. The electrode 5 on the semiconductor carrier 4 is laid out on the surface of the semiconductor carrier 4 by the wiring pattern 8 and is electrically connected to the external electrode terminal 10 on the back surface of the semiconductor carrier 4 by the via 9. The wiring pattern 8 on the surface of the semiconductor carrier 4 has a via 9
Is routed inside the semiconductor carrier 4, which is a laminated substrate, to form an array of the external electrode terminals 10 on the back surface of the semiconductor carrier 4, as shown in FIG.
【０００５】そして従来の半導体装置では、平面形状が
略正方形状の半導体キャリア４の左上、右上、右下に位
置認識のための認識マーク１１ａ，１１ｂ，１１ｃが形
成されており、プリント基板等への実装の際は、この認
識マーク１１ａ，１１ｃによって上下左右の位置認識を
し、それにもとづいて実装していた。In the conventional semiconductor device, the recognition marks 11a, 11b and 11c for position recognition are formed on the upper left, upper right and lower right of the semiconductor carrier 4 having a substantially square planar shape, and the recognition marks 11a, 11b and 11c are formed on a printed circuit board or the like. At the time of mounting, the recognition marks 11a and 11c are used to recognize the vertical and horizontal positions, and the mounting is performed based on the recognition.
【０００６】次に従来の半導体装置の製造方法について
図面を参照しながら説明する。図１３〜図１７は従来の
半導体装置の製造方法を工程順に示した断面図である。
なお図１６は半導体キャリアを示す平面図である。Next, a conventional method of manufacturing a semiconductor device will be described with reference to the drawings. 13 to 17 are sectional views showing a conventional method of manufacturing a semiconductor device in the order of steps.
16 is a plan view showing the semiconductor carrier.
【０００７】まず図１３に示すように、半導体素子３の
電極パッド１上にワイヤーボンディング法（ボールボン
ディング法）を用いて、Ａｕバンプ２（Ａｕ二段突起）
を形成する。この方法はＡｕワイヤー先端に形成したボ
ールをアルミニウム電極に熱圧接することにより、二段
突起の下段部を形成し（第１ボンド）、さらにワイヤー
ボンダーのキャピラリを移動させることにより形成した
Ａｕワイヤーループをもって二段突起の上段部を形成す
る（第２ボンド）。この状態においては、Ａｕ二段突起
の高さが均一でなくかつ頭頂部の平坦性にも欠けている
ために、Ａｕ二段突起を加圧することにより高さの均一
化と頭頂部の平坦化、いわゆるレベリングを行なう。First, as shown in FIG. 13, Au bumps 2 (Au two-step protrusions) are formed on the electrode pads 1 of the semiconductor element 3 by a wire bonding method (ball bonding method).
To form. In this method, the ball formed at the tip of the Au wire is thermally pressed against the aluminum electrode to form the lower step portion of the two-step protrusion (first bond), and further the Au wire loop formed by moving the capillary of the wire bonder. To form the upper step portion of the two-step protrusion (second bond). In this state, the height of the Au two-step protrusion is not uniform and the flatness of the crown is also lacking. Therefore, by pressing the Au two-step protrusion, the height is made uniform and the crown is flattened. , So-called leveling.
【０００８】次に図１４に示すように、半導体素子３上
のＡｕバンプ２に導電性接着剤６を供給する。導電性接
着剤６としては、前述と同様に信頼性、熱応力などを考
慮してたとえばバインダーとしてエポキシレジン、導体
フィラーとしてＡｇ−Ｐｄ合金によりなる接着剤を用い
ている。Next, as shown in FIG. 14, a conductive adhesive 6 is supplied to the Au bumps 2 on the semiconductor element 3. As the conductive adhesive 6, an adhesive made of, for example, an epoxy resin as a binder and an Ag-Pd alloy as a conductor filler is used in consideration of reliability, thermal stress and the like as described above.
【０００９】次に図１５に示すように、半導体素子３の
表面を下向きにして実装する方法であるフリップチップ
方式によって、半導体素子３上の導電性接着剤６が供給
されたＡｕバンプ２と、表面の電極５が配線パターン８
により表面で引き回され、ビア９によりその内部で引き
回されてその裏面の外部電極端子１０に導通された半導
体キャリア４の電極５とを位置精度よく合わせて接合し
た後、一定の温度にて熱硬化させる。この半導体素子３
と半導体キャリア４との接合は、図１６の半導体キャリ
ア４の概略平面図に示すように、半導体キャリア４の左
上、右上、右下の認識マーク１１ａ，１１ｂ，１１ｃの
うち、左上、右下の認識マーク１１ａ，１１ｃを認識し
て行なうもので、左上、右下に認識マークが存在するか
どうかにより行なうものである。Next, as shown in FIG. 15, an Au bump 2 to which the conductive adhesive 6 is supplied on the semiconductor element 3 is provided by a flip chip method, which is a method of mounting with the surface of the semiconductor element 3 facing downward. Surface electrode 5 is wiring pattern 8
After that, the electrode 5 of the semiconductor carrier 4 which is routed on the front side by the via 9 and routed inside by the via 9 and conducted to the external electrode terminal 10 on the back side thereof is aligned with high accuracy and joined, and then at a constant temperature. Heat cure. This semiconductor element 3
As shown in the schematic plan view of the semiconductor carrier 4 of FIG. 16, the semiconductor carrier 4 and the semiconductor carrier 4 are bonded to each other by recognizing the upper left, lower right, and lower right of the recognition marks 11a, 11b, 11c on the upper left, upper right, lower right of the semiconductor carrier 4. It is performed by recognizing the recognition marks 11a and 11c, and is performed depending on whether or not the recognition marks are present at the upper left and lower right.
【００１０】そして図１７に示すように、エポキシ系封
止樹脂７を半導体素子３の周辺端部と、半導体素子３と
半導体キャリア４との間に形成された隙間に注入し、一
定の温度にて封止樹脂を硬化させ樹脂モールドし、半導
体装置を完成させていた。Then, as shown in FIG. 17, the epoxy type encapsulating resin 7 is injected into the peripheral edge portion of the semiconductor element 3 and the gap formed between the semiconductor element 3 and the semiconductor carrier 4 to keep a constant temperature. Then, the encapsulating resin was cured and resin-molded to complete the semiconductor device.
【００１１】[0011]
【発明が解決しようとする課題】しかしながら従来は、
半導体キャリア４と半導体素子３との接合工程時の認識
は、自動工程の省時間化のため、半導体キャリア４の左
上、右上、右下の認識マーク１１ａ，１１ｂ，１１ｃの
うち、左上、右下の認識マーク１１ａ，１１ｃの存在を
認識して行なうものであり、半導体キャリア４と半導体
素子３との接合工程の初期の段階で、図１８の半導体キ
ャリア４の概略平面図に示すように、半導体キャリア４
のセッティングを１８０度間違えてセットした場合で
も、対角上の２点の認識であるので、そのまま正常認識
し、半導体素子３を接合すると逆マウントになってしま
うという課題があった。また同様に完成した半導体装置
においても、プリント基板等への実装時は、半導体キャ
リア４の１１ａ，１１ｃの対角上の２点の認識であるの
で、セッティングを１８０度間違えてセットした場合で
も、そのまま正常と認識し、逆マウントになってしまう
おそれがあった。However, in the prior art,
The recognition at the time of joining the semiconductor carrier 4 and the semiconductor element 3 is performed in order to save time in an automatic process, and the upper left, lower right, among the recognition marks 11a, 11b, 11c at the upper left, upper right, lower right of the semiconductor carrier 4 are recognized. Is performed by recognizing the existence of the recognition marks 11a and 11c of the semiconductor carrier 4. As shown in the schematic plan view of the semiconductor carrier 4 in FIG. Carrier 4
Even if the setting is made by mistake by 180 degrees, since two points on the diagonal are recognized, there is a problem that if the semiconductor elements 3 are directly recognized and the semiconductor element 3 is joined, the mount becomes reverse. Similarly, in a similarly completed semiconductor device, when mounted on a printed circuit board or the like, since two points on the diagonal of 11a and 11c of the semiconductor carrier 4 are recognized, even if the setting is mistaken by 180 degrees, There was a risk that it would be recognized as normal and the mount would be reversed.
【００１２】本発明は、このような不都合を解決するも
のであって、半導体装置をプリント基板等へ実装する
際、平面形状が略正方形状の半導体キャリアを正しく認
識して、逆マウントを防止することができる半導体装置
を提供することを目的とする。The present invention solves such a problem, and when mounting a semiconductor device on a printed circuit board or the like, a semiconductor carrier having a substantially square planar shape is correctly recognized to prevent reverse mounting. It is an object to provide a semiconductor device that can be manufactured.
【００１３】[0013]
【課題を解決するための手段】従来の課題を解決するた
め本発明における半導体装置は、上面に複数の電極と、
その電極を引き回す配線パターンと、底面に配列され、
上面の電極と導通した外部電極端子とを有した半導体キ
ャリア、その半導体キャリア上面にバンプ電極を介して
接合された半導体素子、ならびに、半導体素子と半導体
キャリアとの間隔と、前記半導体素子周辺端部とを充填
被覆している樹脂からなり、前記半導体キャリアは四つ
の角部のうちの三つの角部に円形の認識マークを有し、
対角線上の二つの認識マークのうちのどちらかの一つの
認識マークが他の認識マークよりも寸法の大きい認識マ
ークである。この認識マークの付設は、半導体キャリア
が略正方形状である場合に特に効果がある。In order to solve the conventional problems, a semiconductor device according to the present invention has a plurality of electrodes on the upper surface,
Arranged on the bottom with the wiring pattern that draws the electrode,
A semiconductor carrier having an upper surface electrode and an external electrode terminal that is electrically connected, a semiconductor element bonded to the upper surface of the semiconductor carrier via a bump electrode, a gap between the semiconductor element and the semiconductor carrier, and a peripheral edge portion of the semiconductor element. And filling
It consists of a resin coating, and the semiconductor carrier has four
Has a circular recognition mark at three corners of the
One of the two recognition marks on the diagonal
A recognition mark whose recognition mark is larger than other recognition marks.
It's ark . The provision of the recognition mark is particularly effective when the semiconductor carrier has a substantially square shape.
【００１４】この半導体装置では、半導体キャリアは四
つの角部のうちの三つの角部に円形の認識マークを有
し、対角線上の二つの認識マークのうちのどちらかの一
つの認識マークが他の認識マークよりも寸法の大きい認
識マークであるので、人為的ミスにより半導体キャリア
の方向を１８０度間違えて実装装置にセットした場合で
も、確実に１８０度方向が逆になっていることが認識で
きるので、その逆マウントが防止される。そして、この
認識マークは半導体キャリアが略正方形状である場合に
特に効果がある。In this semiconductor device, four semiconductor carriers are used.
There are circular recognition marks on three of the three corners.
One of the two recognition marks on the diagonal
One recognition mark has a larger dimension than the other recognition mark.
Since in identification mark, by human error even when set in the direction of the semiconductor carrier to the mounting device by mistake 180 degrees, since it recognized that securely 180 degree direction is reversed, the opposite mount is prevented It The recognition mark is particularly effective when the semiconductor carrier has a substantially square shape.
【００１５】[0015]
【発明の実施の形態】以下、本発明の実施の形態につい
て図面を参照しながら説明する。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.
【００１６】図１は本実施の形態における半導体装置の
平面図、図２はその底面図、図３は図１のＡ−Ａ１線に
沿った断面図である。FIG. 1 is a plan view of the semiconductor device according to the present embodiment, FIG. 2 is a bottom view thereof, and FIG. 3 is a sectional view taken along line AA1 of FIG.
【００１７】図示するように、表面の電極パッド１にＡ
ｕバンプ２の形成された半導体素子３が、フェースダウ
ン方式、すなわち表面側を下にして多層回路基板である
半導体キャリア４に接合されている。その半導体キャリ
ア４の上面には半導体素子３との導通のための複数の電
極５が形成されており、その電極５と半導体素子３上に
形成された二段形状のＡｕバンプ２とが導電性接着剤６
で接合されている。そして接合された半導体素子３と半
導体キャリア４との間の隙間と、半導体素子３の端部は
エポキシ系の封止樹脂７により充填被覆されている。半
導体素子３の端部と半導体キャリア４にかかる部分は、
封止樹脂７のフィレット部である。また半導体キャリア
４上の電極５は、配線パターン８により半導体キャリア
４表面で引き回され、ビア９により半導体キャリア４の
裏面の外部電極端子１０に導通されている。なお、半導
体キャリア４表面の配線パターン８は、ビア９により積
層基板である半導体キャリア４の内部で引き回されて、
図２に示すように、半導体キャリア４の裏面で外部電極
端子１０の配列を構成する。As shown in FIG.
The semiconductor element 3 on which the u bump 2 is formed is bonded to the semiconductor carrier 4 which is a multilayer circuit board with the face down method, that is, with the front surface side facing down. A plurality of electrodes 5 for electrical connection with the semiconductor element 3 are formed on the upper surface of the semiconductor carrier 4, and the electrodes 5 and the two-stepped Au bumps 2 formed on the semiconductor element 3 are electrically conductive. Adhesive 6
Are joined together. The gap between the joined semiconductor element 3 and the semiconductor carrier 4 and the end of the semiconductor element 3 are filled and covered with an epoxy-based sealing resin 7. The end portion of the semiconductor element 3 and the portion that covers the semiconductor carrier 4 are
It is a fillet portion of the sealing resin 7. The electrode 5 on the semiconductor carrier 4 is laid out on the surface of the semiconductor carrier 4 by the wiring pattern 8 and is electrically connected to the external electrode terminal 10 on the back surface of the semiconductor carrier 4 by the via 9. The wiring pattern 8 on the surface of the semiconductor carrier 4 is routed inside the semiconductor carrier 4 which is a laminated substrate by the via 9,
As shown in FIG. 2, an array of external electrode terminals 10 is formed on the back surface of the semiconductor carrier 4.
【００１８】そして本実施の形態では、図１に示すよう
に、平面形状が略正方形状の半導体キャリア４の左上、
右上、右下に位置認識のための認識マーク１２ａ，１２
ｂ，１２ｃが形成されており、プリント基板等への実装
の際、この認識マーク１２ａ，１２ｃにもとづいて上下
左右の位置認識を行なってから、実装する。これら認識
マーク１２ａ，１２ｃのうち、認識マーク１２ａは認識
マーク１２ｃと形状が異なり、認識マーク１２ｃよりも
大きい円形のマークとしている。In the present embodiment, as shown in FIG. 1, the upper left of the semiconductor carrier 4 having a substantially square planar shape,
Recognition marks 12a, 12 for position recognition are provided on the upper right and lower right.
b and 12c are formed, and when mounted on a printed circuit board or the like, the vertical and horizontal positions are recognized based on the recognition marks 12a and 12c, and then mounted. Of these recognition marks 12a and 12c, the recognition mark 12a is different from the recognition mark 12c in shape, and is a circular mark larger than the recognition mark 12c.
【００１９】本実施の形態のように、認識マーク１２ａ
を認識マーク１２ｃよりも寸法の大きいマークとするこ
とにより、プリント基板等へ実装する際、半導体キャリ
ア４の方向を１８０度間違えてセットした場合でも、実
装装置は確実に１８０度方向が逆になっていることを認
識するので、逆マウントを防止することができる。As in the present embodiment, the recognition mark 12a
By making the mark larger than the recognition mark 12c, even when the semiconductor carrier 4 is mounted on a printed circuit board or the like in the wrong direction by 180 degrees, the mounting device is surely reversed in the 180 degree direction. It is possible to prevent reverse mounting.
【００２０】次に半導体装置の製造方法の実施の形態に
ついて、図面を参照しながら説明する。図４〜図９は本
実施の形態を工程順に示した図である。なお図７，図８
は半導体キャリアを示す平面図である。Next, an embodiment of a method of manufacturing a semiconductor device will be described with reference to the drawings. 4 to 9 are diagrams showing the present embodiment in the order of steps. 7 and 8
FIG. 4 is a plan view showing a semiconductor carrier.
【００２１】まず図４に示すように、半導体素子３の電
極パッド１上にワイヤーボンディング法（ボールボンデ
ィング法）を用いて、Ａｕバンプ２（Ａｕ二段突起）を
形成する。この方法はＡｕワイヤー先端に形成したボー
ルをアルミニウム電極に熱圧接することにより、二段突
起の下段部を形成し（第１ボンド）、さらにワイヤーボ
ンダーのキャピラリを移動させることにより形成したＡ
ｕワイヤーループをもって二段突起の上段部を形成する
（第２ボンド）。前記状態においては、Ａｕ二段突起の
高さは均一でなくかつ頭頂部の平坦性にも欠けているた
めにＡｕ二段突起を加圧することにより高さの均一化と
頭頂部の平坦化、いわゆるレベリングを行なう。First, as shown in FIG. 4, Au bumps 2 (Au two-step projections) are formed on the electrode pads 1 of the semiconductor element 3 by the wire bonding method (ball bonding method). In this method, the ball formed at the tip of the Au wire is thermally pressed against the aluminum electrode to form the lower step portion of the two-step protrusion (first bond), and further the capillary of the wire bonder is moved to form A.
The upper step portion of the two-step projection is formed with the u wire loop (second bond). In the above state, since the height of the Au two-step protrusion is not uniform and lacks the flatness of the crown, the Au two-step protrusion is pressed to make the height uniform and the crown flat, Performs so-called leveling.
【００２２】次に図５に示すように、半導体素子３上の
Ａｕバンプ２に導電性接着剤６を供給する。導電性接着
剤６としては、前記同様に信頼性、熱応力などを考慮し
て、たとえばバインダーとしてエポキシレジン、導体フ
ィラーとしてＡｇ−Ｐｄ合金によりなる接着剤を用いて
いる。Next, as shown in FIG. 5, the conductive adhesive 6 is supplied to the Au bumps 2 on the semiconductor element 3. As the electrically conductive adhesive 6, in consideration of reliability, thermal stress, etc., as described above, an adhesive made of, for example, an epoxy resin as a binder and an Ag-Pd alloy as a conductor filler is used.
【００２３】次に図６に示すように、半導体素子３の表
面を下にして実装する方法であるフリップチップ方式に
よって、半導体素子３上の導電性接着剤６が供給された
Ａｕバンプ２と、表面の電極５が配線パターン８により
表面で引き回され、ビア９によりその内部で引き回され
てその裏面の外部電極端子１０に導通された半導体キャ
リア４の前記電極５とを位置精度よく合わせて接合した
後、一定の温度にて熱硬化させる。Next, as shown in FIG. 6, an Au bump 2 to which the conductive adhesive 6 is supplied on the semiconductor element 3 is provided by a flip chip method, which is a method of mounting the semiconductor element 3 with the surface thereof facing down. The electrode 5 on the front surface is routed by the wiring pattern 8 on the front side, is routed inside by the via 9 and is aligned with the electrode 5 of the semiconductor carrier 4 electrically connected to the external electrode terminal 10 on the back side with high positional accuracy. After joining, they are thermoset at a constant temperature.
【００２４】この半導体素子３と半導体キャリア４との
接合は、図７の半導体キャリア４の概略平面図に示すよ
うに、半導体キャリア４の左上、右上、右下の認識マー
ク１２ａ，１２ｂ，１２ｃのうち、左上、右下の認識マ
ーク１２ａ，１２ｃを認識して行なうもので、左上、右
下に認識マークが存在するかどうかにより行なう。この
工程では、半導体キャリア４に付された認識マーク１２
ａ，１２ｃにおいて、１２ａの方を１２ｃよりも大きく
したので、初期の段階で、図８の半導体キャリア４の概
略平面図に示すように、人為的ミスにより半導体キャリ
ア４のセッティングを１８０度間違えてセットした場合
でも、マウンター（実装装置）は、半導体キャリア４の
方向が１８０度ズレていることを正しく認識し、マウン
ター停止等のエラーを発生させ、半導体素子３の逆マウ
ントを防止することができる。As shown in the schematic plan view of the semiconductor carrier 4 of FIG. 7, the semiconductor element 3 and the semiconductor carrier 4 are joined to each other by the recognition marks 12a, 12b, 12c on the upper left, upper right and lower right of the semiconductor carrier 4. Among them, the upper left and lower right recognition marks 12a and 12c are recognized and performed, and it is performed depending on whether the upper left and lower right recognition marks exist. In this step, the recognition mark 12 attached to the semiconductor carrier 4
In a and 12c, since 12a is made larger than 12c, in the initial stage, as shown in the schematic plan view of the semiconductor carrier 4 in FIG. Even when set, the mounter (mounting device) can correctly recognize that the direction of the semiconductor carrier 4 is shifted by 180 degrees, generate an error such as a stop of the mounter, and prevent the semiconductor element 3 from being reversely mounted. .
【００２５】そして図９に示すように、エポキシ系の封
止樹脂７を半導体素子３の周辺端部と、半導体素子３と
半導体キャリア４との間に形成された隙間に注入し、一
定の温度にて封止樹脂を硬化させ樹脂モールドし、半導
体装置を完成させていた。Then, as shown in FIG. 9, epoxy-based encapsulating resin 7 is injected into the peripheral edge portion of the semiconductor element 3 and a gap formed between the semiconductor element 3 and the semiconductor carrier 4 to keep a constant temperature. Then, the sealing resin was cured and resin-molded to complete the semiconductor device.
【００２６】次に参考として、本実施の形態で使用した
半導体キャリア４の作製方法について説明する。まずセ
ラミック粉末をガラス粉末と溶剤と共に混合ミルに投入
し、回転混合粉砕を行なう。さらに有機バインダーを添
加しさらに混合する。このセラミック粉末は通常アルミ
ナを主体とするが特に熱伝導性を向上させるために窒化
アルミニウム（ＡｌＮ）、炭化珪素（ＳｉＣ）等の粉末
も添加する。十分混合を行なった後、得られる泥しょ
う、いわゆるスラリーはグリーンシート成型のために搬
送シート上に任意の厚みで塗布される。厚みの調整はド
クターブレード法等を用いる。搬送シート上のスラリー
は、赤外線および熱風を用いてその溶剤を乾燥すること
により、弾力性に富み導電ペースト印刷時のペースト溶
剤の浸透性にすぐれたグリーンシートとなる。このグリ
ーンシートに対して位置合わせ手法として配線ルール２
００μｍ以上の場合には、グリーンシートに直接ガイド
穴を設け、２００μｍ未満の場合には、ガイド穴を有し
た保持枠に張り付ける。次にグリーンシートの表裏の電
気的導通が必要な部分に機械的加工法にて穴を設ける。
この穴に印刷法にてＣｕ粉末を主成分とした導電性ペー
ストを充填する。次にグリーンシート表面に必要な回路
を印刷した後乾燥を行い適当な荷重にて印刷された回路
をグリーンシート中に埋没させる。この目的は回路が印
刷されたグリーンシート表面を平坦にすることにより、
次の工程である積層工程における積層不良、いわゆるデ
ラミネーションを防止するためである。積層工程におい
ては、グリーンシートに設けられたガイド穴もしくは保
持枠のガイド穴により精度よく積層されたグリーンシー
トを加圧することにより強固に接着する。こうして完成
したセラミックキャリアの背面に形成された格子状電極
にＳｎ−Ｐｂの共晶はんだクリームを塗布する。そして
整列治具を用いて高融点はんだボールを塗布されたはん
だクリームに供給した後、リフロー炉等を用いて加熱溶
融することによりはんだ突起バンプである外部電極端子
を形成し、半導体キャリア４を形成する。なお、認識マ
ーク１２の形成は、マウンターに設けられている認識装
置によって識別可能なインクなどの材料により形成す
る。Next, as a reference, a method of manufacturing the semiconductor carrier 4 used in the present embodiment will be described. First, ceramic powder is put into a mixing mill together with glass powder and a solvent, and rotary mixing and pulverization are performed. Further, an organic binder is added and further mixed. This ceramic powder is usually composed mainly of alumina, but powders of aluminum nitride (AlN), silicon carbide (SiC), etc. are also added to improve the thermal conductivity. After thorough mixing, the obtained sludge, so-called slurry, is applied to a conveying sheet in an arbitrary thickness for forming a green sheet. A doctor blade method or the like is used to adjust the thickness. The slurry on the carrier sheet is dried with infrared rays and hot air to dry the solvent, and becomes a green sheet having excellent elasticity and excellent permeability of the paste solvent at the time of printing the conductive paste. Wiring rule 2 as an alignment method for this green sheet
When the thickness is 00 μm or more, the green sheet is directly provided with a guide hole, and when the thickness is less than 200 μm, the green sheet is attached to the holding frame having the guide hole. Next, holes are formed by mechanical processing in the front and back portions of the green sheet where electrical conduction is required.
The hole is filled with a conductive paste containing Cu powder as a main component by a printing method. Next, after printing a necessary circuit on the surface of the green sheet and drying, the printed circuit is embedded in the green sheet with an appropriate load. The purpose of this is to flatten the surface of the green sheet on which the circuit is printed,
This is to prevent stacking failure, so-called delamination, in the stacking step which is the next step. In the laminating step, the laminated green sheets are accurately pressed by the guide holes provided in the green sheet or the guide holes of the holding frame to firmly bond the green sheets. Sn-Pb eutectic solder cream is applied to the grid-like electrodes formed on the back surface of the thus completed ceramic carrier. Then, a high melting point solder ball is supplied to the coated solder cream using an alignment jig, and then heated and melted using a reflow furnace or the like to form an external electrode terminal which is a solder bump bump, thereby forming a semiconductor carrier 4. To do. The recognition mark 12 is formed of a material such as ink that can be recognized by a recognition device provided on the mounter.
【００２７】以上、本発明の実施の形態の半導体装置に
よれば、半導体キャリア４は、認識マーク１２ａを認識
マーク１２ｃよりも大きくして有しており、プリント基
板等へ実装する際、半導体キャリア４の方向を１８０度
間違えてセットした場合でも、実装装置は確実に１８０
度方向が逆になっていることを認識するので、逆マウン
トを防止することができる。As described above, according to the semiconductor device of the embodiment of the present invention, the semiconductor carrier 4 has the recognition mark 12a larger than the recognition mark 12c, and the semiconductor carrier 4 is mounted on a printed circuit board or the like. Even if the direction 4 is set 180 degrees incorrectly, the mounting device is
Recognizing that the directions are reversed, it is possible to prevent reverse mounting.
【００２８】また本発明の実施の形態の方法によれば、
特に半導体キャリア４と半導体素子３との接合工程にお
いて、半導体キャリア４の方向認識を半導体キャリア４
の対角に設けた認識マークにもとづいて行なうものであ
り、半導体キャリア４の左上の認識マーク１２ａと右下
の認識マーク１２ｃとの形状を両者で異なるように形成
し、マウンターに１８０度方向を間違えてセットした場
合でも、間違いを確実に認識することができ、半導体キ
ャリア４に半導体素子３が逆マウントされることを防止
することができる。According to the method of the embodiment of the present invention,
In particular, in the process of joining the semiconductor carrier 4 and the semiconductor element 3, the direction of the semiconductor carrier 4 is recognized by the semiconductor carrier 4.
This is done based on the recognition marks provided on the diagonal of the carrier carrier 4. The upper left recognition mark 12a of the semiconductor carrier 4 and the lower right recognition mark 12c of the semiconductor carrier 4 are formed to have different shapes, and the mounter is oriented at 180 degrees. Even when they are set by mistake, the mistake can be surely recognized and the semiconductor element 3 can be prevented from being reverse-mounted on the semiconductor carrier 4.
【００２９】[0029]
【発明の効果】本発明にかかる半導体装置によれば、平
面形状が略正方形状の半導体キャリアが、他と異なる形
状、色などの認識マークを有しており、プリント基板等
へ実装する際、半導体キャリアの方向を１８０度間違え
てセットした場合でも、実装装置は確実に１８０度方向
が逆になっていることを認識できるので、逆マウントを
防止できるものである。According to the semiconductor device of the present invention, the semiconductor carrier having a substantially square planar shape has recognition marks of different shapes, colors, etc., and when mounted on a printed circuit board or the like, Even if the semiconductor carrier is set in the wrong direction by 180 degrees, the mounting apparatus can surely recognize that the direction is 180 degrees reversed, so that reverse mounting can be prevented.
【００３０】また、半導体キャリアと半導体素子との接
合工程において、半導体キャリアの方向認識を半導体キ
ャリアの対角に設けた認識マークにより行なうものであ
り、半導体キャリアの左上の認識マークと右下の認識マ
ークとの形状を両者で異なるように形成し、人為的ミス
でマウンターに１８０度方向を間違えてセットした場合
でも、間違いを確実に認識することができ、半導体キャ
リアに半導体素子が逆マウントされることを防止するこ
とができる。Further, in the step of joining the semiconductor carrier and the semiconductor element, the direction of the semiconductor carrier is recognized by the recognition mark provided on the diagonal of the semiconductor carrier. The recognition mark at the upper left and the recognition at the lower right of the semiconductor carrier. Even if the mark and the mark are formed so that they are different from each other and are set in the mounter in the wrong direction by 180 degrees due to human error, the mistake can be surely recognized and the semiconductor element is reversely mounted on the semiconductor carrier. Can be prevented.
【図１】本発明の半導体装置の実施の形態の平面図FIG. 1 is a plan view of an embodiment of a semiconductor device of the present invention.
【図２】本発明の半導体装置の実施の形態の底面図FIG. 2 is a bottom view of the embodiment of the semiconductor device of the present invention.
【図３】本発明の半導体装置の実施の形態の断面図FIG. 3 is a sectional view of an embodiment of a semiconductor device of the present invention.
【図４】本発明の半導体装置の製造方法の実施の形態を
説明するための工程断面図FIG. 4 is a process sectional view for explaining the embodiment of the method for manufacturing the semiconductor device of the present invention.
【図５】本発明の半導体装置の製造方法の実施の形態を
説明するための工程断面図FIG. 5 is a process sectional view for explaining an embodiment of the method for manufacturing a semiconductor device of the present invention.
【図６】本発明の半導体装置の製造方法の実施の形態を
説明するための工程断面図FIG. 6 is a process sectional view for explaining an embodiment of the method for manufacturing a semiconductor device of the present invention.
【図７】本発明の実施の形態で使用した半導体キャリア
の一例の平面図FIG. 7 is a plan view of an example of a semiconductor carrier used in the embodiment of the present invention.
【図８】本発明の実施の形態で使用した半導体キャリア
の他の例の平面図FIG. 8 is a plan view of another example of the semiconductor carrier used in the embodiment of the present invention.
【図９】本発明の半導体装置の製造方法の実施の形態を
説明するための工程断面図FIG. 9 is a process sectional view for explaining an embodiment of a method for manufacturing a semiconductor device of the present invention.
【図１０】従来の半導体装置の平面図FIG. 10 is a plan view of a conventional semiconductor device.
【図１１】従来の半導体装置の底面図FIG. 11 is a bottom view of a conventional semiconductor device.
【図１２】従来の半導体装置の断面図FIG. 12 is a sectional view of a conventional semiconductor device.
【図１３】従来の半導体装置の製造方法を説明するため
の工程断面図FIG. 13 is a process sectional view for explaining the conventional method for manufacturing a semiconductor device.
【図１４】従来の半導体装置の製造方法を説明するため
の工程断面図FIG. 14 is a process sectional view for explaining the conventional method for manufacturing a semiconductor device.
【図１５】従来の半導体装置の製造方法を説明するため
の工程断面図FIG. 15 is a process sectional view for explaining a conventional method for manufacturing a semiconductor device.
【図１６】従来の半導体装置の製造方法において使用し
た半導体キャリアの一例の平面図FIG. 16 is a plan view of an example of a semiconductor carrier used in a conventional method for manufacturing a semiconductor device.
【図１７】従来の半導体装置の製造方法を説明するため
の工程断面図FIG. 17 is a process sectional view for explaining a conventional method for manufacturing a semiconductor device.
【図１８】従来の半導体装置の製造方法において使用し
た半導体キャリアの他の例の平面図FIG. 18 is a plan view of another example of a semiconductor carrier used in a conventional method for manufacturing a semiconductor device.
１ 電極パッド ２ Ａｕバンプ ３ 半導体素子 ４ 半導体キャリア ５ 電極 ６ 導電性接着剤 ７ 封止樹脂 ８ 配線パターン ９ ビア １０ 外部電極端子 １１ａ，１１ｂ，１１ｃ 認識マーク １２ａ，１２ｂ，１２ｃ 認識マーク 1 electrode pad 2 Au bump 3 Semiconductor element 4 Semiconductor carrier 5 electrodes 6 Conductive adhesive 7 Sealing resin 8 wiring patterns 9 beer 10 External electrode terminal 11a, 11b, 11c Recognition mark 12a, 12b, 12c Recognition mark
───────────────────────────────────────────────────── フロントページの続き (72)発明者 竹岡 嘉昭 大阪府高槻市幸町１番１号 松下電子工 業株式会社内 (72)発明者 入村 光男 大阪府高槻市幸町１番１号 松下電子工 業株式会社内 (56)参考文献 特開 平７−226455（ＪＰ，Ａ) 特開 平４−315459（ＪＰ，Ａ) 特開 昭63−42132（ＪＰ，Ａ) 実開 平３−10537（ＪＰ，Ｕ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/60 H01L 23/00 H01L 23/12 H01L 23/32 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yoshiaki Takeoka 1-1 Sachimachi, Takatsuki, Osaka Prefecture Matsushita Electronics Industrial Co., Ltd. (72) Inventor Mitsuo Irimura 1-1, Sachimachi, Takatsuki, Osaka Matsushita Electronics Within Kogyo Co., Ltd. (56) Reference JP-A-7-226455 (JP, A) JP-A-4-315459 (JP, A) JP-A-63-42132 (JP, A) Jitsukaihei 3-10537 ( JP, U) (58) Fields investigated (Int.Cl. 7 , DB name) H01L 21/60 H01L 23/00 H01L 23/12 H01L 23/32
Claims (2)
す配線パターンと、底面に配列され、前記電極と導通し
た外部電極端子とを有した半導体キャリア、前記半導体
キャリア上面にバンプ電極を介して接合された半導体素
子、ならびに、前記半導体素子および前記半導体キャリ
アの間の間隙と、前記半導体素子周辺端部とを充填被覆
している樹脂からなり、前記半導体キャリアは四つの角
部のうちの三つの角部に円形の認識マークを有し、対角
線上の二つの認識マークのうちのどちらかの一つの認識
マークが他の認識マークよりも寸法の大きい認識マーク
であることを特徴とする半導体装置。1. A semiconductor carrier having a plurality of electrodes on an upper surface thereof, a wiring pattern for routing the electrodes, and an external electrode terminal arranged on the bottom surface and electrically connected to the electrodes, and a bump electrode on the upper surface of the semiconductor carrier. The bonded semiconductor element and a resin filling and covering the gap between the semiconductor element and the semiconductor carrier and the peripheral edge portion of the semiconductor element, wherein the semiconductor carrier has three of four corners. A semiconductor device having circular recognition marks at one corner, and one of the two recognition marks on a diagonal line is a recognition mark having a larger dimension than the other recognition marks. .
を特徴とする請求項１に記載の半導体装置。2. The semiconductor device according to claim 1, wherein the semiconductor carrier has a substantially square shape.
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| JP2000366693A JP3397201B2 (en) | 2000-12-01 | 2000-12-01 | Semiconductor device |
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