JP3392665B2 - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JP3392665B2
JP3392665B2 JP29396696A JP29396696A JP3392665B2 JP 3392665 B2 JP3392665 B2 JP 3392665B2 JP 29396696 A JP29396696 A JP 29396696A JP 29396696 A JP29396696 A JP 29396696A JP 3392665 B2 JP3392665 B2 JP 3392665B2
Authority
JP
Japan
Prior art keywords
layer
conductivity type
type
electrode
type semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP29396696A
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Japanese (ja)
Other versions
JPH09191109A (en
Inventor
一郎 大村
智樹 井上
弘通 大橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
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Toshiba Corp
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Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP29396696A priority Critical patent/JP3392665B2/en
Publication of JPH09191109A publication Critical patent/JPH09191109A/en
Application granted granted Critical
Publication of JP3392665B2 publication Critical patent/JP3392665B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
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    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
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    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】本発明は、大電力の制御に用
いられる半導体装置に係わり、特に、オン状態での電圧
降下を低下し得る半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device used for high power control, and more particularly to a semiconductor device capable of reducing a voltage drop in an ON state.

【０００２】[0002]

【従来の技術】最近、電力制御用の半導体装置としてＳ
ｉ ＭＯＳＦＥＴが広く用いられている。このＭＯＳＦ
ＥＴは、ユニポーラ素子であり、高速性、制御の容易性
などの種々の利点を有している。2. Description of the Related Art Recently, as a semiconductor device for power control, S
i MOSFETs are widely used. This MOSF
The ET is a unipolar element, and has various advantages such as high speed and easy control.

【０００３】図４９はこの種のＭＯＳＦＥＴの構成を示
す模式図である。このＭＯＳＦＥＴは、ｎ型ドレイン層
としてのｎ型基板３０１上にｎ型ベース層３０２が形成
され、ｎ型ベース層３０２の表面には複数のｐ型ベース
層３０３が選択的に拡散形成されており、各ｐ型ベース
層３０３の表面にはｎ型ソース層３０４が選択的に形成
されている。FIG. 49 is a schematic diagram showing the structure of this type of MOSFET. In this MOSFET, an n-type base layer 302 is formed on an n-type substrate 301 as an n-type drain layer, and a plurality of p-type base layers 303 are selectively formed on the surface of the n-type base layer 302 by diffusion. An n-type source layer 304 is selectively formed on the surface of each p-type base layer 303.

【０００４】ｐ型ベース層３０３及びｎ型ソース層３０
４からｎ型ベース層３０２を介して他方のｐ型ベース層
３０３及びｎ型ソース層３０４に至る領域上には、ゲー
ト絶縁膜３０５を介して、ゲート電極３０６が設けられ
ている。また、ゲート電極３０６を挟むように、一方の
ｐ型ベース層３０３上及びｎ型ソース層３０４上と、他
方のｐ型ベース層３０３上及びｎ型ソース層３０４上と
には各々ソース電極３０７が形成されている。The p-type base layer 303 and the n-type source layer 30
A gate electrode 306 is provided on a region from 4 to the other p-type base layer 303 and the n-type source layer 304 through the n-type base layer 302 and a gate insulating film 305. A source electrode 307 is provided on each of the p-type base layer 303 and the n-type source layer 304 and the other p-type base layer 303 and the n-type source layer 304 so as to sandwich the gate electrode 306. Has been formed.

【０００５】また、ｎ型基板３０１は、ｎ型ベース層３
０２とは反対側の表面上にドレイン電極３０８が形成さ
れている。The n-type substrate 301 is composed of the n-type base layer 3
A drain electrode 308 is formed on the surface opposite to 02.

【０００６】このようなＭＯＳＦＥＴは、１種類のキャ
リアが伝導に寄与するユニポーラデバイスである。よっ
て、ＭＯＳＦＥＴの抵抗を低下させるためには、ｎ型ベ
ース層３０２の不純物濃度を増加させて抵抗率を低下さ
せ、ｎ型ベース層３０２の厚さを薄くすることが要求さ
れる。Such a MOSFET is a unipolar device in which one type of carrier contributes to conduction. Therefore, in order to reduce the resistance of the MOSFET, it is required to increase the impurity concentration of the n-type base layer 302 to reduce the resistivity and reduce the thickness of the n-type base layer 302.

【０００７】しかしながら、ｎ型ベース層３０２の不純
物濃度を増加させると、ＭＯＳＦＥＴのオフ状態でｐ型
ベース層３０３の直下に形成される電界強度の最大値が
大きくなる。このため、ＭＯＳＦＥＴでは、この電界強
度の最大値がｎ型ベース層３０２の電界強度の限界値を
越えないようにｎ型ベース層３０２中の不純物濃度が抑
制される必要がある。また、ＭＯＳＦＥＴは、耐圧がｎ
型ベース層３０２中の不純物の総量によって決定される
ので、耐圧を向上させるときにはｎ型ベース層３０２が
厚く形成される。このため、高耐圧ＭＯＳＦＥＴではオ
ン状態での電圧降下が急激に大きくなる。However, when the impurity concentration of the n-type base layer 302 is increased, the maximum value of the electric field strength formed directly below the p-type base layer 303 in the off state of the MOSFET increases. Therefore, in the MOSFET, the impurity concentration in the n-type base layer 302 needs to be suppressed so that the maximum value of the electric field intensity does not exceed the limit value of the electric field intensity of the n-type base layer 302. The withstand voltage of the MOSFET is n.
Since it is determined by the total amount of impurities in the type base layer 302, the n-type base layer 302 is formed thick when improving the breakdown voltage. For this reason, in the high breakdown voltage MOSFET, the voltage drop in the ON state rapidly increases.

【０００８】まとめると、この種のＭＯＳＦＥＴは、耐
圧の向上とオン抵抗の低下が望まれており、耐圧の向上
にはｎ型ベース層３０２の厚さＷを厚くする方式か、ｎ
型ベース層３０２のキャリア密度Ｎを低下させる方式が
ある。In summary, in this type of MOSFET, it is desired that the breakdown voltage be improved and the ON resistance be lowered. To improve the breakdown voltage, a method of increasing the thickness W of the n-type base layer 302, or n
There is a method of reducing the carrier density N of the mold base layer 302.

【０００９】しかしながら、これらの方式は、図５０の
実線で示すように、耐圧を１桁も向上させないうちに、
オン抵抗を２桁程度も増加させてしまうことが理論的に
求められている。すなわち、図５０の実線によれば、Ｓ
ｉの物性値から求められる理論限界であり、耐圧の高い
ＭＯＳＦＥＴはＩＧＢＴ等に比べてオン抵抗も高いこと
が理論的に分かっている。However, in these methods, as shown by the solid line in FIG.
It is theoretically required to increase the on-resistance by about two digits. That is, according to the solid line in FIG.
It is a theoretical limit obtained from the physical property value of i, and it is theoretically known that a MOSFET having a high breakdown voltage has a higher ON resistance than an IGBT or the like.

【００１０】次に、ＭＯＳＦＥＴと同様に電力制御に用
いられるバイポーラトランジスタ（以下、ＢＪＴとい
う）及びＩＧＢＴについて順次説明する。Next, a bipolar transistor (hereinafter referred to as BJT) and an IGBT which are used for power control similarly to the MOSFET will be sequentially described.

【００１１】図５１はバイポーラトランジスタの構成を
模式的に示す断面図である。このＢＪＴは、ｎ型コレク
タ層としてのｎ型基板３１１上にｎ型ベース層３１２が
形成されている。ｎ型ベース層３１２の表面にはｐ型ベ
ース層３１３が選択的に拡散形成されている。ｐ型ベー
ス層３１３の表面にはｎ型エミッタ層３１４が選択的に
形成されている。ｐ型ベース層３１３上にはベース電極
３１５が形成されている。ｎ型エミッタ層３１４上には
エミッタ電極３１６が形成されている。FIG. 51 is a sectional view schematically showing the structure of the bipolar transistor. In this BJT, an n-type base layer 312 is formed on an n-type substrate 311 serving as an n-type collector layer. A p-type base layer 313 is selectively diffused on the surface of the n-type base layer 312. An n-type emitter layer 314 is selectively formed on the surface of the p-type base layer 313. A base electrode 315 is formed on the p-type base layer 313. An emitter electrode 316 is formed on the n-type emitter layer 314.

【００１２】また、ｎ型基板３１１には、ｎ型ベース層
３１２とは反対側の表面上にコレクタ電極３１７が形成
されている。A collector electrode 317 is formed on the surface of the n-type substrate 311 opposite to the n-type base layer 312.

【００１３】このようなＢＪＴは、ｎ型ベース層３１２
中を流れる電流の大部分が電子によるので、ＭＯＳＦＥ
Ｔと同様に、耐圧の上昇に従って急激にオン状態での電
圧降下が増大してしまう。Such a BJT has an n-type base layer 312.
Since most of the current flowing inside is due to electrons, MOSFE
As with T, the voltage drop in the ON state rapidly increases as the breakdown voltage increases.

【００１４】また一方、ＩＧＢＴのように高抵抗のｎ型
ベース層を高注入状態にして、オン状態での電圧降下を
低下させる試みがなされている。On the other hand, an attempt has been made to reduce the voltage drop in the ON state by making a high resistance n-type base layer such as an IGBT into a highly-implanted state.

【００１５】図５２はＩＧＢＴの構成を模式的に示す断
面図である。このＩＧＢＴは、高抵抗のｎ型ベース層３
２１の表面には複数のｐ型ベース層３２２が選択的に形
成されている。各ｐ型ベース層３２２の表面にはｎ型ソ
ース層３２３が選択的に拡散形成されている。ｐ型ベー
ス層３２２およびｎ型ソース層３２３からｎ型ベース層
３２１を介して他方のｐ型ベース層３２２に至る領域上
には、ゲート絶縁膜３２４を介して、ゲート電極３２５
が設けられている。また、ゲート電極３２５を挟むよう
に、一方のｐ型ベース層３２２上およびｎ型ソース層３
２３上と、他方のｐ型ベース層３２２上およびｎ型ソー
ス層３２３上とには各々ソース電極３２６が形成されて
いる。また、ｎ型ベース層３２１の裏面にはｐ型ドレイ
ン層３２７を介してドレイン電極３２８が形成されてい
る。FIG. 52 is a sectional view schematically showing the structure of the IGBT. This IGBT has a high resistance n-type base layer 3
A plurality of p-type base layers 322 are selectively formed on the surface of 21. An n-type source layer 323 is selectively diffused on the surface of each p-type base layer 322. A gate electrode 325 is provided on a region from the p-type base layer 322 and the n-type source layer 323 to the other p-type base layer 322 via the n-type base layer 321 and a gate insulating film 324.
Is provided. The p-type base layer 322 and the n-type source layer 3 are sandwiched so as to sandwich the gate electrode 325.
23, and the source electrode 326 is formed on the other p-type base layer 322 and the n-type source layer 323, respectively. A drain electrode 328 is formed on the back surface of the n-type base layer 321 via a p-type drain layer 327.

【００１６】このようなＩＧＢＴは、ゲート電極３２５
に正の電圧が印加されると、ｐ型ベース層３２２のゲー
ト電極３２５下の部分にｎ型の反転層が形成され、ｎ型
ベース層３２１とｎ型ソース層３２３とが短絡される。
よって、ｎ型ベース層３２１中に電子が注入され、その
電子の量に応じてｐ型ドレイン層３２７から正孔が注入
されてｎ型ベース層３２１が高注入状態となりＩＧＢＴ
がオン状態となる。このオン状態のときには、ｎ型ベー
ス層３２１が高注入状態であるため、ｎ型ベース層３２
１の抵抗率が高くてもＩＧＢＴの抵抗が低くなる。Such an IGBT has a gate electrode 325.
When a positive voltage is applied to the n-type base layer 322, an n-type inversion layer is formed below the gate electrode 325, and the n-type base layer 321 and the n-type source layer 323 are short-circuited.
Therefore, electrons are injected into the n-type base layer 321, holes are injected from the p-type drain layer 327 in accordance with the amount of the electrons, and the n-type base layer 321 is in a high injection state, so that the IGBT is
Turns on. In this ON state, the n-type base layer 321 is in a high implantation state, and therefore the n-type base layer 32 is
Even if the resistivity of 1 is high, the resistance of the IGBT is low.

【００１７】[0017]

【発明が解決しようとする課題】しかしながら、このＩ
ＧＢＴは、ソース電極３２６とドレイン電極３２８との
間に、ｎ型ベース層３２１とｐ型ドレイン層３２７の拡
散電位差以上の電圧が印加されなければ電流が流れな
い。従って、このＩＧＢＴは、図５３に示すように、電
流値が低いときにはＭＯＳＦＥＴに比べてオン状態での
電圧降下が高くなり、通電損失が大きくなる。However, this I
In the GBT, a current does not flow unless a voltage higher than the diffusion potential difference between the n-type base layer 321 and the p-type drain layer 327 is applied between the source electrode 326 and the drain electrode 328. Therefore, as shown in FIG. 53, when the current value of this IGBT is low, the voltage drop in the ON state is higher than that of the MOSFET, and the conduction loss is large.

【００１８】詳しくは、ＭＯＳＦＥＴ又はＢＪＴは、耐
圧が高くなるにしたがって、オン状態での電圧降下が急
激に増大する問題がある。一方、ＩＧＢＴは低電流状態
のときに通電損失が大きくなる問題がある。More specifically, the MOSFET or BJT has a problem that the voltage drop in the ON state rapidly increases as the withstand voltage increases. On the other hand, the IGBT has a problem that the conduction loss increases in the low current state.

【００１９】本発明は上記実情を考慮してなされたもの
で、高耐圧であってもオン状態での電圧降下を低下し得
る半導体装置を提供することを目的とする。The present invention has been made in consideration of the above situation, and an object thereof is to provide a semiconductor device capable of reducing the voltage drop in the ON state even with a high breakdown voltage.

【００２０】[0020]

【課題を解決するための手段】請求項１に対応する発明
は、第１の主電極と、第２の主電極と、前記第１の主電
極と前記第２の主電極との間に介在して設けられた高抵
抗の第１導電型半導体層と、前記第１の主電極と第２の
主電極とを結ぶ方向とは略直交する層であって、電流経
路となる複数の間隙を有し、前記第１の主電極付近から
伸びる空乏層が達したときにパンチスルー状態となって
半導体装置本体のどの電極とも異なる電位となる、前記
第１導電型半導体層中に選択的に形成された第２導電型
埋込み層とを備えたことを特徴とする縦型の半導体装置
である。The invention according to claim 1 provides a first main electrode, a second main electrode, and an interposition between the first main electrode and the second main electrode. The first conductive type semiconductor layer having a high resistance and the direction connecting the first main electrode and the second main electrode are substantially orthogonal to each other, and a plurality of gaps serving as current paths are formed. A first conductive type semiconductor layer, which has a punch-through state when reaching a depletion layer extending from the vicinity of the first main electrode and has a potential different from that of any electrode of the semiconductor device body. A vertical semiconductor device comprising a selectively formed second conductive type buried layer.

【００２１】また、請求項２に対応する発明は、第１の
主電極と、第２の主電極と、前記第１の主電極と前記第
２の主電極との間に介在して設けられた高抵抗の第１導
電型半導体層と、前記第１導電型半導体層に接して設け
られ、前記第１の主電極から前記第２の主電極へ流れる
電流を制御するための制御電極を有する電流制御構造
と、前記第１の主電極と前記第２の主電極とを結ぶ方向
とは略直交する層であって、前記第１導電型半導体層中
に選択的に形成され、前記第１の主電極付近から伸びる
空乏層が達したときにパンチスルー状態となって電位固
定される第２導電型埋込み層とを備えた縦型の半導体装
置である。The invention according to claim 2 is provided so as to be interposed between the first main electrode, the second main electrode, and the first main electrode and the second main electrode. And a control electrode for controlling a current flowing from the first main electrode to the second main electrode, the control electrode being provided in contact with the first conductivity type semiconductor layer and having a high resistance. The current control structure is a layer that is substantially orthogonal to the direction connecting the first main electrode and the second main electrode, and is formed selectively in the first conductivity type semiconductor layer . From near the main electrode of
When the depletion layer reaches the punch-through state, the potential is fixed.
A vertical semiconductor device having a second conductivity type buried layer to be constant.

【００２２】さらに、請求項３に対応する発明は、ドレ
イン層と、このドレイン層の表面上に形成されたドレイ
ン電極と、前記ドレイン層における前記ドレイン電極と
は反対側の面に形成された高抵抗の第１導電型半導体層
と、この第１導電型半導体層の前記ドレイン層を形成し
た側とは反対側の表面上に選択的に形成された第２導電
型ベース層と、この第２導電型ベース層の表面に選択的
に形成された第１導電型ソース層と、この第１導電型ソ
ース層と前記第２導電型ベース層とに形成されたソース
電極と、前記第１導電型ソース層と前記第２導電型ベー
ス層と前記第１導電型半導体層とにゲート絶縁膜を介し
て接するゲート電極と、前記ドレイン電極と前記ソース
電極とを結ぶ方向とは略直交する層であって、電流経路
となる複数の間隙を有して前記第１導電型半導体層中に
選択的に形成され、前記ソース電極付近から伸びる空乏
層が達したときにパンチスルー状態となって電位固定さ
れる第２導電型埋込み層とを備えた縦型の半導体装置で
ある。Further, in the invention corresponding to claim 3, the drain layer, the drain electrode formed on the surface of the drain layer, and the high-level electrode formed on the surface of the drain layer opposite to the drain electrode. A first conductive type semiconductor layer of a resistor; a second conductive type base layer selectively formed on a surface of the first conductive type semiconductor layer opposite to the side where the drain layer is formed; A first conductive type source layer selectively formed on the surface of the conductive type base layer; a source electrode formed on the first conductive type source layer and the second conductive type base layer; and a first conductive type The gate electrode is in contact with the source layer, the second conductivity type base layer, and the first conductivity type semiconductor layer via the gate insulating film, and the direction connecting the drain electrode and the source electrode is substantially orthogonal to each other. , Multiple gaps that serve as current paths Selectively formed on the first conductive semiconductor layer has, depletion extending from the source electrode near
When the layer reaches the punch-through state, the potential is fixed.
It is a vertical semiconductor device having a second conductivity type buried layer.

【００２３】また、請求項４に対応する発明は、請求項
３に対応する半導体装置であって、前記ゲート絶縁膜と
前記ゲート電極とは、前記第２導電型ベース層を貫通
し、前記第１導電型半導体層の途中の深さまで達する溝
内に形成されている半導体装置である。The invention according to claim 4 is the semiconductor device according to claim 3, wherein the gate insulating film and the gate electrode penetrate the second conductivity type base layer, This is a semiconductor device formed in a groove that reaches a depth in the middle of a one-conductivity type semiconductor layer.

【００２４】さらに、請求項５に対応する発明は、請求
項１乃至請求項３のいずれか１項に対応する半導体装置
であって、前記第２導電型埋込み層がメッシュ形状を有
する半導体装置である。Further, an invention according to claim 5 is the semiconductor device according to any one of claims 1 to 3, wherein the second conductivity type buried layer has a mesh shape. is there.

【００２５】また、請求項６に対応する発明は、請求項
１乃至請求項３のいずれか１項に対応する半導体装置で
あって、前記第２導電型埋込み層がストライプ形状を有
する半導体装置である。さらに、請求項７に対応する発
明は、請求項１乃至請求項３のいずれか１項に対応する
半導体装置であって、前記第２導電型埋込み層がドット
形状を有する半導体装置である。また、請求項８に対応
する発明は、請求項７に対応する半導体装置であって、
前記第２導電型埋込み層としては、前記ドット形状を有
する各ドットが１行毎に半間隔ずれ、互いに隣り合う行
及び列のドットと等間隔に配置された半導体装置であ
る。 The invention according to claim 6 is the semiconductor device according to any one of claims 1 to 3, wherein the second conductivity type buried layer has a stripe shape. is there. Furthermore, the invention corresponding to claim 7
Ming corresponds to any one of claims 1 to 3.
A semiconductor device, wherein the second conductive type buried layer is a dot
A semiconductor device having a shape. Also, it corresponds to claim 8.
The invention according to claim 7 is the semiconductor device according to claim 7,
The second conductivity type buried layer has the dot shape.
Dot dots are offset by half a line for each line and are adjacent to each other
And semiconductor devices arranged at equal intervals with the dots in the rows.
It

【００２６】さらに、請求項９に対応する発明は、請求
項３に対応する半導体装置であって、前記ドレイン層が
第１導電型である半導体装置である。The invention according to claim 9 is the semiconductor device according to claim 3, wherein the drain layer is of the first conductivity type.

【００２７】また、請求項１０に対応する発明は、請求
項３に対応する半導体装置であって、前記ドレイン層が
第２導電型である半導体装置である。The invention according to claim 10 is the semiconductor device according to claim 3, wherein the drain layer is of the second conductivity type.

【００２８】さらに、請求項１１に対応する発明は、請
求項２に対応する半導体装置であって、前記第２導電型
埋込み層が前記制御電極とは異なる電位である半導体装
置である。Further, the invention according to claim 11 is the semiconductor device according to claim 2, wherein the second conductivity type buried layer has a potential different from that of the control electrode.

【００２９】また、請求項１２に対応する発明は、請求
項１又は請求項２に対応する半導体装置であって、前記
第１の主電極と前記第２の主電極との間の耐圧ＢＶと、
前記第１の主電極と前記第２の主電極との間における前
記第２導電型埋込み層の層数Ｍと、これら第２導電型埋
込み層により（Ｍ＋１）層に分割された第１導電型半導
体層のうち、前記第１の主電極に最も近い第１導電型半
導体層の分担する電圧Ｖ1 と、前記第１の主電極に最も
近い第１導電型半導体層の不純物濃度Ｎ1 と、前記第１
の主電極に最も近い第１導電型半導体層の厚さＷ1 と、
前記各第２導電型埋込み層により（Ｍ＋１）層に分割さ
れた第１導電型半導体層のうち、前記第２の主電極に最
も近い第１導電型半導体層の分担する電圧Ｖ2 と、前記
第２の主電極に最も近い第１導電型半導体層の不純物濃
度Ｎ2 と、前記各第２導電型埋込み層により（Ｍ＋１）
層に分割された第１導電型半導体層のうち、前記第１の
主電極及び前記第２の主電極から離れた（Ｍ−１）層の
第１導電型半導体層の分担する電圧Ｖｓと、前記（Ｍ−
１）層の第１導電型半導体層の不純物濃度Ｎｓと、前記
（Ｍ−１）層の第１導電型半導体層の厚さＷｓとが下記
式の関係にある半導体装置である。The invention according to claim 12 is the semiconductor device according to claim 1 or 2, wherein the breakdown voltage BV between the first main electrode and the second main electrode is ,
The number M of buried layers of the second conductivity type between the first main electrode and the second main electrode, and the first conductivity type divided into (M + 1) layers by these buried layers of the second conductivity type. Of the semiconductor layers, the voltage V 1 shared by the first conductivity type semiconductor layer closest to the first main electrode, and the impurity concentration N 1 of the first conductivity type semiconductor layer closest to the first main electrode, The first
The thickness W 1 of the first conductivity type semiconductor layer closest to the main electrode of
Of the first conductivity type semiconductor layers divided into the (M + 1) layers by the respective second conductivity type buried layers, the voltage V 2 shared by the first conductivity type semiconductor layer closest to the second main electrode, and Due to the impurity concentration N 2 of the first conductivity type semiconductor layer closest to the second main electrode and the second conductivity type buried layer, (M + 1)
Of the first conductivity type semiconductor layers divided into layers, the voltage Vs shared by the first conductivity type semiconductor layers of the (M-1) layer separated from the first main electrode and the second main electrode, (M-
In the semiconductor device, the impurity concentration Ns of the first conductivity type semiconductor layer of the 1) layer and the thickness Ws of the first conductivity type semiconductor layer of the (M-1) layer have the following relationship.

【００３０】 Ｖｓ＝（ＢＶ−Ｖ1 −Ｖ2 ）／（Ｍ−１）［Ｖ］ Ｖ1 ≧Ｖｓ Ｖ2 ≧Ｖｓ Ｎ1 ＜１．８９７ ×１０18×Ｖ1 -1.35 ［ｃｍ-3］ Ｎ2 ＜１．８９７ ×１０18×Ｖ2 -1.35 ［ｃｍ-3］ Ｎｓ＜１．８９７ ×１０18×Ｖｓ-1.35 ［ｃｍ-3］ Ｗ1 ＜１．１２４７×１０10×Ｎ1 -0.85 ［ｃｍ］ Ｗｓ＜１．１２４７×１０10×Ｎｓ-0.85 ［ｃｍ］ さらに、請求項１３に対応する発明は、請求項３に対応
する半導体装置であって、前記ソース電極と前記ドレイ
ン電極との間の耐圧ＢＶと、前記ソース電極と前記ドレ
イン電極との間における前記第２導電型埋込み層の層数
Ｍと、これら第２導電型埋込み層により（Ｍ＋１）層に
分割された第１導電型半導体層のうち、前記第２導電型
ベース層に接する第１導電型半導体層の分担する電圧Ｖ
1 と、前記第２導電型ベース層に接する第１導電型半導
体層の不純物濃度Ｎ1 と、前記第２導電型ベース層に接
する第１導電型半導体層の厚さＷ1 と、前記各第２導電
型埋込み層により（Ｍ＋１）層に分割された第１導電型
半導体層のうち、前記ドレイン層に接する第１導電型半
導体層の分担する電圧Ｖ2 と、前記ドレイン層に接する
第１導電型半導体層の不純物濃度Ｎ2 と、前記各第２導
電型埋込み層により（Ｍ＋１）層に分割された第１導電
型半導体層のうち、前記第２導電型ベース層及び前記ド
レイン層の双方に接しない（Ｍ−１）層の第１導電型半
導体層の分担する電圧Ｖｓと、前記（Ｍ−１）層の第１
導電型半導体層の不純物濃度Ｎｓと、前記（Ｍ−１）層
の第１導電型半導体層の厚さＷｓとが下記式の関係にあ
る半導体装置である。Vs = (BV−V 1 −V 2 ) / (M−1) [V] V 1 ≧ Vs V 2 ≧ Vs N 1 <1.897 × 10 18 × V 1 -1.35 [cm −3 ] N 2 <1.897 × 10 18 × V 2 −1.35 [cm −3 ] Ns <1.897 × 10 18 × Vs −1.35 [cm −3 ] W 1 <1.1247 × 10 10 × N 1 −0.85 [Cm] Ws <1.1247 × 10 10 × Ns −0.85 [cm] Furthermore, the invention corresponding to claim 13 is the semiconductor device according to claim 3, wherein the source electrode and the drain electrode are Withstand voltage BV between them, the number M of buried layers of the second conductivity type between the source electrode and the drain electrode, and a first conductivity type divided into (M + 1) layers by these second conductivity type buried layers. Among the semiconductor layers, the voltage V shared by the first conductive type semiconductor layer in contact with the second conductive type base layer
1 , the impurity concentration N 1 of the first conductive type semiconductor layer in contact with the second conductive type base layer, the thickness W 1 of the first conductive type semiconductor layer in contact with the second conductive type base layer, and Of the first conductivity type semiconductor layers divided into (M + 1) layers by the two conductivity type buried layer, the voltage V 2 shared by the first conductivity type semiconductor layer in contact with the drain layer and the first conductivity type in contact with the drain layer Of the impurity concentration N 2 of the first conductivity type semiconductor layer and the second conductivity type base layer and the drain layer of the first conductivity type semiconductor layer divided into (M + 1) layers by the second conductivity type buried layers. The voltage Vs shared by the first conductivity type semiconductor layer of the (M-1) layer which is not in contact with the first conductivity type semiconductor layer of the (M-1) layer
In the semiconductor device, the impurity concentration Ns of the conductivity type semiconductor layer and the thickness Ws of the first conductivity type semiconductor layer of the (M-1) layer have the following relationship.

【００３１】 Ｖｓ＝（ＢＶ−Ｖ1 −Ｖ2 ）／（Ｍ−１）［Ｖ］ Ｖ1 ≧Ｖｓ Ｖ2 ≧Ｖｓ Ｎ1 ＜１．８９７ ×１０18×Ｖ1 -1.35 ［ｃｍ-3］ Ｎ2 ＜１．８９７ ×１０18×Ｖ2 -1.35 ［ｃｍ-3］ Ｎｓ＜１．８９７ ×１０18×Ｖｓ-1.35 ［ｃｍ-3］ Ｗ1 ＜１．１２４７×１０10×Ｎ1 -0.85 ［ｃｍ］ Ｗｓ＜１．１２４７×１０10×Ｎｓ-0.85 ［ｃｍ］ また、請求項１４に対応する発明は、請求項１乃至請求
項３のいずれか１項に対応する半導体装置であって、前
記第２導電型埋込み層を取り囲むように略方形状に形成
された埋込み第２導電型ガードリング領域を備えた半導
体装置である。Vs = (BV−V 1 −V 2 ) / (M−1) [V] V 1 ≧ Vs V 2 ≧ Vs N 1 <1.897 × 10 18 × V 1 -1.35 [cm −3 ] N 2 <1.897 × 10 18 × V 2 −1.35 [cm −3 ] Ns <1.897 × 10 18 × Vs −1.35 [cm −3 ] W 1 <1.1247 × 10 10 × N 1 −0.85 [Cm] Ws <1.1247 × 10 10 × Ns −0.85 [cm] The invention according to claim 14 is the semiconductor device according to any one of claims 1 to 3. A semiconductor device having a buried second conductivity type guard ring region formed in a substantially rectangular shape so as to surround the second conductivity type buried layer.

【００３２】さらに、請求項１５に対応する発明は、請
求項１乃至請求項３のいずれか１項対応する半導体装置
であって、前記第２導電型埋込み層を取り囲むように略
方形状に形成され、前記第２導電型埋込み層のキャリア
密度よりも低いキャリア密度を有する埋込み第２導電型
リサーフ領域を備えた半導体装置である。Further, an invention according to claim 15 is the semiconductor device according to any one of claims 1 to 3, wherein the semiconductor device is formed in a substantially rectangular shape so as to surround the second conductive type buried layer. And a buried second conductivity type RESURF region having a carrier density lower than the carrier density of the second conductivity type buried layer.

【００３３】また、請求項１６に対応する発明は、請求
項１乃至請求項３のいずれか１項に対応する半導体装置
であって、前記第１導電型半導体層の終端部が、傾斜を
有するベベル構造に形成された半導体装置である。さら
に、請求項１７に対応する発明は、第１の主電極と、第
２の主電極と、前記第１の主電極と前記第２の主電極と
の間に介在して設けられた高抵抗の第１導電型半導体層
と、前記第１導電型半導体層中に選択的に形成され、浮
いた電位を有して前記第１の主電極と第２の主電極とを
結ぶ方向とは略直交する方向に拡がって配置されてお
り、電流経路として機能する複数の間隙を有し、前記第
１の主電極付近から伸びる空乏層が自己に達したときに
半導体装置本体のどの電極とも異なる前記浮いた電位と
なる第２導電型埋込み層とを備えた半導体装置であっ
て、前記第１の主電極と前記第２の主電極との間の耐圧
ＢＶと、前記第１の主電極と前記第２の主電極との間に
おける前記第２導電型埋込み層の層数Ｍと、前記第２導
電型埋込み層と前記第１の主電極との間で前記第１の主
電極に近接して配置された前記第１導電型半導体層の第
１領域の分担する電圧Ｖ 1 と、前記第１導電型半導体層
の第１領域の不純物濃度Ｎ 1 と、前記第１導電型半導体
層の第１領域の厚さＷ 1 と、前記第２導電型埋込み層と
前記第２の主電極との間で前記第２の主電極に近接して
配置された第１導電型半導体層の第２領域の分担する電
圧Ｖ 2 と、前記第１導電型半導体層の第２領域の不純物
濃度Ｎ 2 と、前記第１導電型半導体層における第１領域
と第２領域との間である第３領域の分担する電圧Ｖｓ
と、前記第１導電型半導体層の第３領域の不純物濃度Ｎ
ｓ と、前記第１導電型半導体層の第３領域の厚さＷ
ｓ と、が下記式の関係にある半導体装置である。 Ｖｓ＝（ＢＶ−Ｖ 1 −Ｖ 2 ）／（Ｍ−１）［Ｖ］ Ｖ 1 ≧Ｖｓ Ｖ 2 ≧Ｖｓ Ｎ 1 ＜１．８９７ ×１０ 18 ×Ｖ 1 -1.35 ［ｃｍ -3 ］ Ｎ 2 ＜１．８９７ ×１０ 18 ×Ｖ 2 -1.35 ［ｃｍ -3 ］ Ｎｓ＜１．８９７ ×１０ 18 ×Ｖｓ -1.35 ［ｃｍ -3 ］ Ｗ 1 ＜１．１２４７×１０ 10 ×Ｎ 1 -0.85 ［ｃｍ］ Ｗｓ＜１．１２４７×１０ 10 ×Ｎｓ -0.85 ［ｃｍ］ また、請求項１８に対応する発明は、請求項１７に対応
する半導体装置であって、前記第１導電型半導体層に接
して設けられ、前記第１の主電極から前記第２の主電極
へ流れる電流を制御するための制御電極を有する電流制
御構造を備えた半導体装置である。さらに、請求項１９
に対応する発明は、ドレイン層と、このドレイン層の表
面上に形成されたドレイン電極と、前記ドレイン層にお
ける前記ドレイン電極とは反対側の面に形成された高抵
抗の第１導電型半導体層と、この第１導電型半導体層の
前記ドレイン層を形成した側とは反対側の表面に選択的
に形成された第２導電型ベース層と、この第２導電型ベ
ース層の表面に選択的に形成された第１導電型ソース層
と、この第１導電型ソース層と前記第２導電型ベース層
とに形成されたソース電極と、前記第１導電型ソース層
と前記第２導電型ベース層と前記第１導電型半導体層と
にゲート絶縁膜を介して接するゲート電極と、前記第１
導電型半導体層中に選択的に形成され、浮いた電位を有
して前記ドレイン電極と前記ソース電極とを結ぶ方向と
は略直交する方向に拡がって配置されており、電流経路
として機能する複数の間隙を有し、前記ソース電極付近
から伸びる空乏層が自己に達したときに半導体装置本体
のどの電極とも異なる前記浮いた電位となる第２導電型
埋込み層とを備えた半導体装置であって、前記ドレイン
電極と前記ソース電極との間の耐圧ＢＶと、前記ドレイ
ン電極と前記ソース電極との間における前記第２導電型
埋込み層の層数Ｍと、前記第２導電型埋込み層と前記ソ
ース電極との間で前記ソース電極に近接して配置された
前記第１導電型半導体層の第１領域の分担する電圧Ｖ 1
と、前記第１導電型半導体層の第１領域の不純物濃度Ｎ
1 と、前記第１導電型半導体層の第１領域の厚さＷ
1 と、前記第２導電型埋込み層と前記ドレイン電極との
間で前記ドレイン電極に近接して配置された第１導電型
半導体層の第２領域の分担する電圧Ｖ 2 と、前記第１導
電型半導体層の第２領域の不純物濃度Ｎ 2 と、前記第１
導電型半導体層における第１領域と第２領域との間であ
る第３領域の分担する電圧Ｖｓと、前記第１導電型半導
体層の第３領域の不純物濃度Ｎ ｓ と、前記第１導電型半
導体層の第３領域の厚さＷ ｓ と、が下記式の関係にある
半導体装置である。 Ｖｓ＝（ＢＶ−Ｖ 1 −Ｖ 2 ）／（Ｍ−１）［Ｖ］ Ｖ 1 ≧Ｖｓ Ｖ 2 ≧Ｖｓ Ｎ 1 ＜１．８９７ ×１０ 18 ×Ｖ 1 -1.35 ［ｃｍ -3 ］ Ｎ 2 ＜１．８９７ ×１０ 18 ×Ｖ 2 -1.35 ［ｃｍ -3 ］ Ｎｓ＜１．８９７ ×１０ 18 ×Ｖｓ -1.35 ［ｃｍ -3 ］ Ｗ 1 ＜１．１２４７×１０ 10 ×Ｎ 1 -0.85 ［ｃｍ］ Ｗｓ＜１．１２４７×１０ 10 ×Ｎｓ -0.85 ［ｃｍ］ Claims16The invention corresponding to
A semiconductor device corresponding to any one of claims 1 to 3.
And the terminating portion of the first conductivity type semiconductor layer has an inclination.
The semiconductor device has a bevel structure.Furthermore
The invention corresponding to claim 17 provides a first main electrode,
Two main electrodes, the first main electrode and the second main electrode
High-resistance first-conductivity-type semiconductor layer provided between
And is selectively formed in the first conductive type semiconductor layer and floats.
The first main electrode and the second main electrode with a predetermined potential.
It is arranged so as to extend in a direction substantially orthogonal to the connecting direction.
Has a plurality of gaps that function as current paths,
When the depletion layer extending from the vicinity of the main electrode of 1 reaches itself
The floating potential different from any electrode of the semiconductor device body
A semiconductor device having a second conductivity type buried layer
The breakdown voltage between the first main electrode and the second main electrode.
BV and between the first main electrode and the second main electrode
The number M of the buried layers of the second conductivity type in the
The first main electrode between the electric buried layer and the first main electrode.
A first conductive type semiconductor layer disposed adjacent to the electrode;
Voltage V shared by one region 1 And the first conductive type semiconductor layer
Concentration N of the first region of 1 And the first conductivity type semiconductor
Thickness W of the first region of the layer 1 And the buried layer of the second conductivity type
Between the second main electrode and close to the second main electrode
The charge sharing of the second region of the arranged first conductivity type semiconductor layer
Pressure V 2 And impurities in the second region of the first conductivity type semiconductor layer
Concentration N 2 And a first region in the first conductivity type semiconductor layer
And the voltage Vs shared by the third region between the second region and the second region
And the impurity concentration N of the third region of the first conductivity type semiconductor layer.
s And the thickness W of the third region of the first conductivity type semiconductor layer
s And are semiconductor devices that have the following relationship. Vs = (BV-V 1 -V 2 ) / (M-1) [V] V 1 ≧ Vs V 2 ≧ Vs N 1 <1.897 × 10 18 × V 1 -1.35 [Cm -3 ] N 2 <1.897 × 10 18 × V 2 -1.35 [Cm -3 ] Ns <1.897 × 10 18 × Vs -1.35 [Cm -3 ] W 1 <1.1247 × 10 Ten × N 1 -0.85 [Cm] Ws <1.1247 × 10 Ten × Ns -0.85 [Cm] The invention corresponding to claim 18 corresponds to claim 17.
A semiconductor device that is connected to the first conductivity type semiconductor layer.
Provided from the first main electrode to the second main electrode
Current control with control electrode for controlling current flowing to
It is a semiconductor device having a control structure. Further, claim 19
The invention corresponding to is a drain layer and a surface of this drain layer.
The drain electrode formed on the surface and the drain layer.
The high resistance formed on the surface opposite to the drain electrode.
Of the first conductive type semiconductor layer and the first conductive type semiconductor layer
Selective on the surface opposite to the side where the drain layer is formed
And a second conductive type base layer formed on the second conductive type base layer.
Source layer selectively formed on the surface of the source layer
And the first conductive type source layer and the second conductive type base layer
And a source electrode formed on the first conductivity type source layer
And the second conductive type base layer and the first conductive type semiconductor layer
A gate electrode in contact with the first electrode via a gate insulating film,
It is selectively formed in the conductive semiconductor layer and has a floating potential.
And the direction connecting the drain electrode and the source electrode
Are arranged so as to extend in a direction substantially orthogonal to each other.
Near the source electrode with multiple gaps that function as
When the depletion layer extending from the self reaches the semiconductor device body
Second conductivity type having the floating potential different from any of the electrodes
A semiconductor device having a buried layer, wherein the drain
The breakdown voltage BV between the electrode and the source electrode, and the drain voltage.
Second conductivity type between the source electrode and the source electrode
The number M of buried layers, the buried layer of the second conductivity type and the
A source electrode and a source electrode in close proximity to the source electrode.
The voltage V shared by the first region of the first conductivity type semiconductor layer 1
And the impurity concentration N of the first region of the first conductivity type semiconductor layer
1 And the thickness W of the first region of the first conductive type semiconductor layer
1 Of the buried layer of the second conductivity type and the drain electrode
First conductivity type disposed between and adjacent to the drain electrode
The voltage V shared by the second region of the semiconductor layer 2 And the first guide
Impurity concentration N in the second region of the electric semiconductor layer 2 And the first
Between the first region and the second region in the conductivity type semiconductor layer
Voltage Vs shared by the third region and the first conductivity type semiconductor
Impurity concentration N in the third region of the body layer s And said first conductivity type half
Thickness W of the third region of the conductor layer s And are related by the following formula
It is a semiconductor device. Vs = (BV-V 1 -V 2 ) / (M-1) [V] V 1 ≧ Vs V 2 ≧ Vs N 1 <1.897 × 10 18 × V 1 -1.35 [Cm -3 ] N 2 <1.897 × 10 18 × V 2 -1.35 [Cm -3 ] Ns <1.897 × 10 18 × Vs -1.35 [Cm -3 ] W 1 <1.1247 × 10 Ten × N 1 -0.85 [Cm] Ws <1.1247 × 10 Ten × Ns -0.85 [Cm]

【００３４】（作用）従って、請求項１に対応する発明
は以上のような手段を講じたことにより、オフ状態の際
に、印加電圧の増加に比例して空乏層が第１導電型半導
体層中を第２の主電極側から第１の主電極側に広がり、
この空乏層が第２導電型埋込み層に到達したとき、パン
チスルー現象により、第２導電型埋込み層が当該空乏層
中の電界強度を固定してその上昇を抑止するので、この
ときの電界強度の最大値を越える電界強度の限界値をも
つ範囲で第１導電型半導体層の不純物濃度を増加させて
オン抵抗を低下させることにより、高耐圧であってもオ
ン状態での電圧降下を低下させることができる。(Operation) Therefore, in the invention corresponding to claim 1, the depletion layer has the first conductivity type semiconductor layer in proportion to the increase of the applied voltage in the off state by taking the above means. The inside spreads from the second main electrode side to the first main electrode side,
When this depletion layer reaches the second-conductivity-type buried layer, the second-conductivity-type buried layer fixes the electric field strength in the depletion layer and suppresses its rise due to the punch-through phenomenon. Of the first conductivity type semiconductor layer is increased within a range having a limit value of the electric field strength exceeding the maximum value of the above-mentioned value to reduce the on-resistance, thereby reducing the voltage drop in the on-state even with a high breakdown voltage. be able to.

【００３５】また、請求項２の発明によれば、請求項１
に対応する作用に加え、電流制御構造により、第１の主
電極から第２の主電極へ流れる電流を制御することがで
きる。According to the invention of claim 2, claim 1
In addition to the action corresponding to, the current control structure can control the current flowing from the first main electrode to the second main electrode.

【００３６】さらに、請求項３の発明によれば、オフ状
態の際に、印加電圧の増加に比例して空乏層が第２導電
型ベース層からドレイン電極側に広がり、この空乏層が
第２導電型埋込み層に到達したとき、パンチスルー現象
により、第２導電型埋込み層が当該空乏層中の電界強度
を固定してその上昇を抑止するので、このときの電界強
度の最大値を越える電界強度の限界値をもつ範囲で第１
導電型半導体層の不純物濃度を増加させてオン抵抗を低
下させることにより、高耐圧であってもオン状態での電
圧降下を低下させることができる。Further, according to the third aspect of the invention, in the off state, the depletion layer spreads from the second conductivity type base layer to the drain electrode side in proportion to the increase of the applied voltage, and the depletion layer becomes the second depletion layer. When reaching the conductivity type buried layer, the second conductivity type buried layer fixes the electric field strength in the depletion layer and suppresses its rise due to the punch-through phenomenon, so that an electric field exceeding the maximum value of the electric field strength at this time is reached. First in the range with a limit value of strength
By increasing the impurity concentration of the conductive type semiconductor layer to reduce the on-resistance, it is possible to reduce the voltage drop in the on-state even with a high breakdown voltage.

【００３７】また、請求項４の発明によれば、ゲート絶
縁膜とゲート電極とが第２導電型ベース層を貫通し、第
１導電型半導体層の途中の深さまで達する溝内に形成さ
れているので、請求項３に対応する作用を奏するトレン
チ構造の半導体装置を実現させることができる。Further, according to the invention of claim 4, the gate insulating film and the gate electrode are formed in the groove penetrating the second conductivity type base layer and reaching the depth of the middle of the first conductivity type semiconductor layer. Therefore, it is possible to realize a semiconductor device having a trench structure that achieves the action corresponding to claim 3.

【００３８】さらに、請求項５の発明によれば、請求項
１乃至請求項３のいずれかに対応する作用に加え、第２
導電型埋込み層がメッシュ形状を有しているため、スト
ライプ形状に比べて容易に高耐圧化させることができ
る。Further, according to the invention of claim 5, in addition to the action corresponding to any one of claims 1 to 3,
Since the conductive type buried layer has a mesh shape, it is possible to easily increase the breakdown voltage as compared with the stripe shape.

【００３９】また、請求項６の発明によれば、第２導電
型埋込み層がストライプ形状を有しているため、請求項
１乃至請求項３のいずれかと同様の作用を奏することが
できる。さらに、請求項７の発明によれば、第２導電型
埋込み層がドット形状を有することにより、請求項１乃
至請求項３のいずれかと同様の作用に加え、素子の終端
部にてガードリングと同様に作用するため、プレーナ構
造の場合、高耐圧の半導体装置を形成することができ
る。また、請求項８の発明によれば、第２導電型埋込み
層としては、ドット形状を有する各ドットが１行毎に半
間隔ずれ、互いに隣り合う行及び列のドットと等間隔に
配置されたので、請求項７に対応する作用に加え、高密
度なドットパターンを形成でき、耐圧的に有利なものと
なる。 Further, according to the invention of claim 6, since the second conductivity type buried layer has a stripe shape, the same operation as that of any one of claims 1 to 3 can be achieved. Further, according to the invention of claim 7, the second conductivity type
The embedding layer has a dot shape, whereby the embedding layer has a dot shape.
In addition to the same effect as that of any one of claims 3 to 3, the termination of the element
Part acts like a guard ring,
In the case of manufacturing, it is possible to form a high breakdown voltage semiconductor device.
It According to the invention of claim 8, the second conductivity type embedded
As a layer, each dot with a dot shape is half a line
Spacing, equidistant with dots in adjacent rows and columns
Since it is arranged, in addition to the action corresponding to claim 7, high density
It is possible to form a precise dot pattern, which is advantageous in terms of pressure resistance.
Become.

【００４０】さらに、請求項９の発明によれば、請求項
３に対応する作用に加え、高耐圧であっても、オン状態
での電圧降下を低下できるＭＯＳＦＥＴ等の半導体装置
を実現させることができる。Further, according to the invention of claim 9 , in addition to the action corresponding to claim 3, it is possible to realize a semiconductor device such as a MOSFET capable of reducing the voltage drop in the ON state even with a high breakdown voltage. it can.

【００４１】また、請求項１０の発明によれば、請求項
３の効果に加え、ドレイン電極側に第２導電型ドレイン
層を有するバイポーラ素子であっても、前述同様に、高
耐圧であっても、オン状態での電圧降下を低下できるＩ
ＧＢＴ等の半導体装置を提供できる。Further, according to the invention of claim 10 , in addition to the effect of claim 3, even a bipolar element having a second conductivity type drain layer on the drain electrode side has a high breakdown voltage as described above. Can reduce the voltage drop in the ON state
A semiconductor device such as a GBT can be provided.

【００４２】さらに、請求項１１の発明によれば、第２
導電型埋込み層が、制御電極とは異なる電位であり、電
位的に浮いた状態であるので、請求項２に対応する作用
と同様の作用を奏することができる。Further, according to the invention of claim 11 , the second
Since the conductivity type buried layer has a potential different from that of the control electrode and is in a potential floating state, the same action as the action corresponding to claim 2 can be achieved.

【００４３】また、請求項１２，１７，１８の発明によ
れば、第１の主電極と第２の主電極との間の耐圧ＢＶ
と、第１の主電極と第２の主電極との間における第２導
電型埋込み層の層数Ｍと、これら第２導電型埋込み層に
より（Ｍ＋１）層に分割された第１導電型半導体層のう
ち、第１の主電極に最も近い第１導電型半導体層の分担
する電圧Ｖ1 と、第１の主電極に最も近い第１導電型半
導体層の不純物濃度Ｎ1と、第１の主電極に最も近い第
１導電型半導体層の厚さＷ1 と、各第２導電型埋込み層
により（Ｍ＋１）層に分割された第１導電型半導体層の
うち、第２の主電極に最も近い第１導電型半導体層の分
担する電圧Ｖ2 と、第２の主電極に最も近い第１導電型
半導体層の不純物濃度Ｎ2 と、各第２導電型埋込み層に
より（Ｍ＋１）層に分割された第１導電型半導体層のう
ち、第１の主電極及び第２の主電極から離れた （Ｍ−
１）層の第１導電型半導体層の分担する電圧Ｖｓと、
（Ｍ−１）層の第１導電型半導体層の不純物濃度Ｎｓ
と、（Ｍ−１）層の第１導電型半導体層の厚さＷｓとの
夫々の設計条件を所定の式にて明確化しているので、請
求項１又は請求項２の効果に加え、確実に動作する素子
を再現性よく形成することができる。According to the twelfth , seventeenth and eighteenth inventions, the breakdown voltage BV between the first main electrode and the second main electrode is high.
And the number M of the second conductivity type buried layers between the first main electrode and the second main electrode, and the first conductivity type semiconductor divided into (M + 1) layers by these second conductivity type buried layers. Among the layers, the voltage V 1 shared by the first conductivity type semiconductor layer closest to the first main electrode, the impurity concentration N 1 of the first conductivity type semiconductor layer closest to the first main electrode, and the first The thickness W 1 of the first-conductivity-type semiconductor layer closest to the main electrode and the first main-conductivity-type semiconductor layer divided into (M + 1) layers by the respective second-conductivity-type buried layers are the closest to the second main electrode. The voltage is divided into (M + 1) layers by the voltage V 2 shared by the nearby first conductivity type semiconductor layer, the impurity concentration N 2 of the first conductivity type semiconductor layer closest to the second main electrode, and each second conductivity type buried layer. Of the first conductive type semiconductor layer separated from the first main electrode and the second main electrode (M−
Voltage Vs shared by the first conductivity type semiconductor layer of layer 1),
Impurity concentration Ns of the first conductivity type semiconductor layer of the (M-1) layer
And the thickness Ws of the first conductivity type semiconductor layer of the (M-1) layer are clarified by predetermined formulas, so that in addition to the effect of claim 1 or claim 2, It is possible to form a device that operates in good condition with good reproducibility.

【００４４】さらに、請求項１３，１９の発明によれ
ば、ソース電極とドレイン電極との間の耐圧ＢＶと、ソ
ース電極とドレイン電極との間における第２導電型埋込
み層の層数Ｍと、これら第２導電型埋込み層により（Ｍ
＋１）層に分割された第１導電型半導体層のうち、第２
導電型ベース層に接する第１導電型半導体層の分担する
電圧Ｖ1 と、第２導電型ベース層に接する第１導電型半
導体層の不純物濃度Ｎ1と、第２導電型ベース層に接す
る第１導電型半導体層の厚さＷ1 と、各第２導電型埋込
み層により（Ｍ＋１）層に分割された第１導電型半導体
層のうち、ドレイン層に接する第１導電型半導体層の分
担する電圧Ｖ2 と、ドレイン層に接する第１導電型半導
体層の不純物濃度Ｎ2 と、各第２導電型埋込み層により
（Ｍ＋１）層に分割された第１導電型半導体層のうち、
第２導電型ベース層及びドレイン層の双方に接しない
（Ｍ−１）層の第１導電型半導体層の分担する電圧Ｖｓ
と、（Ｍ−１）層の第１導電型半導体層の不純物濃度Ｎ
ｓと、（Ｍ−１）層の第１導電型半導体層の厚さＷｓと
の夫々の設計条件を所定の式にて明確化しているので、
請求項３の効果に加え、確実に動作する素子を再現性よ
く形成することができる。Further, according to the invention of claims 13 and 19 , the breakdown voltage BV between the source electrode and the drain electrode, the number M of the buried layers of the second conductivity type between the source electrode and the drain electrode, By these second conductive type buried layers (M
The second of the first conductivity type semiconductor layers divided into +1) layers
The voltage V 1 shared by the first conductive type semiconductor layer in contact with the conductive type base layer, the impurity concentration N 1 of the first conductive type semiconductor layer in contact with the second conductive type base layer, and the first conductive type semiconductor layer in contact with the second conductive type base layer. The thickness W 1 of the first conductivity type semiconductor layer and the first conductivity type semiconductor layer in contact with the drain layer among the first conductivity type semiconductor layers divided into (M + 1) layers by the respective second conductivity type buried layers are shared. Of the voltage V 2 , the impurity concentration N 2 of the first conductivity type semiconductor layer in contact with the drain layer, and the first conductivity type semiconductor layer divided into (M + 1) layers by each second conductivity type buried layer,
The voltage Vs shared by the first conductivity type semiconductor layer of the (M-1) layer that is not in contact with both the second conductivity type base layer and the drain layer.
And the impurity concentration N of the first conductivity type semiconductor layer of the (M-1) layer
Since the respective design conditions of s and the thickness Ws of the first conductivity type semiconductor layer of the (M-1) layer are clarified by predetermined formulas,
In addition to the effect of the third aspect, it is possible to form elements that operate reliably with good reproducibility.

【００４５】また、請求項１４の発明によれば、第２導
電型埋込み層を取り囲むように略方形状に形成された埋
込み第２導電型ガードリング領域を備えた終端構造なの
で、請求項１乃至請求項３のいずれかの効果に加え、各
埋込み第２導電型ガードリング領域により、半導体装置
終端部における等電位線の間隔を広げて電界集中を緩和
すると共に、半導体装置終端部の耐圧劣化を阻止するこ
とができる。Further, according to the invention of claim 14, buried formed Ryakukata shape so as to surround the second conductivity type buried layer
In addition to the effect of any one of claims 1 to 3, since the termination structure is provided with the embedded second conductivity type guard ring region,
By the buried second conductivity type guard ring region, it is possible to widen the interval between equipotential lines in the terminal portion of the semiconductor device to mitigate the electric field concentration and prevent the breakdown voltage of the terminal portion of the semiconductor device from deteriorating.

【００４６】さらに、請求項１５の発明によれば、第２
導電型埋込み層を取り囲むように略方形状に形成され、
第２導電型埋込み層のキャリア密度よりも低いキャリア
密度を有する埋込み第２導電型リサーフ領域を備えたの
で、請求項１乃至請求項３のいずれかに対応する作用と
同様の作用を奏することができる。Further, according to the invention of claim 15, the second
Formed in a substantially rectangular shape so as to surround the conductive type buried layer,
Since the embedded second-conductivity-type RESURF region having a carrier density lower than that of the second-conductivity-type buried layer is provided, the same operation as that according to any one of claims 1 to 3 can be achieved. it can.

【００４７】また、請求項１６の発明によれば、請求項
１乃至請求項３のいずれかに対応する作用に加え、第１
導電型半導体層の終端部が、傾斜を有するベベル構造に
形成されたことにより、ｐｎ接合終端の電界強度を緩和
するベベル構造の利点を奏することができる。According to the sixteenth aspect of the invention, in addition to the action corresponding to any one of the first to third aspects, the first aspect
Since the terminal end portion of the conductive type semiconductor layer is formed in the bevel structure having an inclination, it is possible to exert the advantage of the bevel structure that relaxes the electric field strength at the pn junction terminal.

【００４８】[0048]

【発明の実施の形態】以下、本発明の実施の形態につい
て図面を参照しながら説明する。なお、以下の実施形態
では第１導電型をｎ型、第２導電型をｐ型としている。
また、添付図面中の同類の参照符号は数多の図中の同等
部分を示すものである。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. In the following embodiments, the first conductivity type is n-type and the second conductivity type is p-type.
Further, like reference numerals in the accompanying drawings indicate the same parts in many drawings.

【００４９】（第１の実施の形態）図１は本発明の第１
の実施の形態に係るＭＯＳＦＥＴの構成を示す模式図で
ある。このＭＯＳＦＥＴは、ｎ型ドレイン層としてのｎ
型基板１１上にドレイン電極１２が形成されている。ま
た、ｎ型基板１１におけるドレイン電極１２とは反対側
の表面には下段のｎ型ベース層１３がエピタキシャル成
長により形成され、下段のｎ型ベース層１３の表面には
ストライプ形状をもつ下側の（floating mesh layer と
しての）ｐ型埋込み層１４が形成される。(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
FIG. 3 is a schematic diagram showing the structure of the MOSFET according to the embodiment of FIG. This MOSFET has n as an n-type drain layer.
The drain electrode 12 is formed on the mold substrate 11. A lower n-type base layer 13 is formed by epitaxial growth on the surface of the n-type substrate 11 opposite to the drain electrode 12, and the lower n-type base layer 13 has a stripe-shaped lower surface ( A p-type buried layer 14 (as a floating mesh layer) is formed.

【００５０】下側のｐ型埋込み層１４上には中段の第２
のｎ型ベース層１５がｎ型ベース層１３と同様に形成さ
れ、中段のｎ型ベース層１５の表面にはストライプ形状
をもつ上側のｐ型埋込み層１６が形成され、同様に、上
側のｐ型埋込み層１６上には上段のｎ型ベース層１７が
形成される。上段のｎ型ベース層１７の表面には複数の
ｐ型ベース層１８が選択的に拡散形成されており、各ｐ
型ベース層１８の表面にはｎ型ソース層１９が選択的に
形成されている。The second p-type buried layer 14 on the lower side has a second middle layer.
Is formed in the same manner as the n-type base layer 13, and an upper p-type buried layer 16 having a stripe shape is formed on the surface of the n-type base layer 15 in the middle stage. An upper n-type base layer 17 is formed on the mold burying layer 16. A plurality of p-type base layers 18 are selectively formed on the surface of the upper n-type base layer 17 by diffusion.
An n-type source layer 19 is selectively formed on the surface of the mold base layer 18.

【００５１】ｐ型ベース層１８及びｎ型ソース層１９か
ら上段のｎ型ベース層１７を介して他方のｐ型ベース層
１８及びｎ型ソース層１９に至る領域上には、Ｓｉ酸化
膜２０を介して、ゲート電極２１が設けられている。ま
た、ゲート電極２１を挟むように、一方のｐ型ベース層
１８上及びｎ型ソース層１９上と、他方のｐ型ベース層
１８上及びｎ型ソース層１９上とには各々ソース電極２
２が形成されている。A Si oxide film 20 is formed on the region from the p-type base layer 18 and the n-type source layer 19 to the other p-type base layer 18 and the n-type source layer 19 through the upper n-type base layer 17. A gate electrode 21 is provided through the gate electrode 21. Further, the source electrode 2 is provided on each of the p-type base layer 18 and the n-type source layer 19 and the other p-type base layer 18 and the n-type source layer 19 so as to sandwich the gate electrode 21.
2 is formed.

【００５２】ここで、このＭＯＳＦＥＴは耐圧ＢＶが６
００Ｖである。Here, this MOSFET has a withstand voltage BV of 6
It is 00V.

【００５３】下段、中段及び上段のｎ型ベース層１３，
１５，１７の各々は、耐圧ＢＶ＝６００Ｖを電圧Ｖｓ＝
２００Ｖずつ分担するため、不純物濃度Ｎｓ＜１．８９
７×１０18×Ｖｓ-1.35 ［ｃｍ-3］となっており、ここ
では前式にＶｓ＝２００を代入した結果に２５％の余裕
をみて不純物濃度Ｎｓ＝１×１０15［ｃｍ-3］となるよ
うに形成されている。なお、この不純物濃度Ｎｓは、従
来よりも３倍程度増加された値となっている。The lower, middle and upper n-type base layers 13,
Each of 15 and 17 has a withstand voltage BV = 600V and a voltage Vs =
Since the voltage is shared by 200 V, the impurity concentration Ns <1.89
7 × 10 18 × Vs −1.35 [cm −3 ], and here, the impurity concentration Ns = 1 × 10 15 [cm −3 ] with a 25% margin in the result of substituting Vs = 200 in the previous equation. It is formed so that. The impurity concentration Ns has a value about three times higher than the conventional one.

【００５４】また、中段及び上段のｎ型ベース層１５，
１７の各々は、厚さＷｓ＜１．１２４７×１０10×Ｎｓ
-0.85 ［ｃｍ］となっており、同様にこの式にＮｓ＝１
×１０15を代入した結果に２５％の余裕をみて厚さＷｓ
＝１４μｍとなるように形成されている。In addition, the middle and upper n-type base layers 15,
Each of 17 has a thickness Ws <1.1247 × 10 10 × Ns
-0.85 [cm], and Ns = 1 in this formula as well.
With a margin of 25% for the result of substituting × 10 15 , the thickness Ws
= 14 μm.

【００５５】一方、下側及び上側のｐ型埋込み層１４，
１６の各々は、図２に示すように、その厚さｔと、形成
間隔Ｗとの関係が５ｔ＞Ｗを満たすように形成されてい
る。理由は、形成間隔Ｗが狭いと電流経路が狭くなって
ＪＦＥＴ効果によりオン抵抗の増大を招き、形成間隔Ｗ
が広いとｐ型埋込み層１４，１６を設けない素子と等価
な構造となるからである。On the other hand, the lower and upper p-type buried layers 14,
As shown in FIG. 2, each of 16 is formed so that the relationship between its thickness t and the formation interval W satisfies 5t> W. The reason for this is that if the formation interval W is narrow, the current path becomes narrow and the on-resistance increases due to the JFET effect.
Is wide, the structure is equivalent to an element in which the p-type buried layers 14 and 16 are not provided.

【００５６】また、下側及び上側のｐ型埋込み層１４，
１６の各々は、下段乃至上段のｎ型ベース層１３，１
５，１７の各々の厚さをｌbulkとしたとき、３Ｗｓ＞ｔ
Ｗ／Ｗｓの関係を満たすように形成される。これらｐ型
埋込み層１４，１６は、電位的に浮いた状態を有し、そ
れぞれストライプ状の複数のｐ型領域が終端部にて互い
に接続されるように形成されている。The lower and upper p-type buried layers 14,
16 of the n-type base layers 13 and 1 in the lower to upper stages, respectively.
When the thickness of each of 5 and 17 is 1 bulk, 3 Ws> t
It is formed so as to satisfy the W / Ws relationship. These p-type buried layers 14 and 16 have a potential floating state, and are formed such that a plurality of stripe-shaped p-type regions are connected to each other at their terminal ends.

【００５７】次に、このようなＭＯＳＦＥＴの作用を説
明する。Next, the operation of such a MOSFET will be described.

【００５８】２００Ｖ以下の印加電圧の場合、図３
（ａ）に示すように、通常のＭＯＳＦＥＴと同様に、ｐ
型ベース層１８からドレイン電極１２側に向けて上段の
ｎ型ベース層１７中に空乏層が広がり、ｐ型ベース層１
８と上側のｎ型ベース層１７との間の界面近傍に電界の
最強点が発生する。When the applied voltage is 200 V or less, FIG.
As shown in (a), p
A depletion layer spreads in the upper n-type base layer 17 from the type base layer 18 toward the drain electrode 12 side.
The strongest point of the electric field occurs in the vicinity of the interface between 8 and the upper n-type base layer 17.

【００５９】印加電圧が２００Ｖに到達すると、図３
（ｂ）に示すように、空乏層が上側のｐ型埋込み層１６
に到達したとき、ｎ型ベース層１７が空乏化し、ｐ型埋
込み層１６がパンチスルー状態となって電位固定され
る。これにより、ｐ型ベース層１８側の電界の最強点の
上昇が抑止される。なお、ｐ型埋込み層１６の全領域で
パンチスルーする必要は無く、ｐ型埋込み層１６の一部
でのみパンチスルーすればよい。When the applied voltage reaches 200 V, as shown in FIG.
As shown in (b), the depletion layer is on the upper side of the p-type buried layer 16
When n reaches, the n-type base layer 17 is depleted and the p-type buried layer 16 is in a punch-through state and the potential is fixed. This suppresses an increase in the strongest point of the electric field on the p-type base layer 18 side. It is not necessary to punch through the entire region of the p-type burying layer 16, and it is sufficient to punch through only a part of the p-type burying layer 16.

【００６０】印加電圧が２００Ｖを越えると、図３
（ｃ）に示すように、新たに空乏層がこのｐ型埋込み層
１６からドレイン電極１２側に向けて中段のｎ型ベース
層１５中を広がり、前述した電界の最強点とは別に、電
界の最強点がｐ型埋込み層１６側に発生する。When the applied voltage exceeds 200 V, FIG.
As shown in (c), a new depletion layer spreads from the p-type buried layer 16 toward the drain electrode 12 side in the middle n-type base layer 15, and in addition to the strongest point of the electric field described above, The strongest point occurs on the p-type buried layer 16 side.

【００６１】印加電圧が４００Ｖに到達すると、図３
（ｄ）に示すように、空乏層が下側のｐ型埋込み層１４
に到達し、ｐ型埋込み層１４がパンチスルー状態となっ
て電位固定される。When the applied voltage reaches 400 V, as shown in FIG.
As shown in (d), the p-type buried layer 14 with the depletion layer on the lower side is formed.
And the potential of the p-type buried layer 14 is fixed in the punch-through state.

【００６２】以下同様に、印加電圧が４００Ｖを越える
と、図３（ｅ）に示すように、このｐ型埋込み層１４か
らドレイン電極１２側に向けて下段のｎ型ベース層１３
中を空乏層が広がる。Similarly, when the applied voltage exceeds 400 V, as shown in FIG. 3E, the n-type base layer 13 in the lower stage from the p-type buried layer 14 toward the drain electrode 12 side.
A depletion layer spreads inside.

【００６３】印加電圧が６００Ｖに到達すると、図３
（ｆ）に示すように、空乏層がｎ型基板１１に到達す
る。なお、このような電界強度分布の２次元数値計算に
よる算出結果を図４に示す。When the applied voltage reaches 600 V, as shown in FIG.
As shown in (f), the depletion layer reaches the n-type substrate 11. The calculation result of such an electric field intensity distribution by two-dimensional numerical calculation is shown in FIG.

【００６４】このように、ｎ型ベース層を３分割するよ
うに２つのｐ型埋込み層１４，１６を設け、これら各ｐ
型埋込み層１４，１６により各ｎ型ベース層１３，１
５，１７における電界の最大強度を固定することにより
各ｎ型ベース層１３，１５，１７に夫々２００Ｖずつを
分担させ、もって、耐圧６００Ｖを実現することができ
る。In this way, the two p-type buried layers 14 and 16 are provided so as to divide the n-type base layer into three parts, and each of these p-type buried layers 14 and 16 is formed.
The n-type base layers 13 and 1 are formed by the mold burying layers 14 and 16.
By fixing the maximum strength of the electric field at 5, 17, each of the n-type base layers 13, 15, 17 is allowed to share a voltage of 200 V, thereby achieving a breakdown voltage of 600 V.

【００６５】また、電界の最大強度を越える電界の限界
値をもつ範囲でｎ型ベース層１３，１５，１７の不純物
濃度を増加させてオン抵抗を低下させるように素子を設
計することにより、高耐圧であってもオン状態での電圧
降下を低下させることができる。Further, by designing the element to increase the impurity concentration of the n-type base layers 13, 15 and 17 and lower the on-resistance in a range having an electric field limit value exceeding the maximum electric field strength, Even with a withstand voltage, the voltage drop in the on state can be reduced.

【００６６】詳述すると、本実施の形態に係るＭＯＳＦ
ＥＴにおいては、図５（ａ）に示すように、ｎ型ベース
層１３，１５，１７の不純物濃度が１×１０15ｃｍ-3で
ある。しかしながら、従来、この不純物濃度では耐圧２
５０Ｖしか実現できず、図５（ｂ）に示すように、耐圧
６００Ｖを実現するには約１／３の不純物濃度の３．３
×１０14ｃｍ-3にする必要があった。本実施の形態に係
るＭＯＳＦＥＴは、ｐ型埋込み層１４，１６で分割され
た３つのｎ型ベース層が２００Ｖづつ電圧を分担するの
で、１×１０15ｃｍ-3という高い不純物濃度でも、耐圧
６００Ｖを実現することができる。また、高耐圧ＭＯＳ
ＦＥＴのオン抵抗は高抵抗層（ｎ型ベース層）のキャリ
ア密度に反比例して低下する。このため、従来型ＭＯＳ
ＦＥＴでは低オン抵抗が実現不可であるのに対し、本実
施の形態に係るＭＯＳＦＥＴでは、従来とは異なり、大
幅にオン状態での電圧降下を低下させることができる。More specifically, the MOSF according to this embodiment is
In ET, as shown in FIG. 5A, the impurity concentration of the n-type base layers 13, 15, 17 is 1 × 10 15 cm −3 . However, conventionally, with this impurity concentration, the withstand voltage is 2
Only 50 V can be realized, and as shown in FIG. 5B, in order to realize a withstand voltage of 600 V, an impurity concentration of about 3.3 is 3.3.
It was necessary to make it 10 14 cm -3 . In the MOSFET according to the present embodiment, the three n-type base layers divided by the p-type buried layers 14 and 16 share the voltage of 200 V each, so that the withstand voltage of 600 V is achieved even with a high impurity concentration of 1 × 10 15 cm −3. Can be realized. In addition, high breakdown voltage MOS
The on-resistance of the FET decreases in inverse proportion to the carrier density of the high resistance layer (n-type base layer). Therefore, conventional MOS
While low on-resistance cannot be realized by the FET, the MOSFET according to the present embodiment can greatly reduce the voltage drop in the on-state unlike the conventional case.

【００６７】次に、このような作用を奏するＭＯＳＦＥ
Ｔの設計方法を具体的に説明する。Next, a MOSFE having such an action
A method of designing T will be specifically described.

【００６８】下段、中段及び上段のｎ型ベース層１３，
１５，１７の各々は、耐圧ＢＶ＝６００Ｖを電圧Ｖｓ＝
２００Ｖずつ分担する。なお、この電圧Ｖｓ＝２００Ｖ
は次の（１）式により得られる。The lower, middle and upper n-type base layers 13,
Each of 15 and 17 has a withstand voltage BV = 600V and a voltage Vs =
Allocate 200V each. This voltage Vs = 200V
Is obtained by the following equation (1).

【００６９】Ｖｓ＝ＢＶ／（Ｍ＋１） …（１） 但し、Ｍ；ｐ型埋込み層１４，１６の層数（＝２；本実
施の形態の場合）。また、この（１）式は、各ｎ型ベー
ス層１３，１５，１７の分担する電圧Ｖｓあるいは不純
物濃度Ｎｓが互いに等しい場合の式である。Vs = BV / (M + 1) (1) Here, M; the number of p-type buried layers 14 and 16 (= 2; in the case of the present embodiment). Further, the expression (1) is an expression when the voltages Vs or the impurity concentrations Ns shared by the n-type base layers 13, 15, and 17 are equal to each other.

【００７０】また、各ｎ型ベース層１３，１５，１７
は、この電圧Ｖｓにより、図６又は次の（２）式に基づ
いて、不純物濃度Ｎｓが決定される。Further, each n-type base layer 13, 15, 17
The impurity concentration Ns is determined by this voltage Vs based on FIG. 6 or the following equation (2).

【００７１】 Ｎｓ＜１．８９７×１０18×Ｖｓ-1.35 ［ｃｍ-3］ …（２） 具体的には、各ｎ型ベース層１３，１５，１７は、
（２）式に２５％程度の余裕をもたせた（３）式に基づ
いて、不純物濃度Ｎｓ＝１×１０15［ｃｍ-3］をもつよ
うに形成される。Ns <1.897 × 10 18 × Vs −1.35 [cm −3 ] (2) Specifically, each of the n-type base layers 13, 15, 17 is
The impurity concentration Ns = 1 × 10 15 [cm −3 ] is formed based on the equation (3) in which the equation (2) has a margin of about 25%.

【００７２】 Ｎｓ〜０．７５×１．８９７×１０18×Ｖｓ-1.35 ［ｃｍ-3］ …（３） また、中段及び上段のｎ型ベース層１５，１７の各々
は、この不純物濃度Ｎｓにより、図７又は次の（４）式
に基づいて、厚さＷｓが決定される。Ns to 0.75 × 1.897 × 10 18 × Vs −1.35 [cm −3 ] (3) Further, each of the n-type base layers 15 and 17 in the middle stage and the upper stage depends on the impurity concentration Ns. The thickness Ws is determined based on FIG. 7 or the following equation (4).

【００７３】 Ｗｓ＜１．１２４７×１０10×Ｎｓ-0.85 ［ｃｍ］ …（４） 但し、厚さＷｓは、中段のｎ型ベース層１５では各ｐ型
埋込み層１４，１６相互間の最短距離であり、上段のｎ
型ベース層１７ではｐ型ベース層１８と上側のｐ型埋込
み層１６との間の最短距離を意味している。Ws <1.1247 × 10 10 × Ns −0.85 [cm] (4) However, the thickness Ws is the shortest distance between the p-type buried layers 14 and 16 in the middle n-type base layer 15. And the upper n
In the mold base layer 17, it means the shortest distance between the p-type base layer 18 and the upper p-type buried layer 16.

【００７４】ところで具体的には、中段及び上段のｎ型
ベース層１５，１７の各々は、（４）式に２５％程度の
余裕をもたせた（５）式に基づいて、厚さＷｓ＝１４μ
ｍをもつように形成される。Specifically, each of the middle and upper n-type base layers 15 and 17 has a thickness Ws = 14 μm based on the equation (5) in which a margin of about 25% is added to the equation (4).
is formed to have m.

【００７５】 Ｗｓ〜０．７５×１．１２４７×１０10×Ｎｓ-0.85 ［ｃｍ］ …（５） 一方、下段のｎ型ベース層１３の厚さＷｓは、（４）式
及び（５）式を適用せず、（４）式の値を越える値でも
よい。これは、下段のｎ型ベース層１３はｎ型基板１１
に接する層であるため、空乏層が伸びてパンチスルーさ
せる必要がないためである。Ws to 0.75 × 1.1247 × 10 10 × Ns −0.85 [cm] (5) On the other hand, the thickness Ws of the lower n-type base layer 13 is expressed by the equations (4) and (5). A value exceeding the value of the expression (4) may be applied without applying. This is because the lower n-type base layer 13 is the n-type substrate 11.
This is because there is no need to punch through the depletion layer because it is a layer in contact with.

【００７６】続いて、ｐ型埋込み層１４，１６の設計方
法について述べる。Next, a method of designing the p type buried layers 14 and 16 will be described.

【００７７】本実施の形態に係るＭＯＳＦＥＴは、図８
に示すように、ＭＯＳＦＥＴと２つのＳＩＴ（Static I
nduction Transistor ）とが直列接続されたものと仮定
でき、オン抵抗が次の（６）式にて示される。The MOSFET according to this embodiment is shown in FIG.
As shown in, a MOSFET and two SITs (Static I
nduction Transistor) can be assumed to be connected in series, and the on-resistance is expressed by the following equation (6).

【００７８】 オン抵抗＝Ｒch＋ＲJFET１＋Ｒbulk１＋ＲJFET２＋Ｒbulk２＋ＲJFET３＋Ｒbu lk３ …（６） オン抵抗を低減するには、（６）式によると、ＲJFET１
〜３を低い値に抑える必要がある。ON resistance = Rch + RJFET1 + Rbulk1 + RJFET2 + Rbulk2 + RJFET3 + Rbulk3 (6) To reduce the ON resistance, according to the formula (6), RJFET1
It is necessary to keep ~ 3 low.

【００７９】ところで、従来型のＭＯＳＦＥＴのオン抵
抗のうちのｎ型ベース層３０２の抵抗は、本実施の形態
のＭＯＳＦＥＴのパラメータを使うと、次の（７）式の
ように示される。By the way, the resistance of the n-type base layer 302 of the on-resistance of the conventional MOSFET is expressed by the following equation (7) using the parameters of the MOSFET of the present embodiment.

【００８０】従来型の ｎ型ベース層の抵抗＝（Ｍ＋１）×Ｗｓ／（ｑμ（Ｎｓ／（Ｍ＋１））） ＝（Ｍ＋１）2 ×Ｗｓ／（ｑμＮｓ） …（７） 但し、ｑは素電荷であり、μは移動度である。また、従
来型ＭＯＳＦＥＴのキャリア密度は、本実施の形態のキ
ャリア密度Ｎｓの１／（Ｍ＋１）倍である。Resistance of conventional n-type base layer = (M + 1) × Ws / (qμ (Ns / (M + 1))) = (M + 1) 2 × Ws / (qμNs) (7) where q is elementary charge And μ is the mobility. The carrier density of the conventional MOSFET is 1 / (M + 1) times the carrier density Ns of the present embodiment.

【００８１】一方、本実施の形態のＭＯＳＦＥＴのオン
抵抗のうちのｎ型ベース層１３，１５，１７の抵抗は、
次の（８）式のように示される。On the other hand, the resistance of the n-type base layers 13, 15, and 17 of the on-resistance of the MOSFET of this embodiment is
It is expressed as the following equation (8).

【００８２】本実施の形態の ｎ型ベース層の抵抗＝（Ｍ＋１）Ｗｓ／（ｑμＮｓ）＋Ｍ（ｔＷ／Ｗｓ）／（ｑ μＮｓ） …（８） これより、本実施の形態のオン抵抗が従来のＭＯＳＦＥ
Ｔに比べて小さい条件は、上の（７）式及び（８）式に
基づいて次の（９）式のように示される。Resistance of n-type base layer of the present embodiment = (M + 1) Ws / (qμNs) + M (tW / Ws) / (qμNs) (8) Therefore, the on-resistance of the present embodiment is conventional. MOSFE
The condition that is smaller than T is expressed by the following equation (9) based on the above equations (7) and (8).

【００８３】 （Ｍ＋１）Ｗｓ＞ｔＷ／Ｗｓ …（９） このような設計方法により、本実施の形態に係るＭＯＳ
ＦＥＴを確実に作成することができる。(M + 1) Ws> tW / Ws (9) With such a design method, the MOS according to the present embodiment
The FET can be surely created.

【００８４】図９はこのように設計されたＭＯＳＦＥＴ
におけるオン抵抗と耐圧の関係を示す図である。図示す
るように、耐圧６００Ｖの場合に理論限界の半分のオン
抵抗を実現している。また、耐圧１２００Ｖの場合に
は、理論限界の数分の一までオン抵抗を低減可能なこと
を示している。FIG. 9 shows a MOSFET designed in this way.
6 is a diagram showing the relationship between on-resistance and breakdown voltage in FIG. As shown in the figure, when the breakdown voltage is 600 V, the on-resistance which is half the theoretical limit is realized. Further, it has been shown that when the withstand voltage is 1200 V, the on-resistance can be reduced to a fraction of the theoretical limit.

【００８５】図１０は本発明に係るＭＯＳＦＥＴにて理
論的に可能なオン抵抗と耐圧の関係を示す図である。図
示するように、ｐ型埋込み層の層数Ｍに比例してオン抵
抗が低減可能となっている。なお、図９と図１０とは層
数Ｍの増加に伴ってずれが生じるが、これは図９に示す
関係は、本素子が３次元構造をもつのに対して数値計算
上、２次元構造と仮定したからである。FIG. 10 is a diagram showing a theoretically possible relationship between on-resistance and breakdown voltage in the MOSFET according to the present invention. As shown, the on-resistance can be reduced in proportion to the number M of p-type buried layers. It should be noted that although there is a difference between FIGS. 9 and 10 as the number of layers M increases, this is because the relationship shown in FIG. This is because it was assumed.

【００８６】上述したように第１の実施の形態によれ
ば、オフ状態の際に、印加電圧の増加に比例して空乏層
がｐ型ベース層１８からドレイン電極１２側に広がり、
この空乏層がｐ型埋込み層１６に到達したとき、パンチ
スルー現象により、ｐ型埋込み層１６が当該空乏層中の
電界強度を固定してその上昇を抑止するので、このとき
の電界強度の最大値を越える電界強度の限界値をもつ範
囲でｎ型ベース層１７のキャリア密度を増加させてオン
抵抗を低下させることにより、高耐圧であってもオン状
態での電圧降下を低下させることができる。As described above, according to the first embodiment, in the off state, the depletion layer spreads from the p-type base layer 18 to the drain electrode 12 side in proportion to the increase of the applied voltage.
When this depletion layer reaches the p-type buried layer 16, the punch-through phenomenon causes the p-type buried layer 16 to fix the electric field strength in the depletion layer and suppress its rise. By increasing the carrier density of the n-type base layer 17 and lowering the on-resistance within a range having an electric field strength limit value exceeding the value, the voltage drop in the on-state can be reduced even with a high breakdown voltage. .

【００８７】また、本実施の形態によれば、設計条件を
（１）式〜（２）式、（４）式や図６及び図７にて明確
化しているので、確実に動作する素子を再現性よく形成
することができる。Further, according to the present embodiment, the design conditions are clarified by the equations (1) to (2), the equation (4) and FIGS. It can be formed with good reproducibility.

【００８８】（第２の実施の形態）次に、本発明の第２
の実施の形態に係るＭＯＳＦＥＴについて説明する。(Second Embodiment) Next, the second embodiment of the present invention will be described.
The MOSFET according to the embodiment will be described.

【００８９】図１１（ａ）はこのＭＯＳＦＥＴのｐ型埋
込み層の構成を示す模式図であり、図１１（ｂ）は図１
に示すｐ型埋込み層の拡大図であって、図１と同一部分
には同一符号を付してその詳しい説明は省略し、ここで
は異なる部分についてのみ述べる。FIG. 11 (a) is a schematic view showing the structure of the p-type buried layer of this MOSFET, and FIG. 11 (b) is shown in FIG.
2 is an enlarged view of the p-type buried layer shown in FIG. 2, and the same parts as those in FIG.

【００９０】すなわち、このＭＯＳＦＥＴは、第１の実
施の形態の変形構成であり、図１１（ｂ）に示すごとき
ｐ型埋込み層１６（又は１４）内部のｐ型部相互間の抵
抗ＲJFETを低減させてオン抵抗の低下を図るものであっ
て、具体的には図１１（ａ）に示すように、ｐ型埋込み
層１６（又は１４）内部のｐ型部相互間のｎ型ベース層
１５に該ｎ型ベース層１５のキャリア密度Ｎｓよりも高
いキャリア密度を有するｎ+ 型層１５ａを設けた構成と
なっている。That is, this MOSFET is a modification of the first embodiment, and the resistance RJFET between the p-type portions inside the p-type buried layer 16 (or 14) as shown in FIG. 11B is reduced. In order to reduce the on-resistance, specifically, as shown in FIG. 11A, the n-type base layer 15 between the p-type portions inside the p-type buried layer 16 (or 14) is formed. The n + type layer 15a having a carrier density higher than the carrier density Ns of the n type base layer 15 is provided.

【００９１】これにより、第１の実施の形態の効果に加
え、ＲJFETを低減したので、より一層、オン抵抗を低下
させることができる。As a result, in addition to the effect of the first embodiment, the RJFET is reduced, so that the ON resistance can be further reduced.

【００９２】（第３の実施の形態）次に、本発明の第３
の実施の形態に係るショットキーバリアダイオードにつ
いて説明する。(Third Embodiment) Next, the third embodiment of the present invention will be described.
The Schottky barrier diode according to the embodiment will be described.

【００９３】図１２はこのショットキーバリアダイオー
ドの構成を示す模式図である。このショットキーバリア
ダイオードは、ｎ型基板３１上に下段のｎ型ベース層３
２が拡散形成され、下段のｎ型ベース層３２の表面には
ストライプ形状のｐ型埋込み層３３が形成される。FIG. 12 is a schematic diagram showing the structure of this Schottky barrier diode. This Schottky barrier diode has a structure in which a lower n-type base layer 3 is formed on an n-type substrate 31.
2 is diffused to form a stripe-shaped p-type buried layer 33 on the surface of the lower n-type base layer 32.

【００９４】ｐ型埋込み層３３上には上段のｎ型ベース
層３４が形成され、上段のｎ型ベース層３４の表面には
ショットキー電極３５が形成される。なお、上段のｎ型
ベース層３４の厚さは、ショットキー接合からのリーク
電流の少ない低電圧でショットキー界面の空乏層がｐ型
埋込み層３３に到達するように設計される。一方、ｎ型
基板３１における下段のｎ型ベース層３２とは反対側の
表面にはオーミック電極３６が形成される。An upper n-type base layer 34 is formed on the p-type buried layer 33, and a Schottky electrode 35 is formed on the surface of the upper n-type base layer 34. The thickness of the upper n-type base layer 34 is designed so that the depletion layer at the Schottky interface reaches the p-type buried layer 33 at a low voltage with a small leak current from the Schottky junction. On the other hand, an ohmic electrode 36 is formed on the surface of the n-type substrate 31 opposite to the lower n-type base layer 32.

【００９５】次に、このショットキーバリアダイオード
の作用を説明する。Next, the operation of this Schottky barrier diode will be described.

【００９６】このショットキーバリアダイオードにおい
ては、逆バイアス電圧（ショットキー電極３５に負電
圧、オーミック電極３６に正電圧）が印加されたとす
る。In this Schottky barrier diode, it is assumed that a reverse bias voltage (a negative voltage is applied to the Schottky electrode 35 and a positive voltage is applied to the ohmic electrode 36).

【００９７】このとき、下段のｎ型ベース層３４では、
ショットキー電極３５との界面から空乏層がオーミック
電極３６側に向けて広がり、このショットキー電極３５
界面に電界の最強点が発生する。At this time, in the lower n-type base layer 34,
A depletion layer spreads from the interface with the Schottky electrode 35 toward the ohmic electrode 36 side.
The strongest point of the electric field occurs at the interface.

【００９８】しかしながら、逆バイアス電圧の上昇に伴
なって空乏層がｐ型埋込み層３３に到達し、前述同様に
ショットキー界面の電界の最強点が固定されて上昇しな
くなり、空乏層は埋込み層より新たにアノード側（図中
下方）に広がる。ここで、逆バイアス電圧は低い値であ
るように設計されているので、ショットキー界面での電
界も低い値で固定される。これにより、リーク電流を低
減させることができる。However, as the reverse bias voltage rises, the depletion layer reaches the p-type buried layer 33, the strongest point of the electric field at the Schottky interface is fixed and does not rise, and the depletion layer becomes the buried layer. It spreads more to the anode side (downward in the figure). Here, since the reverse bias voltage is designed to have a low value, the electric field at the Schottky interface is also fixed at a low value. Thereby, the leak current can be reduced.

【００９９】なお、このショットキーバリアダイオード
によれば、特に高温動作時のリーク電流を低減させるこ
とができる。さらに、周知技術とは異なり、ｐ型層によ
るガードリングを形成する必要がなく、また、ガードリ
ング部分でバイポーラ動作が起こる問題もない。According to this Schottky barrier diode, it is possible to reduce the leak current particularly during high temperature operation. Further, unlike the known technique, it is not necessary to form a guard ring with a p-type layer, and there is no problem that a bipolar operation occurs in the guard ring portion.

【０１００】（第４の実施の形態）次に、本発明の第４
の実施の形態に係るショットキーバリアダイオードにつ
いて説明する。(Fourth Embodiment) Next, the fourth embodiment of the present invention will be described.
The Schottky barrier diode according to the embodiment will be described.

【０１０１】図１３はこのショットキーバリアダイオー
ドの構成を示す模式図であり、図１２と同一部分には同
一符号を付してその詳しい説明は省略し、ここでは異な
る部分についてのみ述べる。FIG. 13 is a schematic diagram showing the structure of this Schottky barrier diode. The same parts as those in FIG. 12 are designated by the same reference numerals, and detailed description thereof will be omitted. Only different parts will be described here.

【０１０２】すなわち、このショットキーバリアダイオ
ードは、第３の実施の形態の変形構成であり、高耐圧化
及びオン状態での電圧降下の低減化を図るものであり、
具体的には図１３に示すように、ｎ型基板３１上に複数
のｎ型ベース層３２1 〜３２3 、複数のｐ型埋込み層３
３1 〜３３3 とが互いに個別に積層されて形成されてい
る。That is, this Schottky barrier diode is a modified structure of the third embodiment and is intended to have a high breakdown voltage and a reduced voltage drop in the ON state.
Specifically, as shown in FIG. 13, a plurality of n-type base layers 32 1 to 32 3 and a plurality of p-type buried layers 3 are provided on an n-type substrate 31.
3 1 to 33 3 are formed by being individually laminated with each other.

【０１０３】これにより、第３の実施の形態の効果に加
え、前述同様に、各ｐ型埋込み層３３1 〜３３3 により
分割されたｎ型ベース層３２1 〜３２3 が耐圧を分担す
るので、従来実現不可能であった高耐圧で、オン状態で
の電圧降下の低いショットキーバリアダイオードを実現
することができる。As a result, in addition to the effects of the third embodiment, the breakdown voltage is shared by the n-type base layers 32 1 to 32 3 divided by the p-type buried layers 33 1 to 33 3 as described above. It is possible to realize a Schottky barrier diode having a high breakdown voltage and a low voltage drop in the ON state, which has been impossible to realize in the past.

【０１０４】（第５の実施の形態）次に、本発明の第５
の実施の形態に係るＩＧＢＴについて説明する。(Fifth Embodiment) Next, the fifth embodiment of the present invention will be described.
The IGBT according to the embodiment will be described.

【０１０５】図１４はこのＩＧＢＴの構成を示す模式図
である。このＩＧＢＴは、ｐ型エミッタ層としてのｐ型
基板４１上にドレイン電極４２が形成されている。ま
た、ｐ型基板４１におけるドレイン電極４２とは反対側
の表面にはｎ型バッファ層４３及び下段のｎ型ベース層
４４が形成され、下段のｎ型ベース層４４の表面にはス
トライプ形状のｐ型埋込み層４５が形成される。FIG. 14 is a schematic diagram showing the structure of this IGBT. In this IGBT, a drain electrode 42 is formed on a p-type substrate 41 as a p-type emitter layer. Further, an n-type buffer layer 43 and a lower n-type base layer 44 are formed on the surface of the p-type substrate 41 opposite to the drain electrode 42, and a stripe-shaped p-type p-layer is formed on the lower n-type base layer 44. The mold embedding layer 45 is formed.

【０１０６】ｐ型埋込み層４５上には上段のｎ型ベース
層４６が形成され、上段のｎ型ベース層４６の表面には
このｎ型ベース層４６のキャリア密度よりも高いキャリ
ア密度を有するｎ+ 型層４７が形成されている。ｎ+ 型
層４７にはｎ型ベース層４６に達する深さをもつ複数の
ｐ型ベース層４８が選択的に拡散形成されており、各ｐ
型ベース層４８の表面にはｎ型ソース層４９が選択的に
形成されている。なお、ｐ型埋込み層４５とｐ型ベース
層４８とは、電界の最大強度を低い値に抑えるように互
いに近い位置に形成される。An upper n-type base layer 46 is formed on the p-type buried layer 45, and the surface of the upper n-type base layer 46 has a carrier density higher than that of the n-type base layer 46. A + type layer 47 is formed. A plurality of p-type base layers 48 having a depth reaching the n-type base layer 46 are selectively formed in the n + -type layer 47 by diffusion.
An n-type source layer 49 is selectively formed on the surface of the mold base layer 48. The p-type buried layer 45 and the p-type base layer 48 are formed at positions close to each other so as to suppress the maximum strength of the electric field to a low value.

【０１０７】ｐ型ベース層４８及びｎ型ソース層４９か
らｎ+ 型層４７を介して他方のｐ型ベース層４８及びｎ
型ソース層４９に至る領域上には、Ｓｉ酸化膜５０を介
して、ゲート電極５１が設けられている。また、ゲート
電極５１を挟むように、一方のｐ型ベース層４８上及び
ｎ型ソース層４９上と、他方のｐ型ベース層４８上及び
ｎ型ソース層４９上とには各々ソース電極５２が形成さ
れている。From the p-type base layer 48 and the n-type source layer 49 through the n + -type layer 47, the other p-type base layer 48 and n
A gate electrode 51 is provided on a region reaching the mold source layer 49 with a Si oxide film 50 interposed therebetween. A source electrode 52 is provided on each of the p-type base layer 48 and the n-type source layer 49 and the other p-type base layer 48 and the n-type source layer 49 so as to sandwich the gate electrode 51. Has been formed.

【０１０８】このような構成としても、ｎ+ 型層４７が
キャリア密度の高さに比例してオン状態での電圧降下を
低下させる効果を有し、さらに、このオン状態での電圧
降下の低下に伴なう耐圧の低下をｐ型埋込み層４５によ
って阻止している。すなわち、ｐ型埋込み層４５をｐ型
ベース層４８に近い部分に設けたことにより、ｎ+ 型層
４７付近での電界の最強点の上昇を低めに抑えるので、
オン状態での電圧降下の低下と高耐圧化とを同時に実現
することができる。Even with such a structure, the n + -type layer 47 has an effect of reducing the voltage drop in the ON state in proportion to the height of the carrier density, and further, the voltage drop in the ON state is lowered. The p-type buried layer 45 prevents the breakdown voltage from being lowered due to the above. That is, since the p-type buried layer 45 is provided in the portion close to the p-type base layer 48, the rise of the strongest point of the electric field in the vicinity of the n + -type layer 47 is suppressed to a low level.
It is possible to simultaneously realize a reduction in voltage drop in the ON state and a high breakdown voltage.

【０１０９】（第６の実施の形態）次に、本発明の第６
の実施の形態に係るＩＧＢＴについて説明する。(Sixth Embodiment) Next, the sixth embodiment of the present invention will be described.
The IGBT according to the embodiment will be described.

【０１１０】図１５はこのＩＢＧＴの構成を示す模式図
であり、図１４と同一部分には同一符号を付し、ほぼ同
一部分にはａの添字を付してその詳しい説明は省略し、
ここでは異なる部分についてのみ述べる。FIG. 15 is a schematic diagram showing the structure of the IBGT. The same parts as those in FIG. 14 are designated by the same reference numerals, and substantially the same parts are designated by a subscript a, and detailed description thereof will be omitted.
Here, only different parts will be described.

【０１１１】すなわち、このＩＧＢＴは、第５の実施の
形態の変形構成であり、さらなるオン状態での電圧降下
の低下を図るものであり、具体的には図１５に示すよう
に、ｎ+ 型層４７及び上段のｎ型ベース層４６に代え
て、ｎ+ 型層４７と上段のｎ型ベース層４６との領域を
有するｎ+ 型層４７ａがｐ型埋込み層４５上に形成され
ている。That is, this IGBT is a modified structure of the fifth embodiment and is intended to further reduce the voltage drop in the ON state. Specifically, as shown in FIG. 15, as shown in FIG. Instead of the layer 47 and the upper n-type base layer 46, an n + -type layer 47a having a region of the n + -type layer 47 and the upper n-type base layer 46 is formed on the p-type buried layer 45.

【０１１２】ｎ+ 型層４７ａは、前述同様に、ｎ型ベー
ス層４４のキャリア密度よりも高いキャリア密度を有し
ている。The n + type layer 47a has a carrier density higher than that of the n type base layer 44, as described above.

【０１１３】このように、高いキャリア密度をもつｎ+
型層４７ａをｐ型埋込み層４５の上全体に形成したの
で、第５の実施の形態の効果に加え、一層、オン状態で
の電圧降下を低下させることができる。Thus, n + having a high carrier density
Since the mold layer 47a is formed over the entire p-type buried layer 45, the voltage drop in the ON state can be further reduced in addition to the effect of the fifth embodiment.

【０１１４】（第７の実施の形態）次に、本発明の第７
の実施の形態に係るＩＧＢＴについて説明する。(Seventh Embodiment) Next, the seventh embodiment of the present invention will be described.
The IGBT according to the embodiment will be described.

【０１１５】図１６はこのＩＧＢＴの構成を示す模式図
であり、図１４と同一部分には同一符号を付してその詳
しい説明は省略し、ここでは異なる部分についてのみ述
べる。FIG. 16 is a schematic diagram showing the structure of the IGBT. The same parts as those in FIG. 14 are designated by the same reference numerals and detailed description thereof will be omitted. Only different parts will be described here.

【０１１６】すなわち、このＩＧＢＴは、第５の実施の
形態の変形構成であり、より一層のオン状態での電圧降
下の低下を図るものであり、具体的には図１６に示すよ
うに、複数のｎ型ベース層４４1 〜４４4 ，４６と複数
のｐ型埋込み層４５1 〜４５4 とが個別に交互に積層形
成されている。That is, this IGBT is a modified configuration of the fifth embodiment and is intended to further reduce the voltage drop in the ON state. Specifically, as shown in FIG. N type base layers 44 1 to 44 4 and 46 and a plurality of p type embedded layers 45 1 to 45 4 are individually and alternately laminated.

【０１１７】このような構成としても、第５の実施の形
態の効果に加え、複数のｐ型埋込み層４５1 〜４５4 の
存在によりｎ型ベース層４４1 〜４４4 、４６のキャリ
ア密度が増加可能となるので、より一層オン状態での電
圧降下を低下させることができる。Even with such a structure, in addition to the effect of the fifth embodiment, the carrier density of the n-type base layers 44 1 to 44 4 and 46 is increased by the existence of the plurality of p-type buried layers 45 1 to 45 4. Since it can be increased, the voltage drop in the on-state can be further reduced.

【０１１８】次に、上記実施の形態に係るＭＯＳＦＥＴ
及びショットキーバリアダイオードの具体的な４通りの
形成方法（ａ）〜（ｄ）を図１７乃至図２０に示す工程
断面図を用いて説明する。なお、以下の説明は、ｎ型基
板に代えて、ｎ型バッファ層を上部に有するｐ型基板
（ｐ型エミッタ層）を用いることにより、ＩＧＢＴの形
成方法にも適用可能である。Next, the MOSFET according to the above embodiment
Further, four specific methods (a) to (d) for forming the Schottky barrier diode will be described with reference to process sectional views shown in FIGS. The following description is also applicable to the method of forming an IGBT by using a p-type substrate (p-type emitter layer) having an n-type buffer layer on the top instead of the n-type substrate.

【０１１９】（形成方法Ａ）図１７（ａ）〜１７（ｂ）
に示すように、ｎ型ドレイン層としてのｎ型基板６１に
対し、第１のｎ型ベース層６２をエピタキシャル成長さ
せる。(Forming Method A) FIGS. 17 (a) to 17 (b)
As shown in, the first n-type base layer 62 is epitaxially grown on the n-type substrate 61 as the n-type drain layer.

【０１２０】続いて図１７（ｃ）に示すように、第１の
ｎ型ベース層６２上にマスク６３を形成し、しかる後、
インジウム、ガリウム、ボロン等のいずれかのイオン６
４をイオン注入する。このとき、イオンを高電圧で加速
し、表面から０．２μｍ〜３μｍ程度の深さまで打ち込
むことにより、後のエピタキシャル成長時のｐの拡散を
小さくでき、ｐ型埋込み層のメッシュを細かく形成でき
る。なお、このイオン注入層６５がｐ型埋込み層の元と
なる。イオン注入後、マスク６３を除去し、図１７
（ｄ）に示すように、イオン注入された第１のｎ型ベー
ス層６２の表面上に第２のｎ型ベース層６６をエピタキ
シャル成長させる。Subsequently, as shown in FIG. 17C, a mask 63 is formed on the first n-type base layer 62, and thereafter,
Any ion such as indium, gallium, or boron 6
4 is ion-implanted. At this time, by accelerating the ions at a high voltage and implanting ions to a depth of about 0.2 μm to 3 μm from the surface, the diffusion of p during the subsequent epitaxial growth can be reduced and the mesh of the p-type buried layer can be formed finely. The ion-implanted layer 65 is the source of the p-type buried layer. After the ion implantation, the mask 63 is removed, and FIG.
As shown in (d), a second n-type base layer 66 is epitaxially grown on the surface of the ion-implanted first n-type base layer 62.

【０１２１】以下同様に、イオン注入とエピタキシャル
成長とを繰返すことにより、層数Ｍのｐ型埋込み層をも
つＭＯＳＦＥＴ（又はショットキーバリアダイオード、
ＩＧＢＴ等）を形成することができる。Similarly, by repeating the ion implantation and the epitaxial growth, MOSFET (or Schottky barrier diode, Schottky barrier diode,
IGBT, etc.) can be formed.

【０１２２】（形成方法Ｂ）前述した図１７（ａ）〜１
７（ｂ）と同様にして第１のｎ型ベース層６２を上部に
有するｎ型基板６１を用意する。(Forming Method B) FIGS. 17 (a) -1 mentioned above.
An n-type substrate 61 having a first n-type base layer 62 on its upper portion is prepared in the same manner as in 7 (b).

【０１２３】一方、図１８（ａ）に示すように、このｎ
型基板６１よりも低キャリア密度のｎ型基板６７上にマ
スク６３を形成し、しかる後、インジウム、ガリウム、
ボロン等のいずれかのイオン６４をイオン注入する。イ
オン注入後、図１８（ｂ）に示すように、マスク６３を
除去する。On the other hand, as shown in FIG.
A mask 63 is formed on an n-type substrate 67 having a carrier density lower than that of the mold substrate 61, and then indium, gallium,
Any ion 64 such as boron is ion-implanted. After the ion implantation, the mask 63 is removed as shown in FIG.

【０１２４】続いて図１８（ｃ）に示すように、このイ
オン注入面を前述した第１のｎ型ベース層６２に接着す
る。Subsequently, as shown in FIG. 18C, this ion-implanted surface is bonded to the above-mentioned first n-type base layer 62.

【０１２５】さらに、図１８（ｄ）に示すように、反転
接着したｎ型基板６７をポリッシングして所定の厚さに
形成する。Further, as shown in FIG. 18D, the reverse bonded n-type substrate 67 is polished to a predetermined thickness.

【０１２６】以下同様に、選択イオン注入とウエハ接着
とを繰り返すことにより、任意の層数Ｍのｐ型埋込み層
をもつＭＯＳＦＥＴ（又はショットキーバリアダイオー
ド、ＩＧＢＴ等）を形成することができる。なお、ウエ
ハ接着後、イオン注入及びエピタキシャル成長によりＭ
ＯＳＦＥＴを形成してもよい。Similarly, by repeating selective ion implantation and wafer adhesion, a MOSFET (or Schottky barrier diode, IGBT, etc.) having an arbitrary number M of p-type buried layers can be formed. After the wafer is bonded, M is formed by ion implantation and epitaxial growth.
An OSFET may be formed.

【０１２７】（形成方法Ｃ）前述同様に、図１９（ａ）
〜１９（ｃ）に示すように、ｎ型基板６１上に第１のｎ
型ベース層６２を形成し、第１のｎ型ベース層６２の表
面にイオン注入層６５を選択的に形成する。(Forming Method C) As described above, FIG.
-19 (c), the first n
The mold base layer 62 is formed, and the ion implantation layer 65 is selectively formed on the surface of the first n-type base layer 62.

【０１２８】しかる後、図１９（ｄ）に示すように、こ
の第１のｎ型ベース層６２の表面上に、他のｎ型基板６
８を接着する。Thereafter, as shown in FIG. 19D, another n-type substrate 6 is formed on the surface of the first n-type base layer 62.
Adhere 8

【０１２９】このような形成方法Ｃとしても、形成方法
Ｂと同様に、層数Ｍのｐ型埋込み層をもつＭＯＳＦＥＴ
等を形成することができる。As in the case of the forming method B, the MOSFET having a p-type buried layer having the number of layers M is also used as the forming method C.
Etc. can be formed.

【０１３０】これら形成方法（Ａ）〜（Ｃ）において
は、ｐ型埋込み層は、逐次拡散させてもよい。しかしな
がら、全てのｐ型埋込み層を形成した後、ｐ型ベース層
を形成する際に、同時に拡散させる方がｐ型埋込み層の
大きさ、厚さ及び間隔を均一化する観点から好ましい。In these forming methods (A) to (C), the p-type buried layer may be sequentially diffused. However, it is preferable to diffuse the p-type base layer at the same time when forming the p-type base layer after forming all the p-type buried layers, from the viewpoint of making the size, thickness and interval of the p-type buried layer uniform.

【０１３１】また、層数Ｍのｐ型埋込み層を形成する際
に、形成時の温度などの影響により、上層のｐ型埋込み
層１６よりも下層のｐ型埋込み層１４の方が大きく形成
される場合があるので、図２１に示すように、ｐ型埋込
み層１４，１６における各ｐ型部相互間の間隔を下層の
ｐ型埋込み層１４ほど大きくすることが望ましい。Further, when forming the p-type buried layer having the number M of layers, the lower p-type buried layer 14 is formed larger than the upper p-type buried layer 16 due to the influence of the temperature during the formation. Therefore, as shown in FIG. 21, it is desirable to increase the distance between the p-type portions in the p-type buried layers 14 and 16 as much as the lower p-type buried layer 14.

【０１３２】また、ｐ型埋込み層は、拡散により形成し
なくてもポリシリコンを埋込んで形成してもよい。The p-type buried layer may be formed by burying polysilicon without being formed by diffusion.

【０１３３】（形成方法ｄ）図２０（ａ）〜２０（ｃ）
に示すように、ｎ型ドレイン層としてのｎ型基板６１に
対し、ｎ型ベース層６２をエピタキシャル成長させる。
続いて、所定のパターンにパタ−ニングされたマスク６
３がｎ型ベース層６２上に形成される。次に高エネルギ
ー加速器により、ＢＦ2 等のｐ型不純物層を形成するイ
オン６４がｎ型ベース層６２中に注入される。なお、イ
オン注入時の加速エネルギーを変化させることにより、
所定の深さにイオン注入層６５を形成することができ
る。次に、マスク６３を除去した後、ｎ型基板６１及び
ｎ型ベース層６２が高温で熱処理されることにより、イ
オン注入層６５のイオンは拡散され及び活性化されてｐ
型埋込み層となる。なお、この熱処理により、イオン注
入の際に、図２０（ｂ）の図中点線で囲まれた領域６５
ａに生じた欠陥が消滅され、ｎ型ベース層６２の結晶性
が回復される。(Forming method d) FIGS. 20 (a) to 20 (c)
As shown in, the n-type base layer 62 is epitaxially grown on the n-type substrate 61 as the n-type drain layer.
Subsequently, the mask 6 patterned into a predetermined pattern
3 is formed on the n-type base layer 62. Next, ions 64 forming a p-type impurity layer such as BF 2 are implanted into the n-type base layer 62 by a high energy accelerator. By changing the acceleration energy during ion implantation,
The ion implantation layer 65 can be formed at a predetermined depth. Next, after removing the mask 63, the n-type substrate 61 and the n-type base layer 62 are heat-treated at a high temperature to diffuse and activate the ions in the ion implantation layer 65.
It becomes the mold embedding layer. By this heat treatment, at the time of ion implantation, a region 65 surrounded by a dotted line in FIG.
The defects generated in a are eliminated, and the crystallinity of the n-type base layer 62 is restored.

【０１３４】また、互いに異なる加速エネルギーを用
い、数回、不純物イオンをｎ型ベース層６２中に注入す
ることにより、夫々異なる深さの数層のｐ型電位固定層
を形成することもできる。By implanting impurity ions into the n-type base layer 62 several times by using different acceleration energies, it is possible to form several p-type potential fixed layers having different depths.

【０１３５】次に、このような形成方法に用いられるマ
スクパターンについて説明する。Next, the mask pattern used in such a forming method will be described.

【０１３６】図２２乃至図２９は夫々ｐ型埋込み層を形
成するためのマスクパターンの平面図である。図２２は
ストライプ形状のｐ型埋込み層１４，…を形成するため
のマスクパターンを示す平面図である。このマスクパタ
ーンは、略正方形の枠部７１と、枠部７１の内側に形成
されたストライプ部７２と、枠部７１の内側の略中央に
配置された略正方形の中心部７３とからなり、これら枠
部７１、ストライプ部７２及び中心部７３は互いにつな
がって構成されている。22 to 29 are plan views of mask patterns for forming a p-type buried layer, respectively. 22 is a plan view showing a mask pattern for forming the stripe-shaped p-type buried layers 14, .... This mask pattern is composed of a substantially square frame portion 71, a stripe portion 72 formed inside the frame portion 71, and a substantially square central portion 73 arranged substantially in the center of the frame portion 71. The frame portion 71, the stripe portion 72, and the central portion 73 are connected to each other.

【０１３７】ここで、中心部７３はパンチスルーにより
ｐ型埋込み層１４，…の電位を決定するためのものであ
り、同図２２のXXXV−XXXV線矢視断面図である図３０に
示すように、ゲート電極パッド７４下方にて空乏層の広
がる（図中破線でしめす）領域７５に位置するように位
置合せされる。また、中心部７３は、位置合せによりゲ
ート電極パッド７４の下方に破線で示す広い面積の領域
７５を用いて電位決定しているので、形成工程上のばら
つきにより位置合せがズレても重なる部分が十分あるこ
とから耐圧変化を無くして歩留まり向上を期待でき、ま
た、半導体装置の有効面積の縮小化を回避できる。但
し、耐圧の向上効果のみであれば、位置合せをしなくて
もよい。Here, the central portion 73 is for determining the potential of the p-type buried layers 14, ... By punch-through, and as shown in FIG. 30, which is a sectional view taken along the line XXXV-XXXV in FIG. In addition, the gate electrode pad 74 is positioned below the gate electrode pad 74 in a region 75 where the depletion layer extends (indicated by a broken line in the drawing). Further, since the central portion 73 determines the potential by using the region 75 having a large area indicated by the broken line below the gate electrode pad 74 by the alignment, even if the alignment is misaligned due to variations in the forming process, the overlapping portion is Since it is sufficient, it is possible to expect a yield improvement by eliminating a change in breakdown voltage, and it is possible to avoid reduction of the effective area of the semiconductor device. However, if only the effect of improving the breakdown voltage is provided, the alignment may not be performed.

【０１３８】図２３は図２２の変形パターンを示す平面
図であり、中心部７３と枠部７１との間にストライプ部
７２と直交するように直線状の接続部７６を有してい
る。この接続部７６は、中心部７３と枠部７１とを確実
に電気的に接続するためのものであり、ストライプ部７
２の個々の平行直線の幅よりも広い幅を有している。FIG. 23 is a plan view showing the modified pattern of FIG. 22 and has a linear connecting portion 76 between the central portion 73 and the frame portion 71 so as to be orthogonal to the stripe portion 72. The connecting portion 76 is for reliably electrically connecting the central portion 73 and the frame portion 71, and the stripe portion 7
It has a width greater than the width of the two individual parallel straight lines.

【０１３９】図２４及び図２５はメッシュ形状のｐ型埋
込み層を形成するためのマスクパターンを示す平面図で
あり、夫々図２２又は図２３のストライプ部７２に代え
て、格子状のメッシュ部７７を有している。これらメッ
シュ形状のマスクパターンによれば、ストライプ状のマ
スクパターンを用いた場合よりも高耐圧の半導体装置を
形成することができる。24 and 25 are plan views showing mask patterns for forming a mesh-shaped p-type buried layer. Instead of the stripe portion 72 shown in FIG. 22 or 23, a grid-like mesh portion 77 is shown. have. With these mesh-shaped mask patterns, it is possible to form a semiconductor device having a higher breakdown voltage than when a stripe-shaped mask pattern is used.

【０１４０】図２６はドット状のマスクパターンを示す
平面図である。このマスクパターンは、複数のドット７
８が行方向及び列方向に互いに等間隔に配置されてい
る。ドット状に形成されたｐ型埋込み層は、互いに電気
的に接続されていないので、素子の終端部にてガードリ
ングと同様に作用するため、プレーナ構造の場合、高耐
圧の半導体装置を形成することができる。FIG. 26 is a plan view showing a dot-shaped mask pattern. This mask pattern consists of multiple dots 7
8 are arranged at equal intervals in the row direction and the column direction. Since the p-type buried layers formed in the dot shape are not electrically connected to each other, they act similarly to the guard ring at the terminal end of the element. Therefore, in the case of the planar structure, a high breakdown voltage semiconductor device is formed. be able to.

【０１４１】図２７は図２６の変形パターンを示す平面
図であり、図２６と比べ、各ドット７８が１行毎に半間
隔ずれ、互いに隣り合う行及び列のドット７８と等間隔
に配置される高密度なドットパターンを形成しているた
め、耐圧的に有利である。FIG. 27 is a plan view showing the modified pattern of FIG. 26. Compared with FIG. 26, the dots 78 are displaced by half a space for each row, and are arranged at equal intervals with the dots 78 in the adjacent rows and columns. Since a high-density dot pattern is formed, it is advantageous in terms of pressure resistance.

【０１４２】図２８はストライプ形状で且つ位置合せの
不要なマスクパターンを示す平面図であり、複数の平行
直線からなるストライプ部８１と、ストライプ部８１と
直交するように互いに平行に配置された複数の接続部８
２を有している。この接続部８２は、ストライプ部８１
の個々の平行直線の幅よりも広い幅を有し、ストライプ
部８１の各平行直線相互を確実に電気的に接続する機能
と、パンチスルーによりｐ型埋込み層１４，…の電位を
決定する機能とをもっている。FIG. 28 is a plan view showing a mask pattern which is stripe-shaped and does not require alignment. A stripe portion 81 composed of a plurality of parallel straight lines and a plurality of stripe portions 81 arranged in parallel to each other so as to be orthogonal to the stripe portion 81. Connection part 8
Have two. The connecting portion 82 is the stripe portion 81.
Has a width wider than the width of each parallel straight line, and has a function of reliably electrically connecting the parallel straight lines of the stripe portion 81 with each other, and a function of determining the potentials of the p-type buried layers 14, ... By punch-through. Has.

【０１４３】ここで、各接続部８２の間隔は、少なくと
も１本の接続部８２が各チップの素子部分に位置するよ
う、チップの大きさに基づいて設定されている。なお、
各接続部８２とストライプ部８１とは互いに斜交する関
係でもよい。Here, the interval between the connecting portions 82 is set based on the chip size so that at least one connecting portion 82 is located at the element portion of each chip. In addition,
The connection portions 82 and the stripe portions 81 may be in a relationship of obliquely crossing each other.

【０１４４】図２９は図２８の変形パターンを示す平面
図であり、接続部８２よりも広い幅をもつ方形部８３を
設けている。この方形部８３は、パンチスルーによりｐ
型埋込み層の電位が決定される領域を広くするものであ
り、ｐ型埋込み層の電位の変動を阻止している。また、
この方形部は、位置合せなしでも、各チップの素子部分
には少なくとも１つが入るように大きさ及び間隔が設定
される。FIG. 29 is a plan view showing the modified pattern of FIG. 28, in which a rectangular portion 83 having a width wider than that of the connecting portion 82 is provided. This square portion 83 is p
It widens the region where the potential of the buried layer is determined, and prevents fluctuations in the potential of the p buried layer. Also,
The square portions are sized and spaced so that at least one is included in the element portion of each chip without alignment.

【０１４５】なお、前述した図２２乃至図２９におい
て、枠部７１、中心部７３、接続部７６、接続部８２及
び方形部８３はそれぞれ白抜きで示されているが、実線
以外の白抜き部分もマスクパターンにおける露光部であ
り、その他の部分が遮光部となっている。22 to 29, the frame portion 71, the central portion 73, the connecting portion 76, the connecting portion 82, and the rectangular portion 83 are shown as white portions, but white portions other than solid lines are shown. Also is an exposed portion in the mask pattern, and the other portion is a light shielding portion.

【０１４６】（第８の実施の形態）次に、本発明の第８
の実施の形態に係るＭＯＳＦＥＴについて説明する。(Eighth Embodiment) Next, the eighth embodiment of the present invention
The MOSFET according to the embodiment will be described.

【０１４７】図３１はこのＭＯＳＦＥＴの終端構造を示
す模式図であり、図１と同一部分には同一符号を付して
その詳しい説明は省略し、ここでは異なる部分について
のみ述べる。FIG. 31 is a schematic diagram showing the termination structure of this MOSFET. The same parts as those in FIG. 1 are designated by the same reference numerals and detailed description thereof will be omitted. Only different parts will be described here.

【０１４８】すなわち、このＭＯＳＦＥＴは、各実施の
形態の変形構成であり、プレーナ構造の素子終端部での
耐圧劣化の阻止を図るものであって、具体的には図３１
に示すように、各ｐ型埋込み層１４，１６の外周側に、
素子上方からみてｐ型埋込み層１４，１６を取り囲むよ
うに略方形状に形成された複数の埋込みガードリング９
１を備えている。That is, this MOSFET is a modification of each of the embodiments and is intended to prevent breakdown of breakdown voltage at the element termination portion of the planar structure. Specifically, FIG.
As shown in, on the outer peripheral side of each p-type buried layer 14, 16,
A plurality of embedded guard rings 9 formed in a substantially rectangular shape so as to surround the p-type embedded layers 14 and 16 when viewed from above the element.
1 is provided.

【０１４９】従って、このような終端構造によれば、各
埋込みガードリング９１により、素子終端部における等
電位線９２の間隔を広げて電界強度を緩和すると共に、
素子終端部の耐圧劣化を阻止することができる。Therefore, according to such a termination structure, each embedded guard ring 91 widens the interval between the equipotential lines 92 at the element termination portion to relax the electric field strength, and
It is possible to prevent the breakdown voltage of the element end portion from deteriorating.

【０１５０】（第９の実施の形態）次に、本発明の第９
の実施の形態に係るＭＯＳＦＥＴについて説明する。(Ninth Embodiment) Next, the ninth embodiment of the present invention will be described.
The MOSFET according to the embodiment will be described.

【０１５１】図３２はこのＭＯＳＦＥＴの終端構造を示
す模式図であり、図３１と同一部分には同一符号を付し
てその詳しい説明は省略し、ここでは異なる部分につい
てのみ述べる。FIG. 32 is a schematic diagram showing the termination structure of this MOSFET. The same parts as those in FIG. 31 are designated by the same reference numerals and detailed description thereof will be omitted. Only different parts will be described here.

【０１５２】すなわち、このＭＯＳＦＥＴは、上記実施
の形態の変形構成であり、プレーナ構造の素子終端部で
の耐圧劣化の阻止を図るものであって、具体的には図３
２に示すように、各ｐ型埋込み層１４，１６の外周部
に、素子上方からみてｐ型埋込み層１４，１６を取り囲
むように略方形状に形成され、ｐ型埋込み層１４，１６
よりも低いキャリア密度を有する埋込みリサーフ（RESU
RF）９３を備えている。That is, this MOSFET is a modified structure of the above-mentioned embodiment, and is intended to prevent breakdown voltage deterioration at the element termination portion of the planar structure. Specifically, FIG.
As shown in FIG. 2, the p-type buried layers 14 and 16 are formed in a substantially rectangular shape on the outer peripheral portions of the p-type buried layers 14 and 16 so as to surround the p-type buried layers 14 and 16 when viewed from above the element.
Embedded RESURF (RESU with lower carrier density than
RF) 93.

【０１５３】このような構成としても、第８の実施例と
同様の効果を得ることができる。Even with such a structure, the same effect as that of the eighth embodiment can be obtained.

【０１５４】（第１０の実施の形態）次に、本発明の第
１０の実施の形態に係るＭＯＳＦＥＴについて説明す
る。(Tenth Embodiment) Next, a MOSFET according to a tenth embodiment of the present invention will be described.

【０１５５】図３３はこのＭＯＳＦＥＴの終端構造を示
す模式図であり、図１と同一部分には同一符号を付し、
ほぼ同一部分にはａの添字を付してその詳しい説明は省
略し、ここでは異なる部分についてのみ述べる。FIG. 33 is a schematic diagram showing the termination structure of this MOSFET. The same parts as those in FIG.
Substantially the same parts are denoted by a subscript a and detailed description thereof is omitted, and only different parts will be described here.

【０１５６】すなわち、このＭＯＳＦＥＴは、第１の実
施の形態の変形構成であり、ベベル構造又はメサエッチ
ングによる終端構造をもつものであり、具体的には図３
３に示すように、素子終端部に傾斜を有するベベル構造
が形成され、且つ素子終端部のｐ型埋込み層１４ａ，１
６ａがストライプ部又はメッシュ部を取り囲むように略
方形の枠形状に形成されている。That is, this MOSFET is a modification of the first embodiment and has a bevel structure or a termination structure by mesa etching. Specifically, FIG.
As shown in FIG. 3, a bevel structure having an inclination is formed at the device end portion, and the p-type buried layers 14a, 1 at the device end portion are formed.
6a is formed in a substantially rectangular frame shape so as to surround the stripe portion or the mesh portion.

【０１５７】従って、このような終端構造によれば、ｐ
ｎ接合終端の電界を緩和するベベル構造の利点に加え、
終端部のｐ型埋込み層１４ａ，１６ａが枠形状を有して
いるので終端部の電位を決定でき、もって、動作の信頼
性向上を図ることができる。Therefore, according to such a termination structure, p
In addition to the advantage of the bevel structure that relaxes the electric field at the n-junction termination,
Since the p-type buried layers 14a and 16a at the terminal end have a frame shape, the potential at the terminal end can be determined, and thus the reliability of the operation can be improved.

【０１５８】（第１１の実施の形態）次に、本発明の第
１１の実施の形態に係るＭＯＳＦＥＴについて説明す
る。(Eleventh Embodiment) Next, a MOSFET according to an eleventh embodiment of the present invention will be described.

【０１５９】図３４はこのＭＯＳＦＥＴの終端構造を示
す模式図であり、図３３と同一部分には同一符号を付し
てその詳しい説明は省略し、ここでは異なる部分につい
てのみ述べる。FIG. 34 is a schematic diagram showing the termination structure of this MOSFET. The same parts as those in FIG. 33 are designated by the same reference numerals and detailed description thereof will be omitted. Only different parts will be described here.

【０１６０】すなわち、このＭＯＳＦＥＴは、第１０の
実施の形態の変形構成であり、ベベル構造又はメサエッ
チングによる終端構造にてｐ型埋込み層１４ａ，１６ｂ
の形状を変えたものであって、具体的には図３４に示す
ように、ｐ型埋込み層１４ａ，１６ａの枠形状に代え
て、ストライプ部又はメッシュ部が素子終端部にまで延
長して形成されている。That is, this MOSFET is a modified structure of the tenth embodiment, and the p-type buried layers 14a and 16b have a bevel structure or a termination structure by mesa etching.
34. Specifically, as shown in FIG. 34, instead of the frame shape of the p-type buried layers 14a and 16a, a stripe portion or a mesh portion is formed to extend to the element end portion. Has been done.

【０１６１】従って、このような終端構造によれば、ｐ
ｎ接合端面の電界集中を緩和するベベル構造の利点に加
え、ｐ型埋込み層１４，１６が枠形状をもたないので、
ｐ型埋込み層１４，１６のマスクパターンの位置合せを
省略することができる。Therefore, according to such a termination structure, p
In addition to the advantage of the bevel structure that alleviates the electric field concentration on the n-junction end face, the p-type buried layers 14 and 16 do not have a frame shape
The alignment of the mask patterns of the p-type buried layers 14 and 16 can be omitted.

【０１６２】次に、本発明の第１２の実施の形態に係る
ＭＯＳＦＥＴについて説明する。Next explained is a MOSFET according to the twelfth embodiment of the invention.

【０１６３】図３５はこのＭＯＳＦＥＴの構成を模式的
に示す断面図であり、図３６はこのＭＯＳＦＥＴの平面
図である。このＭＯＳＦＥＴは、基板１０１上にｎ- 型
層（又はｐ- 型層）１０２が形成され、ｎ- 型層１０２
上に不純物総量（ドーズ量）が１×１０12ｃｍ-2以上の
ｎ型オフセット層１０３が選択的に形成される。ｎ型オ
フセット層１０３表面には、ｎ型ドレイン層１０５がｎ
- 型層１０２に達する深さに選択的に形成される一方、
ｐ型埋込み層１０４がドット状に選択的に形成されてい
る。なお、ｐ型埋込み層１０４は、図３７に示すよう
に、ストライプ状としてもよい。また、ｐ型埋込み層１
０４におけるドット状（又はストライプ状）のパターン
は、図３７（又は図３６）と異なって不揃いでもよい。FIG. 35 is a sectional view schematically showing the structure of this MOSFET, and FIG. 36 is a plan view of this MOSFET. In this MOSFET, an n-type layer (or p-type layer) 102 is formed on a substrate 101, and an n-type layer 102 is formed.
An n-type offset layer 103 having a total impurity amount (dose amount) of 1 × 10 12 cm −2 or more is selectively formed thereon. An n-type drain layer 105 is formed on the surface of the n-type offset layer 103.
-While selectively formed to a depth reaching the mold layer 102,
The p-type buried layer 104 is selectively formed in a dot shape. The p-type buried layer 104 may have a stripe shape as shown in FIG. In addition, the p-type buried layer 1
The dot-shaped (or stripe-shaped) pattern in 04 may be irregular, unlike FIG. 37 (or FIG. 36).

【０１６４】また、ｎ- 型層１０２表面にはｐ型ベース
層１０６がｎ型オフセット層１０３に接するように選択
的に形成され、ｐ型ベース層１０６表面にはｎ型ソース
層１０７が選択的に形成されている。A p-type base layer 106 is selectively formed on the surface of the n − -type layer 102 so as to be in contact with the n-type offset layer 103, and an n-type source layer 107 is selectively formed on the surface of the p-type base layer 106. Is formed in.

【０１６５】ｐ型ベース層１０６上及びｎ型ソース層１
０７上にはソース電極１０８が選択的に形成されてい
る。ｎ型ソース層１０７上、ｐ型ベース層１０６上及び
ｎ型オフセット層１０３上には酸化膜１０９を介してゲ
ート電極１１０が選択的に埋込み形成されている。On the p-type base layer 106 and the n-type source layer 1
A source electrode 108 is selectively formed on 07. A gate electrode 110 is selectively formed on the n-type source layer 107, the p-type base layer 106, and the n-type offset layer 103 via an oxide film 109.

【０１６６】ｎ型ドレイン層１０５上には、選択的にド
レイン電極１１１が形成されている。A drain electrode 111 is selectively formed on the n-type drain layer 105.

【０１６７】ここで、ｎ型オフセット層１０３の表面に
ｐ型埋込み層１０４を形成することにより、前述同様に
ｎ型オフセット層１０３では不純物量を増加可能となる
ため、オン抵抗を低減することができる。Here, by forming the p-type buried layer 104 on the surface of the n-type offset layer 103, it is possible to increase the amount of impurities in the n-type offset layer 103 as described above, so that the on-resistance can be reduced. it can.

【０１６８】（第１３の実施の形態）次に、本発明の第
１３の実施の形態に係るＭＯＳＦＥＴについて説明す
る。(Thirteenth Embodiment) Next, a MOSFET according to the thirteenth embodiment of the present invention will be described.

【０１６９】図３８はこのＭＯＳＦＥＴの構成を示す模
式図であり、図３５と同一部分には同一符号を付してそ
の詳しい説明は省略し、ここでは異なる部分についての
み述べる。FIG. 38 is a schematic diagram showing the structure of this MOSFET. The same parts as those in FIG. 35 are designated by the same reference numerals and detailed description thereof will be omitted. Only different parts will be described here.

【０１７０】すなわち、このＭＯＳＦＥＴは、第１２の
実施の形態の変形構成であり、具体的には図３８に示す
ように、ｐ型埋込み層１０４に代えて、ｎ型オフセット
層１０３表面に、ｐ型ソース層１０６の深さと同様の深
さまで選択的に形成されたｐ型埋込み層１１２を備えて
いる。That is, this MOSFET has a modified structure of the twelfth embodiment. Specifically, as shown in FIG. 38, instead of the p-type buried layer 104, the p-type on the surface of the n-type offset layer 103. The p-type buried layer 112 is selectively formed to a depth similar to the depth of the mold source layer 106.

【０１７１】ここで、ｐ型埋込み層１１２は、ｎ型オフ
セット層１０３上に形成されたマスクにＲＩＥ等により
トレンチ（例えば丸穴）を形成し、イオン注入等により
トレンチを介してｐ型のドーパントをｎ型オフセット層
１０３及びｎ- 型層１０２にドーピングし、マスクを除
去することにより形成可能である。なお、ｎ型オフセッ
ト層１０３表面にｎ- 型層１０２まで到達する深さのト
レンチを形成し、このトレンチにｐ型多結晶を埋込んで
もよい。Here, the p-type buried layer 112 has a trench (for example, a round hole) formed in the mask formed on the n-type offset layer 103 by RIE or the like, and a p-type dopant is formed through the trench by ion implantation or the like. Can be formed by doping the n-type offset layer 103 and the n-type layer 102 with and removing the mask. A trench having a depth reaching the n-type layer 102 may be formed on the surface of the n-type offset layer 103, and the p-type polycrystal may be embedded in the trench.

【０１７２】このような構成としても、第１２の実施の
形態と同様の効果を得ることができる。With such a structure, the same effect as that of the twelfth embodiment can be obtained.

【０１７３】（第１４の実施の形態）次に、本発明の第
１４の実施の形態に係るＭＯＳＦＥＴについて説明す
る。(Fourteenth Embodiment) Next, a MOSFET according to a fourteenth embodiment of the present invention will be described.

【０１７４】図３９はこのＭＯＳＦＥＴの構成を示す模
式図である。このＭＯＳＦＥＴは、ＳＯＩ（Silicon-On
-Insulator）基板を用いたものであり、基板１２１上に
埋込み酸化膜１２２及びＳｉのｎ型オフセット層１２３
が順次形成されている。FIG. 39 is a schematic diagram showing the structure of this MOSFET. This MOSFET is SOI (Silicon-On
-Insulator) substrate, a buried oxide film 122 and an n-type offset layer 123 of Si are formed on the substrate 121.
Are sequentially formed.

【０１７５】ｎ型オフセット層１２３はドーズ量が１×
１０12ｃｍ-2以上であり、表面にｐ型ベース層１２４及
びｎ型ドレイン層１２５が選択的に形成され、ｐ型ベー
ス層１２４は表面にｎ型ソース層１２６が選択的に形成
されている。また、ｎ型オフセット層１２３は、ｐ型ベ
ース層１２４とｎ型ドレイン層１２５との間の表面から
埋込み酸化膜１２２に達するｐ型埋込み層１２７が例え
ばＲＩＥによる丸穴形状で選択的に形成されている。The dose of the n-type offset layer 123 is 1 ×
10 12 cm −2 or more, the p-type base layer 124 and the n-type drain layer 125 are selectively formed on the surface, and the n-type source layer 126 is selectively formed on the surface of the p-type base layer 124. . In the n-type offset layer 123, the p-type buried layer 127 reaching the buried oxide film 122 from the surface between the p-type base layer 124 and the n-type drain layer 125 is selectively formed in a round hole shape by RIE, for example. ing.

【０１７６】ｐ型ベース層１２４上及びｎ型ソース層１
２６上にはソース電極１２８が選択的に形成されてい
る。ｎ型ソース層１２６上、ｐ型ベース層１２４上及び
ｎ型オフセット層１２３上には酸化膜１２９を介してゲ
ート電極１３０が選択的に埋込み形成されている。On p-type base layer 124 and n-type source layer 1
A source electrode 128 is selectively formed on 26. A gate electrode 130 is selectively embedded and formed on the n-type source layer 126, the p-type base layer 124, and the n-type offset layer 123 via an oxide film 129.

【０１７７】ｎ型ドレイン層１２５上には、選択的にド
レイン電極１３１が形成されている。A drain electrode 131 is selectively formed on the n-type drain layer 125.

【０１７８】このような構成としても、第１２及び第１
３の実施の形態と同様の効果を得ることができる。Even with such a configuration, the twelfth and first
The same effect as that of the third embodiment can be obtained.

【０１７９】（第１５の実施の形態）次に、本発明の第
１５の実施の形態に係るＭＯＳＦＥＴについて説明す
る。(Fifteenth Embodiment) Next, a MOSFET according to the fifteenth embodiment of the present invention will be described.

【０１８０】図４０はこのＭＯＳＦＥＴの構成を示す模
式図であり、図４１は図４０のXLVI−XLVI線矢視断面図
であって、図３５と同一部分には同一符号を付してその
詳しい説明は省略し、ここでは異なる部分についてのみ
述べる。FIG. 40 is a schematic diagram showing the structure of this MOSFET, and FIG. 41 is a sectional view taken along the line XLVI-XLVI of FIG. 40, in which the same parts as in FIG. Description is omitted, and only different parts will be described here.

【０１８１】すなわち、このＭＯＳＦＥＴは、第１２の
実施の形態の変形構成であり、形成工程上のばらつきに
よる耐圧劣化を阻止するものであって、具体的には図４
０及び図４１に示すように、ｎ型オフセット層１０３
上、ｐ型埋込み層１０４上及びｎ型ドレイン層１０５上
に絶縁膜１４１が形成され、この絶縁膜１４１表面に各
ｐ型埋込み層１０４に達するようにコンタクトホール１
４２が形成され、ゲート電極から等距離の各ｐ型埋込み
層１０４相互を接続するように４本の等電位電極１４３
が形成されている。That is, this MOSFET has a modified structure of the twelfth embodiment and prevents deterioration of breakdown voltage due to variations in the forming process. Specifically, FIG.
0 and FIG. 41, the n-type offset layer 103
An insulating film 141 is formed on the p-type buried layer 104 and the n-type drain layer 105, and contact holes 1 are formed on the surface of the insulating film 141 so as to reach the p-type buried layers 104.
42 are formed, and four equipotential electrodes 143 are formed so as to connect each p-type buried layer 104 equidistant from the gate electrode.
Are formed.

【０１８２】ここで、４本の等電位電極１４３は、コン
タクトホール１４２の径よりも長い幅を有し、この径か
ら突出る部分がドレイン電極１１１側に突出していわゆ
るフィールドプレート構造となるように形成されてい
る。Here, each of the four equipotential electrodes 143 has a width longer than the diameter of the contact hole 142, and a portion protruding from this diameter projects toward the drain electrode 111 to form a so-called field plate structure. Has been formed.

【０１８３】従って、等電位電極１４３により、ゲート
電極１１０からの等距離の各ｐ型埋込み層１０４が等電
位に接続されて形成工程上のばらつきによる耐圧劣化を
阻止でき、且つ、等電位電極１４３がフィールドプレー
ト構造をとることにより、ｐ型埋込み層１０４での電界
集中を阻止して耐圧の向上を図ることができる。Therefore, the equipotential electrodes 143 connect the p-type buried layers 104 equidistant from the gate electrode 110 to the equipotential, and prevent the breakdown voltage from deteriorating due to variations in the formation process, and the equipotential electrodes 143. By adopting the field plate structure, it is possible to prevent electric field concentration in the p-type buried layer 104 and improve the breakdown voltage.

【０１８４】（第１６の実施の形態）次に、本発明の第
１６の実施の形態に係るＭＯＳＦＥＴについて説明す
る。(Sixteenth Embodiment) Next, a MOSFET according to the sixteenth embodiment of the present invention will be described.

【０１８５】図４２はこのＭＯＳＦＥＴの構成を示す模
式図であり、図４０と同一部分には同一符号を付してそ
の詳しい説明は省略し、ここでは異なる部分についての
み述べる。FIG. 42 is a schematic diagram showing the structure of this MOSFET. The same parts as those in FIG. 40 are designated by the same reference numerals and detailed description thereof will be omitted. Only different parts will be described here.

【０１８６】すなわち、このＭＯＳＦＥＴは、第１５の
実施の形態の変形構成であり、ｐ型埋込み層による抵抗
ＲJFETの低下を図るものであって、具体的には図４２に
示すように、ｎ型オフセット層１０３内のｐ型埋込み層
１０４を省略し、ｎ型オフセット層１０３上及びｎ型ド
レイン層１０５上に絶縁膜１４１が形成され、この絶縁
膜表面にｎ型オフセット層に達するように複数のコンタ
クトホール１４２がドット状（又は図３７と同様のスト
ライプ状）に形成され、コンタクトホール１４２に埋込
まれたｐ形多結晶によりｐ型埋込み層１４４が形成さ
れ、前述同様に、ゲート電極１１０から等距離の各ｐ型
埋込み層１４４相互を接続するように４本のｐ型接続層
１４５が形成されている。That is, this MOSFET has a modified structure of the fifteenth embodiment and is intended to reduce the resistance RJFET by the p-type buried layer. Specifically, as shown in FIG. The p-type buried layer 104 in the offset layer 103 is omitted, an insulating film 141 is formed on the n-type offset layer 103 and the n-type drain layer 105, and a plurality of insulating films 141 are formed on the surface of the insulating film so as to reach the n-type offset layer. The contact hole 142 is formed in a dot shape (or a stripe shape similar to FIG. 37), and the p-type buried layer 144 is formed by the p-type polycrystal embedded in the contact hole 142. Four p-type connecting layers 145 are formed so as to connect the p-type buried layers 144 that are equidistant from each other.

【０１８７】ここで、４本のｐ型接続層１４５は、前述
同様に、フィールドプレート構造となるように形成され
ている。Here, the four p-type connection layers 145 are formed so as to have a field plate structure as described above.

【０１８８】従って、第１５の実施の形態の効果に加
え、ｐ形埋込み層１４４をｎ型オフセット層１０３上に
形成したことにより、ｐ型埋込み層１４４による抵抗Ｒ
JFETを低下させることができる。Therefore, in addition to the effects of the fifteenth embodiment, since the p-type buried layer 144 is formed on the n-type offset layer 103, the resistance R due to the p-type buried layer 144 is increased.
The JFET can be lowered.

【０１８９】（第１７の実施の形態）次に、本発明の第
１７の実施の形態に係るＭＯＳＦＥＴについて説明す
る。(Seventeenth Embodiment) Next, a MOSFET according to a seventeenth embodiment of the present invention will be described.

【０１９０】図４３はこのＭＯＳＦＥＴの構成を示す模
式図であり、図４０と同一部分には同一符号を付してそ
の詳しい説明は省略し、ここでは異なる部分についての
み述べる。FIG. 43 is a schematic diagram showing the structure of this MOSFET. The same parts as those in FIG. 40 are designated by the same reference numerals and detailed description thereof will be omitted. Only different parts will be described here.

【０１９１】すなわち、このＭＯＳＦＥＴは、第１２の
実施の形態の変形構成であり、ＳＩＰＯＳ（Semi-Insul
ating POlycrystalline Silicon ）等の抵抗膜を用いて
各ｐ型埋込み層１０４の電位を固定するものである。That is, this MOSFET has a modified structure of the twelfth embodiment, and has a SIPOS (Semi-Insul) structure.
The potential of each p-type buried layer 104 is fixed by using a resistance film such as ating POlycrystalline silicon).

【０１９２】本実施形態に係るＭＯＳＦＥＴは、ＳＩＰ
ＯＳ等の高抵抗膜を介して電極に接続された状態に関す
る。The MOSFET according to this embodiment is SIP
It relates to a state of being connected to an electrode through a high resistance film such as OS.

【０１９３】具体的にはこのＭＯＳＦＥＴは、図４３に
示すように、ｎ型オフセット層１０３上、ｐ型埋込み層
１０４上及びｎ型ドレイン層１０５上に絶縁膜１４１が
形成され、この絶縁膜１４１表面に各ｐ型埋込み層１０
４に達するようにコンタクトホール１４２が形成され、
この絶縁膜１４１上にゲート電極１１０からドレイン電
極１１１に向けて各ｐ型埋込み層１０４相互と当該両電
極１１０，１１１を接続するようにＳＩＰＯＳ部１４６
が形成されている。Specifically, in this MOSFET, as shown in FIG. 43, an insulating film 141 is formed on the n-type offset layer 103, the p-type buried layer 104 and the n-type drain layer 105, and the insulating film 141 is formed. Each p-type buried layer 10 on the surface
The contact hole 142 is formed to reach 4
The SIPOS portion 146 is formed on the insulating film 141 so as to connect the p-type buried layers 104 to each other and the electrodes 110 and 111 from the gate electrode 110 to the drain electrode 111.
Are formed.

【０１９４】従って、ＳＩＰＯＳ部１４６の有する電気
抵抗により、ゲート電極１１０とドレイン電極１１１と
の間の電圧が各ｐ型埋込み層１０４に分担され、各ｐ型
埋込み層１０４が電位固定されるため、高耐圧化を期待
することができる。Therefore, due to the electric resistance of the SIPOS portion 146, the voltage between the gate electrode 110 and the drain electrode 111 is shared by each p-type buried layer 104, and the potential of each p-type buried layer 104 is fixed. High breakdown voltage can be expected.

【０１９５】（第１８の実施の形態）次に、本発明の第
１８の実施の形態に係るＭＯＳＦＥＴについて説明す
る。(Eighteenth Embodiment) Next, a MOSFET according to an eighteenth embodiment of the present invention will be described.

【０１９６】図４４はこのＭＯＳＦＥＴの構成を示す模
式図であり、図４０と同一部分には同一符号を付してそ
の詳しい説明は省略し、ここでは異なる部分についての
み述べる。FIG. 44 is a schematic diagram showing the structure of this MOSFET. The same parts as those in FIG. 40 are designated by the same reference numerals and detailed description thereof will be omitted. Only different parts will be described here.

【０１９７】すなわち、このＭＯＳＦＥＴは、第１２又
は第１７の実施の形態の変形構成であり、ＳＩＰＯＳ等
の抵抗膜を用いて各ｐ型埋込み層の電位を固定するもの
であり、具体的には図４４に示すように、ｎ型オフセッ
ト層１０３上、ｐ型埋込み層１０４上及びｎ型ドレイン
層１０５上に絶縁膜１４１が形成され、この絶縁膜１４
１表面に各ｐ型埋込み層１０４に達するようにコンタク
トホール１４２が形成され、この絶縁膜１４１上にソー
ス電極１０８からドレイン電極１１１に向けて各ｐ型埋
込み層１０４相互と当該両電極１０８，１１１を接続す
るようにＳＩＰＯＳ部１４７が形成されている。That is, this MOSFET has a modified structure of the twelfth or seventeenth embodiment, in which the potential of each p-type buried layer is fixed by using a resistance film such as SIPOS. As shown in FIG. 44, an insulating film 141 is formed on the n-type offset layer 103, the p-type buried layer 104, and the n-type drain layer 105.
A contact hole 142 is formed on one surface so as to reach each p-type buried layer 104, and each p-type buried layer 104 and both electrodes 108, 111 are formed on the insulating film 141 from the source electrode 108 toward the drain electrode 111. The SIPOS unit 147 is formed so as to connect to each other.

【０１９８】従って、ＳＩＰＯＳ部１４７の有する電気
抵抗により、ソース電極１０８とドレイン電極１１１と
の間の電圧が各ｐ型埋込み層１０４に分担され、各ｐ型
埋込み層１０４が電位固定されるため、高耐圧化を期待
することができる。Therefore, due to the electric resistance of the SIPOS portion 147, the voltage between the source electrode 108 and the drain electrode 111 is shared by each p-type buried layer 104, and the potential of each p-type buried layer 104 is fixed. High breakdown voltage can be expected.

【０１９９】（第１９の実施の形態）次に、本発明の第
１９の実施の形態に係るＭＯＳＦＥＴについて説明す
る。(Nineteenth Embodiment) Next, a MOSFET according to a nineteenth embodiment of the present invention will be described.

【０２００】図４５はこのＭＯＳＦＥＴの構成を模式的
に示す断面図である。このＭＯＳＦＥＴは、ｎ型ドレイ
ン層としてのｎ型基板２０１上にｎ型ベース層２０２が
形成され、ｎ型ベース層２０２内にはストライプ状のｐ
型埋込み層２１０が形成されている。また、ｎ型ベース
層２０２の表面にはｐ型ベース層２０３が形成されてい
る。ｐ型ベース層２０３およびｎ型ベース層２０２内に
は、ｐ型ベース層２０３を貫通し、ｎ型ベース層２０２
の途中の深さまで達する深さの複数のトレンチ２０４が
形成される。トレンチ２０４内にはゲート絶縁膜２０５
を介してゲート電極２０６が埋め込み形成されている。FIG. 45 is a sectional view schematically showing the structure of this MOSFET. In this MOSFET, an n-type base layer 202 is formed on an n-type substrate 201 as an n-type drain layer, and stripe-shaped p layers are formed in the n-type base layer 202.
A mold embedding layer 210 is formed. A p-type base layer 203 is formed on the surface of the n-type base layer 202. In the p-type base layer 203 and the n-type base layer 202, the p-type base layer 203 is penetrated and
A plurality of trenches 204 having a depth reaching the middle depth are formed. A gate insulating film 205 is formed in the trench 204.
A gate electrode 206 is embedded and formed via the.

【０２０１】ｐ型ベース層２０３の表面内にはトレンチ
２０４の上部に接してｎ型ソース層２０７が形成されて
いる。ｐ型ベース層２０３およびｎ型ソース層２０７の
両方にコンタクトするようにソース電極２０８が設けら
れている。また、ｎ型基板２０１には、ｎ型ベース層２
０２とは反対側の表面上にドレイン電極２０９が形成さ
れている。An n-type source layer 207 is formed in the surface of the p-type base layer 203 in contact with the upper portion of the trench 204. A source electrode 208 is provided so as to contact both the p-type base layer 203 and the n-type source layer 207. In addition, the n-type base layer 2 is formed on the n-type substrate 201.
A drain electrode 209 is formed on the surface opposite to 02.

【０２０２】ここで、ｐ型埋込み層２１０は、前述同様
に、複数のストライプ状のｐ型領域が終端部にて互いに
接続されて形成されている。Here, the p-type buried layer 210 is formed by connecting a plurality of stripe-shaped p-type regions to each other at the terminal end, as described above.

【０２０３】次に、このようなＭＯＳＦＥＴの作用を説
明する。Next, the operation of such a MOSFET will be described.

【０２０４】始めに、このＭＯＳＦＥＴのオン状態につ
いて述べる。First, the on-state of this MOSFET will be described.

【０２０５】いま、ソース電極２０８に対して正となる
電圧がドレイン電極２０９に印加された状態で、ゲート
電極２０６が正バイアスされたとする。このゲート電極
２０６の正バイアスにより、ｐ型ベース層２０３のトレ
ンチ２０４に接した部分はｎ型の反転層が形成される。
よって、電子がこの反転層を通ってｎ型ソース層２０７
からｎ型ベース層２０２に流れ、ＭＯＳＦＥＴが導通状
態となる。Now, it is assumed that the gate electrode 206 is positively biased in the state where a voltage which is positive with respect to the source electrode 208 is applied to the drain electrode 209. By the positive bias of the gate electrode 206, an n-type inversion layer is formed in the portion of the p-type base layer 203 in contact with the trench 204.
Therefore, electrons pass through the inversion layer and the n-type source layer 207.
To the n-type base layer 202, the MOSFET becomes conductive.

【０２０６】次に、このＭＯＳＦＥＴのオフ状態につい
て説明する。Next, the off state of this MOSFET will be described.

【０２０７】いま、ゲート電極２０６が０バイアス又は
負バイアスされた状態で、ソース電極２０８に対して正
となる電圧がドレイン電極２０９に印加されたとする。It is now assumed that a positive voltage with respect to the source electrode 208 is applied to the drain electrode 209 while the gate electrode 206 is biased to 0 or negative.

【０２０８】このとき、ｎ型ベース層２０２では、ｐ型
ベース層２０３からドレイン電極２０９に向けて空乏層
が広がり、各トレンチ２０４に挟まれたｎ型ベース層２
０２内に、電界の最強点が発生する。At this time, in the n-type base layer 202, a depletion layer spreads from the p-type base layer 203 toward the drain electrode 209, and the n-type base layer 2 sandwiched between the trenches 204 is formed.
In 02, the strongest point of the electric field occurs.

【０２０９】さらに、ソース−ドレイン間電圧が上昇す
ると、空乏層がｐ型埋込み層２１０に到達し、ｐ型埋込
み層２１０はパンチスルー状態となって電位が固定され
る。またさらに、ソース−ドレイン間電圧が上昇する
と、空乏層はｐ型埋込み層２１０からドレイン電極２０
９側に広がる。したがって、ｎ型ベース層２０２内の電
界最強点の電界は固定されて上昇が阻止される。Further, when the source-drain voltage rises, the depletion layer reaches the p-type buried layer 210, and the p-type buried layer 210 becomes a punch-through state and the potential is fixed. Furthermore, when the source-drain voltage rises, the depletion layer changes from the p-type buried layer 210 to the drain electrode 20.
Spread on the 9 side. Therefore, the electric field at the strongest electric field in the n-type base layer 202 is fixed and prevented from rising.

【０２１０】ここで、ｐ型埋込み層２１０とトレンチ２
０４との間の距離と、ｎ型ベース層２０２の不純物濃度
とを、電界最強点の電界がｎ型ベース層２０２の電界強
度の限界値を越えないように設計することにより、半導
体装置の高耐圧化、低抵抗化を図ることができる。Here, the p-type buried layer 210 and the trench 2 are formed.
04 and the impurity concentration of the n-type base layer 202 are designed so that the electric field at the strongest electric field does not exceed the limit value of the electric field strength of the n-type base layer 202. The breakdown voltage and the resistance can be reduced.

【０２１１】また、ｎ型ベース層２０２内にｐ型埋込み
層２１０を複数積層することにより、更に高耐圧化、低
抵抗化を図ることができる。Further, by stacking a plurality of p-type buried layers 210 in the n-type base layer 202, higher breakdown voltage and lower resistance can be achieved.

【０２１２】（第２０の実施の形態）図４６は本発明の
第２０の実施の形態に係る半導体装置の構成を模式的に
示す断面図である。この半導体装置は、ｎ型ドレイン層
としてのｎ型基板２１１上にｎ型ベース層２１２が形成
され、ｎ型ベース層２１２内にはストライプ状のｐ型埋
込み層２２０が形成されている。また、ｎ型ベース層２
１２の表面にはｎ型ソース層２１３が形成されている。
また、ｎ型ベース層２１２内にはｐ型ベース層２１４が
埋め込み形成されている。各々のｐ型ベース層２１４は
電気的に接続されており、ｐ型ベース層２１４に接して
ベース電極２１５が設けられている。またｎ型ソース層
２１３の表面にはソース電極２１６が設けられている。
さらに、ｎ型基板２１１には、ｎ型ベース層２１２とは
反対側の表面上にドレイン電極２１７が形成されてい
る。(Twentieth Embodiment) FIG. 46 is a sectional view schematically showing the structure of a semiconductor device according to a twentieth embodiment of the present invention. In this semiconductor device, an n-type base layer 212 is formed on an n-type substrate 211 as an n-type drain layer, and a stripe-shaped p-type buried layer 220 is formed in the n-type base layer 212. In addition, the n-type base layer 2
An n-type source layer 213 is formed on the surface of 12.
A p-type base layer 214 is embedded in the n-type base layer 212. Each p-type base layer 214 is electrically connected, and a base electrode 215 is provided in contact with the p-type base layer 214. A source electrode 216 is provided on the surface of the n-type source layer 213.
Further, on the n-type substrate 211, a drain electrode 217 is formed on the surface opposite to the n-type base layer 212.

【０２１３】次に、この半導体装置の動作を説明する。Next, the operation of this semiconductor device will be described.

【０２１４】いま、ベース電極２１５が０バイアスされ
た状態で、ソース電極２１６に対して正となる電圧がド
レイン電極２１７に印加されたとする。半導体装置は、
電子がｎ型ソース層２１３から各ｐ型ベース層２１４の
間を通ってｎ型ドレイン層２１１に流れ、導通状態とな
る。It is now assumed that a positive voltage with respect to the source electrode 216 is applied to the drain electrode 217 while the base electrode 215 is biased to 0. Semiconductor device
Electrons flow from the n-type source layer 213 between the p-type base layers 214 to the n-type drain layer 211, and become conductive.

【０２１５】ここで、ベース電極２１５を正バイアス状
態にすると、正孔がｐ型ベース層２１４からｎ型ベース
層２１２中に注入され、ｐ型ベース層２１４の近傍で導
伝変調が起こり、半導体装置の抵抗が減少する。Here, when the base electrode 215 is placed in a positive bias state, holes are injected from the p-type base layer 214 into the n-type base layer 212, and conduction modulation occurs near the p-type base layer 214, so that the semiconductor The resistance of the device is reduced.

【０２１６】一方、半導体装置のオフ状態、すなわちベ
ース電極２１５が負バイアスされた状態で、ソース電極
２１６に対して正となる電圧がドレイン電極２１７に印
加されたとする。ベース電極２１５が負バイアスされる
と、空乏層が各ｐ型ベース層２１４からｎ型ベース層中
に広がり、これら空乏層同士が接触して電流経路が遮断
される。さらに、ドレイン電極２１７に向かって空乏層
が広がり、ｐ型ベース層２１４直下に電界の最強点が発
生する。On the other hand, it is assumed that a positive voltage with respect to the source electrode 216 is applied to the drain electrode 217 while the semiconductor device is in the off state, that is, the base electrode 215 is negatively biased. When the base electrode 215 is negatively biased, a depletion layer spreads from each p-type base layer 214 into the n-type base layer, these depletion layers contact each other, and the current path is cut off. Further, the depletion layer spreads toward the drain electrode 217, and the strongest point of the electric field occurs just below the p-type base layer 214.

【０２１７】さらに、ソース・ドレイン間電圧が上昇す
ると、空乏層がｐ型埋込み層２２０に到達し、このと
き、ｐ型埋込み層２２０はパンチスルー状態となって電
位が固定される。またさらに、ソース−ドレイン間電圧
が上昇すると、空乏層は埋込み層２２０からドレイン電
極側に広がる。したがって、ｎ型ベース層２内の電界最
強点の電界は固定されて上昇が阻止される。Further, when the source-drain voltage rises, the depletion layer reaches the p-type buried layer 220, and at this time, the p-type buried layer 220 is in a punch-through state and the potential is fixed. Furthermore, when the source-drain voltage rises, the depletion layer spreads from the buried layer 220 to the drain electrode side. Therefore, the electric field at the strongest electric field in the n-type base layer 2 is fixed and prevented from rising.

【０２１８】ｐ型埋込み層２２０とｐ型ベース層２１４
との間の距離と、ｎ型ベース層２１２の不純物濃度と
を、電界最強点の電界がｎ型ベース層２１２の電界強度
の限界値を越えないように設計することにより、この半
導体装置の高耐圧化、低抵抗化を図ることができる。P-type buried layer 220 and p-type base layer 214
And the impurity concentration of the n-type base layer 212 are designed such that the electric field at the strongest electric field does not exceed the limit value of the electric field strength of the n-type base layer 212. The breakdown voltage and the resistance can be reduced.

【０２１９】また、ｎ型ベース層２１２内にｐ型埋込み
層２２０を複数積層することにより、更に高耐圧化、低
抵抗化を図ることができる。Further, by stacking a plurality of p-type buried layers 220 in the n-type base layer 212, higher breakdown voltage and lower resistance can be achieved.

【０２２０】（第２１の実施の形態）図４７は本発明の
第２１の実施の形態に係る半導体装置の構成を模式的に
示す断面図であり、図４６と同一部分には同一符号を付
してその詳しい説明は省略し、ここでは異なる部分につ
いてのみ述べる。(Twenty-first Embodiment) FIG. 47 is a sectional view schematically showing the structure of a semiconductor device according to a twenty-first embodiment of the present invention. The same parts as those in FIG. The detailed description is omitted, and only different parts will be described here.

【０２２１】すなわち、この半導体装置は、第２０の実
施形態の半導体装置の変形構成であり、ターンオフの確
実性を向上させたものである。具体的にはｎ型ベース層
２１２の途中の深さまで達するトレンチ２１８を形成
し、その側壁および底面全面にｐ型ベース層２１４が形
成されている。That is, this semiconductor device is a modified structure of the semiconductor device of the twentieth embodiment and has improved reliability of turn-off. Specifically, a trench 218 that reaches a depth in the middle of the n-type base layer 212 is formed, and a p-type base layer 214 is formed on the entire sidewall and bottom surface thereof.

【０２２２】これにより、ベース電極２１５が負バイア
スされたオフ状態のとき、破線で示すように、各々のｐ
型ベース層２１４から伸びる空乏層が接する部分が面状
になるので、電流経路を確実に遮断することができる。As a result, when the base electrode 215 is in a negatively biased off state, as shown by a broken line, each p
Since the portion in contact with the depletion layer extending from the mold base layer 214 is planar, the current path can be reliably cut off.

【０２２３】（第２２の実施の形態）図４８は本発明の
第２２の実施の形態に係る半導体装置の構成を模式的に
示す断面斜視図である。この半導体装置は、ｎ型ドレイ
ン層としてのｎ型基板２２１上にｎ型ベース層２２２が
形成され、ｎ型ベース層２２２内にはストライプ状のｐ
型埋込み層２３０が形成されている。また、ｎ型ベース
層２２２内には、ｎ型ベース層２２２の途中の深さまで
達する深さの複数のトレンチ２２４がストライプ状に形
成されている。トレンチ２２４内には絶縁膜２２５を介
してｐ型ポリシリコン電極２２６が埋め込み形成されて
いる。また、ｎ型ベース層２２２の表面内には、トレン
チ２２４の上部に接するように、ｎ型ソース層２２７が
選択的に形成されている。ｐ型ポリシリコン電極２２６
およびｎ型ソース層２２７に接するようにソース電極２
２８が形成されている。(Twenty-second Embodiment) FIG. 48 is a sectional perspective view schematically showing the structure of a semiconductor device according to a twenty-second embodiment of the present invention. In this semiconductor device, an n-type base layer 222 is formed on an n-type substrate 221 as an n-type drain layer, and stripe-shaped p layers are formed in the n-type base layer 222.
A mold embedding layer 230 is formed. Further, in the n-type base layer 222, a plurality of trenches 224 having a depth reaching a depth in the middle of the n-type base layer 222 are formed in a stripe shape. A p-type polysilicon electrode 226 is embedded in the trench 224 with an insulating film 225 interposed therebetween. In addition, an n-type source layer 227 is selectively formed in the surface of the n-type base layer 222 so as to contact the upper portion of the trench 224. p-type polysilicon electrode 226
And the source electrode 2 in contact with the n-type source layer 227.
28 is formed.

【０２２４】また、ｎ型ベース層２２２表面の、トレン
チ２２４の端部付近には、トレンチ２２４より深くｐ型
ベース層２２３が拡散形成されている。ｐ型ベース層２
２３の表面にはベース電極２２９が形成されている。ま
た、ｎ型基板２２１には、ｎ型ベース層２２２とは反対
側の表面上にドレイン電極２３１が形成されている。Further, on the surface of the n-type base layer 222, a p-type base layer 223 is diffused and formed deeper than the trench 224 near the end of the trench 224. p-type base layer 2
A base electrode 229 is formed on the surface of 23. A drain electrode 231 is formed on the surface of the n-type substrate 221 opposite to the n-type base layer 222.

【０２２５】次に、この半導体装置の動作を説明する。Next, the operation of this semiconductor device will be described.

【０２２６】この素子のソース電極２２７に対して、ド
レイン電極２３１に正電圧が印加された状態で、ベース
電極２２９が正バイアスされると、正孔がｐ型ベース層
２２３からｎ型ベース層２２２に注入されると共に、絶
縁膜２２５に沿ってｎ型ソース層２２７に向かって流れ
込む。一方、電子は、流れ込んだ正孔の量に応じてｎ型
ソース層２２７からｎ型ベース層２２２中に注入され、
ソース・ドレイン間に印加された電圧に引かれて、ドレ
イン電極２３１に向かって流れる。よって、半導体装置
が導通状態となる。このとき、ｐ型ベース層２２３から
正孔が注入されたことにより、ｎ型ベース層２２内で導
伝変調が起きるので、更に抵抗が減少する。When the base electrode 229 is positively biased with a positive voltage applied to the drain electrode 231 with respect to the source electrode 227 of this element, holes are transferred from the p-type base layer 223 to the n-type base layer 222. While flowing into the n-type source layer 227 along the insulating film 225. On the other hand, electrons are injected from the n-type source layer 227 into the n-type base layer 222 according to the amount of holes that flow,
Due to the voltage applied between the source and drain, the current flows toward the drain electrode 231. Therefore, the semiconductor device becomes conductive. At this time, since holes are injected from the p-type base layer 223, conduction modulation occurs in the n-type base layer 22, further reducing the resistance.

【０２２７】この半導体装置のオフ状態、すなわちベー
ス電極２２９が０バイアス又は負バイアスされた状態
で、ソース電極２２８に対して正となる電圧がドレイン
電極２３１に印加されたとする。It is assumed that a positive voltage with respect to the source electrode 228 is applied to the drain electrode 231 in the off state of the semiconductor device, that is, with the base electrode 229 biased to 0 or negative.

【０２２８】このとき、ｎ型ベース層２２２とｐ型ポリ
シリコン電極２２６の拡散電位差により、トレンチ２２
４から空乏層が広がり、空乏層同士が接触する。また、
ｐ型ベース層２２３からも同時に空乏層が広がるので、
電流経路が遮断される。さらに、空乏層はドレイン電極
２３１側に向かって広がり、ｐ型ベース電極２３２直下
に、電界の最強点が発生する。At this time, due to the difference in diffusion potential between the n-type base layer 222 and the p-type polysilicon electrode 226, the trench 22 is formed.
The depletion layer spreads from 4, and the depletion layers contact each other. Also,
Since the depletion layer also spreads from the p-type base layer 223 at the same time,
The current path is cut off. Furthermore, the depletion layer expands toward the drain electrode 231 side, and the strongest point of the electric field occurs just below the p-type base electrode 232.

【０２２９】さらに、ソース・ドレイン間電圧の上昇に
比例し、空乏層がｐ型埋込み層２３０に到達し、このと
き、ｐ型埋込み層２３０はパンチスルー状態となって電
位が固定される。さらに、ソース・ドレイン間電圧が上
昇すると、空乏層はｐ型埋込み層２３０からドレイン電
極２３１側に広がる。したがって電界最強点の電界は固
定されて上昇が阻止される。Further, the depletion layer reaches the p-type buried layer 230 in proportion to the increase in the source-drain voltage, and at this time, the p-type buried layer 230 is in a punch-through state and the potential is fixed. Further, when the source-drain voltage rises, the depletion layer spreads from the p-type buried layer 230 to the drain electrode 231 side. Therefore, the electric field at the strongest point of the electric field is fixed and prevented from rising.

【０２３０】ｐ型埋込み層２３０とｐ型ベース層２２３
の距離とｎ型ベース層２２２の不純物濃度を、電界最強
点の電界がｎ型ベース層２２２の電界強度の限界値を越
えないように設計することにより、この半導体装置の高
耐圧化、低抵抗化を図ることができる。また、ｎ型ベー
ス層２２２内にｐ型埋込み層２３０を複数積層すること
により、更に高耐圧化、低抵抗化を図ることができる。P-type buried layer 230 and p-type base layer 223
And the impurity concentration of the n-type base layer 222 are designed so that the electric field at the strongest electric field does not exceed the limit value of the electric field strength of the n-type base layer 222. Can be realized. Further, by stacking a plurality of p-type buried layers 230 in the n-type base layer 222, higher breakdown voltage and lower resistance can be achieved.

【０２３１】なお、第２０ないし第２２の実施の形態に
おいては各ｐ型埋込み層２２０（，２３０）で分けられ
たｎ型ベース層２１２（，２２２）のうち、ｐ型ベース
層２１３（，２２３）と隣接するｎ型ベース層２１
２（，２２２）は濃度を薄くし且つ他のｎ型ベース層２
１２（，２２２）に比べて厚さを厚くし、且つ分担電圧
を高くすることで、さらに低抵抗化、高耐圧化を図るこ
とができる。理由は、ｐ型ベース層２１３（，２２３）
の付近は高注入状態となるので、高抵抗のｎ型ベース層
２１２（，２２２）でもオン状態の抵抗が低く抑制され
るため、ｐ型ベース層２１３（，２２３）から離れたｎ
型ベース層２１２（，２２２）の分担電圧を低下させて
抵抗を下げた方が素子全体の抵抗が低下されるからであ
る。In the twentieth to twenty-second embodiments, of the n-type base layers 212 (, 222) divided by the p-type buried layers 220 (, 230), the p-type base layers 213 (, 223) are included. ) Adjacent to the n-type base layer 21
2 (, 222) is a lighter concentration and the other n-type base layer 2
By making the thickness thicker than 12 (, 222) and increasing the shared voltage, it is possible to further reduce the resistance and the breakdown voltage. The reason is that the p-type base layer 213 (, 223)
Since the high-injection state is present in the vicinity of, the resistance in the on-state is suppressed to be low even in the high-resistance n-type base layer 212 (, 222).
This is because the resistance of the entire element is lowered by lowering the voltage shared by the mold base layers 212 (, 222) to lower the resistance.

【０２３２】次に、このときのｐ型埋込み層の具体的な
設計方法を、前述した図１を用いて説明する。Next, a specific design method of the p-type buried layer at this time will be described with reference to FIG.

【０２３３】例えば製品仕様により、ソース電極２２と
ドレイン電極１２との間の耐圧ＢＶと、ソース電極２２
とドレイン電極１２との間におけるｐ型埋込み層１４，
１６の層数Ｍとが決定されたとする。Depending on the product specifications, for example, the breakdown voltage BV between the source electrode 22 and the drain electrode 12 and the source electrode 22
P-type buried layer 14 between the drain electrode 12 and the drain electrode 12,
It is assumed that the number of layers M of 16 is determined.

【０２３４】続いて、各ｐ型埋込み層１４，１６により
（Ｍ＋１）層に分割されたｎ型ベース層１３，１５，１
７のうち、ソース電極２２側でｐ型ベース層１８に接す
るｎ型ベース層１７の分担する電圧Ｖ1 が決定される。Subsequently, the n-type base layers 13, 15, 1 divided into (M + 1) layers by the p-type buried layers 14, 16 respectively.
Among them, the voltage V 1 shared by the n-type base layer 17 in contact with the p-type base layer 18 on the source electrode 22 side is determined.

【０２３５】具体的には、仮に前述した（１）式による
分担電圧Ｖｓが算出され、この仮の分担電圧Ｖｓ以上と
なる値に、分担電圧Ｖ1 が次の（１０）式の通りに決定
される。More specifically, the sharing voltage Vs is temporarily calculated by the above-mentioned equation (1), and the sharing voltage V 1 is determined to be a value equal to or higher than the provisional sharing voltage Vs according to the following equation (10). To be done.

【０２３６】 Ｖ1 ≧Ｖｓ …（１０） 同様に、分担電圧Ｖ2 が次の（１０ａ）式のように得ら
れる。V 1 ≧ Vs (10) Similarly, the shared voltage V 2 is obtained by the following equation (10a).

【０２３７】 Ｖ2 ≧Ｖｓ …（１０ａ） 但し、Ｖ2 は、ｐ型埋込み層１４，１６により（Ｍ＋
１）層に分割されたｎ型ベース層１３，１５，１７のう
ち、ｎ型ドレイン層１１に接するｎ型ベース層１３の分
担する電圧である。V 2 ≧ Vs (10a) However, V 2 is (M +) due to the p-type buried layers 14 and 16.
The voltage is shared by the n-type base layer 13 in contact with the n-type drain layer 11 among the n-type base layers 13, 15, and 17 divided into 1) layers.

【０２３８】また、以上の決定内容に基づいて、他の部
分の分担電圧Ｖｓが次の（１１）式により得られる。な
お、ここで決定したＶｓも上記（１０）式，（１０ａ）
式を満たすのはいうまでもない。Further, the shared voltage Vs of other portions is obtained by the following equation (11) based on the above determination contents. Note that the Vs determined here is also the above equation (10), (10a)
It goes without saying that the formula is satisfied.

【０２３９】 Ｖｓ＝（ＢＶ−Ｖ1 −Ｖ2 ）／（Ｍ−１）［Ｖ］ …（１１） 但し、Ｖｓは、ｐ型埋込み層１４，１６により（Ｍ＋
１）層に分割されたｎ型ベース層１３，１５，１７のう
ち、ｐ型ベース層１８及びｎ型（又はｐ型）ドレイン層
１１の双方に接しない（Ｍ−１）層のｎ型ベース層１５
の分担する電圧である。Vs = (BV−V 1 −V 2 ) / (M−1) [V] (11) However, Vs is (M +) due to the p-type buried layers 14 and 16.
1) Of the n-type base layers 13, 15, 17 divided into layers, an (M-1) -layer n-type base that is not in contact with both the p-type base layer 18 and the n-type (or p-type) drain layer 11 Layer 15
Is the voltage shared by

【０２４０】Ｖ2 は、ｐ型埋込み層１４，１６により
（Ｍ＋１）層に分割されたｎ型ベース層１３，１５，１
７のうち、ｎ型ドレイン層１１に接するｎ型ベース層１
３の分担する電圧である。V 2 is an n-type base layer 13, 15, 1 divided into (M + 1) layers by the p-type buried layers 14, 16.
N-type base layer 1 in contact with n-type drain layer 11
It is a voltage shared by three.

【０２４１】以下、前述同様に、分担電圧Ｖ1 のｎ型ベ
ース層１７における不純物濃度Ｎ1と厚さＷ1 とが次の
（１２）式及び（１３）式に示すように得られる。Thereafter, similarly to the above, the impurity concentration N 1 and the thickness W 1 in the n-type base layer 17 having the shared voltage V 1 are obtained as shown in the following equations (12) and (13).

【０２４２】 Ｎ1 ＜１．８９７ ×１０18×Ｖ1 -1.35 ［ｃｍ-3］ …（１２） Ｗ1 ＜１．１２４７×１０10×Ｎ1 -0.85 ［ｃｍ］ …（１３） また同様に、分担電圧Ｖ2 のｎ型ベース層１３における
不純物濃度Ｎ2 と厚さＷ2 とが次の（１４）式及び（１
５）式に示すように得られる。N 1 <1.897 × 10 18 × V 1 -1.35 [cm −3 ] (12) W 1 <1.1247 × 10 10 × N 1 -0.85 [cm] (13) Similarly, , The impurity concentration N 2 and the thickness W 2 in the n-type base layer 13 having the sharing voltage V 2 are expressed by the following equation (14) and (1)
It is obtained as shown in the equation (5).

【０２４３】 Ｎ2 ＜１．８９７ ×１０18×Ｖ2 -1.35 ［ｃｍ-3］ …（１４） Ｗ2 ＜１．１２４７×１０10×Ｎ2 -0.85 ［ｃｍ］ …（１５） なお、式（１５）は一例であり、厚さＷ2 は、任意に設
定可能であって式（１５）に制限されない。N 2 <1.897 × 10 18 × V 2 −1.35 [cm −3 ] (14) W 2 <1.1247 × 10 10 × N 2 −0.85 [cm] (15) where (15) is an example, and the thickness W 2 can be set arbitrarily and is not limited to the expression (15).

【０２４４】また同様に、分担電圧Ｖｓのｎ型ベース層
１５における不純物濃度Ｎｓと厚さＷｓとが次の（１
６）式及び（１７）式に示すように得られる。Similarly, the impurity concentration Ns and the thickness Ws in the n-type base layer 15 having the shared voltage Vs are as follows (1)
It is obtained as shown in the equations (6) and (17).

【０２４５】 Ｎｓ＜１．８９７ ×１０18×Ｖｓ-1.35 ［ｃｍ-3］ …（１６） Ｗｓ＜１．１２４７×１０10×Ｎｓ-0.85 ［ｃｍ］ …（１７） 以上のように各ｎ型ベース層１３，１５，１７に異なる
電圧を分担させることもできる。また、（１０）式〜
（１７）式に示すように設計条件を明確化しているの
で、確実に動作する素子を再現性よく形成することがで
きる。さらに、これら（１０）式〜（１７）式に示す設
計条件は、プレーナ構造やトレンチ構造あるいは縦型、
横型などの素子構造を問わず、前述した各実施形態に適
用可能である。Ns <1.897 × 10 18 × Vs −1.35 [cm −3 ] (16) Ws <1.1247 × 10 10 × Ns −0.85 [cm] (17) As described above, each n-type Different voltages may be shared by the base layers 13, 15, and 17. Also, equation (10)
Since the design conditions are clarified as shown in the equation (17), it is possible to form the element that operates reliably with good reproducibility. Furthermore, the design conditions shown in these equations (10) to (17) are as follows:
The invention can be applied to each of the above-described embodiments regardless of a lateral type or the like.

【０２４６】その他、本発明はその要旨を逸脱しない範
囲で種々変形して実施できる。Besides, the present invention can be variously modified and implemented without departing from the gist thereof.

【０２４７】[0247]

【発明の効果】以上説明したように請求項１の発明によ
れば、オフ状態の際に、印加電圧の増加に比例して空乏
層が第１導電型半導体層中を第２の主電極側から第１の
主電極側に広がり、この空乏層が第２導電型埋込み層に
到達したとき、パンチスルー現象により、第２導電型埋
込み層が当該空乏層中の電界強度を固定してその上昇を
抑止するので、このときの電界強度の最大値を越える電
界強度の限界値をもつ範囲で第１導電型半導体層の不純
物濃度を増加させてオン抵抗を低下させることにより、
高耐圧であってもオン状態での電圧降下を低下できる縦
型の半導体装置を提供できる。As described above, according to the first aspect of the invention, in the off state, the depletion layer is proportional to the increase of the applied voltage in the first conductivity type semiconductor layer in the second main electrode side. When the depletion layer reaches the second conductivity type buried layer, the second conductivity type buried layer fixes the electric field strength in the depletion layer and raises it. Therefore, by increasing the impurity concentration of the first conductivity type semiconductor layer and reducing the on-resistance in a range having a limit value of the electric field strength exceeding the maximum value of the electric field strength at this time,
Vertical that can reduce the voltage drop in the ON state even with high withstand voltage
Type semiconductor device can be provided.

【０２４８】また、請求項２の発明によれば、請求項１
と同様の効果に加え、電流制御構造により、第１の主電
極から第２の主電極へ流れる電流を制御できる縦型の半
導体装置を提供できる。According to the invention of claim 2, claim 1
In addition to the effect similar to the above, it is possible to provide a vertical semiconductor device capable of controlling the current flowing from the first main electrode to the second main electrode by the current control structure.

【０２４９】さらに、請求項３の発明によれば、オフ状
態の際に、印加電圧の増加に比例して空乏層が第２導電
型ベース層からドレイン電極側に広がり、この空乏層が
第２導電型埋込み層に到達したとき、パンチスルー現象
により、第２導電型埋込み層が当該空乏層中の電界強度
を固定してその上昇を抑止するので、このときの電界強
度の最大値を越える電界強度の限界値をもつ範囲で第１
導電型半導体層の不純物濃度を増加させてオン抵抗を低
下させることにより、高耐圧であってもオン状態での電
圧降下を低下できる縦型の半導体装置を提供できる。Further, according to the invention of claim 3, in the off state, the depletion layer spreads from the second conductivity type base layer to the drain electrode side in proportion to the increase of the applied voltage, and the depletion layer becomes the second depletion layer. When reaching the conductivity type buried layer, the second conductivity type buried layer fixes the electric field strength in the depletion layer and suppresses its rise due to the punch-through phenomenon. First in the range with a limit value of strength
By increasing the impurity concentration of the conductive type semiconductor layer to reduce the on-resistance, it is possible to provide a vertical semiconductor device capable of reducing the voltage drop in the on-state even with a high breakdown voltage.

【０２５０】また、請求項４の発明によれば、ゲート絶
縁膜とゲート電極とが第２導電型ベース層を貫通し、第
１導電型半導体層の途中の深さまで達する溝内に形成さ
れているので、請求項３と同様の効果を奏するトレンチ
構造の半導体装置を提供できる。Further, according to the invention of claim 4, the gate insulating film and the gate electrode are formed in the trench penetrating the second conductivity type base layer and reaching the depth of the middle of the first conductivity type semiconductor layer. Therefore, it is possible to provide the semiconductor device having the trench structure, which has the same effect as the third aspect.

【０２５１】さらに、請求項５の発明によれば、請求項
１乃至請求項３のいずれかの効果に加え、第２導電型埋
込み層がメッシュ形状を有しているため、ストライプ形
状に比べて容易に高耐圧化できる半導体装置を提供でき
る。Further, according to the invention of claim 5, in addition to the effect of any one of claims 1 to 3, since the second conductivity type buried layer has a mesh shape, it has a mesh shape as compared with the stripe shape. It is possible to provide a semiconductor device whose breakdown voltage can be easily increased.

【０２５２】また、請求項６の発明によれば、第２導電
型埋込み層がストライプ形状を有しているため、請求項
１乃至請求項３のいずれかと同様の作用を奏する半導体
装置を提供できる。さらに、請求項７の発明によれば、
第２導電型埋込み層がドット形状を有することにより、
請求項１乃至請求項３のいずれかの効果に加え、素子の
終端部にてガードリングと同様に作用するため、プレー
ナ構造の場合、高耐圧の半導体装置を形成できる。ま
た、請求項８の発明によれば、請求項７の効果に加え、
第２導電型埋込み層としては、ドット形状を有する各ド
ットが１行毎に半間隔ずれ、互いに隣り合う行及び列の
ドットと等間隔に配置されたので、高密度なドットパタ
ーンを形成でき、耐圧的に有利な半導体装置を提供でき
る。 Further, according to the invention of claim 6, since the second conductivity type buried layer has a stripe shape, it is possible to provide a semiconductor device having the same effect as that of any one of claims 1 to 3. . Further, according to the invention of claim 7,
Since the second conductivity type buried layer has a dot shape,
In addition to the effect of any one of claims 1 to 3,
Since it acts like a guard ring at the end, play
In the case of the trench structure, a high breakdown voltage semiconductor device can be formed. Well
According to the invention of claim 8, in addition to the effect of claim 7,
As the second conductivity type buried layer, each dot-shaped buried layer is formed.
Of rows and columns that are half-spaced apart from each other
Since it is arranged at equal intervals with the dots, it has a high-density dot pattern.
It is possible to provide a semiconductor device that is advantageous in pressure resistance.
It

【０２５３】さらに、請求項９の発明によれば、請求項
３の効果に加え、高耐圧であっても、オン状態での電圧
降下を低下できるＭＯＳＦＥＴ等の半導体装置を提供で
きる。Further, according to the invention of claim 9 , in addition to the effect of claim 3, it is possible to provide a semiconductor device such as a MOSFET capable of reducing the voltage drop in the ON state even with a high breakdown voltage.

【０２５４】また、請求項１０の発明によれば、請求項
３の効果に加え、ドレイン電極側に第２導電型ドレイン
層を有するバイポーラ素子であっても、前述同様に、高
耐圧であっても、オン状態での電圧降下を低下できるＩ
ＧＢＴ等の半導体装置を提供できる。According to the invention of claim 10 , in addition to the effect of claim 3, even a bipolar element having a second conductivity type drain layer on the drain electrode side has a high breakdown voltage as described above. Can reduce the voltage drop in the ON state
A semiconductor device such as a GBT can be provided.

【０２５５】さらに、請求項１１の発明によれば、第２
導電型埋込み層が、制御電極とは異なる電位であり、電
位的に浮いた状態であるので、請求項２と同様の効果を
奏する半導体装置を提供できる。Further, according to the invention of claim 11 , the second
Since the conductivity type buried layer has a potential different from that of the control electrode and is in a state of floating potential, it is possible to provide a semiconductor device having the same effect as that of the second aspect.

【０２５６】また、請求項１２，１７，１８の発明によ
れば、第１の主電極と第２の主電極との間の耐圧ＢＶ
と、第１の主電極と第２の主電極との間における第２導
電型埋込み層の層数Ｍと、これら第２導電型埋込み層に
より（Ｍ＋１）層に分割された第１導電型半導体層のう
ち、第１の主電極に最も近い第１導電型半導体層の分担
する電圧Ｖ1 と、第１の主電極に最も近い第１導電型半
導体層の不純物濃度Ｎ1と、第１の主電極に最も近い第
１導電型半導体層の厚さＷ1 と、各第２導電型埋込み層
により（Ｍ＋１）層に分割された第１導電型半導体層の
うち、第２の主電極に最も近い第１導電型半導体層の分
担する電圧Ｖ2 と、第２の主電極に最も近い第１導電型
半導体層の不純物濃度Ｎ2 と、各第２導電型埋込み層に
より（Ｍ＋１）層に分割された第１導電型半導体層のう
ち、第１の主電極及び第２の主電極から離れた （Ｍ−
１）層の第１導電型半導体層の分担する電圧Ｖｓと、
（Ｍ−１）層の第１導電型半導体層の不純物濃度Ｎｓ
と、（Ｍ−１）層の第１導電型半導体層の厚さＷｓとの
夫々の設計条件を所定の式にて明確化しているので、請
求項１又は請求項２の効果に加え、確実に動作する素子
を再現性よく形成できる半導体装置を提供できる。According to the twelfth , seventeenth and eighteenth aspects of the invention, the breakdown voltage BV between the first main electrode and the second main electrode is BV.
And the number M of the second conductivity type buried layers between the first main electrode and the second main electrode, and the first conductivity type semiconductor divided into (M + 1) layers by these second conductivity type buried layers. Among the layers, the voltage V 1 shared by the first conductivity type semiconductor layer closest to the first main electrode, the impurity concentration N 1 of the first conductivity type semiconductor layer closest to the first main electrode, and the first The thickness W 1 of the first-conductivity-type semiconductor layer closest to the main electrode and the first main-conductivity-type semiconductor layer divided into (M + 1) layers by the respective second-conductivity-type buried layers are the closest to the second main electrode. The voltage is divided into (M + 1) layers by the voltage V 2 shared by the nearby first conductivity type semiconductor layer, the impurity concentration N 2 of the first conductivity type semiconductor layer closest to the second main electrode, and each second conductivity type buried layer. Of the first conductive type semiconductor layer separated from the first main electrode and the second main electrode (M−
Voltage Vs shared by the first conductivity type semiconductor layer of layer 1),
Impurity concentration Ns of the first conductivity type semiconductor layer of the (M-1) layer
And the thickness Ws of the first conductivity type semiconductor layer of the (M-1) layer are clarified by predetermined formulas, so that in addition to the effect of claim 1 or claim 2, It is possible to provide a semiconductor device capable of forming an element that operates in good condition with good reproducibility.

【０２５７】さらに、請求項１３，１９の発明によれ
ば、ソース電極とドレイン電極との間の耐圧ＢＶと、ソ
ース電極とドレイン電極との間における第２導電型埋込
み層の層数Ｍと、これら第２導電型埋込み層により（Ｍ
＋１）層に分割された第１導電型半導体層のうち、第２
導電型ベース層に接する第１導電型半導体層の分担する
電圧Ｖ1 と、第２導電型ベース層に接する第１導電型半
導体層の不純物濃度Ｎ1と、第２導電型ベース層に接す
る第１導電型半導体層の厚さＷ1 と、各第２導電型埋込
み層により（Ｍ＋１）層に分割された第１導電型半導体
層のうち、ドレイン層に接する第１導電型半導体層の分
担する電圧Ｖ2 と、ドレイン層に接する第１導電型半導
体層の不純物濃度Ｎ2 と、各第２導電型埋込み層により
（Ｍ＋１）層に分割された第１導電型半導体層のうち、
第２導電型ベース層及びドレイン層の双方に接しない
（Ｍ−１）層の第１導電型半導体層の分担する電圧Ｖｓ
と、（Ｍ−１）層の第１導電型半導体層の不純物濃度Ｎ
ｓと、（Ｍ−１）層の第１導電型半導体層の厚さＷｓと
の夫々の設計条件を所定の式にて明確化しているので、
請求項３の効果に加え、確実に動作する素子を再現性よ
く形成できる半導体装置を提供できる。According to the thirteenth and nineteenth aspects of the invention, the breakdown voltage BV between the source electrode and the drain electrode, the number M of the buried layers of the second conductivity type between the source electrode and the drain electrode, By these second conductive type buried layers (M
The second of the first conductivity type semiconductor layers divided into +1) layers
The voltage V 1 shared by the first conductive type semiconductor layer in contact with the conductive type base layer, the impurity concentration N 1 of the first conductive type semiconductor layer in contact with the second conductive type base layer, and the first conductive type semiconductor layer in contact with the second conductive type base layer. The thickness W 1 of the first conductivity type semiconductor layer and the first conductivity type semiconductor layer in contact with the drain layer among the first conductivity type semiconductor layers divided into (M + 1) layers by the respective second conductivity type buried layers are shared. Of the voltage V 2 , the impurity concentration N 2 of the first conductivity type semiconductor layer in contact with the drain layer, and the first conductivity type semiconductor layer divided into (M + 1) layers by each second conductivity type buried layer,
The voltage Vs shared by the first conductivity type semiconductor layer of the (M-1) layer that is not in contact with both the second conductivity type base layer and the drain layer.
And the impurity concentration N of the first conductivity type semiconductor layer of the (M-1) layer
Since the respective design conditions of s and the thickness Ws of the first conductivity type semiconductor layer of the (M-1) layer are clarified by predetermined formulas,
In addition to the effect of the third aspect, it is possible to provide a semiconductor device in which an element that operates reliably can be formed with good reproducibility.

【０２５８】また、請求項１４の発明によれば、第２導
電型埋込み層を取り囲むように略方形状に形成された埋
込み第２導電型ガードリング領域を備えた終端構造なの
で、請求項１乃至請求項３のいずれかの効果に加え、各
埋込み第２導電型ガードリング領域により、半導体装置
終端部における等電位線の間隔を広げて電界集中を緩和
すると共に、半導体装置終端部の耐圧劣化を阻止できる
半導体装置を提供できる。[0258] According to the invention of claim 14, buried formed Ryakukata shape so as to surround the second conductivity type buried layer
In addition to the effect of any one of claims 1 to 3, since the termination structure is provided with the embedded second conductivity type guard ring region,
By the buried second conductivity type guard ring region, it is possible to provide a semiconductor device in which the interval between equipotential lines in the end portion of the semiconductor device is widened to reduce electric field concentration and prevent breakdown of breakdown voltage of the end portion of the semiconductor device.

【０２５９】さらに、請求項１５の発明によれば、第２
導電型埋込み層を取り囲むように略方形状に形成され、
第２導電型埋込み層のキャリア密度よりも低いキャリア
密度を有する埋込み第２導電型リサーフ領域を備えたの
で、請求項１乃至請求項３のいずれかと同様の効果を奏
する半導体装置を提供できる。Further, according to the invention of claim 15, the second
Formed in a substantially rectangular shape so as to surround the conductive type buried layer,
Since the buried second conductivity type RESURF region having a carrier density lower than the carrier density of the second conductivity type buried layer is provided, it is possible to provide a semiconductor device having the same effect as that of any one of claims 1 to 3.

【０２６０】また、請求項１６の発明によれば、請求項
１乃至請求項３のいずれかの効果に加え、第１導電型半
導体層の終端部が、傾斜を有するベベル構造に形成され
たことにより、ｐｎ接合終端の電界強度を緩和するベベ
ル構造の利点を奏する半導体装置を提供できる。According to the sixteenth aspect of the invention, in addition to the effect of any one of the first to third aspects, the terminal end portion of the first conductivity type semiconductor layer is formed in a bevel structure having an inclination. As a result, it is possible to provide a semiconductor device having the advantages of the bevel structure for relaxing the electric field strength at the pn junction termination.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の第１の実施の形態に係るＭＯＳＦＥＴ
の構成を示す模式図。FIG. 1 is a MOSFET according to a first embodiment of the present invention.
FIG.

【図２】同実施の形態におけるｐ型埋込み層の寸法を説
明するための模式図。FIG. 2 is a schematic diagram for explaining the dimensions of a p-type buried layer in the same embodiment.

【図３】図３は同実施の形態におけるＭＯＳＦＥＴの作
用を説明するための図。FIG. 3 is a view for explaining the operation of the MOSFET in the same embodiment.

【図４】同実施の形態における電界強度分布の２次元数
値計算による算出結果を示す図。FIG. 4 is a diagram showing a calculation result of a field intensity distribution by two-dimensional numerical calculation in the same embodiment.

【図５】図５は同実施の形態におけるＭＯＳＦＥＴと従
来のＭＯＳＦＥＴとを比較説明するための模式図。FIG. 5 is a schematic diagram for comparatively explaining the MOSFET in the same embodiment and a conventional MOSFET.

【図６】同実施の形態における分担電圧Ｖｓからキャリ
ア密度Ｎｓを決定するための図。FIG. 6 is a diagram for determining a carrier density Ns from a shared voltage Vs in the same embodiment.

【図７】同実施の形態におけるキャリア密度Ｎｓから厚
さＷｓを決定するための図。FIG. 7 is a diagram for determining the thickness Ws from the carrier density Ns in the same embodiment.

【図８】同実施の形態におけるＭＯＳＦＥＴの等価回路
を説明するための模式図。FIG. 8 is a schematic diagram for explaining an equivalent circuit of the MOSFET in the same embodiment.

【図９】同実施の形態におけるＭＯＳＦＥＴにおけるオ
ン抵抗と耐圧の関係を示す図。FIG. 9 is a diagram showing a relationship between on-resistance and breakdown voltage in the MOSFET according to the same embodiment.

【図１０】本発明に係るＭＯＳＦＥＴにて理論的に可能
なオン抵抗と耐圧の関係を示す図。FIG. 10 is a view showing a theoretically possible relationship between on-resistance and breakdown voltage in the MOSFET according to the present invention.

【図１１】図１１は本発明の第２の実施の形態に係るＭ
ＯＳＦＥＴのｐ型埋込み層の構成を示す模式図並びに図
１に示すｐ型埋込み層の拡大図。FIG. 11 is an M according to a second embodiment of the present invention.
FIG. 2 is a schematic view showing the configuration of a p-type buried layer of OSFET and an enlarged view of the p-type buried layer shown in FIG. 1.

【図１２】本発明の第３の実施の形態に係るショットキ
ーバリアダイオードの構成を示す模式図。FIG. 12 is a schematic diagram showing a configuration of a Schottky barrier diode according to a third embodiment of the present invention.

【図１３】本発明の第４の実施の形態に係るショットキ
ーバリアダイオードの構成を示す模式図。FIG. 13 is a schematic diagram showing a configuration of a Schottky barrier diode according to a fourth embodiment of the present invention.

【図１４】本発明の第５の実施の形態に係るＩＧＢＴの
構成を示す模式図。FIG. 14 is a schematic diagram showing a configuration of an IGBT according to a fifth embodiment of the present invention.

【図１５】本発明の第６の実施の形態に係るＩＧＢＴの
構成を示す模式図。FIG. 15 is a schematic diagram showing a configuration of an IGBT according to a sixth embodiment of the present invention.

【図１６】本発明の第７の実施の形態に係るＩＧＢＴの
構成を示す模式図。FIG. 16 is a schematic diagram showing a configuration of an IGBT according to a seventh embodiment of the present invention.

【図１７】本発明に係る半導体装置の形成方法を説明す
るための工程断面図。FIG. 17 is a process sectional view for explaining the method for forming the semiconductor device according to the invention.

【図１８】本発明に係る半導体装置の形成方法を説明す
るための工程断面図。FIG. 18 is a process sectional view for explaining the method for forming the semiconductor device according to the invention.

【図１９】本発明に係る半導体装置の形成方法を説明す
るための工程断面図。FIG. 19 is a process sectional view for explaining the method for forming the semiconductor device according to the invention.

【図２０】本発明に係る半導体装置の形成方法を説明す
るための工程断面図。FIG. 20 is a process sectional view for explaining the method for forming the semiconductor device according to the invention.

【図２１】本発明に係る半導体装置の形成方法を説明す
るための模式図。FIG. 21 is a schematic diagram for explaining a method for forming a semiconductor device according to the present invention.

【図２２】本発明に係るストライプ形状のｐ型埋込み層
を形成するためのマスクパターンを示す平面図。FIG. 22 is a plan view showing a mask pattern for forming a stripe-shaped p-type buried layer according to the present invention.

【図２３】本発明に係る図１６の変形パターンを示す平
面図。FIG. 23 is a plan view showing a modification pattern of FIG. 16 according to the present invention.

【図２４】本発明に係るメッシュ形状のｐ型埋込み層を
形成するためのマスクパターンを示す平面図。FIG. 24 is a plan view showing a mask pattern for forming a mesh-shaped p-type buried layer according to the present invention.

【図２５】本発明に係るメッシュ形状のｐ型埋込み層を
形成するためのマスクパターンを示す平面図。FIG. 25 is a plan view showing a mask pattern for forming a mesh-shaped p-type buried layer according to the present invention.

【図２６】本発明に係るドット状のｐ型埋込み層を形成
するためのマスクパターンを示す平面図。FIG. 26 is a plan view showing a mask pattern for forming a dot-shaped p-type buried layer according to the present invention.

【図２７】本発明に係る図２６の変形パターンを示す平
面図。FIG. 27 is a plan view showing a modified pattern of FIG. 26 according to the present invention.

【図２８】本発明に係るストライプ形状で位置合せの不
要なｐ型埋込み層のマスクパターンを示す平面図。FIG. 28 is a plan view showing a mask pattern of a p-type buried layer which is stripe-shaped and does not require alignment according to the present invention.

【図２９】本発明に係る図２８の変形パターンを示す平
面図。FIG. 29 is a plan view showing a modification pattern of FIG. 28 according to the present invention.

【図３０】本発明に係る図２２のXXXV−XXXV線矢視断面
図、30 is a sectional view taken along the line XXXV-XXXV of FIG. 22 according to the present invention,

【図３１】本発明の第８の実施の形態に係るＭＯＳＦＥ
Ｔの終端構造を示す模式図。FIG. 31 is a MOSFE according to an eighth embodiment of the present invention.
The schematic diagram which shows the termination structure of T.

【図３２】本発明の第９の実施の形態に係るＭＯＳＦＥ
Ｔの終端構造を示す模式図。FIG. 32 is a MOSFE according to a ninth embodiment of the present invention.
The schematic diagram which shows the termination structure of T.

【図３３】本発明の第１０の実施の形態に係るＭＯＳＦ
ＥＴの終端構造を示す模式図。FIG. 33 is a MOSF according to the tenth embodiment of the present invention.
The schematic diagram which shows the termination structure of ET.

【図３４】本発明の第１１の実施の形態に係るＭＯＳＦ
ＥＴの終端構造を示す模式図。FIG. 34 is a MOSF according to an eleventh embodiment of the present invention.
The schematic diagram which shows the termination structure of ET.

【図３５】本発明の第１２の実施の形態に係るＭＯＳＦ
ＥＴの構成を示す模式図。FIG. 35 is a MOSF according to a twelfth embodiment of the present invention.
The schematic diagram which shows the structure of ET.

【図３６】同実施の形態におけるＭＯＳＦＥＴの平面
図。FIG. 36 is a plan view of the MOSFET according to the same embodiment.

【図３７】同実施の形態におけるＭＯＳＦＥＴの変形構
成を示す平面図。FIG. 37 is a plan view showing a modified configuration of the MOSFET according to the same embodiment.

【図３８】本発明の第１３の実施の形態に係るＭＯＳＦ
ＥＴの構成を示す模式図。FIG. 38 is a MOSF according to the thirteenth embodiment of the present invention.
The schematic diagram which shows the structure of ET.

【図３９】本発明の第１４の実施の形態に係るＭＯＳＦ
ＥＴの構成を示す模式図。FIG. 39 is a MOSF according to the fourteenth embodiment of the present invention.
The schematic diagram which shows the structure of ET.

【図４０】本発明の第１５の実施の形態に係るＭＯＳＦ
ＥＴの構成を示す模式図。FIG. 40 is a MOSF according to the fifteenth embodiment of the present invention.
The schematic diagram which shows the structure of ET.

【図４１】同実施の形態における図４０のXLVI−XLVI線
矢視断面図。FIG. 41 is a cross-sectional view taken along the line XLVI-XLVI of FIG. 40 in the embodiment.

【図４２】本発明の第１６の実施の形態に係るＭＯＳＦ
ＥＴの構成を示す模式図。FIG. 42 is a MOSF according to the 16th embodiment of the present invention.
The schematic diagram which shows the structure of ET.

【図４３】本発明の第１７の実施の形態に係るＭＯＳＦ
ＥＴの構成を示す模式図。FIG. 43 is a MOSF according to a seventeenth embodiment of the present invention.
The schematic diagram which shows the structure of ET.

【図４４】本発明の第１８の実施の形態に係るＭＯＳＦ
ＥＴの構成を示す模式図。FIG. 44 is a MOSF according to the eighteenth embodiment of the present invention.
The schematic diagram which shows the structure of ET.

【図４５】本発明の第１９の実施の形態に係るＭＯＳＦ
ＥＴの構成を示す模式図。FIG. 45 is a MOSF according to the nineteenth embodiment of the present invention.
The schematic diagram which shows the structure of ET.

【図４６】本発明の第２０の実施の形態に係る半導体装
置の構成を示す模式図。FIG. 46 is a schematic diagram showing the structure of a semiconductor device according to a twentieth embodiment of the present invention.

【図４７】本発明の第２１の実施の形態に係る半導体装
置の構成を示す模式図。FIG. 47 is a schematic diagram showing the structure of a semiconductor device according to a twenty-first embodiment of the present invention.

【図４８】本発明の第２２の実施の形態に係る半導体装
置の構成を模式的に示す断面斜視図。FIG. 48 is a sectional perspective view schematically showing the configuration of a semiconductor device according to a twenty-second embodiment of the present invention.

【図４９】従来のＭＯＳＦＥＴの構成を示す模式図。FIG. 49 is a schematic diagram showing a configuration of a conventional MOSFET.

【図５０】従来のＭＯＳＦＥＴにおけるオン抵抗と耐圧
の関係を示す図。FIG. 50 is a diagram showing the relationship between on-resistance and breakdown voltage in a conventional MOSFET.

【図５１】従来のバイポーラトランジスタの構成を模式
的に示す断面図。FIG. 51 is a sectional view schematically showing the configuration of a conventional bipolar transistor.

【図５２】従来のＩＧＢＴの構成を模式的に示す断面
図。FIG. 52 is a sectional view schematically showing the configuration of a conventional IGBT.

【図５３】従来のＭＯＳＦＥＴ及びＩＧＢＴにおけるオ
ン状態での電圧降下と電流との関係を示す図。FIG. 53 is a diagram showing a relationship between a voltage drop and a current in an ON state of a conventional MOSFET and IGBT.

【符号の説明】[Explanation of symbols]

１１，３１，６１，６７，６８，２０１，２１１，２２
１…ｎ型基板 １２，４２，１１１，１３１，２０９，２１７，２３１
…ドレイン電極 １３，１５，１７，３２，３２1 〜３２3 ，３４，４
４，４４1 〜４４4 ，４６，６２，６６，２０２，２１
２，２２２…ｎ型ベース層 １４，１４ａ，１６，１６ａ，３３，３３1 〜３３3 ，
４５，４５1 〜４５4，１０４，１１２，１２７，１４
４，２１０，２３０…ｐ型埋込み層 １８，４８，１０６，１２４，２０３，２１４…ｐ型ベ
ース層 １９，４９，１０７，１２６，２０７，２１３，２２７
…ｎ型ソース層 ２０，５０…Ｓｉ酸化膜 ２１，５１，１１０，１３０，２０６…ゲート電極 ２２，５２，１０８，１２８，２０８，２１６，２２８
…ソース電極 ３５…ショットキー電極 ３６…オーミック電極 ４１…ｐ型基板 ４３…ｎ型バッファ層 ４７，４７ａ…ｎ+ 型層 ６３…マスク ６４…イオン ６５…イオン注入層 ７１…枠部 ７２，８１…ストライプ部 ７３…中心部 ７４…ゲート電極パッド ７５…領域 ７６，８２…接続部 ７７…メッシュ部 ７８…ドット ８３…方形部 ９１…埋込みガードリング ９２…等電位線 ９３…埋込みリサーフ １０１，１２１…基板 １０２…ｎ- 型層 １０３，１２３…ｎ型オフセット層 １０５，１２５…ｎ型ドレイン層 １０９，１２９…酸化膜 １２２…埋込み酸化膜 １４１，２２５…絶縁膜 １４２…コンタクトホール １４３…等電位電極 １４５…ｐ型接続層 １４６，１４７…ＳＩＰＯＳ部 ２０４，２１８，２２４…トレンチ ２０５…ゲート絶縁膜 ２１５，２２９…ベース電極 ２２６…ｐ型ポリシリコン電極 ＢＶ…耐圧 Ｖｓ，Ｖ1 ，Ｖ2 …（分担）電圧 Ｎｓ，Ｎ1 ，Ｎ2 …不純物濃度 Ｗｓ，Ｗ1 ，Ｗ2 …厚さ ｔ…厚さ Ｗ…形成間隔 Ｍ…層数11, 31, 61, 67, 68, 201, 211, 22
1 ... N-type substrate 12, 42, 111, 131, 209, 217, 231
... Drain electrodes 13, 15, 17, 32, 32 1 to 32 3 , 34, 4
4,44 1 to 44 4 , 46, 62, 66, 202, 21
2,222 ... n-type base layer 14,14a, 16,16a, 33,33 1 ~33 3 ,
45, 45 1-45 4, 104,112,127,14
4, 210, 230 ... P-type buried layers 18, 48, 106, 124, 203, 214 ... P-type base layers 19, 49, 107, 126, 207, 213, 227
... n-type source layers 20, 50 ... Si oxide films 21, 51, 110, 130, 206 ... Gate electrodes 22, 52, 108, 128, 208, 216, 228
Source electrode 35 Schottky electrode 36 Ohmic electrode 41 p type substrate 43 n type buffer layers 47, 47a n + type layer 63 mask 64 ion 65 ion implantation layer 71 frame 72, 81 Stripe portion 73 ... Central portion 74 ... Gate electrode pad 75 ... Region 76, 82 ... Connection portion 77 ... Mesh portion 78 ... Dot 83 ... Square portion 91 ... Embedded guard ring 92 ... Equipotential line 93 ... Embedded RESURF 101, 121 ... Substrate 102 ... N- type layers 103, 123 ... N type offset layers 105, 125 ... N type drain layers 109, 129 ... Oxide film 122 ... Buried oxide films 141, 225 ... Insulating film 142 ... Contact hole 143 ... Equipotential electrode 145 ... p-type connection layers 146, 147 ... SIPOS portions 204, 218, 224 ... Trench 205 ... Gate insulating films 215, 229 ... Source electrode 226 ... p-type polysilicon electrode BV ... withstand voltage Vs, V 1, V 2 ... ( shared) voltage Ns, N 1, N 2 ... impurity concentration Ws, W 1, W 2 ... thickness t ... thickness W ... Forming interval M ... Number of layers

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平７−7154（ＪＰ，Ａ) 特開 平５−82792（ＪＰ，Ａ) 特開 平７−130996（ＪＰ，Ａ) 特開 平４−332173（ＪＰ，Ａ) 特開 平６−334188（ＪＰ，Ａ) 特開 昭64−11367（ＪＰ，Ａ) 特開 昭55−98872（ＪＰ，Ａ) 実開 昭54−108660（ＪＰ，Ｕ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 29/78 H01L 29/06 H01L 29/47 H01L 29/73 - 29/735 H01L 29/74 - 29/747 H01L 29/80 - 29/812 H01L 29/872 ─────────────────────────────────────────────────── --Continued from the front page (56) References JP-A-7-7154 (JP, A) JP-A-5-82792 (JP, A) JP-A-7-130996 (JP, A) JP-A-4- 332173 (JP, A) JP-A-6-334188 (JP, A) JP-A-64-11367 (JP, A) JP-A-55-98872 (JP, A) Actually developed JP-A-54-108660 (JP, U) (58) Fields investigated (Int.Cl. 7 , DB name) H01L 29/78 H01L 29/06 H01L 29/47 H01L 29/73-29/735 H01L 29/74-29/747 H01L 29/80-29 / 812 H01L 29/872

Claims (19)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 第１の主電極と、 第２の主電極と、 前記第１の主電極と前記第２の主電極との間に介在して
設けられた高抵抗の第１導電型半導体層と、 前記第１の主電極と第２の主電極とを結ぶ方向とは略直
交する層であって、電流経路となる複数の間隙を有し、
前記第１の主電極付近から伸びる空乏層が達したときに
パンチスルー状態となって半導体装置本体のどの電極と
も異なる電位となる、前記第１導電型半導体層中に選択
的に形成された第２導電型埋込み層とを備えたことを特
徴とする縦型の半導体装置。1. A high-resistance first conductivity type semiconductor provided between a first main electrode, a second main electrode, and the first main electrode and the second main electrode. A layer and a layer that is substantially orthogonal to the direction connecting the first main electrode and the second main electrode, and has a plurality of gaps that serve as current paths,
When the depletion layer extending from the vicinity of the first main electrode reaches
A vertical type having a second-conductivity-type buried layer selectively formed in the first-conductivity-type semiconductor layer, which has a potential different from that of any electrode of the semiconductor device body in a punch-through state. semiconductor device. 【請求項２】第１の主電極と、 第２の主電極と、 前記第１の主電極と前記第２の主電極との間に介在して
設けられた高抵抗の第１導電型半導体層と、 前記第１導電型半導体層に接して設けられ、前記第１の
主電極から前記第２の主電極へ流れる電流を制御するた
めの制御電極を有する電流制御構造と、 前記第１の主電極と前記第２の主電極とを結ぶ方向とは
略直交する層であって、前記第１導電型半導体層中に選
択的に形成され、前記第１の主電極付近から伸びる空乏
層が達したときにパンチスルー状態となって電位固定さ
れる第２導電型埋込み層とを備えたことを特徴とする縦
型の半導体装置。2. A high-resistance first conductivity type semiconductor provided between a first main electrode, a second main electrode, and the first main electrode and the second main electrode. A current control structure that has a layer and a control electrode that is provided in contact with the first conductivity type semiconductor layer and that controls a current flowing from the first main electrode to the second main electrode; A depletion layer that is substantially perpendicular to the direction connecting the main electrode and the second main electrode, is selectively formed in the first-conductivity-type semiconductor layer, and extends from the vicinity of the first main electrode.
When the layer reaches the punch-through state, the potential is fixed.
Vertical, characterized in that a second conductivity type buried layer
Type semiconductor device. 【請求項３】ドレイン層と、 このドレイン層の表面上に形成されたドレイン電極と、 前記ドレイン層における前記ドレイン電極とは反対側の
面に形成された高抵抗の第１導電型半導体層と、 この第１導電型半導体層の前記ドレイン層を形成した側
とは反対側の表面上に選択的に形成された第２導電型ベ
ース層と、 この第２導電型ベース層の表面に選択的に形成された第
１導電型ソース層と、 この第１導電型ソース層と前記第２導電型ベース層とに
形成されたソース電極と、 前記第１導電型ソース層と前記第２導電型ベース層と前
記第１導電型半導体層とにゲート絶縁膜を介して接する
ゲート電極と、 前記ドレイン電極と前記ソース電極とを結ぶ方向とは略
直交する層であって、電流経路となる複数の間隙を有し
て前記第１導電型半導体層中に選択的に形成され、前記
ソース電極付近から伸びる空乏層が達したときにパンチ
スルー状態となって電位固定される第２導電型埋込み層
とを備えたことを特徴とする縦型の半導体装置。3. A drain layer, a drain electrode formed on a surface of the drain layer, and a high resistance first conductivity type semiconductor layer formed on a surface of the drain layer opposite to the drain electrode. A second conductivity type base layer selectively formed on the surface of the first conductivity type semiconductor layer opposite to the side where the drain layer is formed, and a second conductivity type base layer selectively formed on the surface of the second conductivity type base layer. A first conductive type source layer formed on the first conductive type source layer, a source electrode formed on the first conductive type source layer and the second conductive type base layer, the first conductive type source layer and the second conductive type base A plurality of gaps serving as current paths, the layers being substantially orthogonal to a direction connecting the drain electrode and the source electrode with a gate electrode that is in contact with the first conductive type semiconductor layer via a gate insulating film. Having the first conductivity type semiconductor layer Selectively formed in the above
Punch when the depletion layer extending from near the source electrode is reached
A vertical semiconductor device, comprising: a second conductive type buried layer in which the potential is fixed in a through state . 【請求項４】 請求項３に記載の半導体装置であって、 前記ゲート絶縁膜と前記ゲート電極とは、前記第２導電
型ベース層を貫通し、前記第１導電型半導体層の途中の
深さまで達する溝内に形成されていることを特徴とする
半導体装置。4. The semiconductor device according to claim 3, wherein the gate insulating film and the gate electrode penetrate the second conductive type base layer, and have a depth in the middle of the first conductive type semiconductor layer. A semiconductor device characterized in that it is formed in a groove reaching up to that point. 【請求項５】 請求項１乃至請求項３のいずれか１項に
記載の半導体装置であって、 前記第２導電型埋込み層はメッシュ形状を有することを
特徴とする半導体装置。5. The semiconductor device according to claim 1, wherein the second-conductivity-type buried layer has a mesh shape. 【請求項６】 請求項１乃至請求項３のいずれか１項に
記載の半導体装置であって、 前記第２導電型埋込み層はストライプ形状を有すること
を特徴とする半導体装置。6. The semiconductor device according to claim 1, wherein the second conductivity type buried layer has a stripe shape. 【請求項７】 請求項１乃至請求項３のいずれか１項に
記載の半導体装置であって、 前記第２導電型埋込み層はドット形状を有することを特
徴とする半導体装置。7. The semiconductor device according to claim 1, wherein the second conductivity type buried layer has a dot shape. 【請求項８】 請求項７に記載の半導体装置であって、 前記第２導電型埋込み層は、前記ドット形状を有する各
ドットが１行毎に半間隔ずれ、互いに隣り合う行及び列
のドットと等間隔に配置されたことを特徴とする半導体
装置。8. The semiconductor device according to claim 7, wherein, in the second conductive type buried layer, the dots having the dot shape are shifted by a half interval for each row, and the dots in rows and columns adjacent to each other. A semiconductor device characterized by being arranged at equal intervals. 【請求項９】 請求項３に記載の半導体装置であって、 前記ドレイン層は第１導電型であることを特徴とする半
導体装置。9. The semiconductor device according to claim 3, wherein the drain layer is of a first conductivity type. 【請求項１０】 請求項３に記載の半導体装置であっ
て、 前記ドレイン層は第２導電型であることを特徴とする半
導体装置。10. The semiconductor device according to claim 3, wherein the drain layer is of a second conductivity type. 【請求項１１】 請求項２に記載の半導体装置であっ
て、 前記第２導電型埋込み層は、前記制御電極とは異なる電
位であることを特徴とする半導体装置。11. The semiconductor device according to claim 2, wherein the second conductivity type buried layer has a potential different from that of the control electrode. 【請求項１２】 請求項１又は請求項２に記載の半導体
装置であって、 前記第１の主電極と前記第２の主電極との間の耐圧ＢＶ
と、 前記第１の主電極と前記第２の主電極との間における前
記第２導電型埋込み層の層数Ｍと、 これら第２導電型埋込み層により（Ｍ＋１）層に分割さ
れた第１導電型半導体層のうち、前記第１の主電極に最
も近い第１導電型半導体層の分担する電圧Ｖ1と、 前記第１の主電極に最も近い第１導電型半導体層の不純
物濃度Ｎ1 と、 前記第１の主電極に最も近い第１導電型半導体層の厚さ
Ｗ1 と、 前記各第２導電型埋込み層により（Ｍ＋１）層に分割さ
れた第１導電型半導体層のうち、前記第２の主電極に最
も近い第１導電型半導体層の分担する電圧Ｖ2と、 前記第２の主電極に最も近い第１導電型半導体層の不純
物濃度Ｎ2 と、 前記各第２導電型埋込み層により（Ｍ＋１）層に分割さ
れた第１導電型半導体層のうち、前記第１の主電極及び
前記第２の主電極から離れた（Ｍ−１）層の第１導電型
半導体層の分担する電圧Ｖｓと、 前記（Ｍ−１）層の第１導電型半導体層の不純物濃度Ｎ
ｓと、 前記（Ｍ−１）層の第１導電型半導体層の厚さＷｓとが
下記式の関係にあることを特徴とする半導体装置。 Ｖｓ＝（ＢＶ−Ｖ1 −Ｖ2 ）／（Ｍ−１）［Ｖ］ Ｖ1 ≧Ｖｓ Ｖ2 ≧Ｖｓ Ｎ1 ＜１．８９７ ×１０18×Ｖ1 -1.35 ［ｃｍ-3］ Ｎ2 ＜１．８９７ ×１０18×Ｖ2 -1.35 ［ｃｍ-3］ Ｎｓ＜１．８９７ ×１０18×Ｖｓ-1.35 ［ｃｍ-3］ Ｗ1 ＜１．１２４７×１０10×Ｎ1 -0.85 ［ｃｍ］ Ｗｓ＜１．１２４７×１０10×Ｎｓ-0.85 ［ｃｍ］12. The semiconductor device according to claim 1, wherein a breakdown voltage BV between the first main electrode and the second main electrode.
And the number M of layers of the second-conductivity-type buried layer between the first main electrode and the second main electrode, and a first (M + 1) layer divided by these second-conductivity-type buried layers. Among the conductivity type semiconductor layers, the voltage V 1 shared by the first conductivity type semiconductor layer closest to the first main electrode and the impurity concentration N 1 of the first conductivity type semiconductor layer closest to the first main electrode. A thickness W 1 of the first conductivity type semiconductor layer closest to the first main electrode, and a first conductivity type semiconductor layer divided into (M + 1) layers by each of the second conductivity type buried layers, The voltage V 2 shared by the first conductivity type semiconductor layer closest to the second main electrode, the impurity concentration N 2 of the first conductivity type semiconductor layer closest to the second main electrode, and the second conductivity type The first main electrode of the first conductivity type semiconductor layer divided into (M + 1) layers by the type burying layer; Serial voltage Vs to share the second distant from the main electrode (M-1) layer first conductive type semiconductor layer, the (M-1) impurity concentration of the first conductivity type semiconductor layer of the layer N
s and the thickness Ws of the first conductivity type semiconductor layer of the (M-1) layer have a relationship of the following formula. Vs = (BV−V 1 −V 2 ) / (M−1) [V] V 1 ≧ Vs V 2 ≧ Vs N 1 <1.897 × 10 18 × V 1 −1.35 [cm −3 ] N 2 < 1.897 × 10 18 × V 2 −1.35 [cm −3 ] Ns <1.897 × 10 18 × Vs −1.35 [cm −3 ] W 1 <1.1247 × 10 10 × N 1 −0.85 [cm] Ws <1.1247 × 10 10 × Ns -0.85 [cm] 【請求項１３】 請求項３に記載の半導体装置であっ
て、 前記ソース電極と前記ドレイン電極との間の耐圧ＢＶ
と、 前記ソース電極と前記ドレイン電極との間における前記
第２導電型埋込み層の層数Ｍと、 これら第２導電型埋込み層により（Ｍ＋１）層に分割さ
れた第１導電型半導体層のうち、前記第２導電型ベース
層に接する第１導電型半導体層の分担する電圧Ｖ1 と、 前記第２導電型ベース層に接する第１導電型半導体層の
不純物濃度Ｎ1 と、 前記第２導電型ベース層に接する第１導電型半導体層の
厚さＷ1 と、 前記各第２導電型埋込み層により（Ｍ＋１）層に分割さ
れた第１導電型半導体層のうち、前記ドレイン層に接す
る第１導電型半導体層の分担する電圧Ｖ2 と、 前記ドレイン層に接する第１導電型半導体層の不純物濃
度Ｎ2 と、 前記各第２導電型埋込み層により（Ｍ＋１）層に分割さ
れた第１導電型半導体層のうち、前記第２導電型ベース
層及び前記ドレイン層の双方に接しない（Ｍ−１）層の
第１導電型半導体層の分担する電圧Ｖｓと、 前記（Ｍ−１）層の第１導電型半導体層の不純物濃度Ｎ
ｓと、 前記（Ｍ−１）層の第１導電型半導体層の厚さＷｓと が下記式の関係にあることを特徴とする半導体装置。 Ｖｓ＝（ＢＶ−Ｖ1 −Ｖ2 ）／（Ｍ−１）［Ｖ］ Ｖ1 ≧Ｖｓ Ｖ2 ≧Ｖｓ Ｎ1 ＜１．８９７ ×１０18×Ｖ1 -1.35 ［ｃｍ-3］ Ｎ2 ＜１．８９７ ×１０18×Ｖ2 -1.35 ［ｃｍ-3］ Ｎｓ＜１．８９７ ×１０18×Ｖｓ-1.35 ［ｃｍ-3］ Ｗ1 ＜１．１２４７×１０10×Ｎ1 -0.85 ［ｃｍ］ Ｗｓ＜１．１２４７×１０10×Ｎｓ-0.85 ［ｃｍ］13. The semiconductor device according to claim 3, wherein a breakdown voltage BV between the source electrode and the drain electrode.
And the number M of the second conductivity type buried layers between the source electrode and the drain electrode, and among the first conductivity type semiconductor layers divided into (M + 1) layers by these second conductivity type buried layers. A voltage V 1 shared by a first conductivity type semiconductor layer in contact with the second conductivity type base layer, an impurity concentration N 1 of a first conductivity type semiconductor layer in contact with the second conductivity type base layer, and the second conductivity The thickness W 1 of the first conductive type semiconductor layer in contact with the type base layer, and the first conductive type semiconductor layer in the (M + 1) layer divided by the second conductive type embedded layers into the first conductive type semiconductor layer in contact with the drain layer. The voltage V 2 shared by the first-conductivity-type semiconductor layer, the impurity concentration N 2 of the first-conductivity-type semiconductor layer in contact with the drain layer, and the first M-layer divided by the second-conductivity-type buried layer Of the conductive type semiconductor layer, the second conductive type ba Not in contact with both layers and the drain layers (M-1) and the voltage Vs to share the first conductive type semiconductor layer of layers, the (M-1) impurity concentration of the first conductivity type semiconductor layer of the layer N
s and the thickness Ws of the first conductivity type semiconductor layer of the (M-1) layer have a relationship of the following formula. Vs = (BV−V 1 −V 2 ) / (M−1) [V] V 1 ≧ Vs V 2 ≧ Vs N 1 <1.897 × 10 18 × V 1 −1.35 [cm −3 ] N 2 < 1.897 × 10 18 × V 2 −1.35 [cm −3 ] Ns <1.897 × 10 18 × Vs −1.35 [cm −3 ] W 1 <1.1247 × 10 10 × N 1 −0.85 [cm] Ws <1.1247 × 10 10 × Ns -0.85 [cm] 【請求項１４】 請求項１乃至請求項３のいずれか１項
に記載の半導体装置であって、 前記第２導電型埋込み層を取り囲むように略方形状に形
成された埋込み第２導電型ガードリング領域を備えたこ
とを特徴とする半導体装置。14. The semiconductor device according to claim 1, wherein the buried second conductivity type guard is formed in a substantially rectangular shape so as to surround the second conductivity type buried layer. A semiconductor device comprising a ring region. 【請求項１５】 請求項１乃至請求項３のいずれか１項
に記載の半導体装置であって、 前記第２導電型埋込み層を取り囲むように略方形状に形
成され、前記第２導電型埋込み層のキャリア密度よりも
低いキャリア密度を有する埋込み第２導電型リサーフ領
域を備えたことを特徴とする半導体装置。15. The semiconductor device according to claim 1, wherein the semiconductor device is formed in a substantially rectangular shape so as to surround the second conductive type buried layer, and the second conductive type buried layer is formed. A semiconductor device comprising a buried second conductivity type RESURF region having a carrier density lower than that of the layer. 【請求項１６】 請求項１乃至請求項３のいずれか１項
に記載の半導体装置であって、 前記第１導電型半導体層の終端部は傾斜を有するベベル
構造に形成されたことを特徴とする半導体装置。16. The semiconductor device according to claim 1, wherein a terminal portion of the first conductivity type semiconductor layer is formed in a bevel structure having an inclination. Semiconductor device. 【請求項１７】 第１の主電極と、 第２の主電極と、 前記第１の主電極と前記第２の主電極との間に介在して
設けられた高抵抗の第１導電型半導体層と、 前記第１導電型半導体層中に選択的に形成され、浮いた
電位を有して前記第１の主電極と第２の主電極とを結ぶ
方向とは略直交する方向に拡がって配置されており、電
流経路として機能する複数の間隙を有し、前記第１の主
電極付近から伸びる空乏層が自己に達したときに半導体
装置本体のどの電極とも異なる前記浮いた電位となる第
２導電型埋込み層とを備えた半導体装置であって、 前記第１の主電極と前記第２の主電極との間の耐圧ＢＶ
と、 前記第１の主電極と前記第２の主電極との間における前
記第２導電型埋込み層の層数Ｍと、 前記第２導電型埋込み層と前記第１の主電極との間で前
記第１の主電極に近接して配置された前記第１導電型半
導体層の第１領域の分担する電圧Ｖ1 と、 前記第１導電型半導体層の第１領域の不純物濃度Ｎ
1 と、 前記第１導電型半導体層の第１領域の厚さＷ1 と、 前記第２導電型埋込み層と前記第２の主電極との間で前
記第２の主電極に近接して配置された第１導電型半導体
層の第２領域の分担する電圧Ｖ2 と、 前記第１導電型半導体層の第２領域の不純物濃度Ｎ
2 と、 前記第１導電型半導体層における第１領域と第２領域と
の間である第３領域の分担する電圧Ｖｓと、 前記第１導電型半導体層の第３領域の不純物濃度Ｎ
ｓと、 前記第１導電型半導体層の第３領域の厚さＷｓと、 が下記式の関係にあることを特徴とする半導体装置。 Ｖｓ＝（ＢＶ−Ｖ1 −Ｖ2 ）／（Ｍ−１）［Ｖ］ Ｖ1 ≧Ｖｓ Ｖ2 ≧Ｖｓ Ｎ1 ＜１．８９７ ×１０18×Ｖ1 -1.35 ［ｃｍ-3］ Ｎ2 ＜１．８９７ ×１０18×Ｖ2 -1.35 ［ｃｍ-3］ Ｎｓ＜１．８９７ ×１０18×Ｖｓ-1.35 ［ｃｍ-3］ Ｗ1 ＜１．１２４７×１０10×Ｎ1 -0.85 ［ｃｍ］ Ｗｓ＜１．１２４７×１０10×Ｎｓ-0.85 ［ｃｍ］17. A high-resistance first conductivity type semiconductor provided between a first main electrode, a second main electrode, and the first main electrode and the second main electrode. A layer and a layer selectively formed in the first conductivity type semiconductor layer and having a floating potential and extending in a direction substantially orthogonal to a direction connecting the first main electrode and the second main electrode. A plurality of gaps that are arranged and function as a current path, and have a floating potential that is different from any electrode of the semiconductor device body when the depletion layer extending from the vicinity of the first main electrode reaches itself. A withstand voltage BV between the first main electrode and the second main electrode, which is a semiconductor device having a two-conductivity type buried layer.
And the number M of layers of the second conductivity type buried layer between the first main electrode and the second main electrode, and between the second conductivity type buried layer and the first main electrode. The voltage V 1 shared by the first region of the first conductivity type semiconductor layer arranged close to the first main electrode and the impurity concentration N of the first region of the first conductivity type semiconductor layer.
1 , a thickness W 1 of the first region of the first conductive type semiconductor layer, and a space between the second conductive type buried layer and the second main electrode, which is disposed close to the second main electrode. It has been the voltage V 2 to share the second region of the first conductivity type semiconductor layer, the impurity concentration of the second region of the first conductivity type semiconductor layer N
2 , a voltage Vs shared by a third region between the first region and the second region of the first conductivity type semiconductor layer, and an impurity concentration N of the third region of the first conductivity type semiconductor layer.
and s and the thickness W s of the third region of the first conductivity type semiconductor layer have the following relationship. Vs = (BV−V 1 −V 2 ) / (M−1) [V] V 1 ≧ Vs V 2 ≧ Vs N 1 <1.897 × 10 18 × V 1 −1.35 [cm −3 ] N 2 < 1.897 × 10 18 × V 2 −1.35 [cm −3 ] Ns <1.897 × 10 18 × Vs −1.35 [cm −3 ] W 1 <1.1247 × 10 10 × N 1 −0.85 [cm] Ws <1.1247 × 10 10 × Ns -0.85 [cm] 【請求項１８】 請求項１７に記載の半導体装置であっ
て、 前記第１導電型半導体層に接して設けられ、前記第１の
主電極から前記第２の主電極へ流れる電流を制御するた
めの制御電極を有する電流制御構造を備えたことを特徴
とする半導体装置。18. The semiconductor device according to claim 17, wherein the semiconductor device is provided in contact with the first conductivity type semiconductor layer and controls a current flowing from the first main electrode to the second main electrode. 7. A semiconductor device comprising a current control structure having the control electrode according to claim 1. 【請求項１９】ドレイン層と、 このドレイン層の表面上に形成されたドレイン電極と、 前記ドレイン層における前記ドレイン電極とは反対側の
面に形成された高抵抗の第１導電型半導体層と、 この第１導電型半導体層の前記ドレイン層を形成した側
とは反対側の表面に選択的に形成された第２導電型ベー
ス層と、 この第２導電型ベース層の表面に選択的に形成された第
１導電型ソース層と、 この第１導電型ソース層と前記第２導電型ベース層とに
形成されたソース電極と、 前記第１導電型ソース層と前記第２導電型ベース層と前
記第１導電型半導体層とにゲート絶縁膜を介して接する
ゲート電極と、 前記第１導電型半導体層中に選択的に形成され、浮いた
電位を有して前記ドレイン電極と前記ソース電極とを結
ぶ方向とは略直交する方向に拡がって配置されており、
電流経路として機能する複数の間隙を有し、前記ソース
電極付近から伸びる空乏層が自己に達したときに半導体
装置本体のどの電極とも異なる前記浮いた電位となる第
２導電型埋込み層とを備えた半導体装置であって、 前記ドレイン電極と前記ソース電極との間の耐圧ＢＶ
と、 前記ドレイン電極と前記ソース電極との間における前記
第２導電型埋込み層の層数Ｍと、 前記第２導電型埋込み層と前記ソース電極との間で前記
ソース電極に近接して配置された前記第１導電型半導体
層の第１領域の分担する電圧Ｖ1 と、 前記第１導電型半導体層の第１領域の不純物濃度Ｎ
1 と、 前記第１導電型半導体層の第１領域の厚さＷ1 と、 前記第２導電型埋込み層と前記ドレイン電極との間で前
記ドレイン電極に近接して配置された第１導電型半導体
層の第２領域の分担する電圧Ｖ2 と、 前記第１導電型半導体層の第２領域の不純物濃度Ｎ
2 と、 前記第１導電型半導体層における第１領域と第２領域と
の間である第３領域の分担する電圧Ｖｓと、 前記第１導電型半導体層の第３領域の不純物濃度Ｎ
ｓと、 前記第１導電型半導体層の第３領域の厚さＷｓと、 が下記式の関係にあることを特徴とする半導体装置。 Ｖｓ＝（ＢＶ−Ｖ1 −Ｖ2 ）／（Ｍ−１）［Ｖ］ Ｖ1 ≧Ｖｓ Ｖ2 ≧Ｖｓ Ｎ1 ＜１．８９７ ×１０18×Ｖ1 -1.35 ［ｃｍ-3］ Ｎ2 ＜１．８９７ ×１０18×Ｖ2 -1.35 ［ｃｍ-3］ Ｎｓ＜１．８９７ ×１０18×Ｖｓ-1.35 ［ｃｍ-3］ Ｗ1 ＜１．１２４７×１０10×Ｎ1 -0.85 ［ｃｍ］ Ｗｓ＜１．１２４７×１０10×Ｎｓ-0.85 ［ｃｍ］19. A drain layer, a drain electrode formed on a surface of the drain layer, and a high resistance first conductivity type semiconductor layer formed on a surface of the drain layer opposite to the drain electrode. A second conductivity type base layer selectively formed on the surface of the first conductivity type semiconductor layer opposite to the side where the drain layer is formed, and a second conductivity type base layer selectively on the surface of the second conductivity type base layer. The formed first conductivity type source layer, the source electrode formed on the first conductivity type source layer and the second conductivity type base layer, the first conductivity type source layer and the second conductivity type base layer A gate electrode in contact with the first conductive type semiconductor layer via a gate insulating film, and the drain electrode and the source electrode selectively formed in the first conductive type semiconductor layer and having a floating potential. A direction that is approximately orthogonal to the direction that connects It is spread over the
A second conductivity type buried layer having a plurality of gaps functioning as a current path and having a floating potential different from any electrode of the semiconductor device body when the depletion layer extending from the vicinity of the source electrode reaches itself. And a breakdown voltage BV between the drain electrode and the source electrode.
A number M of buried layers of the second conductivity type between the drain electrode and the source electrode, and a space between the buried layer of the second conductivity type and the source electrode, which is disposed close to the source electrode. And the voltage V 1 shared by the first region of the first conductivity type semiconductor layer and the impurity concentration N of the first region of the first conductivity type semiconductor layer.
1 , a thickness W 1 of the first region of the first conductive type semiconductor layer, and a first conductive type disposed between the buried layer of the second conductive type and the drain electrode in proximity to the drain electrode. The voltage V 2 shared by the second region of the semiconductor layer and the impurity concentration N of the second region of the first conductivity type semiconductor layer.
2 , a voltage Vs shared by a third region between the first region and the second region of the first conductivity type semiconductor layer, and an impurity concentration N of the third region of the first conductivity type semiconductor layer.
and s and the thickness W s of the third region of the first conductivity type semiconductor layer have the following relationship. Vs = (BV−V 1 −V 2 ) / (M−1) [V] V 1 ≧ Vs V 2 ≧ Vs N 1 <1.897 × 10 18 × V 1 −1.35 [cm −3 ] N 2 < 1.897 × 10 18 × V 2 −1.35 [cm −3 ] Ns <1.897 × 10 18 × Vs −1.35 [cm −3 ] W 1 <1.1247 × 10 10 × N 1 −0.85 [cm] Ws <1.1247 × 10 10 × Ns -0.85 [cm]
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