JP3392665B2 - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JP3392665B2
JP3392665B2 JP29396696A JP29396696A JP3392665B2 JP 3392665 B2 JP3392665 B2 JP 3392665B2 JP 29396696 A JP29396696 A JP 29396696A JP 29396696 A JP29396696 A JP 29396696A JP 3392665 B2 JP3392665 B2 JP 3392665B2
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layer
conductivity type
type
electrode
semiconductor
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JP29396696A
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JPH09191109A (en
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智樹 井上
一郎 大村
弘通 大橋
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株式会社東芝
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Priority to JP28718295 priority
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Priority to JP29396696A priority patent/JP3392665B2/en
Publication of JPH09191109A publication Critical patent/JPH09191109A/en
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    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
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Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device used for high power control, and more particularly to a semiconductor device capable of reducing a voltage drop in an ON state.

[0002]

2. Description of the Related Art Recently, as a semiconductor device for power control, S
i MOSFETs are widely used. This MOSF
The ET is a unipolar element, and has various advantages such as high speed and easy control.

FIG. 49 is a schematic diagram showing the structure of this type of MOSFET. In this MOSFET, an n-type base layer 302 is formed on an n-type substrate 301 as an n-type drain layer, and a plurality of p-type base layers 303 are selectively formed on the surface of the n-type base layer 302 by diffusion. An n-type source layer 304 is selectively formed on the surface of each p-type base layer 303.

The p-type base layer 303 and the n-type source layer 30
A gate electrode 306 is provided on a region from 4 to the other p-type base layer 303 and the n-type source layer 304 through the n-type base layer 302 and a gate insulating film 305. A source electrode 307 is provided on each of the p-type base layer 303 and the n-type source layer 304 and the other p-type base layer 303 and the n-type source layer 304 so as to sandwich the gate electrode 306. Has been formed.

The n-type substrate 301 is composed of the n-type base layer 3
A drain electrode 308 is formed on the surface opposite to 02.

Such a MOSFET is a unipolar device in which one type of carrier contributes to conduction. Therefore, in order to reduce the resistance of the MOSFET, it is required to increase the impurity concentration of the n-type base layer 302 to reduce the resistivity and reduce the thickness of the n-type base layer 302.

However, when the impurity concentration of the n-type base layer 302 is increased, the maximum value of the electric field strength formed directly below the p-type base layer 303 in the off state of the MOSFET increases. Therefore, in the MOSFET, the impurity concentration in the n-type base layer 302 needs to be suppressed so that the maximum value of the electric field intensity does not exceed the limit value of the electric field intensity of the n-type base layer 302. The withstand voltage of the MOSFET is n.
Since it is determined by the total amount of impurities in the type base layer 302, the n-type base layer 302 is formed thick when improving the breakdown voltage. For this reason, in the high breakdown voltage MOSFET, the voltage drop in the ON state rapidly increases.

In summary, in this type of MOSFET, it is desired that the breakdown voltage be improved and the ON resistance be lowered. To improve the breakdown voltage, a method of increasing the thickness W of the n-type base layer 302, or n
There is a method of reducing the carrier density N of the mold base layer 302.

However, in these methods, as shown by the solid line in FIG.
It is theoretically required to increase the on-resistance by about two digits. That is, according to the solid line in FIG.
It is a theoretical limit obtained from the physical property value of i, and it is theoretically known that a MOSFET having a high breakdown voltage has a higher ON resistance than an IGBT or the like.

Next, a bipolar transistor (hereinafter referred to as BJT) and an IGBT which are used for power control similarly to the MOSFET will be sequentially described.

FIG. 51 is a sectional view schematically showing the structure of the bipolar transistor. In this BJT, an n-type base layer 312 is formed on an n-type substrate 311 serving as an n-type collector layer. A p-type base layer 313 is selectively diffused on the surface of the n-type base layer 312. An n-type emitter layer 314 is selectively formed on the surface of the p-type base layer 313. A base electrode 315 is formed on the p-type base layer 313. An emitter electrode 316 is formed on the n-type emitter layer 314.

A collector electrode 317 is formed on the surface of the n-type substrate 311 opposite to the n-type base layer 312.

Such a BJT has an n-type base layer 312.
Since most of the current flowing inside is due to electrons, MOSFE
As with T, the voltage drop in the ON state rapidly increases as the breakdown voltage increases.

On the other hand, an attempt has been made to reduce the voltage drop in the ON state by making a high resistance n-type base layer such as an IGBT into a highly-implanted state.

FIG. 52 is a sectional view schematically showing the structure of the IGBT. This IGBT has a high resistance n-type base layer 3
A plurality of p-type base layers 322 are selectively formed on the surface of 21. An n-type source layer 323 is selectively diffused on the surface of each p-type base layer 322. A gate electrode 325 is provided on a region from the p-type base layer 322 and the n-type source layer 323 to the other p-type base layer 322 via the n-type base layer 321 and a gate insulating film 324.
Is provided. The p-type base layer 322 and the n-type source layer 3 are sandwiched so as to sandwich the gate electrode 325.
23, and the source electrode 326 is formed on the other p-type base layer 322 and the n-type source layer 323, respectively. A drain electrode 328 is formed on the back surface of the n-type base layer 321 via a p-type drain layer 327.

Such an IGBT has a gate electrode 325.
When a positive voltage is applied to the n-type base layer 322, an n-type inversion layer is formed below the gate electrode 325, and the n-type base layer 321 and the n-type source layer 323 are short-circuited.
Therefore, electrons are injected into the n-type base layer 321, holes are injected from the p-type drain layer 327 in accordance with the amount of the electrons, and the n-type base layer 321 is in a high injection state, so that the IGBT is
Turns on. In this ON state, the n-type base layer 321 is in a high implantation state, and therefore the n-type base layer 32 is
Even if the resistivity of 1 is high, the resistance of the IGBT is low.

[0017]

However, this I
In the GBT, a current does not flow unless a voltage higher than the diffusion potential difference between the n-type base layer 321 and the p-type drain layer 327 is applied between the source electrode 326 and the drain electrode 328. Therefore, as shown in FIG. 53, when the current value of this IGBT is low, the voltage drop in the ON state is higher than that of the MOSFET, and the conduction loss is large.

More specifically, the MOSFET or BJT has a problem that the voltage drop in the ON state rapidly increases as the withstand voltage increases. On the other hand, the IGBT has a problem that the conduction loss increases in the low current state.

The present invention has been made in consideration of the above situation, and an object thereof is to provide a semiconductor device capable of reducing the voltage drop in the ON state even with a high breakdown voltage.

[0020]

The invention according to claim 1 provides a first main electrode, a second main electrode, and an interposition between the first main electrode and the second main electrode. The first conductive type semiconductor layer having a high resistance and the direction connecting the first main electrode and the second main electrode are substantially orthogonal to each other, and a plurality of gaps serving as current paths are formed. A first conductive type semiconductor layer, which has a punch-through state when reaching a depletion layer extending from the vicinity of the first main electrode and has a potential different from that of any electrode of the semiconductor device body. A vertical semiconductor device comprising a selectively formed second conductive type buried layer.

The invention according to claim 2 is provided so as to be interposed between the first main electrode, the second main electrode, and the first main electrode and the second main electrode. And a control electrode for controlling a current flowing from the first main electrode to the second main electrode, the control electrode being provided in contact with the first conductivity type semiconductor layer and having a high resistance. The current control structure is a layer that is substantially orthogonal to the direction connecting the first main electrode and the second main electrode, and is formed selectively in the first conductivity type semiconductor layer . From near the main electrode of
When the depletion layer reaches the punch-through state, the potential is fixed.
A vertical semiconductor device having a second conductivity type buried layer to be constant.

Further, in the invention corresponding to claim 3, the drain layer, the drain electrode formed on the surface of the drain layer, and the high-level electrode formed on the surface of the drain layer opposite to the drain electrode. A first conductive type semiconductor layer of a resistor; a second conductive type base layer selectively formed on a surface of the first conductive type semiconductor layer opposite to the side where the drain layer is formed; A first conductive type source layer selectively formed on the surface of the conductive type base layer; a source electrode formed on the first conductive type source layer and the second conductive type base layer; and a first conductive type The gate electrode is in contact with the source layer, the second conductivity type base layer, and the first conductivity type semiconductor layer via the gate insulating film, and the direction connecting the drain electrode and the source electrode is substantially orthogonal to each other. , Multiple gaps that serve as current paths Selectively formed on the first conductive semiconductor layer has, depletion extending from the source electrode near
When the layer reaches the punch-through state, the potential is fixed.
It is a vertical semiconductor device having a second conductivity type buried layer.

The invention according to claim 4 is the semiconductor device according to claim 3, wherein the gate insulating film and the gate electrode penetrate the second conductivity type base layer, This is a semiconductor device formed in a groove that reaches a depth in the middle of a one-conductivity type semiconductor layer.

Further, an invention according to claim 5 is the semiconductor device according to any one of claims 1 to 3, wherein the second conductivity type buried layer has a mesh shape. is there.

The invention according to claim 6 is the semiconductor device according to any one of claims 1 to 3, wherein the second conductivity type buried layer has a stripe shape. is there. Furthermore, the invention corresponding to claim 7
Ming corresponds to any one of claims 1 to 3.
A semiconductor device, wherein the second conductive type buried layer is a dot
A semiconductor device having a shape. Also, it corresponds to claim 8.
The invention according to claim 7 is the semiconductor device according to claim 7,
The second conductivity type buried layer has the dot shape.
Dot dots are offset by half a line for each line and are adjacent to each other
And semiconductor devices arranged at equal intervals with the dots in the rows.
It

The invention according to claim 9 is the semiconductor device according to claim 3, wherein the drain layer is of the first conductivity type.

The invention according to claim 10 is the semiconductor device according to claim 3, wherein the drain layer is of the second conductivity type.

Further, the invention according to claim 11 is the semiconductor device according to claim 2, wherein the second conductivity type buried layer has a potential different from that of the control electrode.

The invention according to claim 12 is the semiconductor device according to claim 1 or 2, wherein the breakdown voltage BV between the first main electrode and the second main electrode is ,
The number M of buried layers of the second conductivity type between the first main electrode and the second main electrode, and the first conductivity type divided into (M + 1) layers by these buried layers of the second conductivity type. Of the semiconductor layers, the voltage V 1 shared by the first conductivity type semiconductor layer closest to the first main electrode, and the impurity concentration N 1 of the first conductivity type semiconductor layer closest to the first main electrode, The first
The thickness W 1 of the first conductivity type semiconductor layer closest to the main electrode of
Of the first conductivity type semiconductor layers divided into the (M + 1) layers by the respective second conductivity type buried layers, the voltage V 2 shared by the first conductivity type semiconductor layer closest to the second main electrode, and Due to the impurity concentration N 2 of the first conductivity type semiconductor layer closest to the second main electrode and the second conductivity type buried layer, (M + 1)
Of the first conductivity type semiconductor layers divided into layers, the voltage Vs shared by the first conductivity type semiconductor layers of the (M-1) layer separated from the first main electrode and the second main electrode, (M-
In the semiconductor device, the impurity concentration Ns of the first conductivity type semiconductor layer of the 1) layer and the thickness Ws of the first conductivity type semiconductor layer of the (M-1) layer have the following relationship.

Vs = (BV−V 1 −V 2 ) / (M−1) [V] V 1 ≧ Vs V 2 ≧ Vs N 1 <1.897 × 10 18 × V 1 -1.35 [cm −3 ] N 2 <1.897 × 10 18 × V 2 −1.35 [cm −3 ] Ns <1.897 × 10 18 × Vs −1.35 [cm −3 ] W 1 <1.1247 × 10 10 × N 1 −0.85 [Cm] Ws <1.1247 × 10 10 × Ns −0.85 [cm] Furthermore, the invention corresponding to claim 13 is the semiconductor device according to claim 3, wherein the source electrode and the drain electrode are Withstand voltage BV between them, the number M of buried layers of the second conductivity type between the source electrode and the drain electrode, and a first conductivity type divided into (M + 1) layers by these second conductivity type buried layers. Among the semiconductor layers, the voltage V shared by the first conductive type semiconductor layer in contact with the second conductive type base layer
1 , the impurity concentration N 1 of the first conductive type semiconductor layer in contact with the second conductive type base layer, the thickness W 1 of the first conductive type semiconductor layer in contact with the second conductive type base layer, and Of the first conductivity type semiconductor layers divided into (M + 1) layers by the two conductivity type buried layer, the voltage V 2 shared by the first conductivity type semiconductor layer in contact with the drain layer and the first conductivity type in contact with the drain layer Of the impurity concentration N 2 of the first conductivity type semiconductor layer and the second conductivity type base layer and the drain layer of the first conductivity type semiconductor layer divided into (M + 1) layers by the second conductivity type buried layers. The voltage Vs shared by the first conductivity type semiconductor layer of the (M-1) layer which is not in contact with the first conductivity type semiconductor layer of the (M-1) layer
In the semiconductor device, the impurity concentration Ns of the conductivity type semiconductor layer and the thickness Ws of the first conductivity type semiconductor layer of the (M-1) layer have the following relationship.

Vs = (BV−V 1 −V 2 ) / (M−1) [V] V 1 ≧ Vs V 2 ≧ Vs N 1 <1.897 × 10 18 × V 1 -1.35 [cm −3 ] N 2 <1.897 × 10 18 × V 2 −1.35 [cm −3 ] Ns <1.897 × 10 18 × Vs −1.35 [cm −3 ] W 1 <1.1247 × 10 10 × N 1 −0.85 [Cm] Ws <1.1247 × 10 10 × Ns −0.85 [cm] The invention according to claim 14 is the semiconductor device according to any one of claims 1 to 3. A semiconductor device having a buried second conductivity type guard ring region formed in a substantially rectangular shape so as to surround the second conductivity type buried layer.

Further, an invention according to claim 15 is the semiconductor device according to any one of claims 1 to 3, wherein the semiconductor device is formed in a substantially rectangular shape so as to surround the second conductive type buried layer. And a buried second conductivity type RESURF region having a carrier density lower than the carrier density of the second conductivity type buried layer.

Claims16The invention corresponding to
A semiconductor device corresponding to any one of claims 1 to 3.
And the terminating portion of the first conductivity type semiconductor layer has an inclination.
The semiconductor device has a bevel structure.Furthermore
The invention corresponding to claim 17 provides a first main electrode,
Two main electrodes, the first main electrode and the second main electrode
High-resistance first-conductivity-type semiconductor layer provided between
And is selectively formed in the first conductive type semiconductor layer and floats.
The first main electrode and the second main electrode with a predetermined potential.
It is arranged so as to extend in a direction substantially orthogonal to the connecting direction.
Has a plurality of gaps that function as current paths,
When the depletion layer extending from the vicinity of the main electrode of 1 reaches itself
The floating potential different from any electrode of the semiconductor device body
A semiconductor device having a second conductivity type buried layer
The breakdown voltage between the first main electrode and the second main electrode.
BV and between the first main electrode and the second main electrode
The number M of the buried layers of the second conductivity type in the
The first main electrode between the electric buried layer and the first main electrode.
A first conductive type semiconductor layer disposed adjacent to the electrode;
Voltage V shared by one region 1 And the first conductive type semiconductor layer
Concentration N of the first region of 1 And the first conductivity type semiconductor
Thickness W of the first region of the layer 1 And the buried layer of the second conductivity type
Between the second main electrode and close to the second main electrode
The charge sharing of the second region of the arranged first conductivity type semiconductor layer
Pressure V 2 And impurities in the second region of the first conductivity type semiconductor layer
Concentration N 2 And a first region in the first conductivity type semiconductor layer
And the voltage Vs shared by the third region between the second region and the second region
And the impurity concentration N of the third region of the first conductivity type semiconductor layer.
s And the thickness W of the third region of the first conductivity type semiconductor layer
s And are semiconductor devices that have the following relationship. Vs = (BV-V 1 -V 2 ) / (M-1) [V] V 1 ≧ Vs V 2 ≧ Vs N 1 <1.897 × 10 18 × V 1 -1.35 [Cm -3 ] N 2 <1.897 × 10 18 × V 2 -1.35 [Cm -3 ] Ns <1.897 × 10 18 × Vs -1.35 [Cm -3 ] W 1 <1.1247 × 10 Ten × N 1 -0.85 [Cm] Ws <1.1247 × 10 Ten × Ns -0.85 [Cm] The invention corresponding to claim 18 corresponds to claim 17.
A semiconductor device that is connected to the first conductivity type semiconductor layer.
Provided from the first main electrode to the second main electrode
Current control with control electrode for controlling current flowing to
It is a semiconductor device having a control structure. Further, claim 19
The invention corresponding to is a drain layer and a surface of this drain layer.
The drain electrode formed on the surface and the drain layer.
The high resistance formed on the surface opposite to the drain electrode.
Of the first conductive type semiconductor layer and the first conductive type semiconductor layer
Selective on the surface opposite to the side where the drain layer is formed
And a second conductive type base layer formed on the second conductive type base layer.
Source layer selectively formed on the surface of the source layer
And the first conductive type source layer and the second conductive type base layer
And a source electrode formed on the first conductivity type source layer
And the second conductive type base layer and the first conductive type semiconductor layer
A gate electrode in contact with the first electrode via a gate insulating film,
It is selectively formed in the conductive semiconductor layer and has a floating potential.
And the direction connecting the drain electrode and the source electrode
Are arranged so as to extend in a direction substantially orthogonal to each other.
Near the source electrode with multiple gaps that function as
When the depletion layer extending from the self reaches the semiconductor device body
Second conductivity type having the floating potential different from any of the electrodes
A semiconductor device having a buried layer, wherein the drain
The breakdown voltage BV between the electrode and the source electrode, and the drain voltage.
Second conductivity type between the source electrode and the source electrode
The number M of buried layers, the buried layer of the second conductivity type and the
A source electrode and a source electrode in close proximity to the source electrode.
The voltage V shared by the first region of the first conductivity type semiconductor layer 1
And the impurity concentration N of the first region of the first conductivity type semiconductor layer
1 And the thickness W of the first region of the first conductive type semiconductor layer
1 Of the buried layer of the second conductivity type and the drain electrode
First conductivity type disposed between and adjacent to the drain electrode
The voltage V shared by the second region of the semiconductor layer 2 And the first guide
Impurity concentration N in the second region of the electric semiconductor layer 2 And the first
Between the first region and the second region in the conductivity type semiconductor layer
Voltage Vs shared by the third region and the first conductivity type semiconductor
Impurity concentration N in the third region of the body layer s And said first conductivity type half
Thickness W of the third region of the conductor layer s And are related by the following formula
It is a semiconductor device. Vs = (BV-V 1 -V 2 ) / (M-1) [V] V 1 ≧ Vs V 2 ≧ Vs N 1 <1.897 × 10 18 × V 1 -1.35 [Cm -3 ] N 2 <1.897 × 10 18 × V 2 -1.35 [Cm -3 ] Ns <1.897 × 10 18 × Vs -1.35 [Cm -3 ] W 1 <1.1247 × 10 Ten × N 1 -0.85 [Cm] Ws <1.1247 × 10 Ten × Ns -0.85 [Cm]

(Operation) Therefore, in the invention corresponding to claim 1, the depletion layer has the first conductivity type semiconductor layer in proportion to the increase of the applied voltage in the off state by taking the above means. The inside spreads from the second main electrode side to the first main electrode side,
When this depletion layer reaches the second-conductivity-type buried layer, the second-conductivity-type buried layer fixes the electric field strength in the depletion layer and suppresses its rise due to the punch-through phenomenon. Of the first conductivity type semiconductor layer is increased within a range having a limit value of the electric field strength exceeding the maximum value of the above-mentioned value to reduce the on-resistance, thereby reducing the voltage drop in the on-state even with a high breakdown voltage. be able to.

According to the invention of claim 2, claim 1
In addition to the action corresponding to, the current control structure can control the current flowing from the first main electrode to the second main electrode.

Further, according to the third aspect of the invention, in the off state, the depletion layer spreads from the second conductivity type base layer to the drain electrode side in proportion to the increase of the applied voltage, and the depletion layer becomes the second depletion layer. When reaching the conductivity type buried layer, the second conductivity type buried layer fixes the electric field strength in the depletion layer and suppresses its rise due to the punch-through phenomenon, so that an electric field exceeding the maximum value of the electric field strength at this time is reached. First in the range with a limit value of strength
By increasing the impurity concentration of the conductive type semiconductor layer to reduce the on-resistance, it is possible to reduce the voltage drop in the on-state even with a high breakdown voltage.

Further, according to the invention of claim 4, the gate insulating film and the gate electrode are formed in the groove penetrating the second conductivity type base layer and reaching the depth of the middle of the first conductivity type semiconductor layer. Therefore, it is possible to realize a semiconductor device having a trench structure that achieves the action corresponding to claim 3.

Further, according to the invention of claim 5, in addition to the action corresponding to any one of claims 1 to 3,
Since the conductive type buried layer has a mesh shape, it is possible to easily increase the breakdown voltage as compared with the stripe shape.

Further, according to the invention of claim 6, since the second conductivity type buried layer has a stripe shape, the same operation as that of any one of claims 1 to 3 can be achieved. Further, according to the invention of claim 7, the second conductivity type
The embedding layer has a dot shape, whereby the embedding layer has a dot shape.
In addition to the same effect as that of any one of claims 3 to 3, the termination of the element
Part acts like a guard ring,
In the case of manufacturing, it is possible to form a high breakdown voltage semiconductor device.
It According to the invention of claim 8, the second conductivity type embedded
As a layer, each dot with a dot shape is half a line
Spacing, equidistant with dots in adjacent rows and columns
Since it is arranged, in addition to the action corresponding to claim 7, high density
It is possible to form a precise dot pattern, which is advantageous in terms of pressure resistance.
Become.

Further, according to the invention of claim 9 , in addition to the action corresponding to claim 3, it is possible to realize a semiconductor device such as a MOSFET capable of reducing the voltage drop in the ON state even with a high breakdown voltage. it can.

Further, according to the invention of claim 10 , in addition to the effect of claim 3, even a bipolar element having a second conductivity type drain layer on the drain electrode side has a high breakdown voltage as described above. Can reduce the voltage drop in the ON state
A semiconductor device such as a GBT can be provided.

Further, according to the invention of claim 11 , the second
Since the conductivity type buried layer has a potential different from that of the control electrode and is in a potential floating state, the same action as the action corresponding to claim 2 can be achieved.

According to the twelfth , seventeenth and eighteenth inventions, the breakdown voltage BV between the first main electrode and the second main electrode is high.
And the number M of the second conductivity type buried layers between the first main electrode and the second main electrode, and the first conductivity type semiconductor divided into (M + 1) layers by these second conductivity type buried layers. Among the layers, the voltage V 1 shared by the first conductivity type semiconductor layer closest to the first main electrode, the impurity concentration N 1 of the first conductivity type semiconductor layer closest to the first main electrode, and the first The thickness W 1 of the first-conductivity-type semiconductor layer closest to the main electrode and the first main-conductivity-type semiconductor layer divided into (M + 1) layers by the respective second-conductivity-type buried layers are the closest to the second main electrode. The voltage is divided into (M + 1) layers by the voltage V 2 shared by the nearby first conductivity type semiconductor layer, the impurity concentration N 2 of the first conductivity type semiconductor layer closest to the second main electrode, and each second conductivity type buried layer. Of the first conductive type semiconductor layer separated from the first main electrode and the second main electrode (M−
Voltage Vs shared by the first conductivity type semiconductor layer of layer 1),
Impurity concentration Ns of the first conductivity type semiconductor layer of the (M-1) layer
And the thickness Ws of the first conductivity type semiconductor layer of the (M-1) layer are clarified by predetermined formulas, so that in addition to the effect of claim 1 or claim 2, It is possible to form a device that operates in good condition with good reproducibility.

Further, according to the invention of claims 13 and 19 , the breakdown voltage BV between the source electrode and the drain electrode, the number M of the buried layers of the second conductivity type between the source electrode and the drain electrode, By these second conductive type buried layers (M
The second of the first conductivity type semiconductor layers divided into +1) layers
The voltage V 1 shared by the first conductive type semiconductor layer in contact with the conductive type base layer, the impurity concentration N 1 of the first conductive type semiconductor layer in contact with the second conductive type base layer, and the first conductive type semiconductor layer in contact with the second conductive type base layer. The thickness W 1 of the first conductivity type semiconductor layer and the first conductivity type semiconductor layer in contact with the drain layer among the first conductivity type semiconductor layers divided into (M + 1) layers by the respective second conductivity type buried layers are shared. Of the voltage V 2 , the impurity concentration N 2 of the first conductivity type semiconductor layer in contact with the drain layer, and the first conductivity type semiconductor layer divided into (M + 1) layers by each second conductivity type buried layer,
The voltage Vs shared by the first conductivity type semiconductor layer of the (M-1) layer that is not in contact with both the second conductivity type base layer and the drain layer.
And the impurity concentration N of the first conductivity type semiconductor layer of the (M-1) layer
Since the respective design conditions of s and the thickness Ws of the first conductivity type semiconductor layer of the (M-1) layer are clarified by predetermined formulas,
In addition to the effect of the third aspect, it is possible to form elements that operate reliably with good reproducibility.

Further, according to the invention of claim 14, buried formed Ryakukata shape so as to surround the second conductivity type buried layer
In addition to the effect of any one of claims 1 to 3, since the termination structure is provided with the embedded second conductivity type guard ring region,
By the buried second conductivity type guard ring region, it is possible to widen the interval between equipotential lines in the terminal portion of the semiconductor device to mitigate the electric field concentration and prevent the breakdown voltage of the terminal portion of the semiconductor device from deteriorating.

Further, according to the invention of claim 15, the second
Formed in a substantially rectangular shape so as to surround the conductive type buried layer,
Since the embedded second-conductivity-type RESURF region having a carrier density lower than that of the second-conductivity-type buried layer is provided, the same operation as that according to any one of claims 1 to 3 can be achieved. it can.

According to the sixteenth aspect of the invention, in addition to the action corresponding to any one of the first to third aspects, the first aspect
Since the terminal end portion of the conductive type semiconductor layer is formed in the bevel structure having an inclination, it is possible to exert the advantage of the bevel structure that relaxes the electric field strength at the pn junction terminal.

[0048]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. In the following embodiments, the first conductivity type is n-type and the second conductivity type is p-type.
Further, like reference numerals in the accompanying drawings indicate the same parts in many drawings.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
FIG. 3 is a schematic diagram showing the structure of the MOSFET according to the embodiment of FIG. This MOSFET has n as an n-type drain layer.
The drain electrode 12 is formed on the mold substrate 11. A lower n-type base layer 13 is formed by epitaxial growth on the surface of the n-type substrate 11 opposite to the drain electrode 12, and the lower n-type base layer 13 has a stripe-shaped lower surface ( A p-type buried layer 14 (as a floating mesh layer) is formed.

The second p-type buried layer 14 on the lower side has a second middle layer.
Is formed in the same manner as the n-type base layer 13, and an upper p-type buried layer 16 having a stripe shape is formed on the surface of the n-type base layer 15 in the middle stage. An upper n-type base layer 17 is formed on the mold burying layer 16. A plurality of p-type base layers 18 are selectively formed on the surface of the upper n-type base layer 17 by diffusion.
An n-type source layer 19 is selectively formed on the surface of the mold base layer 18.

A Si oxide film 20 is formed on the region from the p-type base layer 18 and the n-type source layer 19 to the other p-type base layer 18 and the n-type source layer 19 through the upper n-type base layer 17. A gate electrode 21 is provided through the gate electrode 21. Further, the source electrode 2 is provided on each of the p-type base layer 18 and the n-type source layer 19 and the other p-type base layer 18 and the n-type source layer 19 so as to sandwich the gate electrode 21.
2 is formed.

Here, this MOSFET has a withstand voltage BV of 6
It is 00V.

The lower, middle and upper n-type base layers 13,
Each of 15 and 17 has a withstand voltage BV = 600V and a voltage Vs =
Since the voltage is shared by 200 V, the impurity concentration Ns <1.89
7 × 10 18 × Vs −1.35 [cm −3 ], and here, the impurity concentration Ns = 1 × 10 15 [cm −3 ] with a 25% margin in the result of substituting Vs = 200 in the previous equation. It is formed so that. The impurity concentration Ns has a value about three times higher than the conventional one.

In addition, the middle and upper n-type base layers 15,
Each of 17 has a thickness Ws <1.1247 × 10 10 × Ns
-0.85 [cm], and Ns = 1 in this formula as well.
With a margin of 25% for the result of substituting × 10 15 , the thickness Ws
= 14 μm.

On the other hand, the lower and upper p-type buried layers 14,
As shown in FIG. 2, each of 16 is formed so that the relationship between its thickness t and the formation interval W satisfies 5t> W. The reason for this is that if the formation interval W is narrow, the current path becomes narrow and the on-resistance increases due to the JFET effect.
Is wide, the structure is equivalent to an element in which the p-type buried layers 14 and 16 are not provided.

The lower and upper p-type buried layers 14,
16 of the n-type base layers 13 and 1 in the lower to upper stages, respectively.
When the thickness of each of 5 and 17 is 1 bulk, 3 Ws> t
It is formed so as to satisfy the W / Ws relationship. These p-type buried layers 14 and 16 have a potential floating state, and are formed such that a plurality of stripe-shaped p-type regions are connected to each other at their terminal ends.

Next, the operation of such a MOSFET will be described.

When the applied voltage is 200 V or less, FIG.
As shown in (a), p
A depletion layer spreads in the upper n-type base layer 17 from the type base layer 18 toward the drain electrode 12 side.
The strongest point of the electric field occurs in the vicinity of the interface between 8 and the upper n-type base layer 17.

When the applied voltage reaches 200 V, as shown in FIG.
As shown in (b), the depletion layer is on the upper side of the p-type buried layer 16
When n reaches, the n-type base layer 17 is depleted and the p-type buried layer 16 is in a punch-through state and the potential is fixed. This suppresses an increase in the strongest point of the electric field on the p-type base layer 18 side. It is not necessary to punch through the entire region of the p-type burying layer 16, and it is sufficient to punch through only a part of the p-type burying layer 16.

When the applied voltage exceeds 200 V, FIG.
As shown in (c), a new depletion layer spreads from the p-type buried layer 16 toward the drain electrode 12 side in the middle n-type base layer 15, and in addition to the strongest point of the electric field described above, The strongest point occurs on the p-type buried layer 16 side.

When the applied voltage reaches 400 V, as shown in FIG.
As shown in (d), the p-type buried layer 14 with the depletion layer on the lower side is formed.
And the potential of the p-type buried layer 14 is fixed in the punch-through state.

Similarly, when the applied voltage exceeds 400 V, as shown in FIG. 3E, the n-type base layer 13 in the lower stage from the p-type buried layer 14 toward the drain electrode 12 side.
A depletion layer spreads inside.

When the applied voltage reaches 600 V, as shown in FIG.
As shown in (f), the depletion layer reaches the n-type substrate 11. The calculation result of such an electric field intensity distribution by two-dimensional numerical calculation is shown in FIG.

In this way, the two p-type buried layers 14 and 16 are provided so as to divide the n-type base layer into three parts, and each of these p-type buried layers 14 and 16 is formed.
The n-type base layers 13 and 1 are formed by the mold burying layers 14 and 16.
By fixing the maximum strength of the electric field at 5, 17, each of the n-type base layers 13, 15, 17 is allowed to share a voltage of 200 V, thereby achieving a breakdown voltage of 600 V.

Further, by designing the element to increase the impurity concentration of the n-type base layers 13, 15 and 17 and lower the on-resistance in a range having an electric field limit value exceeding the maximum electric field strength, Even with a withstand voltage, the voltage drop in the on state can be reduced.

More specifically, the MOSF according to this embodiment is
In ET, as shown in FIG. 5A, the impurity concentration of the n-type base layers 13, 15, 17 is 1 × 10 15 cm −3 . However, conventionally, with this impurity concentration, the withstand voltage is 2
Only 50 V can be realized, and as shown in FIG. 5B, in order to realize a withstand voltage of 600 V, an impurity concentration of about 3.3 is 3.3.
It was necessary to make it 10 14 cm -3 . In the MOSFET according to the present embodiment, the three n-type base layers divided by the p-type buried layers 14 and 16 share the voltage of 200 V each, so that the withstand voltage of 600 V is achieved even with a high impurity concentration of 1 × 10 15 cm −3. Can be realized. In addition, high breakdown voltage MOS
The on-resistance of the FET decreases in inverse proportion to the carrier density of the high resistance layer (n-type base layer). Therefore, conventional MOS
While low on-resistance cannot be realized by the FET, the MOSFET according to the present embodiment can greatly reduce the voltage drop in the on-state unlike the conventional case.

Next, a MOSFE having such an action
A method of designing T will be specifically described.

The lower, middle and upper n-type base layers 13,
Each of 15 and 17 has a withstand voltage BV = 600V and a voltage Vs =
Allocate 200V each. This voltage Vs = 200V
Is obtained by the following equation (1).

Vs = BV / (M + 1) (1) Here, M; the number of p-type buried layers 14 and 16 (= 2; in the case of the present embodiment). Further, the expression (1) is an expression when the voltages Vs or the impurity concentrations Ns shared by the n-type base layers 13, 15, and 17 are equal to each other.

Further, each n-type base layer 13, 15, 17
The impurity concentration Ns is determined by this voltage Vs based on FIG. 6 or the following equation (2).

Ns <1.897 × 10 18 × Vs −1.35 [cm −3 ] (2) Specifically, each of the n-type base layers 13, 15, 17 is
The impurity concentration Ns = 1 × 10 15 [cm −3 ] is formed based on the equation (3) in which the equation (2) has a margin of about 25%.

Ns to 0.75 × 1.897 × 10 18 × Vs −1.35 [cm −3 ] (3) Further, each of the n-type base layers 15 and 17 in the middle stage and the upper stage depends on the impurity concentration Ns. The thickness Ws is determined based on FIG. 7 or the following equation (4).

Ws <1.1247 × 10 10 × Ns −0.85 [cm] (4) However, the thickness Ws is the shortest distance between the p-type buried layers 14 and 16 in the middle n-type base layer 15. And the upper n
In the mold base layer 17, it means the shortest distance between the p-type base layer 18 and the upper p-type buried layer 16.

Specifically, each of the middle and upper n-type base layers 15 and 17 has a thickness Ws = 14 μm based on the equation (5) in which a margin of about 25% is added to the equation (4).
is formed to have m.

Ws to 0.75 × 1.1247 × 10 10 × Ns −0.85 [cm] (5) On the other hand, the thickness Ws of the lower n-type base layer 13 is expressed by the equations (4) and (5). A value exceeding the value of the expression (4) may be applied without applying. This is because the lower n-type base layer 13 is the n-type substrate 11.
This is because there is no need to punch through the depletion layer because it is a layer in contact with.

Next, a method of designing the p type buried layers 14 and 16 will be described.

The MOSFET according to this embodiment is shown in FIG.
As shown in, a MOSFET and two SITs (Static I
nduction Transistor) can be assumed to be connected in series, and the on-resistance is expressed by the following equation (6).

ON resistance = Rch + RJFET1 + Rbulk1 + RJFET2 + Rbulk2 + RJFET3 + Rbulk3 (6) To reduce the ON resistance, according to the formula (6), RJFET1
It is necessary to keep ~ 3 low.

By the way, the resistance of the n-type base layer 302 of the on-resistance of the conventional MOSFET is expressed by the following equation (7) using the parameters of the MOSFET of the present embodiment.

Resistance of conventional n-type base layer = (M + 1) × Ws / (qμ (Ns / (M + 1))) = (M + 1) 2 × Ws / (qμNs) (7) where q is elementary charge And μ is the mobility. The carrier density of the conventional MOSFET is 1 / (M + 1) times the carrier density Ns of the present embodiment.

On the other hand, the resistance of the n-type base layers 13, 15, and 17 of the on-resistance of the MOSFET of this embodiment is
It is expressed as the following equation (8).

Resistance of n-type base layer of the present embodiment = (M + 1) Ws / (qμNs) + M (tW / Ws) / (qμNs) (8) Therefore, the on-resistance of the present embodiment is conventional. MOSFE
The condition that is smaller than T is expressed by the following equation (9) based on the above equations (7) and (8).

(M + 1) Ws> tW / Ws (9) With such a design method, the MOS according to the present embodiment
The FET can be surely created.

FIG. 9 shows a MOSFET designed in this way.
6 is a diagram showing the relationship between on-resistance and breakdown voltage in FIG. As shown in the figure, when the breakdown voltage is 600 V, the on-resistance which is half the theoretical limit is realized. Further, it has been shown that when the withstand voltage is 1200 V, the on-resistance can be reduced to a fraction of the theoretical limit.

FIG. 10 is a diagram showing a theoretically possible relationship between on-resistance and breakdown voltage in the MOSFET according to the present invention. As shown, the on-resistance can be reduced in proportion to the number M of p-type buried layers. It should be noted that although there is a difference between FIGS. 9 and 10 as the number of layers M increases, this is because the relationship shown in FIG. This is because it was assumed.

As described above, according to the first embodiment, in the off state, the depletion layer spreads from the p-type base layer 18 to the drain electrode 12 side in proportion to the increase of the applied voltage.
When this depletion layer reaches the p-type buried layer 16, the punch-through phenomenon causes the p-type buried layer 16 to fix the electric field strength in the depletion layer and suppress its rise. By increasing the carrier density of the n-type base layer 17 and lowering the on-resistance within a range having an electric field strength limit value exceeding the value, the voltage drop in the on-state can be reduced even with a high breakdown voltage. .

Further, according to the present embodiment, the design conditions are clarified by the equations (1) to (2), the equation (4) and FIGS. It can be formed with good reproducibility.

(Second Embodiment) Next, the second embodiment of the present invention will be described.
The MOSFET according to the embodiment will be described.

FIG. 11 (a) is a schematic view showing the structure of the p-type buried layer of this MOSFET, and FIG. 11 (b) is shown in FIG.
2 is an enlarged view of the p-type buried layer shown in FIG. 2, and the same parts as those in FIG.

That is, this MOSFET is a modification of the first embodiment, and the resistance RJFET between the p-type portions inside the p-type buried layer 16 (or 14) as shown in FIG. 11B is reduced. In order to reduce the on-resistance, specifically, as shown in FIG. 11A, the n-type base layer 15 between the p-type portions inside the p-type buried layer 16 (or 14) is formed. The n + type layer 15a having a carrier density higher than the carrier density Ns of the n type base layer 15 is provided.

As a result, in addition to the effect of the first embodiment, the RJFET is reduced, so that the ON resistance can be further reduced.

(Third Embodiment) Next, the third embodiment of the present invention will be described.
The Schottky barrier diode according to the embodiment will be described.

FIG. 12 is a schematic diagram showing the structure of this Schottky barrier diode. This Schottky barrier diode has a structure in which a lower n-type base layer 3 is formed on an n-type substrate 31.
2 is diffused to form a stripe-shaped p-type buried layer 33 on the surface of the lower n-type base layer 32.

An upper n-type base layer 34 is formed on the p-type buried layer 33, and a Schottky electrode 35 is formed on the surface of the upper n-type base layer 34. The thickness of the upper n-type base layer 34 is designed so that the depletion layer at the Schottky interface reaches the p-type buried layer 33 at a low voltage with a small leak current from the Schottky junction. On the other hand, an ohmic electrode 36 is formed on the surface of the n-type substrate 31 opposite to the lower n-type base layer 32.

Next, the operation of this Schottky barrier diode will be described.

In this Schottky barrier diode, it is assumed that a reverse bias voltage (a negative voltage is applied to the Schottky electrode 35 and a positive voltage is applied to the ohmic electrode 36).

At this time, in the lower n-type base layer 34,
A depletion layer spreads from the interface with the Schottky electrode 35 toward the ohmic electrode 36 side.
The strongest point of the electric field occurs at the interface.

However, as the reverse bias voltage rises, the depletion layer reaches the p-type buried layer 33, the strongest point of the electric field at the Schottky interface is fixed and does not rise, and the depletion layer becomes the buried layer. It spreads more to the anode side (downward in the figure). Here, since the reverse bias voltage is designed to have a low value, the electric field at the Schottky interface is also fixed at a low value. Thereby, the leak current can be reduced.

According to this Schottky barrier diode, it is possible to reduce the leak current particularly during high temperature operation. Further, unlike the known technique, it is not necessary to form a guard ring with a p-type layer, and there is no problem that a bipolar operation occurs in the guard ring portion.

(Fourth Embodiment) Next, the fourth embodiment of the present invention will be described.
The Schottky barrier diode according to the embodiment will be described.

FIG. 13 is a schematic diagram showing the structure of this Schottky barrier diode. The same parts as those in FIG. 12 are designated by the same reference numerals, and detailed description thereof will be omitted. Only different parts will be described here.

That is, this Schottky barrier diode is a modified structure of the third embodiment and is intended to have a high breakdown voltage and a reduced voltage drop in the ON state.
Specifically, as shown in FIG. 13, a plurality of n-type base layers 32 1 to 32 3 and a plurality of p-type buried layers 3 are provided on an n-type substrate 31.
3 1 to 33 3 are formed by being individually laminated with each other.

As a result, in addition to the effects of the third embodiment, the breakdown voltage is shared by the n-type base layers 32 1 to 32 3 divided by the p-type buried layers 33 1 to 33 3 as described above. It is possible to realize a Schottky barrier diode having a high breakdown voltage and a low voltage drop in the ON state, which has been impossible to realize in the past.

(Fifth Embodiment) Next, the fifth embodiment of the present invention will be described.
The IGBT according to the embodiment will be described.

FIG. 14 is a schematic diagram showing the structure of this IGBT. In this IGBT, a drain electrode 42 is formed on a p-type substrate 41 as a p-type emitter layer. Further, an n-type buffer layer 43 and a lower n-type base layer 44 are formed on the surface of the p-type substrate 41 opposite to the drain electrode 42, and a stripe-shaped p-type p-layer is formed on the lower n-type base layer 44. The mold embedding layer 45 is formed.

An upper n-type base layer 46 is formed on the p-type buried layer 45, and the surface of the upper n-type base layer 46 has a carrier density higher than that of the n-type base layer 46. A + type layer 47 is formed. A plurality of p-type base layers 48 having a depth reaching the n-type base layer 46 are selectively formed in the n + -type layer 47 by diffusion.
An n-type source layer 49 is selectively formed on the surface of the mold base layer 48. The p-type buried layer 45 and the p-type base layer 48 are formed at positions close to each other so as to suppress the maximum strength of the electric field to a low value.

From the p-type base layer 48 and the n-type source layer 49 through the n + -type layer 47, the other p-type base layer 48 and n
A gate electrode 51 is provided on a region reaching the mold source layer 49 with a Si oxide film 50 interposed therebetween. A source electrode 52 is provided on each of the p-type base layer 48 and the n-type source layer 49 and the other p-type base layer 48 and the n-type source layer 49 so as to sandwich the gate electrode 51. Has been formed.

Even with such a structure, the n + -type layer 47 has an effect of reducing the voltage drop in the ON state in proportion to the height of the carrier density, and further, the voltage drop in the ON state is lowered. The p-type buried layer 45 prevents the breakdown voltage from being lowered due to the above. That is, since the p-type buried layer 45 is provided in the portion close to the p-type base layer 48, the rise of the strongest point of the electric field in the vicinity of the n + -type layer 47 is suppressed to a low level.
It is possible to simultaneously realize a reduction in voltage drop in the ON state and a high breakdown voltage.

(Sixth Embodiment) Next, the sixth embodiment of the present invention will be described.
The IGBT according to the embodiment will be described.

FIG. 15 is a schematic diagram showing the structure of the IBGT. The same parts as those in FIG. 14 are designated by the same reference numerals, and substantially the same parts are designated by a subscript a, and detailed description thereof will be omitted.
Here, only different parts will be described.

That is, this IGBT is a modified structure of the fifth embodiment and is intended to further reduce the voltage drop in the ON state. Specifically, as shown in FIG. 15, as shown in FIG. Instead of the layer 47 and the upper n-type base layer 46, an n + -type layer 47a having a region of the n + -type layer 47 and the upper n-type base layer 46 is formed on the p-type buried layer 45.

The n + type layer 47a has a carrier density higher than that of the n type base layer 44, as described above.

Thus, n + having a high carrier density
Since the mold layer 47a is formed over the entire p-type buried layer 45, the voltage drop in the ON state can be further reduced in addition to the effect of the fifth embodiment.

(Seventh Embodiment) Next, the seventh embodiment of the present invention will be described.
The IGBT according to the embodiment will be described.

FIG. 16 is a schematic diagram showing the structure of the IGBT. The same parts as those in FIG. 14 are designated by the same reference numerals and detailed description thereof will be omitted. Only different parts will be described here.

That is, this IGBT is a modified configuration of the fifth embodiment and is intended to further reduce the voltage drop in the ON state. Specifically, as shown in FIG. N type base layers 44 1 to 44 4 and 46 and a plurality of p type embedded layers 45 1 to 45 4 are individually and alternately laminated.

Even with such a structure, in addition to the effect of the fifth embodiment, the carrier density of the n-type base layers 44 1 to 44 4 and 46 is increased by the existence of the plurality of p-type buried layers 45 1 to 45 4. Since it can be increased, the voltage drop in the on-state can be further reduced.

Next, the MOSFET according to the above embodiment
Further, four specific methods (a) to (d) for forming the Schottky barrier diode will be described with reference to process sectional views shown in FIGS. The following description is also applicable to the method of forming an IGBT by using a p-type substrate (p-type emitter layer) having an n-type buffer layer on the top instead of the n-type substrate.

(Forming Method A) FIGS. 17 (a) to 17 (b)
As shown in, the first n-type base layer 62 is epitaxially grown on the n-type substrate 61 as the n-type drain layer.

Subsequently, as shown in FIG. 17C, a mask 63 is formed on the first n-type base layer 62, and thereafter,
Any ion such as indium, gallium, or boron 6
4 is ion-implanted. At this time, by accelerating the ions at a high voltage and implanting ions to a depth of about 0.2 μm to 3 μm from the surface, the diffusion of p during the subsequent epitaxial growth can be reduced and the mesh of the p-type buried layer can be formed finely. The ion-implanted layer 65 is the source of the p-type buried layer. After the ion implantation, the mask 63 is removed, and FIG.
As shown in (d), a second n-type base layer 66 is epitaxially grown on the surface of the ion-implanted first n-type base layer 62.

Similarly, by repeating the ion implantation and the epitaxial growth, MOSFET (or Schottky barrier diode, Schottky barrier diode,
IGBT, etc.) can be formed.

(Forming Method B) FIGS. 17 (a) -1 mentioned above.
An n-type substrate 61 having a first n-type base layer 62 on its upper portion is prepared in the same manner as in 7 (b).

On the other hand, as shown in FIG.
A mask 63 is formed on an n-type substrate 67 having a carrier density lower than that of the mold substrate 61, and then indium, gallium,
Any ion 64 such as boron is ion-implanted. After the ion implantation, the mask 63 is removed as shown in FIG.

Subsequently, as shown in FIG. 18C, this ion-implanted surface is bonded to the above-mentioned first n-type base layer 62.

Further, as shown in FIG. 18D, the reverse bonded n-type substrate 67 is polished to a predetermined thickness.

Similarly, by repeating selective ion implantation and wafer adhesion, a MOSFET (or Schottky barrier diode, IGBT, etc.) having an arbitrary number M of p-type buried layers can be formed. After the wafer is bonded, M is formed by ion implantation and epitaxial growth.
An OSFET may be formed.

(Forming Method C) As described above, FIG.
-19 (c), the first n
The mold base layer 62 is formed, and the ion implantation layer 65 is selectively formed on the surface of the first n-type base layer 62.

Thereafter, as shown in FIG. 19D, another n-type substrate 6 is formed on the surface of the first n-type base layer 62.
Adhere 8

As in the case of the forming method B, the MOSFET having a p-type buried layer having the number of layers M is also used as the forming method C.
Etc. can be formed.

In these forming methods (A) to (C), the p-type buried layer may be sequentially diffused. However, it is preferable to diffuse the p-type base layer at the same time when forming the p-type base layer after forming all the p-type buried layers, from the viewpoint of making the size, thickness and interval of the p-type buried layer uniform.

Further, when forming the p-type buried layer having the number M of layers, the lower p-type buried layer 14 is formed larger than the upper p-type buried layer 16 due to the influence of the temperature during the formation. Therefore, as shown in FIG. 21, it is desirable to increase the distance between the p-type portions in the p-type buried layers 14 and 16 as much as the lower p-type buried layer 14.

The p-type buried layer may be formed by burying polysilicon without being formed by diffusion.

(Forming method d) FIGS. 20 (a) to 20 (c)
As shown in, the n-type base layer 62 is epitaxially grown on the n-type substrate 61 as the n-type drain layer.
Subsequently, the mask 6 patterned into a predetermined pattern
3 is formed on the n-type base layer 62. Next, ions 64 forming a p-type impurity layer such as BF 2 are implanted into the n-type base layer 62 by a high energy accelerator. By changing the acceleration energy during ion implantation,
The ion implantation layer 65 can be formed at a predetermined depth. Next, after removing the mask 63, the n-type substrate 61 and the n-type base layer 62 are heat-treated at a high temperature to diffuse and activate the ions in the ion implantation layer 65.
It becomes the mold embedding layer. By this heat treatment, at the time of ion implantation, a region 65 surrounded by a dotted line in FIG.
The defects generated in a are eliminated, and the crystallinity of the n-type base layer 62 is restored.

By implanting impurity ions into the n-type base layer 62 several times by using different acceleration energies, it is possible to form several p-type potential fixed layers having different depths.

Next, the mask pattern used in such a forming method will be described.

22 to 29 are plan views of mask patterns for forming a p-type buried layer, respectively. 22 is a plan view showing a mask pattern for forming the stripe-shaped p-type buried layers 14, .... This mask pattern is composed of a substantially square frame portion 71, a stripe portion 72 formed inside the frame portion 71, and a substantially square central portion 73 arranged substantially in the center of the frame portion 71. The frame portion 71, the stripe portion 72, and the central portion 73 are connected to each other.

Here, the central portion 73 is for determining the potential of the p-type buried layers 14, ... By punch-through, and as shown in FIG. 30, which is a sectional view taken along the line XXXV-XXXV in FIG. In addition, the gate electrode pad 74 is positioned below the gate electrode pad 74 in a region 75 where the depletion layer extends (indicated by a broken line in the drawing). Further, since the central portion 73 determines the potential by using the region 75 having a large area indicated by the broken line below the gate electrode pad 74 by the alignment, even if the alignment is misaligned due to variations in the forming process, the overlapping portion is Since it is sufficient, it is possible to expect a yield improvement by eliminating a change in breakdown voltage, and it is possible to avoid reduction of the effective area of the semiconductor device. However, if only the effect of improving the breakdown voltage is provided, the alignment may not be performed.

FIG. 23 is a plan view showing the modified pattern of FIG. 22 and has a linear connecting portion 76 between the central portion 73 and the frame portion 71 so as to be orthogonal to the stripe portion 72. The connecting portion 76 is for reliably electrically connecting the central portion 73 and the frame portion 71, and the stripe portion 7
It has a width greater than the width of the two individual parallel straight lines.

24 and 25 are plan views showing mask patterns for forming a mesh-shaped p-type buried layer. Instead of the stripe portion 72 shown in FIG. 22 or 23, a grid-like mesh portion 77 is shown. have. With these mesh-shaped mask patterns, it is possible to form a semiconductor device having a higher breakdown voltage than when a stripe-shaped mask pattern is used.

FIG. 26 is a plan view showing a dot-shaped mask pattern. This mask pattern consists of multiple dots 7
8 are arranged at equal intervals in the row direction and the column direction. Since the p-type buried layers formed in the dot shape are not electrically connected to each other, they act similarly to the guard ring at the terminal end of the element. Therefore, in the case of the planar structure, a high breakdown voltage semiconductor device is formed. be able to.

FIG. 27 is a plan view showing the modified pattern of FIG. 26. Compared with FIG. 26, the dots 78 are displaced by half a space for each row, and are arranged at equal intervals with the dots 78 in the adjacent rows and columns. Since a high-density dot pattern is formed, it is advantageous in terms of pressure resistance.

FIG. 28 is a plan view showing a mask pattern which is stripe-shaped and does not require alignment. A stripe portion 81 composed of a plurality of parallel straight lines and a plurality of stripe portions 81 arranged in parallel to each other so as to be orthogonal to the stripe portion 81. Connection part 8
Have two. The connecting portion 82 is the stripe portion 81.
Has a width wider than the width of each parallel straight line, and has a function of reliably electrically connecting the parallel straight lines of the stripe portion 81 with each other, and a function of determining the potentials of the p-type buried layers 14, ... By punch-through. Has.

Here, the interval between the connecting portions 82 is set based on the chip size so that at least one connecting portion 82 is located at the element portion of each chip. In addition,
The connection portions 82 and the stripe portions 81 may be in a relationship of obliquely crossing each other.

FIG. 29 is a plan view showing the modified pattern of FIG. 28, in which a rectangular portion 83 having a width wider than that of the connecting portion 82 is provided. This square portion 83 is p
It widens the region where the potential of the buried layer is determined, and prevents fluctuations in the potential of the p buried layer. Also,
The square portions are sized and spaced so that at least one is included in the element portion of each chip without alignment.

22 to 29, the frame portion 71, the central portion 73, the connecting portion 76, the connecting portion 82, and the rectangular portion 83 are shown as white portions, but white portions other than solid lines are shown. Also is an exposed portion in the mask pattern, and the other portion is a light shielding portion.

(Eighth Embodiment) Next, the eighth embodiment of the present invention
The MOSFET according to the embodiment will be described.

FIG. 31 is a schematic diagram showing the termination structure of this MOSFET. The same parts as those in FIG. 1 are designated by the same reference numerals and detailed description thereof will be omitted. Only different parts will be described here.

That is, this MOSFET is a modification of each of the embodiments and is intended to prevent breakdown of breakdown voltage at the element termination portion of the planar structure. Specifically, FIG.
As shown in, on the outer peripheral side of each p-type buried layer 14, 16,
A plurality of embedded guard rings 9 formed in a substantially rectangular shape so as to surround the p-type embedded layers 14 and 16 when viewed from above the element.
1 is provided.

Therefore, according to such a termination structure, each embedded guard ring 91 widens the interval between the equipotential lines 92 at the element termination portion to relax the electric field strength, and
It is possible to prevent the breakdown voltage of the element end portion from deteriorating.

(Ninth Embodiment) Next, the ninth embodiment of the present invention will be described.
The MOSFET according to the embodiment will be described.

FIG. 32 is a schematic diagram showing the termination structure of this MOSFET. The same parts as those in FIG. 31 are designated by the same reference numerals and detailed description thereof will be omitted. Only different parts will be described here.

That is, this MOSFET is a modified structure of the above-mentioned embodiment, and is intended to prevent breakdown voltage deterioration at the element termination portion of the planar structure. Specifically, FIG.
As shown in FIG. 2, the p-type buried layers 14 and 16 are formed in a substantially rectangular shape on the outer peripheral portions of the p-type buried layers 14 and 16 so as to surround the p-type buried layers 14 and 16 when viewed from above the element.
Embedded RESURF (RESU with lower carrier density than
RF) 93.

Even with such a structure, the same effect as that of the eighth embodiment can be obtained.

(Tenth Embodiment) Next, a MOSFET according to a tenth embodiment of the present invention will be described.

FIG. 33 is a schematic diagram showing the termination structure of this MOSFET. The same parts as those in FIG.
Substantially the same parts are denoted by a subscript a and detailed description thereof is omitted, and only different parts will be described here.

That is, this MOSFET is a modification of the first embodiment and has a bevel structure or a termination structure by mesa etching. Specifically, FIG.
As shown in FIG. 3, a bevel structure having an inclination is formed at the device end portion, and the p-type buried layers 14a, 1 at the device end portion are formed.
6a is formed in a substantially rectangular frame shape so as to surround the stripe portion or the mesh portion.

Therefore, according to such a termination structure, p
In addition to the advantage of the bevel structure that relaxes the electric field at the n-junction termination,
Since the p-type buried layers 14a and 16a at the terminal end have a frame shape, the potential at the terminal end can be determined, and thus the reliability of the operation can be improved.

(Eleventh Embodiment) Next, a MOSFET according to an eleventh embodiment of the present invention will be described.

FIG. 34 is a schematic diagram showing the termination structure of this MOSFET. The same parts as those in FIG. 33 are designated by the same reference numerals and detailed description thereof will be omitted. Only different parts will be described here.

That is, this MOSFET is a modified structure of the tenth embodiment, and the p-type buried layers 14a and 16b have a bevel structure or a termination structure by mesa etching.
34. Specifically, as shown in FIG. 34, instead of the frame shape of the p-type buried layers 14a and 16a, a stripe portion or a mesh portion is formed to extend to the element end portion. Has been done.

Therefore, according to such a termination structure, p
In addition to the advantage of the bevel structure that alleviates the electric field concentration on the n-junction end face, the p-type buried layers 14 and 16 do not have a frame shape
The alignment of the mask patterns of the p-type buried layers 14 and 16 can be omitted.

Next explained is a MOSFET according to the twelfth embodiment of the invention.

FIG. 35 is a sectional view schematically showing the structure of this MOSFET, and FIG. 36 is a plan view of this MOSFET. In this MOSFET, an n-type layer (or p-type layer) 102 is formed on a substrate 101, and an n-type layer 102 is formed.
An n-type offset layer 103 having a total impurity amount (dose amount) of 1 × 10 12 cm −2 or more is selectively formed thereon. An n-type drain layer 105 is formed on the surface of the n-type offset layer 103.
-While selectively formed to a depth reaching the mold layer 102,
The p-type buried layer 104 is selectively formed in a dot shape. The p-type buried layer 104 may have a stripe shape as shown in FIG. In addition, the p-type buried layer 1
The dot-shaped (or stripe-shaped) pattern in 04 may be irregular, unlike FIG. 37 (or FIG. 36).

A p-type base layer 106 is selectively formed on the surface of the n − -type layer 102 so as to be in contact with the n-type offset layer 103, and an n-type source layer 107 is selectively formed on the surface of the p-type base layer 106. Is formed in.

On the p-type base layer 106 and the n-type source layer 1
A source electrode 108 is selectively formed on 07. A gate electrode 110 is selectively formed on the n-type source layer 107, the p-type base layer 106, and the n-type offset layer 103 via an oxide film 109.

A drain electrode 111 is selectively formed on the n-type drain layer 105.

Here, by forming the p-type buried layer 104 on the surface of the n-type offset layer 103, it is possible to increase the amount of impurities in the n-type offset layer 103 as described above, so that the on-resistance can be reduced. it can.

(Thirteenth Embodiment) Next, a MOSFET according to the thirteenth embodiment of the present invention will be described.

FIG. 38 is a schematic diagram showing the structure of this MOSFET. The same parts as those in FIG. 35 are designated by the same reference numerals and detailed description thereof will be omitted. Only different parts will be described here.

That is, this MOSFET has a modified structure of the twelfth embodiment. Specifically, as shown in FIG. 38, instead of the p-type buried layer 104, the p-type on the surface of the n-type offset layer 103. The p-type buried layer 112 is selectively formed to a depth similar to the depth of the mold source layer 106.

Here, the p-type buried layer 112 has a trench (for example, a round hole) formed in the mask formed on the n-type offset layer 103 by RIE or the like, and a p-type dopant is formed through the trench by ion implantation or the like. Can be formed by doping the n-type offset layer 103 and the n-type layer 102 with and removing the mask. A trench having a depth reaching the n-type layer 102 may be formed on the surface of the n-type offset layer 103, and the p-type polycrystal may be embedded in the trench.

With such a structure, the same effect as that of the twelfth embodiment can be obtained.

(Fourteenth Embodiment) Next, a MOSFET according to a fourteenth embodiment of the present invention will be described.

FIG. 39 is a schematic diagram showing the structure of this MOSFET. This MOSFET is SOI (Silicon-On
-Insulator) substrate, a buried oxide film 122 and an n-type offset layer 123 of Si are formed on the substrate 121.
Are sequentially formed.

The dose of the n-type offset layer 123 is 1 ×
10 12 cm −2 or more, the p-type base layer 124 and the n-type drain layer 125 are selectively formed on the surface, and the n-type source layer 126 is selectively formed on the surface of the p-type base layer 124. . In the n-type offset layer 123, the p-type buried layer 127 reaching the buried oxide film 122 from the surface between the p-type base layer 124 and the n-type drain layer 125 is selectively formed in a round hole shape by RIE, for example. ing.

On p-type base layer 124 and n-type source layer 1
A source electrode 128 is selectively formed on 26. A gate electrode 130 is selectively embedded and formed on the n-type source layer 126, the p-type base layer 124, and the n-type offset layer 123 via an oxide film 129.

A drain electrode 131 is selectively formed on the n-type drain layer 125.

Even with such a configuration, the twelfth and first
The same effect as that of the third embodiment can be obtained.

(Fifteenth Embodiment) Next, a MOSFET according to the fifteenth embodiment of the present invention will be described.

FIG. 40 is a schematic diagram showing the structure of this MOSFET, and FIG. 41 is a sectional view taken along the line XLVI-XLVI of FIG. 40, in which the same parts as in FIG. Description is omitted, and only different parts will be described here.

That is, this MOSFET has a modified structure of the twelfth embodiment and prevents deterioration of breakdown voltage due to variations in the forming process. Specifically, FIG.
0 and FIG. 41, the n-type offset layer 103
An insulating film 141 is formed on the p-type buried layer 104 and the n-type drain layer 105, and contact holes 1 are formed on the surface of the insulating film 141 so as to reach the p-type buried layers 104.
42 are formed, and four equipotential electrodes 143 are formed so as to connect each p-type buried layer 104 equidistant from the gate electrode.
Are formed.

Here, each of the four equipotential electrodes 143 has a width longer than the diameter of the contact hole 142, and a portion protruding from this diameter projects toward the drain electrode 111 to form a so-called field plate structure. Has been formed.

Therefore, the equipotential electrodes 143 connect the p-type buried layers 104 equidistant from the gate electrode 110 to the equipotential, and prevent the breakdown voltage from deteriorating due to variations in the formation process, and the equipotential electrodes 143. By adopting the field plate structure, it is possible to prevent electric field concentration in the p-type buried layer 104 and improve the breakdown voltage.

(Sixteenth Embodiment) Next, a MOSFET according to the sixteenth embodiment of the present invention will be described.

FIG. 42 is a schematic diagram showing the structure of this MOSFET. The same parts as those in FIG. 40 are designated by the same reference numerals and detailed description thereof will be omitted. Only different parts will be described here.

That is, this MOSFET has a modified structure of the fifteenth embodiment and is intended to reduce the resistance RJFET by the p-type buried layer. Specifically, as shown in FIG. The p-type buried layer 104 in the offset layer 103 is omitted, an insulating film 141 is formed on the n-type offset layer 103 and the n-type drain layer 105, and a plurality of insulating films 141 are formed on the surface of the insulating film so as to reach the n-type offset layer. The contact hole 142 is formed in a dot shape (or a stripe shape similar to FIG. 37), and the p-type buried layer 144 is formed by the p-type polycrystal embedded in the contact hole 142. Four p-type connecting layers 145 are formed so as to connect the p-type buried layers 144 that are equidistant from each other.

Here, the four p-type connection layers 145 are formed so as to have a field plate structure as described above.

Therefore, in addition to the effects of the fifteenth embodiment, since the p-type buried layer 144 is formed on the n-type offset layer 103, the resistance R due to the p-type buried layer 144 is increased.
The JFET can be lowered.

(Seventeenth Embodiment) Next, a MOSFET according to a seventeenth embodiment of the present invention will be described.

FIG. 43 is a schematic diagram showing the structure of this MOSFET. The same parts as those in FIG. 40 are designated by the same reference numerals and detailed description thereof will be omitted. Only different parts will be described here.

That is, this MOSFET has a modified structure of the twelfth embodiment, and has a SIPOS (Semi-Insul) structure.
The potential of each p-type buried layer 104 is fixed by using a resistance film such as ating POlycrystalline silicon).

The MOSFET according to this embodiment is SIP
It relates to a state of being connected to an electrode through a high resistance film such as OS.

Specifically, in this MOSFET, as shown in FIG. 43, an insulating film 141 is formed on the n-type offset layer 103, the p-type buried layer 104 and the n-type drain layer 105, and the insulating film 141 is formed. Each p-type buried layer 10 on the surface
The contact hole 142 is formed to reach 4
The SIPOS portion 146 is formed on the insulating film 141 so as to connect the p-type buried layers 104 to each other and the electrodes 110 and 111 from the gate electrode 110 to the drain electrode 111.
Are formed.

Therefore, due to the electric resistance of the SIPOS portion 146, the voltage between the gate electrode 110 and the drain electrode 111 is shared by each p-type buried layer 104, and the potential of each p-type buried layer 104 is fixed. High breakdown voltage can be expected.

(Eighteenth Embodiment) Next, a MOSFET according to an eighteenth embodiment of the present invention will be described.

FIG. 44 is a schematic diagram showing the structure of this MOSFET. The same parts as those in FIG. 40 are designated by the same reference numerals and detailed description thereof will be omitted. Only different parts will be described here.

That is, this MOSFET has a modified structure of the twelfth or seventeenth embodiment, in which the potential of each p-type buried layer is fixed by using a resistance film such as SIPOS. As shown in FIG. 44, an insulating film 141 is formed on the n-type offset layer 103, the p-type buried layer 104, and the n-type drain layer 105.
A contact hole 142 is formed on one surface so as to reach each p-type buried layer 104, and each p-type buried layer 104 and both electrodes 108, 111 are formed on the insulating film 141 from the source electrode 108 toward the drain electrode 111. The SIPOS unit 147 is formed so as to connect to each other.

Therefore, due to the electric resistance of the SIPOS portion 147, the voltage between the source electrode 108 and the drain electrode 111 is shared by each p-type buried layer 104, and the potential of each p-type buried layer 104 is fixed. High breakdown voltage can be expected.

(Nineteenth Embodiment) Next, a MOSFET according to a nineteenth embodiment of the present invention will be described.

FIG. 45 is a sectional view schematically showing the structure of this MOSFET. In this MOSFET, an n-type base layer 202 is formed on an n-type substrate 201 as an n-type drain layer, and stripe-shaped p layers are formed in the n-type base layer 202.
A mold embedding layer 210 is formed. A p-type base layer 203 is formed on the surface of the n-type base layer 202. In the p-type base layer 203 and the n-type base layer 202, the p-type base layer 203 is penetrated and
A plurality of trenches 204 having a depth reaching the middle depth are formed. A gate insulating film 205 is formed in the trench 204.
A gate electrode 206 is embedded and formed via the.

An n-type source layer 207 is formed in the surface of the p-type base layer 203 in contact with the upper portion of the trench 204. A source electrode 208 is provided so as to contact both the p-type base layer 203 and the n-type source layer 207. In addition, the n-type base layer 2 is formed on the n-type substrate 201.
A drain electrode 209 is formed on the surface opposite to 02.

Here, the p-type buried layer 210 is formed by connecting a plurality of stripe-shaped p-type regions to each other at the terminal end, as described above.

Next, the operation of such a MOSFET will be described.

First, the on-state of this MOSFET will be described.

Now, it is assumed that the gate electrode 206 is positively biased in the state where a voltage which is positive with respect to the source electrode 208 is applied to the drain electrode 209. By the positive bias of the gate electrode 206, an n-type inversion layer is formed in the portion of the p-type base layer 203 in contact with the trench 204.
Therefore, electrons pass through the inversion layer and the n-type source layer 207.
To the n-type base layer 202, the MOSFET becomes conductive.

Next, the off state of this MOSFET will be described.

It is now assumed that a positive voltage with respect to the source electrode 208 is applied to the drain electrode 209 while the gate electrode 206 is biased to 0 or negative.

At this time, in the n-type base layer 202, a depletion layer spreads from the p-type base layer 203 toward the drain electrode 209, and the n-type base layer 2 sandwiched between the trenches 204 is formed.
In 02, the strongest point of the electric field occurs.

Further, when the source-drain voltage rises, the depletion layer reaches the p-type buried layer 210, and the p-type buried layer 210 becomes a punch-through state and the potential is fixed. Furthermore, when the source-drain voltage rises, the depletion layer changes from the p-type buried layer 210 to the drain electrode 20.
Spread on the 9 side. Therefore, the electric field at the strongest electric field in the n-type base layer 202 is fixed and prevented from rising.

Here, the p-type buried layer 210 and the trench 2 are formed.
04 and the impurity concentration of the n-type base layer 202 are designed so that the electric field at the strongest electric field does not exceed the limit value of the electric field strength of the n-type base layer 202. The breakdown voltage and the resistance can be reduced.

Further, by stacking a plurality of p-type buried layers 210 in the n-type base layer 202, higher breakdown voltage and lower resistance can be achieved.

(Twentieth Embodiment) FIG. 46 is a sectional view schematically showing the structure of a semiconductor device according to a twentieth embodiment of the present invention. In this semiconductor device, an n-type base layer 212 is formed on an n-type substrate 211 as an n-type drain layer, and a stripe-shaped p-type buried layer 220 is formed in the n-type base layer 212. In addition, the n-type base layer 2
An n-type source layer 213 is formed on the surface of 12.
A p-type base layer 214 is embedded in the n-type base layer 212. Each p-type base layer 214 is electrically connected, and a base electrode 215 is provided in contact with the p-type base layer 214. A source electrode 216 is provided on the surface of the n-type source layer 213.
Further, on the n-type substrate 211, a drain electrode 217 is formed on the surface opposite to the n-type base layer 212.

Next, the operation of this semiconductor device will be described.

It is now assumed that a positive voltage with respect to the source electrode 216 is applied to the drain electrode 217 while the base electrode 215 is biased to 0. Semiconductor device
Electrons flow from the n-type source layer 213 between the p-type base layers 214 to the n-type drain layer 211, and become conductive.

Here, when the base electrode 215 is placed in a positive bias state, holes are injected from the p-type base layer 214 into the n-type base layer 212, and conduction modulation occurs near the p-type base layer 214, so that the semiconductor The resistance of the device is reduced.

On the other hand, it is assumed that a positive voltage with respect to the source electrode 216 is applied to the drain electrode 217 while the semiconductor device is in the off state, that is, the base electrode 215 is negatively biased. When the base electrode 215 is negatively biased, a depletion layer spreads from each p-type base layer 214 into the n-type base layer, these depletion layers contact each other, and the current path is cut off. Further, the depletion layer spreads toward the drain electrode 217, and the strongest point of the electric field occurs just below the p-type base layer 214.

Further, when the source-drain voltage rises, the depletion layer reaches the p-type buried layer 220, and at this time, the p-type buried layer 220 is in a punch-through state and the potential is fixed. Furthermore, when the source-drain voltage rises, the depletion layer spreads from the buried layer 220 to the drain electrode side. Therefore, the electric field at the strongest electric field in the n-type base layer 2 is fixed and prevented from rising.

P-type buried layer 220 and p-type base layer 214
And the impurity concentration of the n-type base layer 212 are designed such that the electric field at the strongest electric field does not exceed the limit value of the electric field strength of the n-type base layer 212. The breakdown voltage and the resistance can be reduced.

Further, by stacking a plurality of p-type buried layers 220 in the n-type base layer 212, higher breakdown voltage and lower resistance can be achieved.

(Twenty-first Embodiment) FIG. 47 is a sectional view schematically showing the structure of a semiconductor device according to a twenty-first embodiment of the present invention. The same parts as those in FIG. The detailed description is omitted, and only different parts will be described here.

That is, this semiconductor device is a modified structure of the semiconductor device of the twentieth embodiment and has improved reliability of turn-off. Specifically, a trench 218 that reaches a depth in the middle of the n-type base layer 212 is formed, and a p-type base layer 214 is formed on the entire sidewall and bottom surface thereof.

As a result, when the base electrode 215 is in a negatively biased off state, as shown by a broken line, each p
Since the portion in contact with the depletion layer extending from the mold base layer 214 is planar, the current path can be reliably cut off.

(Twenty-second Embodiment) FIG. 48 is a sectional perspective view schematically showing the structure of a semiconductor device according to a twenty-second embodiment of the present invention. In this semiconductor device, an n-type base layer 222 is formed on an n-type substrate 221 as an n-type drain layer, and stripe-shaped p layers are formed in the n-type base layer 222.
A mold embedding layer 230 is formed. Further, in the n-type base layer 222, a plurality of trenches 224 having a depth reaching a depth in the middle of the n-type base layer 222 are formed in a stripe shape. A p-type polysilicon electrode 226 is embedded in the trench 224 with an insulating film 225 interposed therebetween. In addition, an n-type source layer 227 is selectively formed in the surface of the n-type base layer 222 so as to contact the upper portion of the trench 224. p-type polysilicon electrode 226
And the source electrode 2 in contact with the n-type source layer 227.
28 is formed.

Further, on the surface of the n-type base layer 222, a p-type base layer 223 is diffused and formed deeper than the trench 224 near the end of the trench 224. p-type base layer 2
A base electrode 229 is formed on the surface of 23. A drain electrode 231 is formed on the surface of the n-type substrate 221 opposite to the n-type base layer 222.

Next, the operation of this semiconductor device will be described.

When the base electrode 229 is positively biased with a positive voltage applied to the drain electrode 231 with respect to the source electrode 227 of this element, holes are transferred from the p-type base layer 223 to the n-type base layer 222. While flowing into the n-type source layer 227 along the insulating film 225. On the other hand, electrons are injected from the n-type source layer 227 into the n-type base layer 222 according to the amount of holes that flow,
Due to the voltage applied between the source and drain, the current flows toward the drain electrode 231. Therefore, the semiconductor device becomes conductive. At this time, since holes are injected from the p-type base layer 223, conduction modulation occurs in the n-type base layer 22, further reducing the resistance.

It is assumed that a positive voltage with respect to the source electrode 228 is applied to the drain electrode 231 in the off state of the semiconductor device, that is, with the base electrode 229 biased to 0 or negative.

At this time, due to the difference in diffusion potential between the n-type base layer 222 and the p-type polysilicon electrode 226, the trench 22 is formed.
The depletion layer spreads from 4, and the depletion layers contact each other. Also,
Since the depletion layer also spreads from the p-type base layer 223 at the same time,
The current path is cut off. Furthermore, the depletion layer expands toward the drain electrode 231 side, and the strongest point of the electric field occurs just below the p-type base electrode 232.

Further, the depletion layer reaches the p-type buried layer 230 in proportion to the increase in the source-drain voltage, and at this time, the p-type buried layer 230 is in a punch-through state and the potential is fixed. Further, when the source-drain voltage rises, the depletion layer spreads from the p-type buried layer 230 to the drain electrode 231 side. Therefore, the electric field at the strongest point of the electric field is fixed and prevented from rising.

P-type buried layer 230 and p-type base layer 223
And the impurity concentration of the n-type base layer 222 are designed so that the electric field at the strongest electric field does not exceed the limit value of the electric field strength of the n-type base layer 222. Can be realized. Further, by stacking a plurality of p-type buried layers 230 in the n-type base layer 222, higher breakdown voltage and lower resistance can be achieved.

In the twentieth to twenty-second embodiments, of the n-type base layers 212 (, 222) divided by the p-type buried layers 220 (, 230), the p-type base layers 213 (, 223) are included. ) Adjacent to the n-type base layer 21
2 (, 222) is a lighter concentration and the other n-type base layer 2
By making the thickness thicker than 12 (, 222) and increasing the shared voltage, it is possible to further reduce the resistance and the breakdown voltage. The reason is that the p-type base layer 213 (, 223)
Since the high-injection state is present in the vicinity of, the resistance in the on-state is suppressed to be low even in the high-resistance n-type base layer 212 (, 222).
This is because the resistance of the entire element is lowered by lowering the voltage shared by the mold base layers 212 (, 222) to lower the resistance.

Next, a specific design method of the p-type buried layer at this time will be described with reference to FIG.

Depending on the product specifications, for example, the breakdown voltage BV between the source electrode 22 and the drain electrode 12 and the source electrode 22
P-type buried layer 14 between the drain electrode 12 and the drain electrode 12,
It is assumed that the number of layers M of 16 is determined.

Subsequently, the n-type base layers 13, 15, 1 divided into (M + 1) layers by the p-type buried layers 14, 16 respectively.
Among them, the voltage V 1 shared by the n-type base layer 17 in contact with the p-type base layer 18 on the source electrode 22 side is determined.

More specifically, the sharing voltage Vs is temporarily calculated by the above-mentioned equation (1), and the sharing voltage V 1 is determined to be a value equal to or higher than the provisional sharing voltage Vs according to the following equation (10). To be done.

V 1 ≧ Vs (10) Similarly, the shared voltage V 2 is obtained by the following equation (10a).

V 2 ≧ Vs (10a) However, V 2 is (M +) due to the p-type buried layers 14 and 16.
The voltage is shared by the n-type base layer 13 in contact with the n-type drain layer 11 among the n-type base layers 13, 15, and 17 divided into 1) layers.

Further, the shared voltage Vs of other portions is obtained by the following equation (11) based on the above determination contents. Note that the Vs determined here is also the above equation (10), (10a)
It goes without saying that the formula is satisfied.

Vs = (BV−V 1 −V 2 ) / (M−1) [V] (11) However, Vs is (M +) due to the p-type buried layers 14 and 16.
1) Of the n-type base layers 13, 15, 17 divided into layers, an (M-1) -layer n-type base that is not in contact with both the p-type base layer 18 and the n-type (or p-type) drain layer 11 Layer 15
Is the voltage shared by

V 2 is an n-type base layer 13, 15, 1 divided into (M + 1) layers by the p-type buried layers 14, 16.
N-type base layer 1 in contact with n-type drain layer 11
It is a voltage shared by three.

Thereafter, similarly to the above, the impurity concentration N 1 and the thickness W 1 in the n-type base layer 17 having the shared voltage V 1 are obtained as shown in the following equations (12) and (13).

N 1 <1.897 × 10 18 × V 1 -1.35 [cm −3 ] (12) W 1 <1.1247 × 10 10 × N 1 -0.85 [cm] (13) Similarly, , The impurity concentration N 2 and the thickness W 2 in the n-type base layer 13 having the sharing voltage V 2 are expressed by the following equation (14) and (1)
It is obtained as shown in the equation (5).

N 2 <1.897 × 10 18 × V 2 −1.35 [cm −3 ] (14) W 2 <1.1247 × 10 10 × N 2 −0.85 [cm] (15) where (15) is an example, and the thickness W 2 can be set arbitrarily and is not limited to the expression (15).

Similarly, the impurity concentration Ns and the thickness Ws in the n-type base layer 15 having the shared voltage Vs are as follows (1)
It is obtained as shown in the equations (6) and (17).

Ns <1.897 × 10 18 × Vs −1.35 [cm −3 ] (16) Ws <1.1247 × 10 10 × Ns −0.85 [cm] (17) As described above, each n-type Different voltages may be shared by the base layers 13, 15, and 17. Also, equation (10)
Since the design conditions are clarified as shown in the equation (17), it is possible to form the element that operates reliably with good reproducibility. Furthermore, the design conditions shown in these equations (10) to (17) are as follows:
The invention can be applied to each of the above-described embodiments regardless of a lateral type or the like.

Besides, the present invention can be variously modified and implemented without departing from the gist thereof.

[0247]

As described above, according to the first aspect of the invention, in the off state, the depletion layer is proportional to the increase of the applied voltage in the first conductivity type semiconductor layer in the second main electrode side. When the depletion layer reaches the second conductivity type buried layer, the second conductivity type buried layer fixes the electric field strength in the depletion layer and raises it. Therefore, by increasing the impurity concentration of the first conductivity type semiconductor layer and reducing the on-resistance in a range having a limit value of the electric field strength exceeding the maximum value of the electric field strength at this time,
Vertical that can reduce the voltage drop in the ON state even with high withstand voltage
Type semiconductor device can be provided.

According to the invention of claim 2, claim 1
In addition to the effect similar to the above, it is possible to provide a vertical semiconductor device capable of controlling the current flowing from the first main electrode to the second main electrode by the current control structure.

Further, according to the invention of claim 3, in the off state, the depletion layer spreads from the second conductivity type base layer to the drain electrode side in proportion to the increase of the applied voltage, and the depletion layer becomes the second depletion layer. When reaching the conductivity type buried layer, the second conductivity type buried layer fixes the electric field strength in the depletion layer and suppresses its rise due to the punch-through phenomenon. First in the range with a limit value of strength
By increasing the impurity concentration of the conductive type semiconductor layer to reduce the on-resistance, it is possible to provide a vertical semiconductor device capable of reducing the voltage drop in the on-state even with a high breakdown voltage.

Further, according to the invention of claim 4, the gate insulating film and the gate electrode are formed in the trench penetrating the second conductivity type base layer and reaching the depth of the middle of the first conductivity type semiconductor layer. Therefore, it is possible to provide the semiconductor device having the trench structure, which has the same effect as the third aspect.

Further, according to the invention of claim 5, in addition to the effect of any one of claims 1 to 3, since the second conductivity type buried layer has a mesh shape, it has a mesh shape as compared with the stripe shape. It is possible to provide a semiconductor device whose breakdown voltage can be easily increased.

Further, according to the invention of claim 6, since the second conductivity type buried layer has a stripe shape, it is possible to provide a semiconductor device having the same effect as that of any one of claims 1 to 3. . Further, according to the invention of claim 7,
Since the second conductivity type buried layer has a dot shape,
In addition to the effect of any one of claims 1 to 3,
Since it acts like a guard ring at the end, play
In the case of the trench structure, a high breakdown voltage semiconductor device can be formed. Well
According to the invention of claim 8, in addition to the effect of claim 7,
As the second conductivity type buried layer, each dot-shaped buried layer is formed.
Of rows and columns that are half-spaced apart from each other
Since it is arranged at equal intervals with the dots, it has a high-density dot pattern.
It is possible to provide a semiconductor device that is advantageous in pressure resistance.
It

Further, according to the invention of claim 9 , in addition to the effect of claim 3, it is possible to provide a semiconductor device such as a MOSFET capable of reducing the voltage drop in the ON state even with a high breakdown voltage.

According to the invention of claim 10 , in addition to the effect of claim 3, even a bipolar element having a second conductivity type drain layer on the drain electrode side has a high breakdown voltage as described above. Can reduce the voltage drop in the ON state
A semiconductor device such as a GBT can be provided.

Further, according to the invention of claim 11 , the second
Since the conductivity type buried layer has a potential different from that of the control electrode and is in a state of floating potential, it is possible to provide a semiconductor device having the same effect as that of the second aspect.

According to the twelfth , seventeenth and eighteenth aspects of the invention, the breakdown voltage BV between the first main electrode and the second main electrode is BV.
And the number M of the second conductivity type buried layers between the first main electrode and the second main electrode, and the first conductivity type semiconductor divided into (M + 1) layers by these second conductivity type buried layers. Among the layers, the voltage V 1 shared by the first conductivity type semiconductor layer closest to the first main electrode, the impurity concentration N 1 of the first conductivity type semiconductor layer closest to the first main electrode, and the first The thickness W 1 of the first-conductivity-type semiconductor layer closest to the main electrode and the first main-conductivity-type semiconductor layer divided into (M + 1) layers by the respective second-conductivity-type buried layers are the closest to the second main electrode. The voltage is divided into (M + 1) layers by the voltage V 2 shared by the nearby first conductivity type semiconductor layer, the impurity concentration N 2 of the first conductivity type semiconductor layer closest to the second main electrode, and each second conductivity type buried layer. Of the first conductive type semiconductor layer separated from the first main electrode and the second main electrode (M−
Voltage Vs shared by the first conductivity type semiconductor layer of layer 1),
Impurity concentration Ns of the first conductivity type semiconductor layer of the (M-1) layer
And the thickness Ws of the first conductivity type semiconductor layer of the (M-1) layer are clarified by predetermined formulas, so that in addition to the effect of claim 1 or claim 2, It is possible to provide a semiconductor device capable of forming an element that operates in good condition with good reproducibility.

According to the thirteenth and nineteenth aspects of the invention, the breakdown voltage BV between the source electrode and the drain electrode, the number M of the buried layers of the second conductivity type between the source electrode and the drain electrode, By these second conductive type buried layers (M
The second of the first conductivity type semiconductor layers divided into +1) layers
The voltage V 1 shared by the first conductive type semiconductor layer in contact with the conductive type base layer, the impurity concentration N 1 of the first conductive type semiconductor layer in contact with the second conductive type base layer, and the first conductive type semiconductor layer in contact with the second conductive type base layer. The thickness W 1 of the first conductivity type semiconductor layer and the first conductivity type semiconductor layer in contact with the drain layer among the first conductivity type semiconductor layers divided into (M + 1) layers by the respective second conductivity type buried layers are shared. Of the voltage V 2 , the impurity concentration N 2 of the first conductivity type semiconductor layer in contact with the drain layer, and the first conductivity type semiconductor layer divided into (M + 1) layers by each second conductivity type buried layer,
The voltage Vs shared by the first conductivity type semiconductor layer of the (M-1) layer that is not in contact with both the second conductivity type base layer and the drain layer.
And the impurity concentration N of the first conductivity type semiconductor layer of the (M-1) layer
Since the respective design conditions of s and the thickness Ws of the first conductivity type semiconductor layer of the (M-1) layer are clarified by predetermined formulas,
In addition to the effect of the third aspect, it is possible to provide a semiconductor device in which an element that operates reliably can be formed with good reproducibility.

[0258] According to the invention of claim 14, buried formed Ryakukata shape so as to surround the second conductivity type buried layer
In addition to the effect of any one of claims 1 to 3, since the termination structure is provided with the embedded second conductivity type guard ring region,
By the buried second conductivity type guard ring region, it is possible to provide a semiconductor device in which the interval between equipotential lines in the end portion of the semiconductor device is widened to reduce electric field concentration and prevent breakdown of breakdown voltage of the end portion of the semiconductor device.

Further, according to the invention of claim 15, the second
Formed in a substantially rectangular shape so as to surround the conductive type buried layer,
Since the buried second conductivity type RESURF region having a carrier density lower than the carrier density of the second conductivity type buried layer is provided, it is possible to provide a semiconductor device having the same effect as that of any one of claims 1 to 3.

According to the sixteenth aspect of the invention, in addition to the effect of any one of the first to third aspects, the terminal end portion of the first conductivity type semiconductor layer is formed in a bevel structure having an inclination. As a result, it is possible to provide a semiconductor device having the advantages of the bevel structure for relaxing the electric field strength at the pn junction termination.

[Brief description of drawings]

FIG. 1 is a MOSFET according to a first embodiment of the present invention.
FIG.

FIG. 2 is a schematic diagram for explaining the dimensions of a p-type buried layer in the same embodiment.

FIG. 3 is a view for explaining the operation of the MOSFET in the same embodiment.

FIG. 4 is a diagram showing a calculation result of a field intensity distribution by two-dimensional numerical calculation in the same embodiment.

FIG. 5 is a schematic diagram for comparatively explaining the MOSFET in the same embodiment and a conventional MOSFET.

FIG. 6 is a diagram for determining a carrier density Ns from a shared voltage Vs in the same embodiment.

FIG. 7 is a diagram for determining the thickness Ws from the carrier density Ns in the same embodiment.

FIG. 8 is a schematic diagram for explaining an equivalent circuit of the MOSFET in the same embodiment.

FIG. 9 is a diagram showing a relationship between on-resistance and breakdown voltage in the MOSFET according to the same embodiment.

FIG. 10 is a view showing a theoretically possible relationship between on-resistance and breakdown voltage in the MOSFET according to the present invention.

FIG. 11 is an M according to a second embodiment of the present invention.
FIG. 2 is a schematic view showing the configuration of a p-type buried layer of OSFET and an enlarged view of the p-type buried layer shown in FIG. 1.

FIG. 12 is a schematic diagram showing a configuration of a Schottky barrier diode according to a third embodiment of the present invention.

FIG. 13 is a schematic diagram showing a configuration of a Schottky barrier diode according to a fourth embodiment of the present invention.

FIG. 14 is a schematic diagram showing a configuration of an IGBT according to a fifth embodiment of the present invention.

FIG. 15 is a schematic diagram showing a configuration of an IGBT according to a sixth embodiment of the present invention.

FIG. 16 is a schematic diagram showing a configuration of an IGBT according to a seventh embodiment of the present invention.

FIG. 17 is a process sectional view for explaining the method for forming the semiconductor device according to the invention.

FIG. 18 is a process sectional view for explaining the method for forming the semiconductor device according to the invention.

FIG. 19 is a process sectional view for explaining the method for forming the semiconductor device according to the invention.

FIG. 20 is a process sectional view for explaining the method for forming the semiconductor device according to the invention.

FIG. 21 is a schematic diagram for explaining a method for forming a semiconductor device according to the present invention.

FIG. 22 is a plan view showing a mask pattern for forming a stripe-shaped p-type buried layer according to the present invention.

FIG. 23 is a plan view showing a modification pattern of FIG. 16 according to the present invention.

FIG. 24 is a plan view showing a mask pattern for forming a mesh-shaped p-type buried layer according to the present invention.

FIG. 25 is a plan view showing a mask pattern for forming a mesh-shaped p-type buried layer according to the present invention.

FIG. 26 is a plan view showing a mask pattern for forming a dot-shaped p-type buried layer according to the present invention.

FIG. 27 is a plan view showing a modified pattern of FIG. 26 according to the present invention.

FIG. 28 is a plan view showing a mask pattern of a p-type buried layer which is stripe-shaped and does not require alignment according to the present invention.

FIG. 29 is a plan view showing a modification pattern of FIG. 28 according to the present invention.

30 is a sectional view taken along the line XXXV-XXXV of FIG. 22 according to the present invention,

FIG. 31 is a MOSFE according to an eighth embodiment of the present invention.
The schematic diagram which shows the termination structure of T.

FIG. 32 is a MOSFE according to a ninth embodiment of the present invention.
The schematic diagram which shows the termination structure of T.

FIG. 33 is a MOSF according to the tenth embodiment of the present invention.
The schematic diagram which shows the termination structure of ET.

FIG. 34 is a MOSF according to an eleventh embodiment of the present invention.
The schematic diagram which shows the termination structure of ET.

FIG. 35 is a MOSF according to a twelfth embodiment of the present invention.
The schematic diagram which shows the structure of ET.

FIG. 36 is a plan view of the MOSFET according to the same embodiment.

FIG. 37 is a plan view showing a modified configuration of the MOSFET according to the same embodiment.

FIG. 38 is a MOSF according to the thirteenth embodiment of the present invention.
The schematic diagram which shows the structure of ET.

FIG. 39 is a MOSF according to the fourteenth embodiment of the present invention.
The schematic diagram which shows the structure of ET.

FIG. 40 is a MOSF according to the fifteenth embodiment of the present invention.
The schematic diagram which shows the structure of ET.

FIG. 41 is a cross-sectional view taken along the line XLVI-XLVI of FIG. 40 in the embodiment.

FIG. 42 is a MOSF according to the 16th embodiment of the present invention.
The schematic diagram which shows the structure of ET.

FIG. 43 is a MOSF according to a seventeenth embodiment of the present invention.
The schematic diagram which shows the structure of ET.

FIG. 44 is a MOSF according to the eighteenth embodiment of the present invention.
The schematic diagram which shows the structure of ET.

FIG. 45 is a MOSF according to the nineteenth embodiment of the present invention.
The schematic diagram which shows the structure of ET.

FIG. 46 is a schematic diagram showing the structure of a semiconductor device according to a twentieth embodiment of the present invention.

FIG. 47 is a schematic diagram showing the structure of a semiconductor device according to a twenty-first embodiment of the present invention.

FIG. 48 is a sectional perspective view schematically showing the configuration of a semiconductor device according to a twenty-second embodiment of the present invention.

FIG. 49 is a schematic diagram showing a configuration of a conventional MOSFET.

FIG. 50 is a diagram showing the relationship between on-resistance and breakdown voltage in a conventional MOSFET.

FIG. 51 is a sectional view schematically showing the configuration of a conventional bipolar transistor.

FIG. 52 is a sectional view schematically showing the configuration of a conventional IGBT.

FIG. 53 is a diagram showing a relationship between a voltage drop and a current in an ON state of a conventional MOSFET and IGBT.

[Explanation of symbols]

11, 31, 61, 67, 68, 201, 211, 22
1 ... N-type substrate 12, 42, 111, 131, 209, 217, 231
... Drain electrodes 13, 15, 17, 32, 32 1 to 32 3 , 34, 4
4,44 1 to 44 4 , 46, 62, 66, 202, 21
2,222 ... n-type base layer 14,14a, 16,16a, 33,33 1 ~33 3 ,
45, 45 1-45 4, 104,112,127,14
4, 210, 230 ... P-type buried layers 18, 48, 106, 124, 203, 214 ... P-type base layers 19, 49, 107, 126, 207, 213, 227
... n-type source layers 20, 50 ... Si oxide films 21, 51, 110, 130, 206 ... Gate electrodes 22, 52, 108, 128, 208, 216, 228
Source electrode 35 Schottky electrode 36 Ohmic electrode 41 p type substrate 43 n type buffer layers 47, 47a n + type layer 63 mask 64 ion 65 ion implantation layer 71 frame 72, 81 Stripe portion 73 ... Central portion 74 ... Gate electrode pad 75 ... Region 76, 82 ... Connection portion 77 ... Mesh portion 78 ... Dot 83 ... Square portion 91 ... Embedded guard ring 92 ... Equipotential line 93 ... Embedded RESURF 101, 121 ... Substrate 102 ... N- type layers 103, 123 ... N type offset layers 105, 125 ... N type drain layers 109, 129 ... Oxide film 122 ... Buried oxide films 141, 225 ... Insulating film 142 ... Contact hole 143 ... Equipotential electrode 145 ... p-type connection layers 146, 147 ... SIPOS portions 204, 218, 224 ... Trench 205 ... Gate insulating films 215, 229 ... Source electrode 226 ... p-type polysilicon electrode BV ... withstand voltage Vs, V 1, V 2 ... ( shared) voltage Ns, N 1, N 2 ... impurity concentration Ws, W 1, W 2 ... thickness t ... thickness W ... Forming interval M ... Number of layers

─────────────────────────────────────────────────── --Continued from the front page (56) References JP-A-7-7154 (JP, A) JP-A-5-82792 (JP, A) JP-A-7-130996 (JP, A) JP-A-4- 332173 (JP, A) JP-A-6-334188 (JP, A) JP-A-64-11367 (JP, A) JP-A-55-98872 (JP, A) Actually developed JP-A-54-108660 (JP, U) (58) Fields investigated (Int.Cl. 7 , DB name) H01L 29/78 H01L 29/06 H01L 29/47 H01L 29/73-29/735 H01L 29/74-29/747 H01L 29/80-29 / 812 H01L 29/872

Claims (19)

(57) [Claims]
1. A high-resistance first conductivity type semiconductor provided between a first main electrode, a second main electrode, and the first main electrode and the second main electrode. A layer and a layer that is substantially orthogonal to the direction connecting the first main electrode and the second main electrode, and has a plurality of gaps that serve as current paths,
When the depletion layer extending from the vicinity of the first main electrode reaches
A vertical type having a second-conductivity-type buried layer selectively formed in the first-conductivity-type semiconductor layer, which has a potential different from that of any electrode of the semiconductor device body in a punch-through state. semiconductor device.
2. A high-resistance first conductivity type semiconductor provided between a first main electrode, a second main electrode, and the first main electrode and the second main electrode. A current control structure that has a layer and a control electrode that is provided in contact with the first conductivity type semiconductor layer and that controls a current flowing from the first main electrode to the second main electrode; A depletion layer that is substantially perpendicular to the direction connecting the main electrode and the second main electrode, is selectively formed in the first-conductivity-type semiconductor layer, and extends from the vicinity of the first main electrode.
When the layer reaches the punch-through state, the potential is fixed.
Vertical, characterized in that a second conductivity type buried layer
Type semiconductor device.
3. A drain layer, a drain electrode formed on a surface of the drain layer, and a high resistance first conductivity type semiconductor layer formed on a surface of the drain layer opposite to the drain electrode. A second conductivity type base layer selectively formed on the surface of the first conductivity type semiconductor layer opposite to the side where the drain layer is formed, and a second conductivity type base layer selectively formed on the surface of the second conductivity type base layer. A first conductive type source layer formed on the first conductive type source layer, a source electrode formed on the first conductive type source layer and the second conductive type base layer, the first conductive type source layer and the second conductive type base A plurality of gaps serving as current paths, the layers being substantially orthogonal to a direction connecting the drain electrode and the source electrode with a gate electrode that is in contact with the first conductive type semiconductor layer via a gate insulating film. Having the first conductivity type semiconductor layer Selectively formed in the above
Punch when the depletion layer extending from near the source electrode is reached
A vertical semiconductor device, comprising: a second conductive type buried layer in which the potential is fixed in a through state .
4. The semiconductor device according to claim 3, wherein the gate insulating film and the gate electrode penetrate the second conductive type base layer, and have a depth in the middle of the first conductive type semiconductor layer. A semiconductor device characterized in that it is formed in a groove reaching up to that point.
5. The semiconductor device according to claim 1, wherein the second-conductivity-type buried layer has a mesh shape.
6. The semiconductor device according to claim 1, wherein the second conductivity type buried layer has a stripe shape.
7. The semiconductor device according to claim 1, wherein the second conductivity type buried layer has a dot shape.
8. The semiconductor device according to claim 7, wherein, in the second conductive type buried layer, the dots having the dot shape are shifted by a half interval for each row, and the dots in rows and columns adjacent to each other. A semiconductor device characterized by being arranged at equal intervals.
9. The semiconductor device according to claim 3, wherein the drain layer is of a first conductivity type.
10. The semiconductor device according to claim 3, wherein the drain layer is of a second conductivity type.
11. The semiconductor device according to claim 2, wherein the second conductivity type buried layer has a potential different from that of the control electrode.
12. The semiconductor device according to claim 1, wherein a breakdown voltage BV between the first main electrode and the second main electrode.
And the number M of layers of the second-conductivity-type buried layer between the first main electrode and the second main electrode, and a first (M + 1) layer divided by these second-conductivity-type buried layers. Among the conductivity type semiconductor layers, the voltage V 1 shared by the first conductivity type semiconductor layer closest to the first main electrode and the impurity concentration N 1 of the first conductivity type semiconductor layer closest to the first main electrode. A thickness W 1 of the first conductivity type semiconductor layer closest to the first main electrode, and a first conductivity type semiconductor layer divided into (M + 1) layers by each of the second conductivity type buried layers, The voltage V 2 shared by the first conductivity type semiconductor layer closest to the second main electrode, the impurity concentration N 2 of the first conductivity type semiconductor layer closest to the second main electrode, and the second conductivity type The first main electrode of the first conductivity type semiconductor layer divided into (M + 1) layers by the type burying layer; Serial voltage Vs to share the second distant from the main electrode (M-1) layer first conductive type semiconductor layer, the (M-1) impurity concentration of the first conductivity type semiconductor layer of the layer N
s and the thickness Ws of the first conductivity type semiconductor layer of the (M-1) layer have a relationship of the following formula. Vs = (BV−V 1 −V 2 ) / (M−1) [V] V 1 ≧ Vs V 2 ≧ Vs N 1 <1.897 × 10 18 × V 1 −1.35 [cm −3 ] N 2 < 1.897 × 10 18 × V 2 −1.35 [cm −3 ] Ns <1.897 × 10 18 × Vs −1.35 [cm −3 ] W 1 <1.1247 × 10 10 × N 1 −0.85 [cm] Ws <1.1247 × 10 10 × Ns -0.85 [cm]
13. The semiconductor device according to claim 3, wherein a breakdown voltage BV between the source electrode and the drain electrode.
And the number M of the second conductivity type buried layers between the source electrode and the drain electrode, and among the first conductivity type semiconductor layers divided into (M + 1) layers by these second conductivity type buried layers. A voltage V 1 shared by a first conductivity type semiconductor layer in contact with the second conductivity type base layer, an impurity concentration N 1 of a first conductivity type semiconductor layer in contact with the second conductivity type base layer, and the second conductivity The thickness W 1 of the first conductive type semiconductor layer in contact with the type base layer, and the first conductive type semiconductor layer in the (M + 1) layer divided by the second conductive type embedded layers into the first conductive type semiconductor layer in contact with the drain layer. The voltage V 2 shared by the first-conductivity-type semiconductor layer, the impurity concentration N 2 of the first-conductivity-type semiconductor layer in contact with the drain layer, and the first M-layer divided by the second-conductivity-type buried layer Of the conductive type semiconductor layer, the second conductive type ba Not in contact with both layers and the drain layers (M-1) and the voltage Vs to share the first conductive type semiconductor layer of layers, the (M-1) impurity concentration of the first conductivity type semiconductor layer of the layer N
s and the thickness Ws of the first conductivity type semiconductor layer of the (M-1) layer have a relationship of the following formula. Vs = (BV−V 1 −V 2 ) / (M−1) [V] V 1 ≧ Vs V 2 ≧ Vs N 1 <1.897 × 10 18 × V 1 −1.35 [cm −3 ] N 2 < 1.897 × 10 18 × V 2 −1.35 [cm −3 ] Ns <1.897 × 10 18 × Vs −1.35 [cm −3 ] W 1 <1.1247 × 10 10 × N 1 −0.85 [cm] Ws <1.1247 × 10 10 × Ns -0.85 [cm]
14. The semiconductor device according to claim 1, wherein the buried second conductivity type guard is formed in a substantially rectangular shape so as to surround the second conductivity type buried layer. A semiconductor device comprising a ring region.
15. The semiconductor device according to claim 1, wherein the semiconductor device is formed in a substantially rectangular shape so as to surround the second conductive type buried layer, and the second conductive type buried layer is formed. A semiconductor device comprising a buried second conductivity type RESURF region having a carrier density lower than that of the layer.
16. The semiconductor device according to claim 1, wherein a terminal portion of the first conductivity type semiconductor layer is formed in a bevel structure having an inclination. Semiconductor device.
17. A high-resistance first conductivity type semiconductor provided between a first main electrode, a second main electrode, and the first main electrode and the second main electrode. A layer and a layer selectively formed in the first conductivity type semiconductor layer and having a floating potential and extending in a direction substantially orthogonal to a direction connecting the first main electrode and the second main electrode. A plurality of gaps that are arranged and function as a current path, and have a floating potential that is different from any electrode of the semiconductor device body when the depletion layer extending from the vicinity of the first main electrode reaches itself. A withstand voltage BV between the first main electrode and the second main electrode, which is a semiconductor device having a two-conductivity type buried layer.
And the number M of layers of the second conductivity type buried layer between the first main electrode and the second main electrode, and between the second conductivity type buried layer and the first main electrode. The voltage V 1 shared by the first region of the first conductivity type semiconductor layer arranged close to the first main electrode and the impurity concentration N of the first region of the first conductivity type semiconductor layer.
1 , a thickness W 1 of the first region of the first conductive type semiconductor layer, and a space between the second conductive type buried layer and the second main electrode, which is disposed close to the second main electrode. It has been the voltage V 2 to share the second region of the first conductivity type semiconductor layer, the impurity concentration of the second region of the first conductivity type semiconductor layer N
2 , a voltage Vs shared by a third region between the first region and the second region of the first conductivity type semiconductor layer, and an impurity concentration N of the third region of the first conductivity type semiconductor layer.
and s and the thickness W s of the third region of the first conductivity type semiconductor layer have the following relationship. Vs = (BV−V 1 −V 2 ) / (M−1) [V] V 1 ≧ Vs V 2 ≧ Vs N 1 <1.897 × 10 18 × V 1 −1.35 [cm −3 ] N 2 < 1.897 × 10 18 × V 2 −1.35 [cm −3 ] Ns <1.897 × 10 18 × Vs −1.35 [cm −3 ] W 1 <1.1247 × 10 10 × N 1 −0.85 [cm] Ws <1.1247 × 10 10 × Ns -0.85 [cm]
18. The semiconductor device according to claim 17, wherein the semiconductor device is provided in contact with the first conductivity type semiconductor layer and controls a current flowing from the first main electrode to the second main electrode. 7. A semiconductor device comprising a current control structure having the control electrode according to claim 1.
19. A drain layer, a drain electrode formed on a surface of the drain layer, and a high resistance first conductivity type semiconductor layer formed on a surface of the drain layer opposite to the drain electrode. A second conductivity type base layer selectively formed on the surface of the first conductivity type semiconductor layer opposite to the side where the drain layer is formed, and a second conductivity type base layer selectively on the surface of the second conductivity type base layer. The formed first conductivity type source layer, the source electrode formed on the first conductivity type source layer and the second conductivity type base layer, the first conductivity type source layer and the second conductivity type base layer A gate electrode in contact with the first conductive type semiconductor layer via a gate insulating film, and the drain electrode and the source electrode selectively formed in the first conductive type semiconductor layer and having a floating potential. A direction that is approximately orthogonal to the direction that connects It is spread over the
A second conductivity type buried layer having a plurality of gaps functioning as a current path and having a floating potential different from any electrode of the semiconductor device body when the depletion layer extending from the vicinity of the source electrode reaches itself. And a breakdown voltage BV between the drain electrode and the source electrode.
A number M of buried layers of the second conductivity type between the drain electrode and the source electrode, and a space between the buried layer of the second conductivity type and the source electrode, which is disposed close to the source electrode. And the voltage V 1 shared by the first region of the first conductivity type semiconductor layer and the impurity concentration N of the first region of the first conductivity type semiconductor layer.
1 , a thickness W 1 of the first region of the first conductive type semiconductor layer, and a first conductive type disposed between the buried layer of the second conductive type and the drain electrode in proximity to the drain electrode. The voltage V 2 shared by the second region of the semiconductor layer and the impurity concentration N of the second region of the first conductivity type semiconductor layer.
2 , a voltage Vs shared by a third region between the first region and the second region of the first conductivity type semiconductor layer, and an impurity concentration N of the third region of the first conductivity type semiconductor layer.
and s and the thickness W s of the third region of the first conductivity type semiconductor layer have the following relationship. Vs = (BV−V 1 −V 2 ) / (M−1) [V] V 1 ≧ Vs V 2 ≧ Vs N 1 <1.897 × 10 18 × V 1 −1.35 [cm −3 ] N 2 < 1.897 × 10 18 × V 2 −1.35 [cm −3 ] Ns <1.897 × 10 18 × Vs −1.35 [cm −3 ] W 1 <1.1247 × 10 10 × N 1 −0.85 [cm] Ws <1.1247 × 10 10 × Ns -0.85 [cm]
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