JP3391676B2 - Semiconductor module and resin sealing method thereof - Google Patents
Semiconductor module and resin sealing method thereofInfo
- Publication number
- JP3391676B2 JP3391676B2 JP29535297A JP29535297A JP3391676B2 JP 3391676 B2 JP3391676 B2 JP 3391676B2 JP 29535297 A JP29535297 A JP 29535297A JP 29535297 A JP29535297 A JP 29535297A JP 3391676 B2 JP3391676 B2 JP 3391676B2
- Authority
- JP
- Japan
- Prior art keywords
- solder resist
- annular
- sealing resin
- resin
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、配線基板上に実装
した半導体素子を流動性のある封止樹脂で封止した半導
体モジュール及びその樹脂封止方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor module in which a semiconductor element mounted on a wiring board is sealed with a fluid sealing resin, and a resin sealing method for the same.
【０００２】[0002]
【従来の技術】一般に、ベアチップのような半導体素子
は、絶縁基板上に配線パターンの形成された配線基板上
に搭載され、半導体素子と配線パターンをワイヤーボン
ディングにより電気的に接続した後、半導体素子及びワ
イヤーボンディング部の全体を覆うように封止樹脂によ
って封止され、半導体素子が保護される構造となってい
る。ここで、封止樹脂としては、封止対象の半導体素子
やワイヤーボンディング等の接続部品の隅々まで保護す
るため、流動性のあるエポキシ樹脂等を使用するのが一
般的である。2. Description of the Related Art Generally, a semiconductor element such as a bare chip is mounted on a wiring board having a wiring pattern formed on an insulating substrate, and the semiconductor element and the wiring pattern are electrically connected by wire bonding, and then the semiconductor element is mounted. Also, the semiconductor element is protected by sealing with a sealing resin so as to cover the entire wire bonding portion. Here, as the sealing resin, in general, a fluid epoxy resin or the like is used in order to protect every corner of the semiconductor element to be sealed and connection parts such as wire bonding.
【０００３】しかしながら、封止樹脂は流動性を有する
ため、余分な領域まで封止樹脂が流れ出るのを防止する
ため、例えば、特開平６−１６９０３３号公報に記載さ
れているように、半導体素子の周囲を囲むように形成さ
れた流れ止めの枠を用いている。この流れ止め枠の内部
に封止樹脂を充填することにより、周囲に封止樹脂が流
れ出るのを防止するとともに、半導体素子を覆うように
封止樹脂を充填して、半導体素子を保護するようにして
いる。However, since the encapsulating resin has fluidity, in order to prevent the encapsulating resin from flowing out to an extra area, for example, as disclosed in Japanese Patent Laid-Open No. 6-169033, a semiconductor element A flow stop frame formed so as to surround the circumference is used. By filling the sealing resin inside the flow stop frame, it is possible to prevent the sealing resin from flowing out, and also to fill the sealing resin so as to cover the semiconductor element to protect the semiconductor element. ing.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、従来の
流れ止め枠は、絶縁基板上に配線パターンの形成され、
さらに、配線パターンを覆うようにソルダーレジストが
形成された配線基板の上に、流動性の低いエポキシ樹脂
を塗布用ノズルを用いて、四角形若しくは円形に描画し
て形成していた。そのため、流れ止め枠の形成工程が必
要であり、半導体モジュールの製造工程が１つ増えるた
め、製造コストが高くなるという問題があった。また、
流動性の低いエポキシ樹脂は、封止樹脂として用いる流
動性の高いエポキシ樹脂に比べて高価であるため、この
点においても、製造コストが高くなるという問題があっ
た。However, in the conventional flow stop frame, the wiring pattern is formed on the insulating substrate,
Further, an epoxy resin having low fluidity is formed in a square or circular shape by using a coating nozzle on a wiring board on which a solder resist is formed so as to cover the wiring pattern. Therefore, the step of forming the flow stop frame is required, and the number of manufacturing steps of the semiconductor module is increased by one, resulting in a problem of increased manufacturing cost. Also,
Since the epoxy resin having a low fluidity is more expensive than the epoxy resin having a high fluidity used as the sealing resin, there is a problem in that the manufacturing cost also increases in this respect.
【０００５】本発明の目的は、安価に製造できる半導体
モジュール及びその樹脂封止方法を提供することにあ
る。An object of the present invention is to provide a semiconductor module which can be manufactured at low cost and a resin sealing method for the same.
【０００６】[0006]
【課題を解決するための手段】（１）上記目的を達成す
るために、本発明は、絶縁基板上に配線パターンが形成
され、この配線パターンの上をソルダレジストにより保
護した配線基板と、この配線基板上に搭載され、上記配
線パターンと電気的に接続された半導体チップとを有
し、上記半導体チップを封止樹脂により封止した半導体
モジュールにおいて、上記ソルダレジストを用いて、上
記配線基板における上記半導体チップの搭載される位置
の外周を環状に囲む環状部と、この環状部の外周におい
てソルダレジストの除去されたソルダレジスト除去部を
設け、上記環状枠と上記ソルダレジスト除去部との境界
部Ｃにおいては、上記環状枠の上端面と、上記環状枠の
側端面がほぼ垂直に近い断面形状を有し、上記環状部の
内側に半導体チップを搭載した後、上記環状部の内側の
閉空間に封止樹脂を充填し、上記環状部と上記ソルダレ
ジスト除去部の境界部までの上記環状部の内側及び上記
環状部の上端面までの領域に充填する封止樹脂を備える
ようにしたものである。かかる構成により、封止樹脂
は、環状部において流出を防止されるため、樹脂封止が
可能になるとともに、環状部は、ソルダレジストにより
形成されるため、安価に製造し得るものとなる。(1) In order to achieve the above object, the present invention provides a wiring board in which a wiring pattern is formed on an insulating substrate and the wiring pattern is protected by a solder resist; A semiconductor module mounted on a wiring board and having a semiconductor chip electrically connected to the wiring pattern, wherein the semiconductor chip is sealed with a sealing resin, in the wiring board using the solder resist. An annular portion that annularly surrounds the outer periphery of the position where the semiconductor chip is mounted, and a solder resist removing portion from which the solder resist has been removed are provided on the outer periphery of the annular portion, and the boundary between the annular frame and the solder resist removing portion is provided .
In the portion C, the upper end surface of the annular frame and the annular frame
The side end surface has a cross-sectional shape that is almost vertical, and
After mounting the semiconductor chip inside,
Fill the closed space with sealing resin, and
Inside the annular part up to the boundary of the distant removal part and above
It is obtained by the so that with a sealing resin to be filled in the region up to the upper end surface of the annular portion. With such a configuration, the sealing resin is prevented from flowing out in the annular portion, so that the resin can be sealed, and since the annular portion is formed of the solder resist, it can be manufactured at low cost.
【０００７】（２）上記（１）において、好ましくは、
上記環状部の幅を０．１ｍｍ〜０．５ｍｍとしたもので
ある。(2) In the above (1), preferably,
The width of the annular portion is 0.1 mm to 0.5 mm.
【０００８】（３）上記（１）において、好ましくは、
上記ソルダレジスト除去部の幅を０．１ｍｍ〜０．３ｍ
ｍとしたものである。(3) In the above item (1), preferably,
The width of the solder resist removal portion is 0.1 mm to 0.3 m
m.
【０００９】（４）上記目的を達成するために、本発明
は、絶縁基板上に配線パターンが形成され、この配線パ
ターンの上をソルダレジストにより保護した配線基板上
に搭載された半導体チップを封止樹脂により封止する半
導体モジュールの樹脂封止方法において、上記ソルダレ
ジストにより、上記配線基板の配線パターンの上に、上
記配線基板における上記半導体チップの搭載される位置
の外周を環状に囲むように形成された環状部と、この環
状部の外周においてソルダレジストの除去されたソルダ
レジスト除去部とを形成し、上記環状枠と上記ソルダレ
ジスト除去部との境界部Ｃにおいては、上記環状枠の上
端面と、上記環状枠の側端面がほぼ垂直に近い断面形状
を有し、上記環状部の内側に半導体チップを搭載した
後、上記環状部の内側の閉空間に封止樹脂を充填し、上
記環状部と上記ソルダレジスト除去部の境界部までの上
記環状部の内側及び上記環状部の上端面までの領域に封
止樹脂を充填するようにしたものである。かかる方法に
より、ソルダレジストで形成された環状部とソルダレジ
スト除去部の境界部まで封止樹脂を充填して、容易に、
樹脂封止を行い得るものとなる。(4) In order to achieve the above object, the present invention seals a semiconductor chip mounted on a wiring substrate in which a wiring pattern is formed on an insulating substrate and the wiring pattern is protected by a solder resist. In a resin sealing method for a semiconductor module in which a sealing resin is used, the solder resist is formed on the wiring pattern of the wiring board so as to surround the outer periphery of the position where the semiconductor chip is mounted on the wiring board in a ring shape. The formed annular portion and the solder resist removed portion from which the solder resist is removed on the outer periphery of the annular portion are formed, and the annular frame and the solder resist are formed.
At the boundary C with the distant removal part, on the annular frame
Cross-sectional shape where the end face and the side end face of the annular frame are nearly vertical
The a, after mounting the semiconductor chip on the inside of the annular portion, filled with a sealing resin in a closed space inside of the annular portion, on to the boundary portion of the annular portion and the solder resist removal portion
The inside of the annular portion and the area up to the upper end surface of the annular portion are filled with the sealing resin. By such a method, the sealing resin is filled up to the boundary portion between the annular portion formed of the solder resist and the solder resist removed portion, and easily,
The resin can be sealed.
【００１０】[0010]
【発明の実施の形態】以下、図１〜図５を用いて、本発
明の一実施形態による半導体モジュールの構成及び樹脂
封止方法について説明する。最初に、図１及び図２を用
いて、本発明の一実施形態による半導体モジュールの構
成について説明する。図１は、本発明の一実施形態によ
る半導体モジュールの平面図であり、図２は、図１のＡ
−Ａ’断面図である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of a semiconductor module and a resin sealing method according to an embodiment of the present invention will be described below with reference to FIGS. First, the configuration of a semiconductor module according to an embodiment of the present invention will be described with reference to FIGS. 1 and 2. 1 is a plan view of a semiconductor module according to an exemplary embodiment of the present invention, and FIG.
It is a -A 'sectional view.
【００１１】最初に、配線基板１００の構成について説
明する。図２にその断面構造を示すように、配線基板１
００は、絶縁基板１１０と、配線パターン１２０と、ソ
ルダーレジスト１３０とから構成されている。First, the structure of the wiring board 100 will be described. As shown in the sectional structure of FIG.
00 includes an insulating substrate 110, a wiring pattern 120, and a solder resist 130.
【００１２】絶縁基板１１０は、例えば、ガラス・エポ
キシ樹脂のような絶縁性材料からなる基板である。絶縁
基板１１０の上には、配線パターン１２０が形成されて
いる。配線パターン１２０は、銅箔の上に、ニッケルメ
ッキ及び金メッキが形成されている。絶縁基板１１０の
表面の全面に銅箔を形成した上で、図１の平面図に示す
ようなパターンとなるように、不要部分をエッチングし
て、所望のパターン形状を有する銅箔面が形成される。
この銅箔面の上に、ニッケルメッキを施し、さらに、ニ
ッケルメッキの上に、金メッキを施して、配線パターン
１２０が形成される。なお、配線パターンの材料は、こ
れに限るものでない。配線パターン１２０の膜厚は、例
えば、４０μｍである。The insulating substrate 110 is a substrate made of an insulating material such as glass epoxy resin. A wiring pattern 120 is formed on the insulating substrate 110. The wiring pattern 120 has nickel plating and gold plating formed on a copper foil. After forming a copper foil on the entire surface of the insulating substrate 110, unnecessary portions are etched to form a copper foil surface having a desired pattern shape so as to form a pattern as shown in the plan view of FIG. It
The wiring pattern 120 is formed by nickel-plating the copper foil surface and gold-plating the nickel plating. The material of the wiring pattern is not limited to this. The film thickness of the wiring pattern 120 is, for example, 40 μm.
【００１３】配線パターン１２０の上には、配線パター
ン１２０を保護するためのソルダーレジスト１３０が形
成される。ソルダーレジスト１３０は、絶縁性のレジス
ト材料からなり、フォトレジストにより所定の形状に形
成される。即ち、絶縁基板１１０及び配線パターン１２
０の全面に、レジスト材が塗布された後、所望の部分を
マスキングして露光硬化させ、エッチング除去して、所
定の部分にのみソルダーレジスト１３０が形成される。
本実施形態においては、配線パターン１２０の一端側で
あって外部と導通させるための電極部１２０Ａと、ワイ
ヤーボンディングによって半導体チップ２００と導通を
とるための電極部１２０Ｂの上からは、ソルダーレジス
トは除去されている。ソルダーレジスト１３０の膜厚
は、例えば、３０μｍである。A solder resist 130 for protecting the wiring pattern 120 is formed on the wiring pattern 120. The solder resist 130 is made of an insulating resist material, and is formed into a predetermined shape by a photoresist. That is, the insulating substrate 110 and the wiring pattern 12
After the resist material is applied to the entire surface of 0, the desired portion is masked, exposed and hardened, and removed by etching to form the solder resist 130 only on a predetermined portion.
In the present embodiment, the solder resist is removed from the electrode portion 120A for conducting to the outside on one end side of the wiring pattern 120 and the electrode portion 120B for conducting to the semiconductor chip 200 by wire bonding. Has been done. The film thickness of the solder resist 130 is, for example, 30 μm.
【００１４】また、図１に示すように、半導体チップ２
００が搭載される領域の外周には、円環状の環状枠１３
０Ａがソルダーレジスト１３０によって形成されるとと
もに、環状枠１３０Ａの外周には、所定の幅を有するソ
ルダーレジスト除去部１３０Ｂが形成されている。ソル
ダレジスト除去部１３０Ｂにおいては、ソルダレジスト
は除去されており、その下の配線パターン１２０や、絶
縁基板１１０が露出している。ソルダレジスト除去部１
３０Ｂの外周には、ソルダレジスト１３０が形成されて
いる。ここで、本実施形態においては、環状枠１３０Ａ
の幅Ｘは、０．３ｍｍとし、ソルダーレジスト除去部１
３０Ｂの幅Ｙは、０．２ｍｍとしている。As shown in FIG. 1, the semiconductor chip 2
00 is mounted on the outer periphery of the ring-shaped annular frame 13
0A is formed by the solder resist 130, and a solder resist removing portion 130B having a predetermined width is formed on the outer periphery of the annular frame 130A. In the solder resist removing section 130B, the solder resist is removed, and the wiring pattern 120 and the insulating substrate 110 thereunder are exposed. Solder resist remover 1
A solder resist 130 is formed on the outer periphery of 30B. Here, in the present embodiment, the annular frame 130A
Has a width X of 0.3 mm, and the solder resist removing portion 1
The width Y of 30B is 0.2 mm.
【００１５】ソルダーレジスト除去部１３０Ｂの形成に
よる環状枠１３０Ａの形成は、配線パターン１２０の両
端の電極部１２０Ａ，１２０Ｂの形成と同時にフォトレ
ジストにより形成される。環状枠１３０Ａは、後述する
ように、半導体チップ２００を樹脂封止する際の流れ止
め枠として用いられるものであり、この環状枠１３０Ａ
は、通常のソルダーレジスト１３０の形成工程と同時に
形成されるため、流れ止め枠の形成のために、工程が増
加することもないものである。また、流れ止め枠となる
環状枠１３０Ａは、ソルダレジスト１３０により形成さ
れるため、流れ止め枠のための特別な材料を用いる必要
もなく、安価に形成することができる。なお、環状枠１
３０Ａの形状としては、図１に示すような円環状に限ら
ず、四角形の環状の形状としてもよく、内部に収容され
る半導体チップ２００を樹脂封止する際に、封止樹脂が
外周に流れ出るのを防止するため、環状に閉じたもので
あればよいものである。The annular frame 130A is formed by forming the solder resist removing portion 130B by using a photoresist simultaneously with the formation of the electrode portions 120A and 120B at both ends of the wiring pattern 120. The annular frame 130A is used as a flow stop frame when the semiconductor chip 200 is resin-sealed, as will be described later.
Since it is formed at the same time as the normal solder resist 130 forming step, the number of steps is not increased due to the formation of the flow stop frame. Further, since the annular frame 130A serving as the flow stop frame is formed of the solder resist 130, it is not necessary to use a special material for the flow stop frame and can be formed at low cost. In addition, the annular frame 1
The shape of 30A is not limited to the annular shape as shown in FIG. 1, but may be a quadrangular annular shape, and when the semiconductor chip 200 housed inside is resin-sealed, the sealing resin flows out to the outer periphery. In order to prevent the above, it is sufficient if it is annularly closed.
【００１６】以上のようにして形成された配線基板１０
０の上に、半導体チップ２００が接着剤等により仮止め
された後、半導体チップ２００の端子部と配線パターン
１２０の電極部１２０Ｂとが、ボンディングワイヤー２
１０により、ワイヤーボンディングされる。さらに、環
状枠１３０Ａの内部に、流動性のよいエポキシ樹脂等の
封止樹脂３００が充填され、半導体チップ２００及びボ
ンディングワイヤー２１０を樹脂封止する。なお、封止
樹脂３００は、不透明である。The wiring board 10 formed as described above
0, the semiconductor chip 200 is temporarily fixed with an adhesive or the like, and then the terminal portion of the semiconductor chip 200 and the electrode portion 120B of the wiring pattern 120 are bonded to each other by the bonding wire 2
Wire bonding is performed by 10. Further, a sealing resin 300 such as an epoxy resin having good fluidity is filled inside the annular frame 130A, and the semiconductor chip 200 and the bonding wire 210 are resin-sealed. The sealing resin 300 is opaque.
【００１７】次に、図３及び図４を用いて、本発明の一
実施形態による封止樹脂による樹脂封止方法について説
明する。図３及び図４は、本発明の一実施形態による封
止樹脂による樹脂封止方法の説明図である。なお、図１
若しくは図２と同一符号は、同一部分を示している。Next, a resin sealing method using a sealing resin according to an embodiment of the present invention will be described with reference to FIGS. 3 and 4. 3 and 4 are explanatory views of a resin sealing method using a sealing resin according to an embodiment of the present invention. Note that FIG.
Alternatively, the same reference numerals as those in FIG. 2 indicate the same parts.
【００１８】図３に示すように、既に半導体チップ２０
０の仮止め及びボンディングワイヤー２１０をボンディ
ング作業の終了している回路基板に、封止樹脂３００を
封止樹脂塗布用ノズル３１０を用いて、ソルダーレジス
ト材による環状枠１３０Ａの内周側の封止樹脂塗布範囲
Ｂ−Ｂ’の内側に充填する。封止樹脂３００は、環状枠
１３０Ａによって環状枠１３０Ａの外周側への流出が防
止され、封止樹脂塗布範囲Ｂ−Ｂ’に充填される。As shown in FIG. 3, the semiconductor chip 20 is already used.
No. 0 temporary fixing and the bonding wire 210 is bonded to the circuit board on which the bonding work has been completed, and the sealing resin 300 is sealed on the inner peripheral side of the annular frame 130A with the solder resist material using the sealing resin coating nozzle 310. It is filled inside the resin application range BB ′. The sealing resin 300 is prevented from flowing out to the outer peripheral side of the annular frame 130A by the annular frame 130A, and is filled in the sealing resin application range BB ′.
【００１９】さらに、図４に示すように、封止樹脂３０
０の充填が進むにつれて、封止樹脂３００は、環状枠１
３０Ａの上端面を超えて行き、環状枠１３０Ａに設けた
ソルダレジスト除去部１３０Ｂとの境界線Ｃ−Ｃ’部
で、環状部１３０Ａを形成するソルダレジストと、ソル
ダレジストが除去されている除去部１３０Ｂとの表面張
力の差により、封止樹脂３００の流れが止まる。Further, as shown in FIG. 4, the sealing resin 30
As the filling of 0 progresses, the sealing resin 300 becomes
The solder resist forming the annular portion 130A and the removing portion where the solder resist is removed at the boundary line CC ′ between the solder resist removing portion 130B provided on the annular frame 130A and over the upper end surface of 30A. Due to the difference in surface tension with 130B, the flow of the sealing resin 300 is stopped.
【００２０】この表面張力の差によりＣ−Ｃ’部で封止
樹脂３００の流れが止まり、かつ搭載した半導体チップ
２００及びボンディングワイヤー２１０が封止樹脂３０
０に被われた所で、樹脂塗布作業が完了する。Due to this difference in surface tension, the flow of the sealing resin 300 is stopped at the CC ′ portion, and the mounted semiconductor chip 200 and the bonding wire 210 are sealed by the sealing resin 30.
When it is covered with 0, the resin coating work is completed.
【００２１】ここで、図５を用いて、環状部１３０Ａと
ソルダレジスト除去部１３０Ｂとの境界部分における封
止樹脂３００の挙動について説明する。図５は、本発明
の一実施形態による樹脂封止方法における封止樹脂の挙
動の説明図であり、図２の要部拡大断面図である。な
お、図１若しくは図２と同一符号は、同一部分を示して
いる。The behavior of the sealing resin 300 at the boundary between the annular portion 130A and the solder resist removing portion 130B will be described with reference to FIG. FIG. 5 is an explanatory diagram of the behavior of the sealing resin in the resin sealing method according to the embodiment of the present invention, and is an enlarged cross-sectional view of the main parts of FIG. 2. The same reference numerals as those in FIG. 1 or 2 indicate the same parts.
【００２２】環状枠１３０Ａ及びソルダレジスト除去部
１３０Ｂは、上述したように、ソルダレジスト１３０の
フォトレジストによって形成される。従って、環状枠１
３０Ａの上端面１３０Ａ１は、平坦部となっている。ま
た、ソルダレジスト除去部１３０Ｂが形成される環状枠
１３０Ａの側端面１３０Ａ２は、ほぼ垂直に近い断面形
状となっている。その結果、環状枠１３０Ａとソルダレ
ジスト除去部１３０Ｂの境界部Ｃにおいては、環状枠１
３０Ａの上端面１３０Ａ１と、環状枠１３０Ａの側端面
１３０Ａ２がほぼ直角に屈曲しており、この部分におい
て変極点を形成している。図３において説明したよう
に、環状枠１３０Ａの内周側から封止樹脂３００を充填
し、その封止樹脂３００が、環状枠１３０Ａの上端面１
３０Ａ１を越えて、ソルダレジスト除去部１３０Ｂ方向
に流れる。封止樹脂３００が、境界部Ｃに至ると、封止
樹脂３００の環状枠１３０Ａに対する表面張力が、封止
樹脂３００のソルダレジスト除去部１３０Ｂに対する表
面張力よりも大きいため、境界部Ｃにおいて、封止樹脂
３００の流れが止まり、封止樹脂３００は、半導体チッ
プ２００及びボンディングワイヤ２１０を覆うように盛
り上がって堆積することになる。即ち、ガラスコップの
中に水を満たしていくと、水の表面張力によって、水が
コップの上端部よりも盛り上がるようになるのと同様に
して、本実施形態においては、環状枠１３０Ａと、その
外周のソルダレジスト除去部１３０Ｂの表面張力の差に
より、環状枠１３０Ａ内に封止樹脂３００を充填するこ
とができる。The annular frame 130A and the solder resist removing portion 130B are formed of the photoresist of the solder resist 130 as described above. Therefore, the annular frame 1
The upper end surface 130A1 of 30A is a flat portion. Further, the side end surface 130A2 of the annular frame 130A in which the solder resist removing portion 130B is formed has a cross-sectional shape that is almost vertical. As a result, in the boundary portion C between the annular frame 130A and the solder resist removing portion 130B, the annular frame 1
An upper end surface 130A1 of 30A and a side end surface 130A2 of the annular frame 130A are bent substantially at right angles, and an inflection point is formed in this portion. As described in FIG. 3, the sealing resin 300 is filled from the inner peripheral side of the annular frame 130A, and the sealing resin 300 is the upper end surface 1 of the annular frame 130A.
It flows over 30A1 toward the solder resist removing portion 130B. When the sealing resin 300 reaches the boundary portion C, the surface tension of the sealing resin 300 with respect to the annular frame 130A is larger than the surface tension of the sealing resin 300 with respect to the solder resist removing portion 130B. The flow of the stop resin 300 is stopped, and the sealing resin 300 rises and is deposited so as to cover the semiconductor chip 200 and the bonding wire 210. That is, as the glass cup is filled with water, the surface tension of the water causes the water to rise higher than the upper end portion of the cup. The sealing resin 300 can be filled in the annular frame 130A due to the difference in surface tension of the solder resist removing portion 130B on the outer periphery.
【００２３】なお、従来の流れ止め枠は、流動性の低い
エポキシ樹脂を用いていたため、その断面形状は、図５
に示した環状枠１３０Ａのような鋭角の形状とならず、
なだらかな丘陵状の形状となっている。従って、本実施
形態における環状枠１３０Ａとソルダレジスト除去部１
３０Ｂの境界部Ｃにおける変極点はないため、曲がれ止
め枠の上端面に流れた封止樹脂は、枠を容易に乗り越え
て、枠の外部に流れ出る問題があった。Since the conventional flow stop frame uses an epoxy resin having low fluidity, its cross-sectional shape is shown in FIG.
The shape does not have an acute angle like the annular frame 130A shown in
It has a gentle hilly shape. Therefore, the annular frame 130A and the solder resist removing unit 1 in this embodiment are
Since there is no inflection point at the boundary portion C of 30B, there is a problem that the sealing resin that has flowed to the upper end surface of the curving stop frame easily gets over the frame and flows out of the frame.
【００２４】それに対して、本実施形態においては、環
状枠１３０Ａとソルダレジスト除去部１３０Ｂとの境界
部Ｃにおいて、表面張力により、封止樹脂３００の流出
が防止できるため、封止樹脂３００の盛り上がりの高さ
を大きくでき、半導体チップ２００及びボンディングワ
イヤ２１０を完全に覆って、保護することが可能となっ
た。図５に示す例において、配線パターン１２０の膜厚
Ｈは４０μｍであり、ソルダレジスト１３０の膜厚Ｉは
３０μｍであり、半導体チップ２００の高さＪは、３０
０〜４００μｍのとき、封止樹脂３００の盛り上がり高
さ（ソルダレジスト１３０の上面からの高さ）Ｋは、８
００〜９００μｍとすることができ、半導体チップ２０
０及びボンディングワイヤ２１０を完全に覆って、保護
することが可能となった。On the other hand, in the present embodiment, at the boundary C between the annular frame 130A and the solder resist removing portion 130B, the sealing resin 300 can be prevented from flowing out due to the surface tension, so that the sealing resin 300 rises. It is possible to increase the height, and it is possible to completely cover and protect the semiconductor chip 200 and the bonding wire 210. In the example shown in FIG. 5, the film thickness H of the wiring pattern 120 is 40 μm, the film thickness I of the solder resist 130 is 30 μm, and the height J of the semiconductor chip 200 is 30 μm.
When the thickness is 0 to 400 μm, the swelling height (height from the upper surface of the solder resist 130) K of the sealing resin 300 is 8
The semiconductor chip 20 can have a thickness of 100 to 900 μm.
0 and the bonding wire 210 can be completely covered and protected.
【００２５】次に、環状枠１３０Ａの幅Ｘ及びソルダレ
ジスト除去部１３０Ｂの幅Ｙについて説明する。Next, the width X of the annular frame 130A and the width Y of the solder resist removing portion 130B will be described.
【００２６】上述した本実施形態においては、環状枠１
３０Ａの幅Ｘは０．３ｍｍとし、ソルダレジスト除去部
１３０Ｂの幅Ｙは０．２ｍｍとしている。環状枠１３０
Ａの幅Ｘについて検討を行ったところ、０．１ｍｍ〜
０．５ｍｍの範囲が好適である。環状枠１３０Ａは、フ
ォトレジストにより形成されるため、その加工精度の観
点から０．１ｍｍより狭くすると、環状枠１３０Ａの一
部が切れる場合がある。環状枠１３０Ａの一部が切れ、
環状とならないと、その切れた部分から封止樹脂が流出
するため、不適当である。また、環状枠１３０Ａの幅Ｘ
が広くなると、配線基板全体に占める環状枠１３０Ａの
面積が大きくなるため、高密度実装に適しないものとな
る。そこで、実用的な環状枠１３０Ａの幅Ｘの上限値
は、０．５ｍｍとなる。In the above-described embodiment, the annular frame 1
The width X of 30A is 0.3 mm, and the width Y of the solder resist removing portion 130B is 0.2 mm. Annular frame 130
When the width X of A is examined, it is 0.1 mm
A range of 0.5 mm is suitable. Since the annular frame 130A is formed of photoresist, if it is narrower than 0.1 mm from the viewpoint of processing accuracy, a part of the annular frame 130A may be cut off. A part of the annular frame 130A is cut,
If it does not form an annular shape, the sealing resin flows out from the cut portion, which is inappropriate. Also, the width X of the annular frame 130A
As the area becomes wider, the area of the annular frame 130A occupying the entire wiring board becomes larger, which is not suitable for high-density mounting. Therefore, the upper limit value of the width X of the practical annular frame 130A is 0.5 mm.
【００２７】また、ソルダレジスト除去部１３０Ｂの幅
Ｙの好適な範囲は、０．１ｍｍ〜０．３ｍｍである。ソ
ルダレジスト除去部１３０Ｂは、フォトレジストにより
形成されるため、その加工精度の観点から０．１ｍｍよ
り狭くすると、ソルダレジスト除去部１３０Ｂの両側の
ソルダレジスト同士がブリッジしてしまう場合があるた
め、不適当である。また、ソルダレジスト除去部１３０
Ｂの幅Ｙは、あまり広くする必要はなく、高密度実装の
観点からすると、０．３ｍｍ以下が好適である。The preferred range of the width Y of the solder resist removing portion 130B is 0.1 mm to 0.3 mm. Since the solder resist removing section 130B is formed of a photoresist, if the width is smaller than 0.1 mm from the viewpoint of processing accuracy, the solder resists on both sides of the solder resist removing section 130B may bridge each other. Appropriate. In addition, the solder resist removing unit 130
The width Y of B does not need to be so large, and is preferably 0.3 mm or less from the viewpoint of high-density mounting.
【００２８】環状枠１３０Ａの幅Ｘを０．３ｍｍとし、
ソルダレジスト除去部１３０Ｂの幅Ｙを０．２ｍｍとす
ることにより、環状枠１３０Ａ及びソルダレジスト除去
部１３０Ｂは、封止樹脂の流れ止めの作用を十分に有す
るとともに、目視でも、状枠１３０Ａ及びソルダレジス
ト除去部１３０Ｂの良・不良を確認できるため、きわめ
て実用的なものである。The width X of the annular frame 130A is 0.3 mm,
By setting the width Y of the solder resist removing portion 130B to 0.2 mm, the annular frame 130A and the solder resist removing portion 130B have a sufficient function of blocking the flow of the sealing resin, and can be visually observed to form the frame 130A and the solder. Since it is possible to confirm whether the resist removal portion 130B is good or bad, it is extremely practical.
【００２９】以上説明したように、本実施形態によれ
ば、流れ止め枠として、ソルダレジストを用いて環状枠
及びソルダレジスト除去部として形成するため、流れ止
め枠形成のための工程や材料が不要となり、従来よりも
安価に半導体モジュールの樹脂封止を実施でき、半導体
モジュールを安価に製造し得るものとなる。As described above, according to the present embodiment, since the annular frame and the solder resist removing portion are formed by using the solder resist as the flow stop frame, the steps and materials for forming the flow stop frame are unnecessary. Therefore, the semiconductor module can be resin-sealed at a lower cost than before, and the semiconductor module can be manufactured at a lower cost.
【００３０】また、環状枠とソルダレジスト除去部の表
面張力の差により、環状枠内に封止樹脂を盛り上がら
せ、半導体チップやボンディングワイヤの保護を十分に
行うことができる。Further, due to the difference in surface tension between the annular frame and the solder resist removing portion, the sealing resin can be raised in the annular frame and the semiconductor chip and the bonding wire can be sufficiently protected.
【００３１】また、環状枠とソルダレジスト除去部の表
面張力の差により、封止樹脂が外周側に流出することを
容易に防止することができる。Further, the sealing resin can be easily prevented from flowing out to the outer peripheral side due to the difference in surface tension between the annular frame and the solder resist removing portion.
【００３２】[0032]
【発明の効果】本発明によれば、樹脂封止作業の工程を
簡略化でき、半導体モジュールを安価で製造し得るもの
となる。According to the present invention, the process of resin sealing work can be simplified, and the semiconductor module can be manufactured at low cost.
【図１】本発明の一実施形態による半導体モジュールの
平面図である。FIG. 1 is a plan view of a semiconductor module according to an exemplary embodiment of the present invention.
【図２】図１のＡ−Ａ’断面図である。FIG. 2 is a cross-sectional view taken along the line A-A ′ of FIG.
【図３】本発明の一実施形態による封止樹脂による樹脂
封止方法の説明図である。FIG. 3 is an explanatory diagram of a resin sealing method using a sealing resin according to an embodiment of the present invention.
【図４】本発明の一実施形態による封止樹脂による樹脂
封止方法の説明図である。FIG. 4 is an explanatory diagram of a resin sealing method using a sealing resin according to an embodiment of the present invention.
【図５】本発明の一実施形態による樹脂封止方法におけ
る封止樹脂の挙動の説明図であり、図２の要部拡大断面
図である。FIG. 5 is an explanatory view of the behavior of the sealing resin in the resin sealing method according to the embodiment of the present invention, and is an enlarged cross-sectional view of the main parts of FIG.
１００…配線基板 １１０…絶縁基板 １２０…配線パターン １３０…ソルダレジスト １３０Ａ…環状枠 １３０Ｂ…ソルダレジスト除去部 ２００…半導体チップ ２１０…ボンディングワイヤー ３００…封止樹脂 ３１０…封止樹脂塗布用ノズル 100 ... Wiring board 110 ... Insulating substrate 120 ... Wiring pattern 130 ... Solder resist 130A ... Ring frame 130B ... Solder resist removing section 200 ... Semiconductor chip 210 ... Bonding wire 300 ... Sealing resin 310 ... Nozzle for applying sealing resin
フロントページの続き (72)発明者 松山 稔 神奈川県横浜市戸塚区吉田町292番地 株式会社 日立製作所 映像情報メディ ア事業部内 (72)発明者 村松 盛生 神奈川県横浜市戸塚区吉田町292番地 株式会社 日立製作所 映像情報メディ ア事業部内 (56)参考文献 特開 昭59−23551（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 23/28 H01L 21/56 Front page continuation (72) Minoru Matsuyama Minoru Matsuyama 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Hitachi, Ltd. Video Information Media Division (72) Inventor Morio Matsumura 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Hitachi, Ltd. Video Information Media Division (56) References JP-A-59-23551 (JP, A) (58) Fields investigated (Int.Cl. 7 , DB name) H01L 23/28 H01L 21/56
Claims (4)
の配線パターンの上をソルダレジストにより保護した配
線基板と、 この配線基板上に搭載され、上記配線パターンと電気的
に接続された半導体チップとを有し、 上記半導体チップを封止樹脂により封止した半導体モジ
ュールにおいて、 上記ソルダレジストを用いて、上記配線基板における上
記半導体チップの搭載される位置の外周を環状に囲む環
状部と、この環状部の外周においてソルダレジストの除
去されたソルダレジスト除去部を設け、 上記環状枠と上記ソルダレジスト除去部との境界部Ｃに
おいては、上記環状枠の上端面と、上記環状枠の側端面
がほぼ垂直に近い断面形状を有し、 上記環状部の内側に半導体チップを搭載した後、 上記環状部の内側の閉空間に封止樹脂を充填し、上記環
状部と上記ソルダレジスト除去部の境界部までの上記環
状部の内側及び上記環状部の上端面までの領域に充填す
る封止樹脂を備えた ことを特徴とする半導体モジュー
ル。1. A wiring board having a wiring pattern formed on an insulating substrate, the wiring pattern being protected by a solder resist, and a semiconductor chip mounted on the wiring board and electrically connected to the wiring pattern. In the semiconductor module in which the semiconductor chip is sealed with a sealing resin, using the solder resist, an annular portion annularly surrounding the outer periphery of the position where the semiconductor chip is mounted on the wiring board, the solder resist removal portion which is removed in the solder resist in the periphery of the annular portion is provided, at the boundary C between the annular frame and the solder resist removal portion
In, the upper end surface of the annular frame and the side end surface of the annular frame
Has a nearly vertical cross-sectional shape, and after mounting the semiconductor chip inside the annular portion, the closed space inside the annular portion is filled with a sealing resin,
The ring from the boundary between the groove and the solder resist removal area
Fill the inside of the groove and the area up to the upper end surface of the annular part.
A semiconductor module, which is provided with a sealing resin .
て、 上記環状部の幅を０．１ｍｍ〜０．５ｍｍとしたことを
特徴とする半導体モジュール。2. The semiconductor module according to claim 1, wherein the annular portion has a width of 0.1 mm to 0.5 mm.
て、 上記ソルダレジスト除去部の幅を０．１ｍｍ〜０．３ｍ
ｍとしたことを特徴とする半導体モジュール。3. The semiconductor module according to claim 1, wherein the solder resist removing portion has a width of 0.1 mm to 0.3 m.
A semiconductor module characterized by having m.
の配線パターンの上をソルダレジストにより保護した配
線基板上に搭載された半導体チップを封止樹脂により封
止する半導体モジュールの樹脂封止方法において、 上記ソルダレジストにより、上記配線基板の配線パター
ンの上に、上記配線基板における上記半導体チップの搭
載される位置の外周を環状に囲むように形成された環状
部と、この環状部の外周においてソルダレジストの除去
されたソルダレジスト除去部とを形成し、 上記環状枠と上記ソルダレジスト除去部との境界部Ｃに
おいては、上記環状枠の上端面と、上記環状枠の側端面
がほぼ垂直に近い断面形状を有し 、上記環状部の内側に 半導体チップを搭載した後、 上記環状部の内側の閉空間に封止樹脂を充填し、上記環
状部と上記ソルダレジスト除去部の境界部までの上記環
状部の内側及び上記環状部の上端面までの領域に封止樹
脂を充填することを特徴とする半導体モジュールの樹脂
封止方法。4. A resin sealing method for a semiconductor module, wherein a wiring pattern is formed on an insulating substrate, and a semiconductor chip mounted on the wiring substrate whose wiring pattern is protected by a solder resist is sealed with a sealing resin. In the wiring pattern of the wiring board,
On the down, the annular portion of the outer periphery is formed so as to surround the annular mounted the position of the semiconductor chip in the wiring substrate, and a solder resist removal portion which is removed in the solder resist in the outer periphery of the annular portion Formed on the boundary C between the annular frame and the solder resist removed portion.
In, the upper end surface of the annular frame and the side end surface of the annular frame
There have substantially almost vertical cross-section, after mounting the semiconductor chip on the inside of the annular portion, filled with a sealing resin in a closed space inside of the annular portion, of the annular portion and the solder resist removal portion The above ring to the boundary
A resin encapsulating method for a semiconductor module, characterized in that an area up to the upper end surface of the annular portion and the inner side of the annular portion is filled with an encapsulating resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29535297A JP3391676B2 (en) | 1997-10-28 | 1997-10-28 | Semiconductor module and resin sealing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29535297A JP3391676B2 (en) | 1997-10-28 | 1997-10-28 | Semiconductor module and resin sealing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH11135685A JPH11135685A (en) | 1999-05-21 |
| JP3391676B2 true JP3391676B2 (en) | 2003-03-31 |
Family
ID=17819508
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29535297A Expired - Fee Related JP3391676B2 (en) | 1997-10-28 | 1997-10-28 | Semiconductor module and resin sealing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3391676B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002164479A (en) * | 2000-11-22 | 2002-06-07 | Niigata Seimitsu Kk | Semiconductor device and method for manufacturing the same |
| JP5511125B2 (en) | 2006-12-27 | 2014-06-04 | キヤノン株式会社 | Semiconductor module and manufacturing method thereof |
| JP7060835B2 (en) * | 2017-09-26 | 2022-04-27 | カシオ計算機株式会社 | Circuit boards, electronic devices, and methods for manufacturing circuit boards |
-
1997
- 1997-10-28 JP JP29535297A patent/JP3391676B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH11135685A (en) | 1999-05-21 |
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