JPH10214924A - Resin sealing structure of semiconductor device - Google Patents
Resin sealing structure of semiconductor deviceInfo
- Publication number
- JPH10214924A JPH10214924A JP1695497A JP1695497A JPH10214924A JP H10214924 A JPH10214924 A JP H10214924A JP 1695497 A JP1695497 A JP 1695497A JP 1695497 A JP1695497 A JP 1695497A JP H10214924 A JPH10214924 A JP H10214924A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- semiconductor element
- wiring board
- spot
- coating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、配線基板上に半導
体素子を搭載し半導体素子周辺をスポットコート樹脂で
封止する構造に関する。The present invention relates to a structure in which a semiconductor element is mounted on a wiring board and the periphery of the semiconductor element is sealed with a spot coat resin.
【0002】[0002]
【従来の技術】現在の半導体素子のスポットコート樹脂
封止構造としては、図6(a)に示すように配線基板1
の上に裸の半導体素子4いわゆるベアチップを搭載し、
半導体素子4の周辺部より配線を金属ワイヤ5で配線基
板1上の配線パターン2に接続した後にスポットコート
樹脂で封止されてなるものである。このような半導体の
樹脂封止構造においては、図6(b)に示すように、適
度の流動性をもつスポットコート樹脂6をシリンジ61
より滴下して該ワイヤ部5を覆い、次に熱硬化処理など
の硬化工程で樹脂封止を完了させている。従来は、この
滴下されたスポットコート樹脂6の滴下量、流動性、被
覆表面の性状により被覆部の拡がり、厚みの諸元を狙い
の範囲に調整しているのが通例であった。2. Description of the Related Art As a current spot-coating resin sealing structure of a semiconductor element, as shown in FIG.
A bare semiconductor element 4 called a bare chip is mounted on the
The wiring is connected to the wiring pattern 2 on the wiring substrate 1 from the peripheral portion of the semiconductor element 4 with the metal wires 5 and then sealed with a spot coat resin. In such a semiconductor resin sealing structure, as shown in FIG. 6B, the spot coat resin 6 having appropriate fluidity is applied to a syringe 61.
The wire portion 5 is further dropped to cover the wire portion 5, and then the resin sealing is completed in a curing step such as a thermosetting treatment. Heretofore, it has been customary to adjust the specifications of the spread portion and the thickness of the spot coat resin 6 to the intended range by the amount of dropping, the flowability, and the properties of the coating surface.
【0003】なお、スポットコート樹脂の硬化工程に先
立って、この配線基板には他の素子たとえば抵抗器など
の部品が既に搭載されている場合がある。Prior to the step of curing the spot coat resin, there may be cases where another element, for example, a component such as a resistor is already mounted on the wiring board.
【0004】[0004]
【発明が解決しようとする課題】ところが、スポットコ
ート樹脂の流動性などのバラツキや配線基板上の部品配
置によって、スポットコート樹脂6が不必要な部分に流
動すると、図6(c)に示すような欠陥を発生するなな
ど品質上の問題を生ずる場合があった。同図Nは流動し
すぎた場合に被覆高さが低くなりワイヤ部5が露出する
部分を指すものであり、被覆するという機能が不完全と
なる場合である。また、同図Kは隣接する電子部品7の
はんだフィレット部8にスポットコート樹脂6が被さる
部分を指すものであり、樹脂の硬化工程以降の後工程で
再度リフロー処理が行われる場合に再溶融したはんだ粒
が硬化したスポットコート樹脂6の隙間より洩れ出る恐
れを生じている。このような再溶融し洩れ出たはんだが
はんだ粒を発生し品質上の欠陥を引き起こす事例は、こ
の半導体素子4を搭載した基板1を、要素回路として搭
載すべく別の基板に組付け、再度はんだ付け工程に通す
際においても経験されている。However, when the spot coat resin 6 flows to an unnecessary portion due to the variation in the fluidity of the spot coat resin and the arrangement of components on the wiring board, as shown in FIG. 6C. In some cases, quality problems such as the occurrence of serious defects may occur. FIG. N shows a portion where the coating height is reduced and the wire portion 5 is exposed when the flow is excessive, and the function of coating is incomplete. FIG. 7K shows a portion where the spot coat resin 6 covers the solder fillet portion 8 of the adjacent electronic component 7 and is re-melted when reflow processing is performed again in a post-process after the resin curing process. There is a possibility that the solder particles may leak out of the gap between the cured spot coat resins 6. In the case where such re-melted and leaked solder generates solder particles and causes quality defects, the substrate 1 on which the semiconductor element 4 is mounted is mounted on another substrate in order to mount it as an element circuit, and then re-assembled. It is also experienced in passing through the soldering process.
【0005】従って、本発明はスポットコート樹脂被覆
が流動するにあたり外周辺への流動を所望の位置で阻止
し、隣接する部品への流動による被さりを防止すること
を目的とする。また、スポットコート6の形状を最小限
の大きさに保持することにより、配線基板の設計に際し
形状バラツキを考慮した余裕代を切り詰めうるので、占
有面積を最小限にでき、設計上の利点や基板コストの節
約に結びつけることを目的とする。SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to prevent the spot coat resin coating from flowing to the outer periphery at a desired position when flowing, and to prevent the adjacent parts from being covered by the flow. Further, by keeping the shape of the spot coat 6 at the minimum size, it is possible to reduce the margin in consideration of the shape variation in the design of the wiring board, so that the occupied area can be minimized, and the design advantage and the substrate The goal is to save money.
【0006】[0006]
【課題を解決するための手段】本発明は、配線基板上に
半導体素子が搭載され、該半導体素子が樹脂で封止され
てなる半導体素子の樹脂封止構造において、前記半導体
素子外周辺に前記配線基板上を保護するレジストが形成
され、該レジストは前記樹脂をはじく材質からなること
を特徴とする。According to the present invention, there is provided a resin sealing structure for a semiconductor device in which a semiconductor element is mounted on a wiring board and the semiconductor element is sealed with a resin. A resist for protecting the wiring substrate is formed, and the resist is made of a material that repels the resin.
【0007】また本発明は、配線基板上に半導体素子が
搭載され、該半導体素子が樹脂で封止されてなる半導体
素子の樹脂封止構造において、前記半導体素子外周辺に
前記配線基板上を保護するレジストが形成され、該レジ
スト上に前記樹脂をはじく材質からなるオイルが枠状に
塗布されてなることを特徴とする。また本発明は、配線
基板上に半導体素子が搭載され、該半導体素子が樹脂で
封止されてなる半導体素子の樹脂封止構造において、前
記半導体素子外周辺に前記配線基板上を保護するレジス
トが形成され、該レジスト上に壁形の固形油脂が枠状に
塗布されてなることを特徴とする。Further, according to the present invention, in a resin sealing structure of a semiconductor element in which a semiconductor element is mounted on a wiring board and the semiconductor element is sealed with a resin, the semiconductor element is protected on the wiring board around the outside of the semiconductor element. A resist is formed, and an oil made of a material that repels the resin is applied on the resist in a frame shape. Further, according to the present invention, in a resin sealing structure of a semiconductor element in which a semiconductor element is mounted on a wiring board and the semiconductor element is sealed with a resin, a resist for protecting the wiring board around the outside of the semiconductor element is provided. It is characterized in that a wall-shaped solid fat is applied in a frame shape on the resist.
【0008】また本発明は、配線基板上に半導体素子が
搭載され、該半導体素子が樹脂で封止されてなる半導体
素子の樹脂封止構造において、前記半導体素子と隣接す
る電子部品に前記樹脂をはじく材質からなるオイルが塗
布されてなることを特徴とする。また本発明は、配線基
板上に半導体素子が搭載され、該半導体素子が樹脂で封
止されてなる半導体素子の樹脂封止構造において、前記
半導体素子外周辺に注型モールドの開口部が接合され、
該注型モールド内に樹脂が注入されてなることを特徴と
する。According to the present invention, in a resin sealing structure of a semiconductor element in which a semiconductor element is mounted on a wiring board and the semiconductor element is sealed with a resin, the resin is applied to an electronic component adjacent to the semiconductor element. It is characterized in that oil made of a repelling material is applied. Further, according to the present invention, in a resin sealing structure of a semiconductor element in which a semiconductor element is mounted on a wiring board and the semiconductor element is sealed with a resin, an opening of a casting mold is joined to an outer periphery of the semiconductor element. ,
A resin is injected into the casting mold.
【0009】[0009]
【実施例】本発明の実施例について、図を用いて説明す
る。図1は、スポットコート樹脂をはじく性質のソルダ
レジストを用いた第1の実施例を示す図である。図1
(a)はスポットコート樹脂被覆前の配置を示す平面
図、(b)はスポットコート樹脂被覆後のA−A断面拡
大図である。11は配線基板であり、12は導電箔から
なる配線パターン、13はソルダレジストであってはん
だが配線パターン12に付着しないための樹脂膜を積層
したものである。ソルダレジスト13は、JCRをはじ
く性質をもつシリコーン樹脂、フッ素樹脂などの樹脂が
使用されており、半導体素子14の外周辺を囲うように
枠状の形態を有している。元々、ソルダレジスト(レジ
スト)はベアチップ等の実装位置を除く基板上に塗布さ
れ該基板上を保護するためのものであるが、本例ではこ
のレジストをスポットコート樹脂をはじく性質のものに
することで、基板保護とスポットコート樹脂の過度の流
動防止を兼用している。An embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a view showing a first embodiment using a solder resist having a property of repelling a spot coat resin. FIG.
(A) is a plan view showing the arrangement before the spot coat resin coating, and (b) is an AA cross-sectional enlarged view after the spot coat resin coating. Reference numeral 11 denotes a wiring board, 12 denotes a wiring pattern made of a conductive foil, and 13 denotes a solder resist, which is formed by laminating a resin film for preventing solder from adhering to the wiring pattern 12. The solder resist 13 is made of a resin such as a silicone resin or a fluorine resin having a property of repelling JCR, and has a frame shape so as to surround the outer periphery of the semiconductor element 14. Originally, the solder resist (resist) is applied on the substrate except for the mounting position of the bare chip or the like to protect the substrate. In this example, the resist is made to have a property of repelling the spot coat resin. Thus, the substrate is used for both protecting the substrate and preventing excessive flow of the spot coat resin.
【0010】14は半導体素子であって通常ベアチップ
とよばれる。15は金属ワイヤであって、半導体素子1
4の電極部より前記配線パターンへの接続に用いられ
る。16はスポットコート樹脂であって例えばエポキシ
樹脂からなり、金属ワイヤ15および半導体素子14を
その被覆によって外部より絶縁するものである。まず、
粘性のある液体であるスポットコート樹脂16は、図1
では図示されていないシリンジより半導体素子14上に
滴下され、配線基板上に流動しながら拡がり、スポット
コート樹脂16が図1(a)に示されたソルダレジスト
13の枠に達すると、スポットコート樹脂16をはじく
性質を有しているソルダレジスト13の表面張力により
はじかれて、(b)に示されたようにソルダレジスト上
への流動が阻止される。スポットコート樹脂16の厚み
は、例えば約2mmであり半導体素子24の厚み約0.6 m
m、金属ワイヤ15の高さ約0.6 mmおよび被覆厚み約0.4
mmの合計を充たすものとされている。従って、このス
ポットコート樹脂16である約2mm厚の粘性のある液状
樹脂の流動がソルダレジスト13に接した位置ではじか
れて阻止される。Reference numeral 14 denotes a semiconductor element, which is usually called a bare chip. Reference numeral 15 denotes a metal wire, and the semiconductor element 1
4 is used for connection from the electrode portion to the wiring pattern. Reference numeral 16 denotes a spot coat resin, which is made of, for example, an epoxy resin, and insulates the metal wire 15 and the semiconductor element 14 from the outside by covering them. First,
The spot coat resin 16 which is a viscous liquid is shown in FIG.
When the spot coat resin 16 reaches the frame of the solder resist 13 shown in FIG. 1A, the spot coat resin is dropped from the syringe (not shown) onto the semiconductor element 14 and spreads while flowing on the wiring board. 16 is repelled by the surface tension of the solder resist 13 having the property of repelling, and the flow onto the solder resist is prevented as shown in FIG. The thickness of the spot coat resin 16 is, for example, about 2 mm, and the thickness of the semiconductor element 24 is about 0.6 m.
m, the height of the metal wire 15 is about 0.6 mm, and the coating thickness is about 0.4 mm.
mm. Accordingly, the flow of the viscous liquid resin having a thickness of about 2 mm, which is the spot coat resin 16, is repelled and stopped at the position in contact with the solder resist 13.
【0011】次に、スポットコート樹脂16は樹脂の硬
化反応処理を加えられて、樹脂封止処理が完了される。
本例によれば、特別にスペースが増えることもなく、過
度の流動を防止できる効果がある。図2は、スポットコ
ート樹脂をはじく性質の粘性を有するオイルの枠による
第2の実施例を示す図である。Next, the spot coat resin 16 is subjected to a resin curing reaction process, and the resin sealing process is completed.
According to this example, there is an effect that excessive flow can be prevented without particularly increasing the space. FIG. 2 is a view showing a second embodiment using an oil frame having a viscosity that repels a spot coat resin.
【0012】図2(a)はスポットコート樹脂被覆前の
配置を示す平面図、(b)はスポットコート樹脂被覆後
のA−A断面拡大図である。図1と同様に、21は配線
基板部、22は配線パターン、23はソルダレジストで
ある。また、24は半導体素子、25は金属ワイヤ、2
6はスポットコート樹脂である。27はスポットコート
樹脂をはじく性質のオイルの枠であって、ソルダレジス
ト23の上に厚さ約0.1 mmで塗布されており、滴下され
たスポットコート樹脂26の粘性のある液状樹脂の流動
はオイルの枠に接した位置ではじかれて阻止される。オ
イル27としては、スポットコート樹脂26をはじく性
質をもつシリコーンまたはフッ素樹脂系の油が使用され
ている。また、油なので特に洗浄で除去可能である。
尚、特にソルダレジスト23を設けなくともオイルの枠
のみを半導体素子24の外周辺にて所望の位置に塗布す
るようにしてもよい。FIG. 2A is a plan view showing the arrangement before the spot coat resin coating, and FIG. 2B is an enlarged cross-sectional view taken along the line AA after the spot coat resin coating. As in FIG. 1, 21 is a wiring board portion, 22 is a wiring pattern, and 23 is a solder resist. 24 is a semiconductor element, 25 is a metal wire, 2
6 is a spot coat resin. Reference numeral 27 denotes an oil frame having a property of repelling the spot coat resin, which is applied on the solder resist 23 with a thickness of about 0.1 mm. The flow of the viscous liquid resin of the dropped spot coat resin 26 is oil. It is repelled and stopped at the position in contact with the frame. As the oil 27, a silicone or fluororesin-based oil having a property of repelling the spot coat resin 26 is used. Since it is oil, it can be removed particularly by washing.
Incidentally, only the oil frame may be applied to a desired position on the outer periphery of the semiconductor element 24 without providing the solder resist 23 in particular.
【0013】次に、スポットコート樹脂26は樹脂の硬
化反応処理を加えられて、樹脂封止処理が完了される。
本例によれば、樹脂封止後油を洗浄すれば余分な構成品
を基板上に残さないようにできる。図3は、ワックス
(固形油脂)の枠による第3の実施例を示す図である。
図3(a)はスポットコート樹脂被覆前の配置を示す平
面図、(b)はスポットコート樹脂被覆後のA−A断面
拡大図である。31は配線基板部、32は配線パター
ン、33はソルダレジストである。また、34は半導体
素子、35は金属ワイヤ、36はスポットコート樹脂で
ある。37はスポットコート樹脂をはじく性質のワック
スを塗布した枠であって、ソルダレジスト33の上に厚
さ約0.7 mmで塗布されており、これにより壁をつくり滴
下されたスポットコート樹脂36の粘性のある液状樹脂
の流動はワックスの枠37に接した位置でせき止められ
て阻止される。このワックス37は、後工程の洗浄で除
去できる性質をもつアピエゾンワックスを用いている。
尚、本例のワックスはスポットコートをはじかない材質
のため、第1、2の実施例よりも枠の厚みを高く設けて
いる。Next, the spot coating resin 26 is subjected to a resin curing reaction process, and the resin sealing process is completed.
According to this example, if the oil is washed after the sealing with the resin, it is possible to prevent extra components from remaining on the substrate. FIG. 3 is a view showing a third embodiment using a wax (solid fat) frame.
FIG. 3A is a plan view showing the arrangement before the spot coat resin coating, and FIG. 3B is an enlarged cross-sectional view taken along the line AA after the spot coat resin coating. 31 is a wiring board part, 32 is a wiring pattern, and 33 is a solder resist. 34 is a semiconductor element, 35 is a metal wire, and 36 is a spot coat resin. Reference numeral 37 denotes a frame to which a wax having a property of repelling the spot coat resin is applied, which is applied with a thickness of about 0.7 mm on the solder resist 33, thereby forming a wall and forming a viscous liquid of the spot coat resin 36 dropped. The flow of a certain liquid resin is blocked and stopped at a position in contact with the wax frame 37. As the wax 37, apiezone wax having a property that can be removed by washing in a later step is used.
Since the wax of this embodiment does not repel the spot coat, the thickness of the frame is set higher than that of the first and second embodiments.
【0014】次に、スポットコート樹脂36は樹脂の硬
化反応処理を加えられ、ワックスが除去処理され、樹脂
封止処理が完了する。本例によれば、樹脂硬化後不用に
なったワックスを除去できるので、配線基板上から余分
なものをなくすという特有の効果を奏する。図4は、半
導体素子外周辺に搭載する電子部品とそのフィレットが
スポットコート樹脂により被覆されないための保護層を
形成する粘性を有するオイルを塗布した第4の実施例を
示す図である。Next, the spot coat resin 36 is subjected to a curing reaction of the resin, the wax is removed, and the resin sealing process is completed. According to this example, since the wax that has become unnecessary after the curing of the resin can be removed, a special effect is achieved in that there is no extra material on the wiring board. FIG. 4 is a diagram showing a fourth embodiment in which an electronic component mounted around the outside of the semiconductor element and a viscous oil for forming a protective layer for preventing the fillet from being covered with the spot coat resin are applied.
【0015】図4(a)はスポットコート樹脂被覆前の
配置を示す平面図、(b)はスポットコート樹脂被覆後
のA−A断面拡大図である。41は配線基板部、42は
配線パターン、43はソルダレジストである。また、4
4は半導体素子、45は金属ワイヤ、46はスポットコ
ート樹脂である。47は、同じ配線基板41上に半導体
素子44に隣接して搭載された抵抗器などの電子部品で
ある。48は、電子部品47のはんだ接続部のフィレッ
トである。49は、電子部品47およびフィレット48
をスポットコート樹脂46から保護するため塗布される
オイルである。滴下されたスポットコート樹脂46の粘
性のある液状樹脂の流動は、このオイルに接した位置で
はじかれて阻止され、電子部品47およびフィレット4
8がスポットコート樹脂46によって被覆されることを
防止できる。なお、オイルは図2で前記のものに同じで
ある。FIG. 4A is a plan view showing the arrangement before the spot coat resin coating, and FIG. 4B is an enlarged cross-sectional view taken along the line AA after the spot coat resin coating. 41 is a wiring board part, 42 is a wiring pattern, and 43 is a solder resist. Also, 4
4 is a semiconductor element, 45 is a metal wire, and 46 is a spot coat resin. Reference numeral 47 denotes an electronic component such as a resistor mounted on the same wiring board 41 adjacent to the semiconductor element 44. Reference numeral 48 denotes a fillet of a solder connection portion of the electronic component 47. 49 denotes an electronic component 47 and a fillet 48
Is an oil that is applied to protect from the spot coat resin 46. The flow of the viscous liquid resin of the dropped spot coat resin 46 is repelled and stopped at the position in contact with the oil, and the electronic component 47 and the fillet 4 are prevented from flowing.
8 can be prevented from being covered with the spot coat resin 46. The oil is the same as that described above in FIG.
【0016】次に、スポットコート樹脂46は樹脂の硬
化反応処理を加えられて、樹脂封止処理が完了する。
尚、特にソルダレジスト43を設けなくともオイル49
を電子部品47およびフィレット48周辺の所望の位置
に塗布するようにしてもよい。図5は、注型モールドを
用いた第5の実施例を示す図である。図5(a)は第1
例の注型モールドを用いた断面図、(b)は第2例の注
型モールドを用いた断面図である。Next, the spot coating resin 46 is subjected to a resin curing reaction process, and the resin sealing process is completed.
Incidentally, even if the solder resist 43 is not provided, the oil 49 is not required.
May be applied to desired positions around the electronic component 47 and the fillet 48. FIG. 5 is a view showing a fifth embodiment using a casting mold. FIG. 5A shows the first
FIG. 4B is a cross-sectional view using the casting mold of the example, and FIG. 4B is a cross-sectional view using the casting mold of the second example.
【0017】51は配線基板部、52は配線パターン、
53はソルダレジスト、54は半導体素子、55は金属
ワイヤ、56及び58はスポットコート樹脂である。5
7はその下面開口部が口の字状を有する注型モールドで
ある。(b)に示す591は注型モールド内の開口部を
横断する連結桿である。両例とも、注型モールド下面を
半導体素子の外周辺を囲うようにソルダレジスト53上
に当接させる。Reference numeral 51 denotes a wiring board, 52 denotes a wiring pattern,
53 is a solder resist, 54 is a semiconductor element, 55 is a metal wire, and 56 and 58 are spot coat resins. 5
Reference numeral 7 denotes a casting mold whose lower surface opening has a shape of a mouth. Reference numeral 591 shown in (b) denotes a connecting rod that crosses the opening in the casting mold. In both cases, the lower surface of the casting mold is brought into contact with the solder resist 53 so as to surround the outer periphery of the semiconductor element.
【0018】図5(a)に示した実施例では、注型モー
ルド57はシェルの中央に開口をもち、開口部よりスポ
ットコート樹脂56を滴下して注型する。注型モールド
57を、被覆の必要な位置に接して注型するため、正確
な形状、寸法精度が得られる。また、(b)に示した実
施例では、注型モールド59は注型モールドのシェル外
周と中央部との間に開口をもち、開口部の複数位置より
スポットコート樹脂58を滴下して注型することができ
る。そのため、スポットコート樹脂58の流動性に応じ
た調整が容易となる。なお、注型モールド59のシェル
外周と中央部との間は、連結桿591で繋がれている。In the embodiment shown in FIG. 5A, the casting mold 57 has an opening at the center of the shell, and the spot coat resin 56 is dropped from the opening to perform casting. Since the casting mold 57 is cast in contact with the position where the coating is required, accurate shape and dimensional accuracy can be obtained. In the embodiment shown in (b), the casting mold 59 has an opening between the outer periphery and the center of the shell of the casting mold, and the spot coating resin 58 is dropped from a plurality of positions of the opening. can do. Therefore, adjustment according to the fluidity of the spot coat resin 58 is facilitated. The outer periphery and the center of the shell of the casting mold 59 are connected by a connecting rod 591.
【0019】次に、スポットコート樹脂58は注型モー
ルドを被せたまま、またはある程度スポットコート樹脂
58を仮硬化させてから注型モールドを取り外した後に
樹脂の硬化処理が加えられ、樹脂封止が完了される。本
例によれば樹脂硬化後不用になった注型モールドを除去
できるので配線基板上の余分なものをなくすことができ
るという特有の効果を奏する。Next, after the spot coat resin 58 is covered with the casting mold, or after the spot coating resin 58 is temporarily cured to some extent, the casting mold is removed, and then the resin is subjected to a curing treatment, whereby the resin sealing is performed. Completed. According to the present example, since the casting mold that has become unnecessary after the resin is cured can be removed, there is a specific effect that an unnecessary thing on the wiring board can be eliminated.
【0020】[0020]
【発明の効果】以上詳細に説明したように、本発明によ
れば樹脂被覆の範囲を適正な形状に保持して、樹脂硬化
処理を行うことにより、樹脂の流動を阻止して樹脂被覆
に関する欠陥発生を防止する。また、スポットコート樹
脂を最小範囲に収めることが可能となる。As described above in detail, according to the present invention, by maintaining the range of the resin coating in an appropriate shape and performing the resin curing treatment, the flow of the resin is prevented and the defect relating to the resin coating is prevented. Prevent occurrence. In addition, the spot coat resin can be kept within the minimum range.
【図1】第1の実施例を示す図であって、(a)はスポ
ットコート樹脂被覆前の平面図、(b)はスポットコー
ト樹脂被覆後のA−A断面拡大図である。FIGS. 1A and 1B are diagrams showing a first embodiment, wherein FIG. 1A is a plan view before coating with a spot coat resin, and FIG. 1B is an enlarged cross-sectional view taken along the line AA after coating with a spot coat resin.
【図2】第2の実施例を示す図であって、(a)はスポ
ットコート樹脂被覆前の平面図、(b)はスポットコー
ト樹脂被覆後のA−A断面拡大図である。FIGS. 2A and 2B are diagrams showing a second embodiment, in which FIG. 2A is a plan view before coating with a spot coat resin, and FIG.
【図3】第3の実施例を示す図であって、(a)はスポ
ットコート樹脂被覆前の平面図、(b)はスポットコー
ト樹脂被覆後のA−A断面拡大図である。FIGS. 3A and 3B are views showing a third embodiment, in which FIG. 3A is a plan view before coating with a spot coat resin, and FIG.
【図4】第4の実施例を示す図であって、(a)はスポ
ットコート樹脂被覆前の平面図、(b)はスポットコー
ト樹脂被覆後のA−A断面拡大図である。4A and 4B are diagrams showing a fourth embodiment, in which (a) is a plan view before coating with a spot coat resin, and (b) is an enlarged cross-sectional view along AA after coating with a spot coat resin.
【図5】第5の実施例を示す図であって、(a)は第1
例の注型モールドを示す断面図、(b)は第2例の注型
モールドを示す断面図である。FIGS. 5A and 5B show a fifth embodiment, in which FIG.
FIG. 7B is a cross-sectional view illustrating an example casting mold, and FIG. 8B is a cross-sectional view illustrating a second example casting mold.
【図6】従来例を示す図であって、(a)はスポットコ
ート樹脂被覆前の平面図、(b)はスポットコート樹脂
被覆後の断面図、(c)はスポットコート樹脂被覆後の
欠陥事例のA−A断面拡大図である。6A and 6B are views showing a conventional example, wherein FIG. 6A is a plan view before spot coating resin coating, FIG. 6B is a cross-sectional view after spot coating resin coating, and FIG. 6C is a defect after spot coating resin coating. It is an AA sectional enlarged view of a case.
11・・・配線基板 12・・・配線パターン 13・・・ソルダレジスト 14・・・半導体素子 15・・・金属ワイヤ 16・・・スポットコート樹脂 27・・・オイル 37・・・ワックス 47・・・電子部品 48・・・フィレット 57、59・・・注型モールド 591・・・注型モールド連結桿 DESCRIPTION OF SYMBOLS 11 ... Wiring board 12 ... Wiring pattern 13 ... Solder resist 14 ... Semiconductor element 15 ... Metal wire 16 ... Spot coat resin 27 ... Oil 37 ... Wax 47 ...・ Electronic components 48 ・ ・ ・ Fillet 57, 59 ・ ・ ・ Cast mold 591 ・ ・ ・ Cast mold connecting rod
Claims (5)
半導体素子が樹脂で封止されてなる半導体素子の樹脂封
止構造において、 前記半導体素子外周辺に前記配線基板上を保護するレジ
ストが形成され、該レジストは前記樹脂をはじく材質か
らなることを特徴とする半導体素子の樹脂封止構造。In a resin sealing structure of a semiconductor element in which a semiconductor element is mounted on a wiring board and the semiconductor element is sealed with a resin, a resist for protecting the wiring board is provided around the outside of the semiconductor element. A resin sealing structure for a semiconductor element, wherein the resist is formed of a material repelling the resin.
半導体素子が樹脂で封止されてなる半導体素子の樹脂封
止構造において、 前記半導体素子外周辺に前記配線基板上を保護するレジ
ストが形成され、該レジスト上に前記樹脂をはじく材質
からなるオイルが枠状に塗布されてなることを特徴とす
る半導体素子の樹脂封止構造。2. In a resin sealing structure of a semiconductor element in which a semiconductor element is mounted on a wiring board and the semiconductor element is sealed with a resin, a resist for protecting the wiring board around the outside of the semiconductor element is provided. A resin sealing structure for a semiconductor element, wherein an oil formed of a material that repels the resin is applied on the resist in a frame shape.
半導体素子が樹脂で封止されてなる半導体素子の樹脂封
止構造において、 前記半導体素子外周辺に前記配線基板上を保護するレジ
ストが形成され、該レジスト上に壁形の固形油脂が枠状
に塗布されてなることを特徴とする半導体素子の樹脂封
止構造。3. A resin sealing structure for a semiconductor element in which a semiconductor element is mounted on a wiring board and the semiconductor element is sealed with a resin, wherein a resist for protecting the wiring board is provided around the outside of the semiconductor element. A resin sealing structure for a semiconductor element, wherein a wall-shaped solid fat or oil is applied on the resist in a frame shape.
半導体素子が樹脂で封止されてなる半導体素子の樹脂封
止構造において、 前記半導体素子と隣接する電子部品に前記樹脂をはじく
材質からなるオイルが塗布されてなることを特徴とする
半導体素子の樹脂封止構造。4. A resin sealing structure for a semiconductor element in which a semiconductor element is mounted on a wiring board and the semiconductor element is sealed with a resin, wherein the electronic component adjacent to the semiconductor element is made of a material that repels the resin. A resin sealing structure for a semiconductor element, characterized by being coated with an oil.
半導体素子が樹脂で封止されてなる半導体素子の樹脂封
止構造において、 前記半導体素子外周辺に注型モールドの開口部が接合さ
れ、該注型モールド内に樹脂が注入されてなることを特
徴とする半導体素子の樹脂封止構造。5. In a resin sealing structure of a semiconductor element in which a semiconductor element is mounted on a wiring board and the semiconductor element is sealed with a resin, an opening of a casting mold is joined to an outer periphery of the semiconductor element. A resin sealing structure for a semiconductor element, wherein a resin is injected into the casting mold.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1695497A JPH10214924A (en) | 1997-01-30 | 1997-01-30 | Resin sealing structure of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1695497A JPH10214924A (en) | 1997-01-30 | 1997-01-30 | Resin sealing structure of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH10214924A true JPH10214924A (en) | 1998-08-11 |
Family
ID=11930515
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1695497A Withdrawn JPH10214924A (en) | 1997-01-30 | 1997-01-30 | Resin sealing structure of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH10214924A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6605864B2 (en) | 2000-07-07 | 2003-08-12 | Infineon Technologies Ag | Support matrix for integrated semiconductors, and method for producing it |
US6979887B2 (en) | 2000-07-07 | 2005-12-27 | Infineon Technologies Ag | Support matrix with bonding channel for integrated semiconductors, and method for producing it |
JP2011096755A (en) * | 2009-10-28 | 2011-05-12 | Kyocera Corp | Substrate for mounting electronic component |
CN114324072A (en) * | 2022-01-17 | 2022-04-12 | 四川大学 | Method for measuring surface tension coefficient of liquid by thin plate method |
-
1997
- 1997-01-30 JP JP1695497A patent/JPH10214924A/en not_active Withdrawn
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6605864B2 (en) | 2000-07-07 | 2003-08-12 | Infineon Technologies Ag | Support matrix for integrated semiconductors, and method for producing it |
US6979887B2 (en) | 2000-07-07 | 2005-12-27 | Infineon Technologies Ag | Support matrix with bonding channel for integrated semiconductors, and method for producing it |
JP2011096755A (en) * | 2009-10-28 | 2011-05-12 | Kyocera Corp | Substrate for mounting electronic component |
CN114324072A (en) * | 2022-01-17 | 2022-04-12 | 四川大学 | Method for measuring surface tension coefficient of liquid by thin plate method |
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