JP2705566B2 - Method for manufacturing semiconductor integrated circuit device - Google Patents

Method for manufacturing semiconductor integrated circuit device

Info

Publication number
JP2705566B2
JP2705566B2 JP6077890A JP7789094A JP2705566B2 JP 2705566 B2 JP2705566 B2 JP 2705566B2 JP 6077890 A JP6077890 A JP 6077890A JP 7789094 A JP7789094 A JP 7789094A JP 2705566 B2 JP2705566 B2 JP 2705566B2
Authority
JP
Japan
Prior art keywords
mounting
bare chip
substrate
frame
semiconductor bare
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP6077890A
Other languages
Japanese (ja)
Other versions
JPH07263617A (en
Inventor
利比古 吉村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP6077890A priority Critical patent/JP2705566B2/en
Publication of JPH07263617A publication Critical patent/JPH07263617A/en
Application granted granted Critical
Publication of JP2705566B2 publication Critical patent/JP2705566B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/181Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は半導体集積回路装置の製
造方法に関し、特に半導体ベアチップと表面実装部品と
を同一基板上に混載状態に搭載する半導体集積回路装置
の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor integrated circuit device, and more particularly to a method of manufacturing a semiconductor integrated circuit device in which a semiconductor bare chip and a surface mount component are mounted in a mixed state on the same substrate.

【0002】[0002]

【従来の技術】従来、半導体ベアチップを基板上に実装
するCOB構造と、チップ抵抗やチップコンデンサ等の
表面実装部品を基板上に実装するSMT構造とが混在す
る半導体集積回路装置の製造に際しては、特に電気的な
信頼性を確保する必要があるCOB構造に対してSMT
構造の実装が悪影響を与えないような配慮が要求され
る。
2. Description of the Related Art Conventionally, when manufacturing a semiconductor integrated circuit device in which a COB structure in which a semiconductor bare chip is mounted on a substrate and an SMT structure in which surface mounting components such as chip resistors and chip capacitors are mounted on the substrate, are mixed. Especially for COB structures that need to ensure electrical reliability, SMT
Care must be taken to ensure that the implementation of the structure does not have any adverse effects.

【0003】この場合、COB工程とSMT工程のいず
れを先に行うかで特に半田工程に違いが生じている。例
えば、先にCOB工程を行う場合には、基板に半導体ベ
アチップを搭載したCOB工程の後に、SMTの実装時
にCOB構造に半田等による温度の悪影響を与えること
がないように、基板の回路部分にディスペンサを使用し
て半田をSMT領域に塗布し、その後に表面実装部品を
搭載してSMT工程を行っている。
[0003] In this case, there is a difference particularly in the soldering process depending on whether the COB process or the SMT process is performed first. For example, when the COB process is performed first, after the COB process in which the semiconductor bare chip is mounted on the substrate, the circuit portion of the substrate is so formed that the temperature of the COB structure is not adversely affected by solder or the like when the SMT is mounted. Solder is applied to the SMT area using a dispenser, and thereafter, the SMT process is performed by mounting a surface mount component.

【0004】或いは、COB工程の後に、特殊形状の半
田マスクを使用してSMT領域にのみ半田を印刷し、そ
の後に表面実装部品を搭載してSMT工程を行ってい
る。このような製造方法の例として、特開昭61−97
893号公報に記載されたものがある。この公報の方法
では、先に実装されたCOBに相当する部分と半田印刷
する部分に窓を設けたマスクを利用し、このマスクのC
OBに相当する部分を可撓性の膜で覆った状態で半田印
刷を行っている。これにより、COBの信頼性を損なう
ことなくSMTを可能とするものである。
Alternatively, after the COB process, solder is printed only in the SMT region using a specially shaped solder mask, and thereafter, the SMT process is performed by mounting surface mount components. Japanese Patent Application Laid-Open No. 61-97 discloses an example of such a manufacturing method.
No. 893. In the method of this publication, a mask provided with a window in a portion corresponding to the previously mounted COB and a portion to be printed with solder is used.
Solder printing is performed in a state where a portion corresponding to OB is covered with a flexible film. Thus, SMT can be performed without impairing the reliability of the COB.

【0005】一方、先にSMT工程を行う場合には、表
面実装部品を実装するために高効率なリフロー方法が採
用でき、かつその際にもCOB構造に対する影響は生じ
ないが、このリフロー工程によってCOB構造領域が汚
染されるため、COB構造領域の洗浄を行った上でCO
B工程を行っている。
On the other hand, when the SMT process is performed first, a high-efficiency reflow method can be adopted for mounting the surface mount components, and the COB structure is not affected at this time. Since the COB structure area is contaminated, the COB structure area is cleaned and then the COB structure area is cleaned.
Step B is performed.

【0006】[0006]

【発明が解決しようとする課題】しかしながら、ディス
ペンサによる半田塗布方法では、半田の塗布量を均一に
管理することが難しいため、微細なチップ部品を実装す
る際に、半田量が多いとチップ部品が半田と共に流動さ
れてしまい、また半田量が少ないと信頼性のある実装が
できないという問題がある。また、前記公報に記載され
ているような半田マスクによる印刷方法では、微細な多
数のチップ部品に対応する窓を開設してマスクを製造す
る工程が極めて煩雑なものとなる上に、基板に対するマ
スクの位置合わせに高精度が要求され、高密度に実装す
る半導体集積回路装置の製造が難しいという問題があ
る。
However, in the solder application method using a dispenser, it is difficult to uniformly control the amount of solder to be applied. There is a problem in that it flows together with the solder, and if the amount of solder is small, reliable mounting cannot be performed. Further, in a printing method using a solder mask as described in the above-mentioned publication, a process of opening a window corresponding to a large number of fine chip components and manufacturing a mask becomes extremely complicated, and a mask for a substrate is also required. There is a problem that high precision is required for the alignment of the semiconductor integrated circuit, and it is difficult to manufacture a semiconductor integrated circuit device mounted at high density.

【0007】また、先にSMTを行う工程では、COB
構造に対する影響は回避できるが、COB実装領域を清
浄する工程が必要とされ、この清浄の管理が煩雑で複雑
な工程が必要とされるため、製造効率が悪いという問題
がある。
In the step of performing SMT first, COB
Although the influence on the structure can be avoided, there is a problem that a step of cleaning the COB mounting area is required, and the management of the cleaning is complicated and a complicated step is required.

【0008】[0008]

【発明の目的】本発明の目的は、COB構造に対するS
MT工程の影響を回避し、COB構造の信頼性を高めた
半導体集積回路装置の製造方法を提供することにある。
また、本発明の他の目的は、SMT工程を簡略化し、特
に半田層の形成及び半田付け工程の容易化を可能にした
製造方法を提供する。更に、本発明の目的は、COB実
装領域の清浄を不要にして製造の容易化及び製造効率の
向上を図った製造方法を提供することにある。
OBJECTS OF THE INVENTION It is an object of the present invention to provide an
An object of the present invention is to provide a method of manufacturing a semiconductor integrated circuit device in which the influence of the MT process is avoided and the reliability of the COB structure is improved.
Another object of the present invention is to provide a manufacturing method which simplifies the SMT process, and particularly enables the formation of the solder layer and the simplification of the soldering process. It is a further object of the present invention to provide a manufacturing method in which the cleaning of the COB mounting area is not required and the manufacturing is facilitated and the manufacturing efficiency is improved.

【0009】[0009]

【課題を解決するための手段】本発明の製造方法は、基
板に半田を印刷する工程と、その基板にSMT部品を搭
載しかつCOB実装領域に保護枠を搭載してCOB実装
領域の基板表面を被覆する工程と、リフロー法によりS
MT部品を半田付けする工程と、保護枠を除去して基板
表面を露呈させ、この露呈面にCOB部品を実装する工
程とを含んでいる。
A manufacturing method according to the present invention comprises a step of printing solder on a substrate, a step of mounting an SMT component on the substrate, and a step of mounting a protective frame in the COB mounting area. Coating step and S by a reflow method.
It includes a step of soldering the MT component and a step of removing the protective frame to expose the substrate surface and mounting the COB component on the exposed surface.

【0010】また、本発明の製造方法は、基板に半田を
印刷する工程と、その基板にSMT部品を搭載しかつC
OB実装領域に保護枠を搭載してCOB実装領域の基板
表面を被覆する工程と、リフロー法によりSMT部品を
半田付けする工程と、保護枠の一部を除去して保護枠の
内部に基板表面を露呈させ、この露呈面にCOB部品を
実装する工程と、保護枠内に樹脂を充填してCOB部品
を樹脂封止する工程とを含んでいる。
The manufacturing method of the present invention comprises the steps of printing solder on a substrate, mounting an SMT component on the substrate, and
A step of mounting a protective frame in the OB mounting area to cover the substrate surface in the COB mounting area, a step of soldering the SMT components by the reflow method, and a step of removing a part of the protective frame and placing the substrate surface inside the protective frame. And a step of mounting the COB component on the exposed surface, and a step of filling the protective frame with resin and sealing the COB component with resin.

【0011】ここで、保護枠は、COB実装領域を囲む
枠体と、この枠体の上面を覆う耐熱シートと、前記枠体
を基板表面に接着させる接着テープとで構成され、SM
T部品の半田付け時には耐熱シートでCOB実装領域を
被覆し、SMT部品を実装した後に前記耐熱シートを剥
がしてCOB実装領域を露呈させる手法が採用される。
また、樹脂封止用の樹脂は、COB部品を覆う高さまで
保護枠の枠体内に滴下させて樹脂封止を行っている。
Here, the protective frame is composed of a frame surrounding the COB mounting area, a heat-resistant sheet covering the upper surface of the frame, and an adhesive tape for bonding the frame to the surface of the substrate.
At the time of soldering the T component, a method is used in which the COB mounting region is covered with a heat-resistant sheet, and after mounting the SMT component, the heat-resistant sheet is peeled off to expose the COB mounting region.
Further, the resin for resin sealing is dropped into the frame of the protective frame to a height covering the COB component to perform resin sealing.

【0012】[0012]

【作用】本発明の製造方法では、COB実装領域を保護
枠で保護した状態でSMT実装工程を行なうため、保護
枠を搭載する以外は従来のSMT実装工程と同様に容易
に行うことができ、かつこのSMT実装工程の間、CO
B実装領域は保護枠によって保持されるため、その汚染
が防止され、かつその清浄工程が不要とされる。
According to the manufacturing method of the present invention, the SMT mounting step is performed in a state where the COB mounting area is protected by the protection frame. Therefore, except for mounting the protection frame, the SMT mounting step can be easily performed similarly to the conventional SMT mounting step. And, during this SMT mounting process, CO
Since the B mounting area is held by the protective frame, the contamination is prevented and the cleaning step is not required.

【0013】また、本発明の製造方法では、COB構造
を封止するための樹脂封止工程では、保護枠により封止
樹脂の外形が拘束されるため、樹脂が周囲のSMT実装
領域にまで流動されることがなく、封止樹脂の外形寸法
及びその高さ寸法を高精度に管理でき、信頼性の高い封
止構造が得られる。
In the manufacturing method of the present invention, in the resin sealing step for sealing the COB structure, since the outer shape of the sealing resin is restricted by the protective frame, the resin flows to the surrounding SMT mounting area. The external dimensions and the height of the sealing resin can be managed with high accuracy without any need for the sealing resin, and a highly reliable sealing structure can be obtained.

【0014】[0014]

【実施例】次に、本発明の実施例を図面を参照して説明
する。図1は本発明の製造方法の第1実施例を工程順に
示す図である。先ず、同図(a)のように、有機絶縁基
板の表面に所要の導電膜パターンが形成され、かつその
COB及びSMTの各部品を搭載する個所を除いて絶縁
被膜で被覆された回路基板11に半田印刷を行う。この
い半田印刷としては、例えば半田ペースト膜を有する半
田シート12を回路基板11上に載せ、その上からヘッ
ド13を回路基板11に押圧させることで、半田ペース
トを回路基板11の表面に所要パターンで印刷する方法
が採用できる。しかる上で、同図(b)のように、SM
T部品14を回路基板11の表面上の所要個所に搭載す
る。このとき、回路基板11上のCOB実装領域には保
護枠15を搭載する。
Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing a first embodiment of the manufacturing method of the present invention in the order of steps. First, as shown in FIG. 1A, a circuit board 11 in which a required conductive film pattern is formed on the surface of an organic insulating substrate and is covered with an insulating coating except for parts where COB and SMT components are mounted. Perform solder printing. In this solder printing, for example, a solder sheet 12 having a solder paste film is placed on the circuit board 11 and a head 13 is pressed against the circuit board 11 from above, so that the solder paste is applied to the surface of the circuit board 11 in a required pattern. Can be adopted. Then, as shown in FIG.
The T component 14 is mounted at a required position on the surface of the circuit board 11. At this time, the protection frame 15 is mounted on the COB mounting area on the circuit board 11.

【0015】この保護枠15は図2及び図3に斜視図と
断面図を示すように、実装する半導体ベアチップ及びそ
の周囲に配置されるボンディング領域を含む縦横寸法
で、半導体ベアチップを実装したときの最大高さよりも
高い寸法の矩形をした枠体151と、この枠体151の
上面に張設された耐熱シート152と、枠体151の下
面に貼着された両面テープ153とで構成されており、
この両面テープ153により回路基板11の表面上に接
着固定される。
As shown in perspective and sectional views in FIGS. 2 and 3, the protective frame 15 has a vertical and horizontal dimension including a semiconductor bare chip to be mounted and a bonding area disposed around the semiconductor bare chip. The frame 151 includes a rectangular frame 151 having a dimension higher than the maximum height, a heat-resistant sheet 152 stretched over the upper surface of the frame 151, and a double-sided tape 153 attached to the lower surface of the frame 151. ,
The double-sided tape 153 is bonded and fixed on the surface of the circuit board 11.

【0016】しかる上で、図1(c)のように、回路基
板11をリフロー炉16に通し、印刷した半田を溶融さ
せてSMT部品14を回路基板11に半田付けして実装
を行う。次いで、同図(d)のように、保護枠15を回
路基板11から除去し、保護枠15で覆われていた回路
基板11のCOB実装領域を露呈させる。そして、
(e)のように、このCOB実装領域に半導体ベアチッ
プ17を搭載する。この搭載には導電性接着剤や金属ロ
ー材等が用いられる。そして、図4に拡大図示するよう
に、搭載された半導体ベアチップ17と回路基板11の
導電膜パターンとをボンディングワイヤ18により電気
接続する。しかる後、半導体ベアチップ17上に封止用
の樹脂19を滴下させ、半導体ベアチップ17及びボン
ディングワイヤ18を樹脂19により封止させる。
Then, as shown in FIG. 1 (c), the circuit board 11 is passed through a reflow furnace 16, the printed solder is melted, and the SMT component 14 is soldered to the circuit board 11 for mounting. Next, as shown in FIG. 3D, the protection frame 15 is removed from the circuit board 11 to expose the COB mounting area of the circuit board 11 covered by the protection frame 15. And
As shown in (e), the semiconductor bare chip 17 is mounted on the COB mounting area. For this mounting, a conductive adhesive, a metal brazing material, or the like is used. Then, as shown in an enlarged view in FIG. 4, the mounted semiconductor bare chip 17 and the conductive film pattern of the circuit board 11 are electrically connected by bonding wires 18. Thereafter, a sealing resin 19 is dropped on the semiconductor bare chip 17, and the semiconductor bare chip 17 and the bonding wires 18 are sealed with the resin 19.

【0017】したがって、この製造方法では、先にSM
T実装を行うが、その際には回路基板11の全面に対し
て先に半田印刷を行い、保護枠15とSMT部品14を
搭載し、その後に半田リフローの各工程を行えばよいた
め、保護枠15を搭載する以外は従来のSMT実装工程
と同じ工程でよい。そして、このSMT実装工程の間、
回路基板11のCOB実装領域は保護枠15によって密
閉状態に保持されるため、この領域が汚染されることは
ない。したがって、その後に保護枠15を回路基板11
上から離脱させたときには、回路基板11には清浄な状
態のCOB実装領域が露呈されることになり、清浄工程
が不要とされる。
Therefore, in this manufacturing method, the SM
T mounting is performed. In this case, solder printing is first performed on the entire surface of the circuit board 11, the protective frame 15 and the SMT component 14 are mounted, and then each step of solder reflow may be performed. Except for mounting the frame 15, the same process as the conventional SMT mounting process may be used. And during this SMT mounting process,
Since the COB mounting area of the circuit board 11 is kept in a sealed state by the protective frame 15, this area is not contaminated. Therefore, after that, the protection frame 15 is attached to the circuit board 11.
When the circuit board 11 is detached from above, the clean COB mounting area is exposed on the circuit board 11, and the cleaning step is not required.

【0018】このため、このCOB実装領域に対して
は、従来のCOB実装工程をそのまま行うことができ
る。そして、COB実装工程の前には既にSMT実装工
程が完了されているため、COB構造がダメージを受け
ることもない。
Therefore, the conventional COB mounting process can be directly performed on the COB mounting area. Since the SMT mounting step has already been completed before the COB mounting step, the COB structure is not damaged.

【0019】図5は本発明の第2実施例を工程順に示す
図である。なお、同図(a)〜(c)の工程は前記第1
実施例と同じである。即ち、同図(a)のように、有機
絶縁基板に所要の導電膜パターンが形成され、かつCO
B及びSMTの各部品を搭載する個所を除いて絶縁被膜
で被覆された回路基板11に半田印刷を行う。しかる上
で、同図(b)のように、SMT部品14を基板上の所
要個所に搭載する。このとき、回路基板11の表面上の
COB実装領域には保護枠15を搭載する。この保護枠
15は第1実施例に示したものと同じであり、枠体15
1の下面に貼り付けられた両面テープ153により回路
基板11の表面上に貼付固定される。
FIG. 5 is a view showing a second embodiment of the present invention in the order of steps. It should be noted that the steps of FIGS.
This is the same as the embodiment. That is, as shown in FIG. 2A, a required conductive film pattern is formed on an organic insulating substrate and
Solder printing is performed on the circuit board 11 covered with the insulating coating except for the parts where the components B and SMT are mounted. Then, as shown in FIG. 3B, the SMT component 14 is mounted at a required position on the substrate. At this time, the protection frame 15 is mounted on the COB mounting area on the surface of the circuit board 11. This protection frame 15 is the same as that shown in the first embodiment,
1 is adhered and fixed on the surface of the circuit board 11 by the double-sided tape 153 attached to the lower surface of the circuit board 11.

【0020】しかる上で、同図(c)のように、回路基
板11をリフロー炉16に通し、印刷した半田を溶融さ
せてSMT部品14を回路基板11に半田付けして実装
を行う。次いで、同図(d)のように、COB実装領域
に固定されている保護枠15の耐熱シート152を枠体
151から剥離し、耐熱シート152で覆われていた回
路基板11のCOB実装領域を枠体151内に露呈させ
る。そして、この枠体151に囲まれたCOB実装領域
の回路基板11上に半導体ベアチップ17を搭載する。
この搭載には導電性接着剤や金属ロー材等が用いられ
る。そして、図6に示すように、搭載された半導体ベア
チップ17と基板の回路とをボンディングワイヤ18に
より電気接続する。
Then, as shown in FIG. 1C, the circuit board 11 is passed through a reflow furnace 16, the printed solder is melted, and the SMT component 14 is soldered to the circuit board 11 for mounting. Next, as shown in FIG. 3D, the heat-resistant sheet 152 of the protection frame 15 fixed to the COB mounting area is peeled off from the frame 151, and the COB mounting area of the circuit board 11 covered with the heat-resistant sheet 152 is removed. It is exposed inside the frame 151. Then, the semiconductor bare chip 17 is mounted on the circuit board 11 in the COB mounting area surrounded by the frame 151.
For this mounting, a conductive adhesive, a metal brazing material, or the like is used. Then, as shown in FIG. 6, the mounted semiconductor bare chip 17 and the circuit on the substrate are electrically connected by bonding wires 18.

【0021】しかる後、前記枠体151内に封止樹脂1
9を滴下させ、搭載した半導体ベアチップ17及びボン
ディングワイヤ18を樹脂19で封止する。このとき、
枠体151は封止樹脂19の外形を拘束し、樹脂19が
周囲に流れ出すことを防止する。封止樹脂19が硬化さ
れた後、枠体151を基板から取り外すことでCOB構
造が完成される。
Thereafter, the sealing resin 1 is placed in the frame 151.
9 is dropped, and the mounted semiconductor bare chip 17 and bonding wire 18 are sealed with resin 19. At this time,
The frame 151 restrains the outer shape of the sealing resin 19 and prevents the resin 19 from flowing out to the surroundings. After the sealing resin 19 is cured, the COB structure is completed by removing the frame 151 from the substrate.

【0022】この第2実施例においても、先にSMT実
装を行っており、その際には回路基板11の全面に対し
て半田印刷を行い、保護枠15とSMT部品14を搭載
し、その後に半田リフローの各工程を行えばよいため、
保護枠15を搭載する以外は従来のSMT実装工程と同
じ工程でよい。そして、このSMT実装工程の間、回路
基板11のCOB実装領域は保護枠15によって密閉状
態に保持されるため、この領域が汚染されることはな
い。したがって、その後に保護枠15の耐熱シート15
2を剥離したときには、清浄な状態のCOB実装領域が
枠体151内に露呈されることになり、清浄工程が不要
とされる。
Also in the second embodiment, the SMT mounting is performed first. In this case, solder printing is performed on the entire surface of the circuit board 11, the protection frame 15 and the SMT components 14 are mounted, and thereafter, Since it is sufficient to perform each step of solder reflow,
Except for mounting the protection frame 15, the same process as the conventional SMT mounting process may be used. During the SMT mounting step, the COB mounting area of the circuit board 11 is kept in a sealed state by the protection frame 15, so that this area is not contaminated. Therefore, after that, the heat-resistant sheet 15
When 2 is peeled off, a clean COB mounting area is exposed in the frame 151, and the cleaning step is not required.

【0023】このため、このCOB実装領域に対して
は、従来のCOB実装工程をそのまま行うことができ
る。そして、COB実装工程の前には既にSMT実装工
程が完了されているため、COB構造がダメージを受け
ることもない。
Therefore, the conventional COB mounting process can be directly performed on the COB mounting area. Since the SMT mounting step has already been completed before the COB mounting step, the COB structure is not damaged.

【0024】更に、この第2実施例では、COB構造を
封止するための樹脂封止工程では、枠体151により封
止樹脂19の流動が拘束されるため、ポッテング法を採
用しても樹脂19が周囲のSMT実装領域にまで流動さ
れることがなく、封止樹脂19の外形寸法及びその高さ
寸法を高精度に管理でき、信頼性の高い封止が実現され
る。なお、この枠体151はそのままCOB構造の一部
として回路基板11上に残しておいてもよい。或いは、
前記したようにその後に除去してもよい。
Further, in the second embodiment, in the resin sealing step for sealing the COB structure, the flow of the sealing resin 19 is restricted by the frame 151, so that the resin may be applied even if the potting method is adopted. The external dimensions and the height of the sealing resin 19 can be managed with high precision without the 19 flowing to the surrounding SMT mounting area, and highly reliable sealing can be realized. The frame 151 may be left on the circuit board 11 as a part of the COB structure. Or,
It may be subsequently removed as described above.

【0025】ここで、前記各実施例は半導体ベアチップ
をワイヤボンディング法により基板に実装した例を示し
ているが、フェースダウンボンディング法により実装す
る場合にも本発明を適用することが可能である。
Although each of the above embodiments shows an example in which a semiconductor bare chip is mounted on a substrate by a wire bonding method, the present invention can be applied to a case where the semiconductor bare chip is mounted by a face down bonding method.

【0026】[0026]

【発明の効果】以上説明したように本発明は、先にSM
T実装を行っており、その際には基板の全面に対して半
田印刷を行い、保護枠とSMT部品を搭載し、その後に
半田リフローの各工程を行っているため、保護枠を搭載
する以外は従来のSMT実装工程と同じ工程でよく、S
MT実装工程を容易に行うことができる。また、このS
MT実装工程の間、COB実装領域は保護枠によって密
閉状態に保持されるため、この領域が汚染されることは
なく、COB実装領域の清浄工程が不要となり、工程の
簡略化、容易化が可能とされ、かつ製造効率が向上され
る。
As described above, according to the present invention, the SM
T-mounting is performed. In this case, solder printing is performed on the entire surface of the board, a protective frame and SMT components are mounted, and then each step of solder reflow is performed. May be the same as the conventional SMT mounting process.
The MT mounting process can be easily performed. Also, this S
During the MT mounting process, the COB mounting area is held in a sealed state by the protective frame, so that this area is not contaminated, and the COB mounting area does not need to be cleaned, and the process can be simplified and simplified. And the manufacturing efficiency is improved.

【0027】また、COB実装領域に対しても、従来の
COB実装工程をそのまま行うことができ、COB実装
工程の前には既にSMT実装工程が完了されているた
め、COB構造がSMT実装工程によってダメージを受
けることもない。
Also, the conventional COB mounting process can be directly performed on the COB mounting region, and the SMT mounting process has already been completed before the COB mounting process. No damage.

【0028】更に、COB実装工程の樹脂封止工程で
は、保護枠により封止樹脂の外形が拘束されるため、ポ
ッテング法等によって樹脂封止を行っても樹脂が周囲の
SMT実装領域にまで流動されることがなく、封止樹脂
の外形寸法及びその高さ寸法を高精度に管理でき、信頼
性の高い封止構造が容易に実現できる。
Further, in the resin sealing step of the COB mounting step, since the outer shape of the sealing resin is constrained by the protective frame, the resin flows to the surrounding SMT mounting area even if the resin sealing is performed by a potting method or the like. The external dimensions and the height of the sealing resin can be managed with high precision, and a highly reliable sealing structure can be easily realized.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1実施例を工程順に示す正面図であ
る。
FIG. 1 is a front view showing a first embodiment of the present invention in the order of steps.

【図2】保護枠の斜視図である。FIG. 2 is a perspective view of a protection frame.

【図3】保護枠の断面図である。FIG. 3 is a sectional view of a protection frame.

【図4】第1実施例のCOB部分の拡大断面図である。FIG. 4 is an enlarged sectional view of a COB portion of the first embodiment.

【図5】本発明の第2実施例を工程順に示す正面図であ
る。
FIG. 5 is a front view showing a second embodiment of the present invention in the order of steps.

【図6】第2実施例のCOB部分の拡大断面図である。FIG. 6 is an enlarged sectional view of a COB portion according to the second embodiment.

【符号の説明】[Explanation of symbols]

11 回路基板 12 半田シート 14 SMT部品 15 保護枠 16 リフロー炉 17 半導体ベアチップ 18 ボンディングワイヤ 19 封止樹脂 151 枠体 152 耐熱シート 153 両面テープ DESCRIPTION OF SYMBOLS 11 Circuit board 12 Solder sheet 14 SMT component 15 Protective frame 16 Reflow furnace 17 Semiconductor bare chip 18 Bonding wire 19 Sealing resin 151 Frame body 152 Heat-resistant sheet 153 Double-sided tape

Claims (4)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 半導体ベアチップと表面実装部品とを同
一基板に実装してなる半導体集積回路装置の製造に際
し、基板に半田を印刷する工程と、前記基板に表面実装
部品を搭載しかつ前記半導体ベアチップを実装する領域
に保護枠を搭載して前記半導体ベアチップ実装領域の基
板表面を被覆する工程と、リフロー法により前記表面実
装部品を半田付けする工程と、前記保護枠を除去して前
記基板表面を露呈させ、この露呈面に半導体ベアチップ
を実装する工程とを含むことを特徴とする半導体集積回
路装置の製造方法。
A step of printing solder on a substrate when manufacturing a semiconductor integrated circuit device in which a semiconductor bare chip and a surface mounting component are mounted on the same substrate; and mounting the surface mounting component on the substrate and the semiconductor bare chip. Mounting a protective frame on the area where the substrate is mounted and covering the substrate surface in the semiconductor bare chip mounting area, soldering the surface mounted component by a reflow method, and removing the protective frame to remove the substrate surface. Exposing and mounting a semiconductor bare chip on the exposed surface.
【請求項2】 半導体ベアチップと表面実装部品とを同
一基板に実装してなる半導体集積回路装置の製造に際
し、基板に半田を印刷する工程と、前記基板に表面実装
部品を搭載しかつ前記半導体ベアチップを実装する領域
に保護枠を搭載して前記半導体ベアチップ実装領域の基
板表面を被覆する工程と、リフロー法により前記表面実
装部品を半田付けする工程と、前記保護枠の一部を除去
して保護枠の内部に前記基板表面を露呈させ、この露呈
面に半導体ベアチップを実装する工程と、前記保護枠内
に樹脂を充填して前半導体ベアチップを樹脂封止する工
程とを含むことを特徴とする半導体集積回路装置の製造
方法。
2. A process for printing a solder on a substrate when manufacturing a semiconductor integrated circuit device in which a semiconductor bare chip and a surface-mounted component are mounted on the same substrate; and mounting the surface-mounted component on the substrate and the semiconductor bare chip. Mounting a protective frame on the area where the semiconductor chip is mounted, covering the surface of the substrate in the semiconductor bare chip mounting area, soldering the surface mounted component by a reflow method, and removing a part of the protective frame for protection. Exposing the surface of the substrate inside a frame, mounting a semiconductor bare chip on the exposed surface, and filling the protective frame with a resin and sealing the front semiconductor bare chip with a resin. A method for manufacturing a semiconductor integrated circuit device.
【請求項3】 保護枠は、半導体ベアチップの実装領域
を囲む枠体と、この枠体の上面を覆う耐熱シートと、前
記枠体を基板表面に接着させる接着テープとで構成さ
れ、表面実装部品の半田付け時には耐熱シートで半導体
ベアチップの実装領域を被覆し、表面実装部品を実装し
た後に前記耐熱シートを剥がして半導体ベアチップ実装
領域を露呈させる請求項2の半導体集積回路装置の製造
方法。
3. The protection frame includes a frame surrounding a mounting region of the semiconductor bare chip, a heat-resistant sheet covering an upper surface of the frame, and an adhesive tape for bonding the frame to a substrate surface. 3. The method for manufacturing a semiconductor integrated circuit device according to claim 2, wherein the heat-resistant sheet covers the mounting area of the semiconductor bare chip at the time of soldering, and after mounting the surface-mounted components, peels off the heat-resistant sheet to expose the semiconductor bare chip mounting area.
【請求項4】 樹脂封止用の樹脂は、半導体ベアチップ
を覆う高さまで保護枠の枠体内に滴下させてなる請求項
2又は3の半導体集積回路装置の製造方法。
4. The method of manufacturing a semiconductor integrated circuit device according to claim 2, wherein the resin for resin encapsulation is dropped into the frame of the protective frame to a height covering the semiconductor bare chip.
JP6077890A 1994-03-25 1994-03-25 Method for manufacturing semiconductor integrated circuit device Expired - Lifetime JP2705566B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6077890A JP2705566B2 (en) 1994-03-25 1994-03-25 Method for manufacturing semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6077890A JP2705566B2 (en) 1994-03-25 1994-03-25 Method for manufacturing semiconductor integrated circuit device

Publications (2)

Publication Number Publication Date
JPH07263617A JPH07263617A (en) 1995-10-13
JP2705566B2 true JP2705566B2 (en) 1998-01-28

Family

ID=13646674

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6077890A Expired - Lifetime JP2705566B2 (en) 1994-03-25 1994-03-25 Method for manufacturing semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JP2705566B2 (en)

Also Published As

Publication number Publication date
JPH07263617A (en) 1995-10-13

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