JP3390895B2 - Method of manufacturing MOS type semiconductor device - Google Patents
Method of manufacturing MOS type semiconductor deviceInfo
- Publication number
- JP3390895B2 JP3390895B2 JP12099595A JP12099595A JP3390895B2 JP 3390895 B2 JP3390895 B2 JP 3390895B2 JP 12099595 A JP12099595 A JP 12099595A JP 12099595 A JP12099595 A JP 12099595A JP 3390895 B2 JP3390895 B2 JP 3390895B2
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- film
- semiconductor device
- type semiconductor
- sidewall
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 20
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 24
- 229910052710 silicon Inorganic materials 0.000 claims description 24
- 239000010703 silicon Substances 0.000 claims description 24
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 20
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 20
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 7
- 238000010438 heat treatment Methods 0.000 claims description 7
- 238000000034 method Methods 0.000 claims description 7
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 claims 2
- 239000000758 substrate Substances 0.000 description 15
- 239000007789 gas Substances 0.000 description 14
- 239000012535 impurity Substances 0.000 description 8
- 230000003647 oxidation Effects 0.000 description 8
- 238000007254 oxidation reaction Methods 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 229910052814 silicon oxide Inorganic materials 0.000 description 7
- 238000005121 nitriding Methods 0.000 description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 5
- 239000001301 oxygen Substances 0.000 description 5
- 229910052760 oxygen Inorganic materials 0.000 description 5
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 4
- 238000009826 distribution Methods 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 229910001882 dioxygen Inorganic materials 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000001272 nitrous oxide Substances 0.000 description 1
- 235000013842 nitrous oxide Nutrition 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000012805 post-processing Methods 0.000 description 1
- 238000002203 pretreatment Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
- H01L29/512—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being parallel to the channel plane
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Formation Of Insulating Films (AREA)
Description
【発明の詳細な説明】
【０００１】
【産業上の利用分野】本発明は、ＭＯＳ型半導体装置の
製造方法に関する。近年、ＭＯＳＦＥＴ、ＭＯＳＦＥＴ
を用いた集積回路装置等のＭＯＳ型半導体装置の高集積
化、微細化が進むにともない、ＭＯＳ型半導体装置のゲ
ート絶縁膜の膜厚は益々薄くなりつつある。
【０００２】
【従来の技術】そのような極微細ＭＯＳ型半導体装置に
おいては、ゲート絶縁膜の絶縁破壊、ホットキャリアに
よる性能の劣化が重大な問題となっている。これらの極
微細ＭＯＳ型半導体装置に生じる諸問題を解決する方法
の一つとして、ゲート絶縁膜に窒素を含有したシリコン
酸化膜（シリコン窒化酸化膜）を用いる方法がある。
【０００３】
【発明が解決しようとする課題】極微細ＭＯＳ型半導体
装置においては、絶縁破壊もホットキャリアによる劣化
もゲート電極とサイドウォールの境界近傍で生じること
が多い。したがって、ゲート電極とサイドウォールの境
界近傍にシリコン窒化酸化膜を形成することが前記の問
題を解決する上での鍵となる。ところで、極微細ＭＯＳ
型半導体装置のゲート絶縁膜は、ゲート長０．２μｍで
５ｎｍ程度と極めて薄いため、ゲート電極の加工時およ
び後処理においてサイドウォールの下になるゲート絶縁
膜が消失してしまうことがある。
【０００４】すなわち、極微細ＭＯＳ型半導体装置で
は、ゲート電極とサイドウォールの境界近傍のサイドウ
ォールの下にはシリコン窒化酸化膜が無いことになり、
そのために特性の劣化が生じることになる。本発明は、
ゲート電極の直下の一部とサイドウォールの下の少なく
とも一部にシリコン窒化酸化膜を形成して前記の特性の
劣化を防ぐことを目的とする。
【０００５】
【課題を解決するための手段】本発明に依るＭＯＳ型半
導体装置の製造方法に於いては、ゲート絶縁膜の上にゲ
ート電極を形成する工程と、該ゲート電極の側壁にサイ
ドウォールを形成する工程と、該サイドウォール形成工
程の後に、前記ゲート電極の直下の一部および該サイド
ウォール直下の少なくとも一部にシリコン窒化膜または
シリコン窒化酸化膜を形成する工程とを有し、該シリコ
ン窒化膜またはシリコン窒化酸化膜を形成する工程は、
アンモニアガスまたは窒化酸化物系のガスを用いた熱処
理によって行われることを特徴とする。
【０００６】前記の窒化酸化膜を形成する場合、アンモ
ニアガスに依る窒化と酸素に依る酸化に依るか、或い
は、Ｎ 2 Ｏガス等窒化酸化物系のガスを用いることがで
きる。
【０００７】また、アンモニアガスに依る窒化と酸素に
依る酸化、或いは、Ｎ 2 Ｏガス等窒化酸化物系のガスを
用いる窒化酸化は、８５０℃以下の温度を適用すること
ができる。
【０００８】また、アンモニアガスに依る窒化と酸素に
依る酸化、或いは、Ｎ 2 Ｏガス等窒化酸化物系のガスを
用いる窒化酸化は、高温短時間熱処理で実現することが
できる。
【０００９】
【００１０】
【作用】前記手段を採ることに依り、極微細ＭＯＳ型半
導体装置のホットキャリア耐性（寿命）を５倍以上にす
ることができ、経時絶縁破壊までの寿命を２倍にするこ
とができる。
【００１１】
【００１２】また、アンモニアガスに依る窒化と酸素に
依る酸化、或いは、Ｎ2 Ｏガス等の窒化酸化物系のガス
によって窒化酸化膜を形成する場合、高純度のガスが安
価に得られ、そして、工程上で困難を生じることもない
から実用面で優れている。
【００１３】更にまた、アンモニアガスに依る窒化と酸
素に依る酸化、または、Ｎ2 Ｏガス等の窒化酸化物系の
ガスによる窒化酸化を８５０℃以下の温度で実施する
か、或いは、高温短時間熱処理によって行うと、ソース
領域やドレイン領域などの不純物分布に悪影響を与える
ことがない。
【００１４】本発明者は多くの実験を行った結果、本発
明を成したので、その実験例の若干を参考の為に掲示す
る。 （実験例１）
図１は、実験例１を説明する為の工程要所に於けるＭＯ
Ｓ型半導体装置を表す製造工程説明図であり、（Ａ）〜
（Ｄ）は各工程を示している。図に於いて、１はシリコ
ン基板、２はフィールド酸化膜、３はゲート絶縁膜、４
はゲート電極、５はシリコン窒化膜、６はシリコン窒化
酸化膜、７はシリコン窒化酸化膜、８はサイドウォール
をそれぞれ示す。
【００１５】第１工程（図１（Ａ）参照）
シリコン基板１の上面に素子形成領域を画定するフィー
ルド酸化膜（ＬＯＣＯＳ酸化膜）２を形成し、この素子
形成領域のシリコン基板１の表面を熱酸化してシリコン
酸化物からなるゲート絶縁膜３を形成する。このゲート
絶縁膜３の上にＣＶＤによってポリシリコン層を形成
し、このポリシリコン層をＲＩＥによってパターニング
してゲート電極４を形成する。このゲート電極４のパタ
ーニングによってゲート電極４の周囲のゲート絶縁膜３
が除去される。
【００１６】第２工程（図１（Ｂ）参照）
第１工程でゲート電極４を形成したシリコン基板１をア
ンモニアガス中で、温度８００℃で１０分間加熱する。
その結果、ゲート電極４の表面と露出しているシリコン
基板の表面にシリコン窒化膜５が形成され、ゲート電極
４の下の内周のゲート絶縁膜３がシリコン窒化酸化膜６
に変換される。
【００１７】第３工程（図１（Ｃ）参照）
第２工程でシリコン窒化膜５が形成されたシリコン基板
１を、酸素ガス中で、８００℃２０分間加熱する。その
結果、シリコン窒化膜５がシリコン窒化酸化膜７に変換
される。
【００１８】第４工程（図１（Ｄ）参照）
第３工程で窒化酸化膜７が形成されたシリコン基板１の
上にＣＶＤによってシリコン酸化膜を堆積し、このシリ
コン酸化膜をＲＩＥによって異方性エッチングすること
によってゲート電極４の側壁にサイドウォール８を形成
する。
【００１９】この製造工程において、シリコン窒化酸化
膜７を形成する前あるいは後に、ＬＤＤを形成するため
の不純物のイオン注入を行い、サイドウォール８を形成
した後にソース領域とドレイン領域を形成するための不
純物のイオン注入を行い、ソース領域とドレイン領域に
電極を形成してＭＯＳ型半導体装置を完成する。
【００２０】この熱処理によって、ゲート電極４の下の
内周のゲート絶縁膜３がシリコン窒化酸化膜６に変換す
ることができるとともに、チャネルプロファイル、ＬＤ
Ｄ構造等の不純物分布が変化することがなかった。
【００２１】（実験例２） 実験例２では、実験例１に於ける
第３工程（図１（Ｃ）
参照）の酸化を、酸素ガス中で、１０００℃で１０秒間
の高温短時間熱処理（Ｒａｐｉｄ Ｔｈｅｒｍａｌ Ｐ
ｒｏｃｅｓｓ：ＲＴＰ）で行う点が特徴である。この熱
処理によって、ゲート電極４の下の内周のゲート絶縁膜
３がシリコン窒化酸化膜６に変換することができると共
にチャネルプロファイル、ＬＤＤ構造などの不純物分布
が変化することはなかった。
【００２２】前記説明した実験例１及び２では、工程を
慎重に進行すれば、作製したＭＯＳ型半導体装置のホッ
トキャリア耐性は充分に向上するのであるが、何れも、
サイドウォールの形成前に窒化を行っている為、その後
の各種前処理などに依って、窒化された膜が失われる危
険がある。 然しながら、以下に説明する本発明の実施例
に依れば、その危険は排除することができる。 （実施例）
図２は、本発明実施例のＭＯＳ型半導体装置の製造工程
説明図であり、（Ａ）〜（Ｃ）は各工程を示している。
図に於いて、１１はシリコン基板、１２はフィールド酸
化膜い、１３はゲート絶縁膜、１４はゲート電極、１５
はサイドウォール、１６はシリコン窒化酸化膜をそれぞ
れ示している。
【００２３】第１工程（図２（Ａ）参照）
シリコン基板１１の上面に素子形成領域を画定するフィ
ールド酸化膜（ＬＯＣＯＳ酸化膜）１２を形成し、この
素子形成領域のシリコン基板１１の表面を熱酸化してシ
リコン酸化物からなるゲート絶縁膜１３を形成する。こ
のゲート絶縁膜１３の上にＣＶＤによってポリシリコン
層を形成し、このポリシリコン層をＲＩＥによってパタ
ーニングしてゲート電極１４を形成する。このゲート電
極１４のパターニングによってゲート電極１４の周囲の
ゲート絶縁膜１３が除去される。
【００２４】第２工程（図２（Ｂ）参照）
第１工程でゲート電極１４が形成されたシリコン基板１
１の上にＣＶＤによってシリコン酸化膜を堆積し、この
シリコン酸化膜を異方性エッチングすることによってゲ
ート電極１４の側壁にサイドウォール１５を形成する。
【００２５】第３工程（図２（Ｃ）参照）
第２工程でゲート電極１４の側壁にサイドウォール１５
を形成したシリコン基板１１をＮ2 Ｏガス（亜酸化窒素
ガス、笑気ガス）中で、１０５０℃の温度で１０分間の
熱処理を行い、ゲート電極１４の表面と、サイドウォー
ル１５の下と、露出しているシリコン基板の表面にシリ
コン窒化酸化膜１６を形成する。
【００２６】この製造工程において、ゲート電極１４を
形成した後に、ＬＤＤを形成するための不純物のイオン
注入を行い、サイドウォール１５を形成した後にソース
領域とドレイン領域を形成するための不純物のイオン注
入を行い、ソース領域とドレイン領域に電極を形成して
ＭＯＳ型半導体装置を完成する。
【００２７】この熱処理によって、ゲート電極４の下の
内周のゲート絶縁膜３がシリコン窒化酸化膜６に変換す
ることができるとともに、チャネルプロファイル、ＬＤ
Ｄ構造等の不純物分布が変化することがなかった。
【００２８】
【発明の効果】以上説明したように、本発明によると、
極微細ＭＯＳ型半導体装置のホットキャリア耐性（寿
命）を５倍以上にすることができ、経時絶縁破壊までの
寿命を２倍にすることができるため、極微細ＭＯＳ型半
導体装置の実用化に寄与するところが大きい。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS type semiconductor device .
It relates to a manufacturing method. Recently, MOSFET, MOSFET
With the progress of high integration and miniaturization of MOS type semiconductor devices such as integrated circuit devices using GaN, the thickness of the gate insulating film of the MOS type semiconductor device is becoming increasingly smaller. 2. Description of the Related Art In such an ultra-fine MOS type semiconductor device, dielectric breakdown of a gate insulating film and deterioration of performance due to hot carriers are serious problems. As one of the methods for solving the problems that occur in these ultrafine MOS type semiconductor devices, there is a method using a silicon oxide film (silicon nitride oxide film) containing nitrogen for the gate insulating film. [0003] In an ultra-small MOS type semiconductor device, both dielectric breakdown and deterioration due to hot carriers often occur near the boundary between the gate electrode and the sidewall. Therefore, forming a silicon oxynitride film near the boundary between the gate electrode and the sidewall is a key to solving the above problem. By the way, ultra-fine MOS
Since the gate insulating film of the type semiconductor device is as thin as about 5 nm with a gate length of 0.2 μm, the gate insulating film below the sidewall may be lost during the processing of the gate electrode and in post-processing. That is, in the ultra-small MOS type semiconductor device, there is no silicon oxynitride film under the sidewall near the boundary between the gate electrode and the sidewall.
Therefore, the characteristics are deteriorated. The present invention
It is an object of the present invention to form a silicon oxynitride film on a part immediately below a gate electrode and at least a part below a sidewall to prevent the above-described characteristics from deteriorating. [0005] In the method of manufacturing a MOS type semiconductor device according to the present invention SUMMARY OF], gate on the gate insulating film
Forming a gate electrode, and forming a gate electrode on a side wall of the gate electrode.
Forming a sidewall, and forming the sidewall
After the step, a part immediately below the gate electrode and the side
A silicon nitride film or at least a part immediately below the wall
Forming a silicon oxynitride film.
Forming a silicon nitride film or a silicon oxynitride film,
Heat treatment using ammonia gas or nitride-based gas
It is characterized by the fact that it is carried out by management . When forming the above-mentioned nitrided oxide film, the
Depending on nitriding by near gas and oxidizing by oxygen, or
Can use nitrided oxide gas such as N 2 O gas.
Wear. In addition, nitriding and oxygen by ammonia gas
Oxidation or nitriding oxide gas such as N 2 O gas
For the nitridation and oxidation used, apply a temperature of 850 ° C or less.
Can be. In addition, nitriding and oxygen caused by ammonia gas
Oxidation or nitriding oxide gas such as N 2 O gas
The nitridation used can be realized by high-temperature short-time heat treatment.
it can. According to the above-mentioned means, an extremely fine MOS type half
Increase the hot carrier resistance (lifetime) of conductor devices by 5 times or more
Doubling the life until dielectric breakdown with time
Can be. [0011] [0012] oxidation due to nitride and oxygen according to the ammonia gas, or, in the case of forming a nitrided oxide film by nitridation oxide-based gas such as N 2 O gas, inexpensively obtained high purity gases And there is no difficulty in the process
Excellent in practical use. [0013] Furthermore, oxidation due to nitride and oxygen according to the ammonia gas, or performs a nitride oxide by oxynitride-based gas such as N 2 O gas at 8 50 ° C. below the temperature
Or, alternatively, it performed by a high-temperature short-time heat treatment, a negative impact on the distribution of impurities such as source <br/> area and drain region
Nothing. The present inventors have conducted many experiments and found that the present invention
As a result, some of the experimental examples are posted for reference.
You. (Experimental Example 1) FIG. 1 shows an MO in a process essential point for explaining Experimental Example 1 .
It is a manufacturing process explanatory view showing an S type semiconductor device, (A)-
(D) shows each step. In the figure, 1 is a silicon substrate, 2 is a field oxide film, 3 is a gate insulating film, 4
Is a gate electrode, 5 is a silicon nitride film, 6 is a silicon nitride oxide film, 7 is a silicon nitride oxide film, 8 is a sidewall.
Are respectively shown. First step (refer to FIG. 1A) A field oxide film (LOCOS oxide film) 2 for defining an element formation region is formed on the upper surface of a silicon substrate 1, and the surface of the silicon substrate 1 in the element formation region is formed. The gate insulating film 3 made of silicon oxide is formed by thermal oxidation. A polysilicon layer is formed on the gate insulating film 3 by CVD, and the polysilicon layer is patterned by RIE to form a gate electrode 4 . The gate insulating film 3 around the gate electrode 4 is formed by the patterning of the gate electrode 4.
Is removed. Second Step (See FIG. 1B) The silicon substrate 1 on which the gate electrode 4 has been formed in the first step is heated in an ammonia gas at a temperature of 800 ° C. for 10 minutes.
As a result, a silicon nitride film 5 is formed on the surface of the gate electrode 4 and the exposed surface of the silicon substrate, and the gate insulating film 3 on the inner periphery under the gate electrode 4 becomes a silicon nitride oxide film 6.
Is converted to Third Step (See FIG. 1C) The silicon substrate 1 on which the silicon nitride film 5 has been formed in the second step is heated in an oxygen gas at 800 ° C. for 20 minutes. As a result, silicon nitride film 5 is converted to silicon nitride oxide film 7. Fourth step (see FIG. 1D) A silicon oxide film is deposited by CVD on the silicon substrate 1 on which the nitrided oxide film 7 has been formed in the third step, and this silicon oxide film is anisotropically formed by RIE. The side wall 8 is formed on the side wall of the gate electrode 4 by the reactive etching. In this manufacturing process, before or after the formation of the silicon oxynitride film 7, ion implantation of impurities for forming the LDD is performed, and after forming the sidewalls 8, the source and drain regions are formed. Impurity ions are implanted, and electrodes are formed in the source region and the drain region to complete the MOS semiconductor device. By this heat treatment, the gate insulating film 3 on the inner periphery under the gate electrode 4 can be converted into the silicon oxynitride film 6, and the channel profile, LD
The impurity distribution such as the D structure did not change. (Experimental Example 2) In Experimental Example 2, the third step in Experimental Example 1 (FIG. 1C)
Oxidation) in oxygen gas at 1000 ° C. for 10 seconds (Rapid Thermal P).
process: RTP). This heat treatment, the gate insulating film 3 in the circumferential Shimonouchi the gate electrode 4 can be converted to silicon nitride oxide film 6 co
Channel profile, the distribution of impurities such as LDD structures did not change to. In Experimental Examples 1 and 2 described above, the steps were
If proceeding carefully, the hot spot of the fabricated MOS semiconductor device
Although the carrier resistance is sufficiently improved,
Since nitriding is performed before forming the sidewall,
Risk of losing nitrided film due to various pretreatments
There is a steep. However, embodiments of the present invention described below
Can eliminate that danger. (Embodiment) FIGS. 2A to 2C are explanatory views of a manufacturing process of a MOS type semiconductor device according to an embodiment of the present invention , wherein FIGS.
In the figure, 11 is a silicon substrate, 12 is a field oxide film, 13 is a gate insulating film, 14 is a gate electrode, 15
Sidewall, 16 is it a silicon nitride oxide film
Is shown. First Step (See FIG. 2A) A field oxide film (LOCOS oxide film) 12 for defining an element formation region is formed on the upper surface of a silicon substrate 11, and the surface of the silicon substrate 11 in the element formation region is removed. The gate insulating film 13 made of silicon oxide is formed by thermal oxidation. A polysilicon layer is formed on the gate insulating film 13 by CVD, and the polysilicon layer is patterned by RIE to form a gate electrode 14. The gate insulating film 13 around the gate electrode 14 is removed by the patterning of the gate electrode 14. Second Step (See FIG. 2B) The silicon substrate 1 on which the gate electrode 14 has been formed in the first step
A silicon oxide film is deposited on the substrate 1 by CVD, and the silicon oxide film is anisotropically etched to form a sidewall 15 on a side wall of the gate electrode 14. Third Step (See FIG. 2C) In the second step, a sidewall 15 is formed on the side wall of the gate electrode 14.
Is heat-treated at 1050 ° C. for 10 minutes in N 2 O gas (nitrous oxide gas, laughing gas), and the surface of the gate electrode 14 and under the sidewall 15 are A silicon nitride oxide film 16 is formed on the exposed surface of the silicon substrate. In this manufacturing process, after the gate electrode 14 is formed, ion implantation of impurities for forming the LDD is performed, and after the sidewall 15 is formed, ion implantation of impurities for forming the source region and the drain region is performed. Then, electrodes are formed in the source region and the drain region to complete the MOS semiconductor device. By this heat treatment, the gate insulating film 3 on the inner periphery under the gate electrode 4 can be converted into the silicon oxynitride film 6, and the channel profile, LD
The impurity distribution such as the D structure did not change. As described above, according to the present invention,
The hot carrier resistance (lifetime) of the ultra-fine MOS type semiconductor device can be increased five times or more, and the life until dielectric breakdown with time can be doubled, contributing to the practical use of the ultra-fine MOS type semiconductor device. The place to do is big.
【図面の簡単な説明】
【図１】実験例１のＭＯＳ型半導体装置の製造工程説明
図であり、（Ａ）〜（Ｄ）は各工程を示している。
【図２】本発明実施例のＭＯＳ型半導体装置の製造工程
説明図であり、（Ａ）〜（Ｃ）は各工程を示している。
【符号の説明】
１ シリコン基板
２ フィールド酸化膜
３ ゲート絶縁膜
４ ゲート電極
５ シリコン窒化膜
６ シリコン窒化酸化膜
７ シリコン窒化酸化膜
８ サイドウォール
１１ シリコン基板
１２ フィールド酸化膜
１３ ゲート絶縁膜
１４ ゲート電極
１５ サイドウォール
１６ シリコン窒化酸化膜BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an explanatory view of a manufacturing process of a MOS type semiconductor device of Experimental Example 1, wherein (A) to (D) show respective steps. FIGS. 2A to 2C are explanatory diagrams of manufacturing steps of a MOS type semiconductor device according to an embodiment of the present invention . FIGS. DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Field oxide film 3 Gate insulating film 4 Gate electrode 5 Silicon nitride film 6 Silicon nitride oxide film 7 Silicon nitride oxide film 8 Side wall 11 Silicon substrate 12 Field oxide film 13 Gate insulating film 14 Gate electrode 15 Side wall 16 Silicon oxynitride film
Claims (1)
工程と、 該ゲート電極の側壁にサイドウォールを形成する工程
と、 該サイドウォール形成工程の後に、前記ゲート電極の直
下の一部および該サイドウォール直下の少なくとも一部
にシリコン窒化膜またはシリコン窒化酸化膜を形成する
工程とを有し、 該シリコン窒化膜またはシリコン窒化酸化膜を形成する
工程は、アンモニアガスまたは窒化酸化物系のガスを用
いた熱処理によって行われる ことを特徴とするＭＯＳ型
半導体装置の製造方法。 (57) [Claim 1] A gate electrode is formed on a gate insulating film.
A step, forming a sidewall on the sidewall of the gate electrode
And immediately after the side wall forming step,
Lower part and at least part immediately below the sidewall
A silicon nitride film or silicon oxynitride film
And a step to form the silicon nitride film or a silicon nitride oxide film
The process uses ammonia gas or nitric oxide based gas.
A method of manufacturing a MOS type semiconductor device , wherein the method is performed by heat treatment .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12099595A JP3390895B2 (en) | 1995-05-19 | 1995-05-19 | Method of manufacturing MOS type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12099595A JP3390895B2 (en) | 1995-05-19 | 1995-05-19 | Method of manufacturing MOS type semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08316466A JPH08316466A (en) | 1996-11-29 |
| JP3390895B2 true JP3390895B2 (en) | 2003-03-31 |
Family
ID=14800183
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12099595A Expired - Lifetime JP3390895B2 (en) | 1995-05-19 | 1995-05-19 | Method of manufacturing MOS type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3390895B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1041506A (en) * | 1996-07-25 | 1998-02-13 | Nec Corp | Semiconductor device and its manufacture |
| US20050101147A1 (en) * | 2003-11-08 | 2005-05-12 | Advanced Micro Devices, Inc. | Method for integrating a high-k gate dielectric in a transistor fabrication process |
| US7157341B2 (en) * | 2004-10-01 | 2007-01-02 | International Business Machines Corporation | Gate stacks |
| KR100889551B1 (en) * | 2007-06-25 | 2009-03-23 | 주식회사 동부하이텍 | Method for manufacturing of semiconductor device |
-
1995
- 1995-05-19 JP JP12099595A patent/JP3390895B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH08316466A (en) | 1996-11-29 |
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