JP3738368B2 - Manufacturing method of MIS field effect semiconductor device - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to an improvement in a method of manufacturing a MIS field effect semiconductor device having an LDD (lightly doped drain) structure.
[0002]
The MIS field effect semiconductor device having the LDD structure has a deterioration in sub-threshold characteristics when the gate length is shortened, the threshold voltage depends on the channel length and the drain voltage, and the loss of current saturation characteristics due to punch through. Since the so-called short channel effect is unlikely to occur, the integrated circuit device that requires miniaturization and high density, such as a memory, is currently being used widely. However, the LDD structure has not yet been improved. There is a point that must not be.
[0003]
[Prior art]
Usually, an LDD structure in a MIS field effect semiconductor device has a shallow low impurity concentration region formed so that at least a drain region slightly protrudes in the direction of a channel region directly below the gate electrode, and the low impurity concentration region. It is well known that the high impurity concentration region is formed so as to be slightly separated from the channel. Note that the source region often has the same structure as the drain region for convenience of use and manufacturing.
[0004]
In order to manufacture such an MIS field effect semiconductor device having an LDD structure, it is common to first form a low impurity concentration region and then form a high impurity concentration region.
[0005]
This is because a low impurity concentration region is formed using a mesa-shaped gate electrode protruding on a semiconductor substrate as a mask, and then a side wall made of an insulating film is formed on the side wall of the gate electrode, etc. This is because by forming the concentration region, the high impurity concentration region can be easily separated from the channel region, and can also be used for electrode separation while leaving the side wall.
[0006]
[Problems to be solved by the invention]
It is indispensable to form the drain region and the source region of the miniaturized MIS field effect semiconductor device in the present day by applying the ion implantation method, and the implanted impurity is heat-treated for activation. There must be.
[0007]
As described above, in the manufacture of the MIS field effect semiconductor device having the LDD structure according to the conventional technique, the high impurity concentration region is formed after the low impurity concentration region is formed. Distribution occurs and it is difficult to form a low impurity concentration region as designed.
[0008]
The present invention makes it possible to satisfactorily suppress implantation redistribution and obtain a low impurity concentration region as designed by adding an extremely simple modification to the manufacturing process of the LDD structure.
[0009]
[Means for Solving the Problems]
In the present invention, the basic process is to reverse the order of the steps for forming the low impurity concentration region and the high impurity concentration region, which is a very simple idea. To do this, some ingenuity is required in the process.
[0010]
In the manufacturing method of the MIS field effect semiconductor device according to the present invention, a field insulating film (e.g., a field insulating film 2 made of SiO ₂₎ silicon is formed a semiconductor substrate (e.g., Si semiconductor substrate 1) made of silicon dioxide top Forming a gate electrode (eg, gate electrode 4 made of amorphous Si) through a gate insulating film made of silicon dioxide (eg, gate insulating film 3 made of SiO ₂ ), and then silicon dioxide is an etching solution or etching Forming a first side wall (for example, side wall 5) that covers the side wall of the gate electrode with a material that is different in gas and containing nitrogen (for example, Si ₃ N ₄ ), and then the channel High impurity concentration source with edge on region side self-aligned by first side wall A step of introducing an impurity (for example, B) for forming a region and a high impurity concentration drain region, and then performing a heat treatment for activating the introduced impurity after removing the first side wall. A step of forming a concentration source region (for example, a high impurity concentration source region 6) and a high impurity concentration drain region (for example, a high impurity concentration drain region 7), and then a low impurity concentration source with the first side wall removed. A step of introducing an impurity (for example, B) for forming a region and a low impurity concentration drain region, and then forming an insulating film (for example, an insulating film made of SiO ₂ ) on the entire surface and then activating the introduced impurity A low impurity concentration source region (for example, low impurity concentration source region 9) and a low impurity concentration drain region (for example, low impurity concentration) Forming a drain region 10), then the side walls of the entire surface formed by the insulating film is etched Gate electrode, lightly doped source region and a high impurity concentration source region a channel region side edge surface of the low impurity A step of forming a second side wall (for example, side wall 11) covering the channel region side edge surface of the concentration drain region and the high impurity concentration drain region, and then the exposed gate electrode top surface and source region surface Forming a gate electrode contact region (eg, gate electrode contact region 12) made of silicide, a source electrode contact region (eg, source electrode contact region 13), and a drain electrode contact region (eg, drain electrode contact region 14) on the surface of the drain region. And is included.
[0011]
[Action]
By adopting the above means, the redistribution of implantation does not occur, and it is possible to realize an LDD structure maintaining a low impurity concentration source region and a low impurity concentration drain region having an impurity concentration substantially as designed. Manufactures a highly integrated and high-density integrated circuit device that can easily and easily produce a fine MIS field-effect transistor having a short gate length in which a short channel effect hardly occurs without requiring a special technique. It is effective.
[0012]
【Example】
FIG. 1 to FIG. 4 are sectional side views showing a principal part of a MIS field-effect semiconductor device at a process point for explaining an embodiment of the present invention, and will be described in detail below with reference to these drawings. To do.
[0013]
See Fig. 1 1- (1)
By applying a selective thermal oxidation method (for example, a LOCOS (local oxidation of silicon) method), a field insulating film 2 made of SiO ₂ having a thickness of, for example, 300 [nm] is formed on the Si semiconductor substrate 1. .
[0014]
1- (2)
In the step 1- (1), when the field insulating film 2 is formed, for example, a Si ₃ N ₄ film used as an oxidation resistant mask is removed, and then a thermal oxidation method is applied. A gate insulating film 3 made of SiO ₂ having a thickness of, for example, 10 [nm] is formed.
[0015]
1- (3)
By applying a chemical vapor deposition (CVD) method, an amorphous Si film having a thickness of, for example, 300 nm is formed.
[0016]
1- (4)
By applying a resist process in lithography technology and a reactive ion etching (RIE) method in which an etching gas is a Cl-based gas, the amorphous formed in the step 1- (3). The gate electrode 4 is formed by patterning the Si film.
[0017]
1- (5)
By applying the CVD method, a Si ₃ N ₄ film having a thickness of, for example, 100 nm is formed. Here, reason for selecting Si ₃ N ₄ as a coating material for forming, for example a field insulating film 2 such as SiO ₂ portions during removal after is because you do not want to be damaged, short, of SiO ₂ Any material can be used as long as the material is different from that of the etchant or etching gas.
[0018]
1- (6)
Anisotropic etching of the Si ₃ N ₄ film formed in step 1- (5) by applying a resist process in the lithography technique and an RIE method using CF ₄ gas as an etching gas Then, the Si ₃ N ₄ film is left only on the side wall of the mesa-shaped gate electrode 4 or the like to form the side wall 5 and the others are removed.
[0019]
1- (7)
By applying the ion implantation method, the ion acceleration energy is set to, for example, 10 [keV], and the dose is set to, for example, 4 × 10 ¹⁵ [cm ⁻² ] to perform B ⁺ implantation.
[0020]
See Fig. 2- (1)
After removing the side wall 5 using an etchant as a hot phosphoric acid solution, the time is 15 minutes in a nitrogen atmosphere at a temperature of 850 ° C., and the time is 15 minutes in an oxygen atmosphere at 850 ° C. The B is activated by performing the heat treatment, and the high impurity concentration source region 6 and the high impurity concentration drain region 7 are generated. At this time, an insulating film 8 made of thin SiO ₂ is formed, and the thickness thereof is about 7.5 nm when Si is exposed.
[0021]
As described above, it is important to improve the reliability of the MIS field effect semiconductor device by performing the heat treatment in an oxidizing atmosphere after removing the side walls 5. The reason is that, when removing the side wall 5, the portion made of SiO ₂ is damaged, but this is an effective means particularly in the sense of repairing damage to the gate insulating film 3.
[0022]
2- (2)
By applying the ion implantation method, ion acceleration energy is set to, for example, 10 [keV], and dose is set to, for example, 1.5 × 10 ¹³ [cm ⁻² ] to perform BF ₂ ⁺ implantation.
[0023]
2- (3)
Subsequently, the ion acceleration energy is set to 80 [keV], and the dose is set to 7 × 10 ¹² [cm ⁻² ], for example, and P ⁺ is tilted by 30 °.
[0024]
See Fig. 3 3- (1)
By applying the CVD method, an insulating film made of SiO _{2 having} a thickness of, for example, 200 nm is formed.
[0025]
3- (2)
A heat treatment for 30 minutes is performed in an oxygen atmosphere at a temperature of 800 ° C. to activate P and B, and the shallow low impurity concentration source region 9 and the shallow low impurity concentration drain region 10, conductivity type inversion. Region 1A is generated. Incidentally, the conductivity type reversal region 1A formed by performing P ⁺ 30 ° tilt rotation implantation plays a role for improving punch-through breakdown voltage, and is formed as necessary.
[0026]
3- (3)
By applying the RIE method in which the etching gas is CF ₄ gas, the gate electrode 4 is formed into a mesa shape by anisotropically etching the insulating film made of SiO ₂ formed in the step 3- (1). The side walls 11 are formed leaving the SiO ₂ film only on the side walls, and the others are removed.
[0027]
See Fig. 4 4- (1)
By forming a Ti film having a thickness of, for example, 50 nm by applying a sputtering method, a heat treatment is performed for 1 minute in a nitrogen atmosphere at a temperature of 650 [° C.] to form TiSi _2. A gate electrode contact region 12, a source electrode contact region 13, and a drain electrode contact region 14 are formed.
[0028]
4- (2)
By applying an immersion method in which the etchant is ammonia-based (NH ₄ OH + H ₂ O ₂ + H ₂ O) or the like, unreacted TiN that has not been silicided is removed.
[0029]
4- (3)
A heat treatment is performed for 1 hour in a nitrogen atmosphere at a temperature of 850 [° C.] to complete silicidation.
[0030]
4- (4)
Thereafter, by applying a normal technique, an interlayer insulating film, electrodes / wirings, a passivation film, and the like are formed and completed.
[0031]
According to experiments, in the MIS field effect semiconductor device having the LDD structure manufactured by the above process, it is confirmed that redistribution of implantation does not occur, and the low impurity concentration source region 9 and the low impurity concentration source region 9 Impurity concentration The impurity concentration of the drain region 10 was kept substantially as designed.
[0032]
【The invention's effect】
In the method of manufacturing a MIS field effect semiconductor device according to the present invention, a gate electrode is formed on a silicon semiconductor substrate on which a field insulating film is formed via a gate insulating film. A side wall that covers the side wall of the gate electrode is formed with a material that uses a different gas, and the edge on the channel region side is self-aligned with the side wall to introduce impurities, and then the side wall is removed and then introduced. The impurity is activated to form a high impurity concentration source region and a high impurity concentration drain region, impurities are introduced again, an insulating film is formed on the entire surface, and then a heat treatment for activating the impurity is performed to perform the low impurity concentration source region and A low impurity concentration drain region is formed, and the insulating film formed on the entire surface is etched to form a side wall that covers the side wall of the gate electrode again. It is formed.
[0033]
By adopting the above configuration, the redistribution of implantation does not occur, and an LDD structure that maintains a low impurity concentration source region and a low impurity concentration drain region having an impurity concentration substantially as designed can be realized. A fine MIS field-effect transistor having a short gate length in which a short channel effect hardly occurs can be easily and easily produced without requiring a special technique, and thus, a highly integrated and highly integrated circuit device is manufactured. It is effective to do.
[0034]
By the way, according to the present invention, a side wall for performing ion implantation by self-alignment is formed, and after the high impurity concentration source region and the high impurity concentration drain region are formed, the side wall is removed, Since the side wall is formed again for electrode separation later, the side wall is formed twice, and the manufacturing process is complicated by that amount. Compared to the effect that the structure can be obtained, there are some that can compensate for the disadvantages, and although it is slightly complicated, no special or difficult technology is required to carry out the manufacturing process. You have to be careful.
[Brief description of the drawings]
FIG. 1 is a cutaway side view of a main part showing a MIS field effect semiconductor device at a process point for explaining an embodiment of the present invention.
FIG. 2 is a cut-away side view of an essential part showing a MIS field effect semiconductor device at a process point for explaining an embodiment of the present invention.
FIG. 3 is a cut-away side view of an essential part showing a MIS field effect semiconductor device at a process point for explaining an embodiment of the present invention.
FIG. 4 is a cut-away side view of an essential part showing a MIS field-effect semiconductor device at a process point for explaining an embodiment of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Si semiconductor substrate 2 Field insulating film 3 Gate insulating film 4 Gate electrode 5 Side wall 6 High impurity concentration source region 7 High impurity concentration drain region 8 Insulating film 9 Low impurity concentration source region 10 Low impurity concentration drain region 11 Side wall 12 Gate electrode contact region 13 Source electrode contact region 14 Drain electrode contact region

Claims (1)

Forming a gate electrode on a silicon semiconductor substrate on which a field insulating film made of silicon dioxide is formed via a gate insulating film made of silicon dioxide;
Next, a step of forming a first side wall that covers the side wall of the gate electrode with a material that is different in etching solution or etching gas from silicon dioxide and contains nitrogen, and then an edge on the channel region side A step of introducing an impurity for forming a high impurity concentration source region and a high impurity concentration drain region by performing self-alignment on the first side wall;
Next, after removing the first side wall, performing a heat treatment for activating the introduced impurities to form a high impurity concentration source region and a high impurity concentration drain region;
Next, a step of introducing impurities for forming a low impurity concentration source region and a low impurity concentration drain region with the first sidewall removed,
A step of forming a low impurity concentration source region and a low impurity concentration drain region by performing a heat treatment for activating the introduced impurity after forming an insulating film on the entire surface;
Then, the side walls of the entire surface formed by the insulating film is etched to Gate electrode, lightly doped source region and a high impurity concentration source region a channel region side edge surface of the low impurity concentration drain region and a high impurity concentration drain region Forming a second sidewall covering the channel region side edge surface ;
And forming a gate electrode contact region, a source electrode contact region, and a drain electrode contact region made of silicide on the exposed top surface of the gate electrode, the surface of the source region, and the surface of the drain region. A method for manufacturing a MIS field effect semiconductor device.

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