JP3385650B2 - Method for manufacturing semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to miniaturization and complication of impurity distribution formation in a substrate, and more particularly to V.
It is suitable for a manufacturing process of an element such as an LSI having an extremely fine and complicated pattern.

[0002]

2. Description of the Related Art Recently, with the miniaturization of semiconductor devices, the distribution of impurities in the substrate has been reduced and complicated as seen in retrograde wells. As for the conventional measure against the reduction, the substrate is a single crystal and the ion injection condition is appropriately adjusted to suppress the spread of the implantation distribution due to the channeling as much as possible (for example, 7 degrees relative to the normal to the surface of the silicon substrate). The above is shifted, and the orientation flat portion is rotated around the center of the substrate by about 20 degrees (hereinafter referred to as "angle adjustment method"), or the method of implanting impurity ions after completely amorphizing the silicon substrate surface (hereinafter referred to as "non- The crystallizing method ”is used (for example, monthly Semiconductor World 1990.8, p.56). Further, regarding the complication, the implantation energy and the implantation dose are variously changed to deal with the problem. Further, in this case, as the ion implantation condition, the angle condition that the channeling phenomenon hardly occurs is intentionally selected.

[0003]

In view of the future of further miniaturization in the future, these methods have a low degree of freedom in forming the impurity distribution, and therefore there is a possibility of being restricted when forming a more complicated impurity distribution. There is a problem that there is. For example, as shown in FIGS. 16 and 17, in the conventional method, the half-value width of the implantation distribution (hereinafter referred to as the distribution half-value width defined in FIG. 20) with respect to the incident ions in each of the angle adjustment method and the amorphization method. The peak depth is uniquely determined and independent control is impossible.

In view of the above problems, the present invention realizes the formation of an impurity distribution with a greater degree of freedom, in which the implantation distribution and the peak depth can be varied even for the same incident ion energy, and An object of the present invention is to provide a method for manufacturing a high-performance semiconductor device based on the method.

[0005]

SUMMARY OF THE INVENTION The present invention is a method of manufacturing a semiconductor device including a step of introducing an impurity into a semiconductor substrate by using an ion implantation method, wherein a region having a predetermined depth deeper than the surface of the semiconductor substrate is damaged. A layer to form the semiconductor substrate
It has a process of giving a crystalline distribution in the depth direction in the plate,
When implanting impurity ions into a semiconductor substrate,
Active use of the ringing phenomenon,
It is said that it is appropriate to mix and adjust the angle appropriately.
The technical means of introducing such a method into the ion implantation process
It is characterized by being adopted .

[0006]

According to the present invention, in the ion implantation of impurities, a damaged layer is formed in a region of a predetermined depth deeper than the surface of the semiconductor substrate, and the crystalline distribution in the depth direction in the semiconductor substrate.
When implanting impurity ions into the semiconductor substrate,
And actively use the channeling phenomenon,
It is necessary to properly adjust the angle of the ring axis.
Because you have to box, it is possible to form a concentrated impurity layer only on any particular location, also it is possible to independently control the injection distribution width and the implantation depth thereof.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) An embodiment of the present invention will be described below with reference to the drawings. 1 to 11 are sectional views showing the N-MOS transistor according to the present embodiment in the middle of each manufacturing process.

First, as shown in FIG. 1, a P-type silicon substrate 1 is thermally oxidized to form a thermal oxide film 2 according to a general manufacturing process.
And the nitride film 3 is formed by the LPCVD method or the like.
Thereafter, as shown in FIG. 2, a mask layer 4 such as a resist is patterned, and the oxide film 2 and the nitride film 3 are patterned by a dry etching method. Then, ion implantation (for example, B ⁺ ) is performed to form the channel stopper layer 5.

Next, as shown in FIG. 3, the mask layer 4 is removed, and field oxidation is performed to form a LOCOS region 6. After removing the nitride film 3, the oxide film 2 is removed by etching from the gate region with a dilute hydrofluoric acid solution. Subsequently, the gate oxide film 7 is formed by the thermal oxidation method. further,
As shown in FIG. 4, prior to ion implantation for adjusting the threshold voltage and forming a punch-through stopper, ions for forming a damaged region (for example, ions for forming a damaged region) are locally formed in the silicon substrate to locally form the region 13 having a disordered crystal structure. Si ⁺ or Ge ⁺ ) ions are implanted to disturb the crystal and damage layer regions 13a and 13b.
To form.

For example, as a way of disturbing the crystal structure, it is as shown in FIG. This figure shows a cross-sectional structure of a portion of the silicon substrate which will be a future channel region.
A region 13a (or a single crystal region) having a relatively small amount of damage is formed on the surface, and a region 13b having a relatively large amount of damage is formed at a depth where a punch-through stopper should be formed. At that time, a low damage region 13 is formed at a place which should be an interface between the source / drain and the punch through stopper.
It is preferable to set so that the interface between a (or the single crystal region) and the highly damaged region 13b comes. As a specific example, the thickness of the low damage region 13a on the surface is 0.16 μm, and the thickness of the high damage region 13b where the punch through stopper is to be formed is 0.14 μm.
Set to m. Under these conditions, the degree of damage and the width of damage to the highly damaged region 13b can be adjusted by appropriately adjusting the energy and dose of the damage forming ions 17.

Then, as shown in FIG. 5, in order to collectively adjust the threshold voltage and form the punch-through stopper region, ion implantation of punch-through stopper forming impurity ions is performed with, for example, 20 keV and B ⁺ ions. In this case, the incident angle of the ions is parallel or appropriately shifted to the channeling axis of the silicon substrate (for example, <100>, <110>, <111>, etc.), and the angle is accurately set, and the energy is set to each channeling axis. Set to an appropriate value.

Next, as shown in FIG. 6, a gate electrode 8 is formed by forming a polycrystalline silicon film or the like and patterning it to a predetermined size by a dry etching method. Next, FIG.
As shown in, source / drain formation impurity ions 1
Ion implantation of 8 (for example, P ⁺ or As ⁺ ) is performed to form source / drain regions 9. In this case, unlike the angle condition used at the time of ion implantation for adjusting the threshold voltage and forming the punch-through stopper region, the channeling condition is intentionally shifted (for example, the incident angle of the ion is 7 degrees with respect to the substrate normal). The source / drain junction depth can be made as shallow as possible by implanting impurity ions after making the substrate surface amorphous by ion implantation (Si ⁺ or Ge ⁺ etc.). preferable.

Then, as shown in FIG. 8, oblique ion implantation (for example, P ⁺ or As ⁺ ) of the impurity ions 19 for forming the electric field relaxation layer is performed to form the electric field relaxation layer 15. Next, as shown in FIG. 9, an insulating film layer 10 such as BPSG is formed by a plasma CVD method or the like, and then reflow is performed. Next, as shown in FIG. 10, a contact hole 11 is formed by a dry etching method or the like.

Next, as shown in FIG. 11, Al--Si--
The Cu 12 or the like is formed by, for example, a sputtering method and then patterned to form the wiring 12. After that, a passivation film is formed to complete the N-MOS transistor. As described above, in the present embodiment, in a silicon substrate or the like, the crystal structure is intentionally locally disturbed by an ion implantation method or the like using an appropriate ion with a certain depth and a certain width. In this state, the impurities to be introduced into the substrate are ion-implanted by appropriately combining the above-mentioned three steps to locally form a region containing a relatively large part of the total amount of the implanted impurities. At that time, the set depth of the high-concentration region can be freely changed by changing the energy of the damage-forming ions, and the high-concentration region width can be freely formed by changing the damage width. be able to. For example, when 20 keV, B ⁺ ions are implanted into a (100) silicon substrate as shown in FIG. 18, the distribution half-value width is 0.085 μm in the angle adjustment method and 0.066 μm in the amorphization method.
However, by using the present invention, it is possible to continuously change from 0.038 μm to 0.206 μm.

Further, as shown in FIG. 19, the peak depth of the implantation distribution is uniquely determined to be 0.08 μm in the angle adjustment method shown in the characteristic X and 0.08 μm in the amorphization method shown in the characteristic Y. By using the method of this embodiment shown in the characteristics Z ₁ to Z ₂ , it is possible to continuously change from 0.08 μm to 0.22 μm. The same applies to the energy of other incident ions.

Further, FIG. 13 shows changes in the implantation distribution of B ⁺ ions, which serve as a punch-through stopper, due to the difference in crystallinity of the silicon substrate. However, the injection energy is 20 ke
V. In the case where the substrate is a perfect single crystal, the characteristic A has a relatively wide trapezoidal distribution in the depth direction as indicated by the dotted line during <100> axis channeling. On the other hand, when the incident angle is appropriately shifted to suppress the channeling phenomenon as much as possible, as shown by the chain double-dashed line as the characteristic B,
Although the peak depth shifts to the shallower side and the implantation distribution width narrows, the slope of the tail region is still moderate. Further, when the silicon substrate is completely amorphized, the concentration gradient in the tail region of the distribution is further increased as indicated by the chain line of characteristic C. When the crystallinity distribution shown in FIG. 12 is provided, a region having a high impurity concentration can be locally formed in the highly damaged region as a characteristic D indicated by a solid line.

Although the gate oxide film 7 is formed first in this embodiment, it may be formed after the damaged region is formed. As described above in detail, in the present embodiment, the problem of the degree of freedom in forming the impurity distribution, which is caused by the complication and the reduction in size with the miniaturization, is taken into consideration. , And a high impurity concentration region can be formed with an arbitrary depth and width by introducing into the ion implantation process a method in which the three processes of forming a locally damaged region on the semiconductor substrate are appropriately mixed. As a result, it is possible to solve the above-mentioned problems, and it is possible to further develop the application area of the ion implantation technique than ever before.

Further, since the threshold voltage adjustment and the punch-through stopper region are collectively formed, the forming process can be simplified, and the punch-through stopper can be formed freely and independently. Can be controlled to realize an optimal device structure. (Second Embodiment) In the first embodiment, the damaged region is set only by ion implantation, but in that case, the energy and dose amount of ion implantation are limited to some extent in order to prevent the substrate surface from being significantly damaged. As a result, the setting of the damaged area is limited. Therefore, after setting the damaged region, a method of locally heating the substrate surface such as a laser beam is used to recover the crystallinity of the substrate surface. As a result, the degree of freedom in forming the damaged region with respect to the set conditions can be further increased. Details are as follows.

Gate oxide film forming step in the first embodiment
The same steps are followed until (Figs. 1 to 3). Next, the figure
14, the damaged region forming ions 17 (for example,
Si⁺And Ge ⁺Etc. are implanted to form the damaged region 13.
At that time, unlike the case of the first embodiment, low damage near the surface
There is no particular need to save the area.

Next, as shown in FIG. 15, laser irradiation is carried out to form a recrystallized layer 21 in a damaged region having a desired depth. At that time, in order to adjust the recrystallization depth, the wavelength and power of the laser may be adjusted. As a result, the crystallinity can be recovered in the surface region to cause the channeling phenomenon, and the damaged region can remain in the underlying layer. As for the subsequent steps, the impurity ion implantation step of Example 1 (corresponding to FIG. 5) and the subsequent steps are followed.

As described above, in the present embodiment, after the desired damaged region is set by ion implantation, the substrate surface is heated by a laser beam or the like to recover the crystallinity, so that the damaged region is not damaged. The setting can be performed without considering the damage on the substrate surface.

[0022]

As described in detail above, according to the present invention, it is possible to form an impurity layer in a concentrated manner only at an arbitrary specific place, and the implantation distribution width and the implantation depth are independently controlled. Therefore, it becomes possible to further miniaturize and complicate the ion implantation of impurities, and it is possible to provide a method of manufacturing a semiconductor device with higher performance.

[Brief description of drawings]

FIG. 1 is a cross-sectional view for explaining a manufacturing process of an N-MOS transistor of a first embodiment.

FIG. 2 is a cross-sectional view for explaining a manufacturing process of the N-MOS transistor of the first embodiment.

FIG. 3 is a cross-sectional view for explaining the manufacturing process of the N-MOS transistor of the first embodiment.

FIG. 4 is a cross-sectional view for explaining the manufacturing process of the N-MOS transistor of the first embodiment.

FIG. 5 is a cross-sectional view for explaining a manufacturing process of the N-MOS transistor of the first embodiment.

FIG. 6 is a cross-sectional view for explaining the manufacturing process of the N-MOS transistor of the first embodiment.

FIG. 7 is a cross-sectional view for explaining the manufacturing process of the N-MOS transistor of the first embodiment.

FIG. 8 is a cross-sectional view for explaining the manufacturing process of the N-MOS transistor of the first embodiment.

FIG. 9 is a cross-sectional view for explaining the manufacturing process of the N-MOS transistor of the first embodiment.

FIG. 10 is a cross-sectional view for explaining the manufacturing process of the N-MOS transistor of the first embodiment.

FIG. 11 is a cross-sectional view for explaining the manufacturing process of the N-MOS transistor of the first embodiment.

FIG. 12 is a depth distribution of crystallinity in a substrate for adjusting a threshold voltage and forming a punch-through stopper all together.

FIG. 13 shows the dependence of the implantation distribution of 20 keV B ^{+ on} the silicon substrate, which is the crystallinity distribution of the substrate.

FIG. 14 is a cross-sectional view for explaining the manufacturing process of the N-MOS transistor of the second embodiment.

FIG. 15 is a cross-sectional view for explaining the manufacturing process for the N-MOS transistor of the second embodiment.

FIG. 16 is a diagram showing dependency of distribution half width on incident ion energy.

FIG. 17 is a diagram showing the dependence of peak depth on incident ion energy.

FIG. 18 is a diagram showing incident ion energy dependence of a distribution half width.

FIG. 19 is a diagram showing dependency of peak depth on incident ion energy.

FIG. 20 is a diagram showing an impurity concentration depth distribution chart for defining a distribution half width.

[Explanation of symbols]

1 P-type silicon substrate 2 Thermal oxide film 3 Nitride film 4 Mask layer 5 channel stopper 6 LOCOS area 7 Gate oxide film 8 gate electrodes 9 Source / drain region 10 Insulating film layer 11 contact holes 12 wiring 13a Low damage area 13b Highly damaged area 14 Punch through stopper 15 Electric field relaxation layer 16 Impurity ions for channel stopper formation 17 Ions for forming damaged areas 18 Source / drain formation impurity ions 19 Impurity ions for forming electric field relaxation layer 20 laser beam 21 Recrystallized layer

─────────────────────────────────────────────────── --- Continuation of the front page (56) References JP-A-2-183521 (JP, A) JP-A-3-262117 (JP, A) JP-A-4-715 (JP, A) JP-A 61- 26220 (JP, A) JP-A-57-34332 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21/265

Claims (4)

(57) [Claims] 1. A method of manufacturing a semiconductor device including a step of introducing an impurity into a semiconductor substrate by using an ion implantation method, wherein a damaged layer is formed in a region of a predetermined depth deeper than the surface of the semiconductor substrate, and the semiconductor is formed. A step of providing a crystallinity distribution in the depth direction in the substrate, and a step of implanting impurity ions under an angle condition that causes channeling to the semiconductor substrate to form a region of high impurity concentration in the region where the damaged layer is formed. And a first impurity ion implantation step of forming a region of low impurity concentration in a region shallower than the region in which the damaged layer is formed; and an angular condition deviated from an angular condition in which channeling occurs in the semiconductor substrate. And a second impurity ion implantation step of implanting impurity ions of a conductivity type different from that of the impurity ions of the first impurity ion implantation step. The method of manufacturing a semiconductor device according to. 2. The first impurity ion implantation step is MO
7. A step of forming a punch through stopper region and a threshold voltage adjusting region of an S transistor, and the second impurity ion implantation step is a step of forming a source / drain region of the MOS transistor. 1. The method for manufacturing a semiconductor device according to 1. 3. The first impurity ion implantation step comprises:
3. The method of manufacturing a semiconductor device according to claim 1, which is a step of implanting the impurity ions under an angle condition parallel to the 100> axis, the <110> axis, and the <111> axis. 4. The step of forming the damaged layer comprises Si ⁺
2. The step of forming the damaged layer by an ion beam of Ge or Ge.sup. ⁺ , And then recovering the crystallinity of a partial surface region by a laser beam to give the crystallinity distribution. Manufacturing method of semiconductor device.