JP3383129B2 - Wiring structure of semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring structure in a semiconductor device, and more particularly to a wiring structure of a wide portion. [0002] In recent years, with the miniaturization of semiconductor elements, wiring layers connecting elements have been finely processed, and so-called submicron wiring structures (wiring widths and wiring intervals of 1 μm or less) have been developed. Layer) is formed. However, if a heat treatment is performed after forming a wiring (for example, aluminum (Al) wiring) on a substrate during a manufacturing process of a semiconductor device, the Al crystal of the Al wiring becomes May grow partially abnormally. In particular, those that abnormally grow from the side wall portion of the Al wiring in a direction parallel to the substrate surface are called lateral hillocks. This lateral hillock is likely to occur on the side wall portion of the Al wiring where the width or area of the wiring is wide. this is,
This is because a greater stress is applied in the lateral direction to the side wall portion of the portion where the width or area of the wiring is large than to the side wall portion of the portion where the width is small. A large lateral hillock may grow to 1 μm or more, and may be electrically short-circuited with other adjacent structures such as Al wiring.
Since a semiconductor device in which a short circuit has occurred is a defective product, lateral hillocks have been a factor in lowering the yield of the semiconductor device. In addition, wirings such as power supply wirings through which a large amount of current flows and wirings requiring low resistance are required to have a wide width. In such a relatively wide wiring, in order to prevent a short circuit due to a lateral hillock, it is necessary to make the distance between adjacent wirings larger than the minimum processing size in that era. [0006] Incidentally, regarding the lateter hillock of the Al wiring, reference: (1985, "Symposium on VLS")
I Technology Digest of Technical Paper ", pp. 50-51). Therefore, it has been desired to realize a wiring structure capable of suppressing the occurrence of lateral hillocks. The wiring structure of the semiconductor device according to the present invention according to the present application has the following structural features. That is, the first wiring formed on the substrate and the second wiring
The first wiring is disposed adjacent to the second wiring, has a wider width than the second wiring, and has a side facing the second wiring. A recess for increasing the distance between the second wiring and the second wiring is formed in the second wiring .
The convex portion corresponding to the concave portion on the side opposite to the side facing the wiring of
Is formed . Here, the semiconductor underlayer includes not only a substrate in general but also a state in which an insulating film or the like is laminated on a substrate, for example. According to the wiring structure of the semiconductor device of the present invention, the side walls of the wiring structure have irregularities. As a result, the stress in the lateral direction of the side wall can be reduced. By relaxing the stress, the generation of lateral hillocks can be suppressed. Even if lateral hillocks are generated in a portion provided with irregularities, the lateral hillocks are mainly generated from the concave portions and are less likely to be generated from the convex portions. This is because, for example, the stress applied to the convex portion is smaller than the stress applied to the concave portion by the passivation film. In addition, when the wiring is provided on the passivation film, for example, the stress is applied to the side wall of the wiring by the passivation film. Therefore, it is not necessary to consider the occurrence of lateral hillocks. Therefore, the distance between the structure (for example, adjacent wiring) close to the wiring structure and the convex portion of the side wall portion is reduced to the minimum processing size of the era. A wiring structure can be provided. As a result, the wiring can be further integrated. Further, in a wiring structure having irregularities formed on one side wall, irregularities are formed on the other side wall so that the width of the wiring is constant, so that electromigration can be suppressed. . Referring to the accompanying drawings, an example of a wiring structure according to the present invention will be described below. It should be noted that the drawings referred to merely schematically show the shapes, sizes, and arrangements of the components so that the present invention can be understood. Therefore, the present invention is not limited only to the illustrated example. Although not shown in the drawings, the wiring portions are hatched in order to facilitate understanding of the invention. <First Reference Example> Referring now to FIG. 1, a first reference example of the wiring structure of the present invention will be described.
Examples will be described. FIG. 1A is a plan view for explaining a first reference example . FIG. 1B is an enlarged view of a portion surrounded by a circle indicated by Z in FIG. 1A. In a first reference example , in a semiconductor device,
A first wiring 12 having a width of about 5 μm is provided as a wiring structure on a Si substrate 10 as a semiconductor base. Further, a second wiring 14 having a width of about 1 μm is provided as a structure close to, that is, adjacent to, the first wiring 12 on the substrate 10. Each of the first and second wirings is formed on the substrate 10 with a thickness of 1000 .ANG.
Ａｌ of Al and 1000 Å of TiN are sequentially laminated. In the first reference example , the second reference
On the side wall portion 16 of the first wiring adjacent to the wiring 14, continuous rectangular irregularities are provided. This unevenness is preferably formed by using a conventionally known photolithography and etching technique. Further, the distance between the tip of the convex portion of the concavo-convex portion and the second wiring is set to a minimum processing dimension (for example, about submicron) so that the shortest distance between the first and second wirings does not become smaller than this minimum processing dimension. This is because a short circuit may occur from the viewpoint of processing accuracy even when lateral hillocks do not occur below the minimum processing size. As shown in FIG. 1B, the dimensions of the unevenness are, for example, a depth a = 1 μm, a width b of the concave portion = 1 μm, and a width c of the convex portion = 1 μm. Here, the depth of the unevenness refers to the height of the concave portion (hollow) and the height of the convex portion in the direction perpendicular to the side wall (when no unevenness is provided), and the width of the concave portion and the convex portion refers to the first wiring. Refers to the length of the concave portion and the convex portion in the direction along the direction in which. In the first reference example , the depth a of the unevenness a =
Although the depth was 1 μm, the depth of the unevenness was the height of the lateral hillock 18 (from the bottom of the recess to the tip of the lateral hillock) when the lateral hillock 18 was generated in the recess.
It is good to set it to the same or larger value as h. The specific dimensions may be set empirically based on the height h of the lateral hillock generated in the uneven portion. [0019] <First Embodiment> Hereinafter, with reference to FIG. 2, the first embodiment of the wiring structure of a semiconductor device of the present invention. FIG. 2A is a plan view for explaining the first embodiment. In the first embodiment , in a semiconductor device, a wiring structure of 5 μm is formed on a substrate 20 as a semiconductor base.
The first wiring 22 having a width of about m is provided. Also, the substrate 2
A second wiring 24 having a width of about 1 μm is provided as a structure close to, that is, adjacent to, the first wiring 22 on the zero. Both the first and second wirings have a thickness of 1 on the substrate 20.
A wiring layer is formed by sequentially laminating 000% of TiN, Al of 1000 to 7000% in thickness, and TiN of 1000% in thickness. In the first embodiment, the second wiring 2
A saw-toothed unevenness is provided on the side wall portion 26 of the first wiring close to 4. Further, the tip of the sawtooth-shaped tooth and the second wiring 2
The distance between the first and second wirings is set to a minimum processing dimension (for example, about a submicron) so that the shortest distance between the first and second wirings does not become smaller than the minimum processing dimension. This is because a short circuit may occur from the viewpoint of processing accuracy even when lateral hillocks do not occur below the minimum processing size. Further, in the first embodiment , the side wall portion 26a having the saw-toothed unevenness and the side wall portion 26a
To, by equipped irregularities corresponding to the irregularities, the width W ₁ of the first wiring portion held both side wall portions is constant. Here, the width of the wiring refers to the width of the wiring along a direction perpendicular to the direction in which the wiring extends (that is, the direction in which current flows). For example, the distance to the tip of the concave portion of the side wall portion 26a made of back-to-back and the convex portion from the tip of the convex portion of the side wall portion 26 (the deepest) corresponds to W _1. Usually, a large amount of current flows through a wide wiring. At this time, if the line width is not constant, electromigration is likely to occur in a place where the line width is narrow. In this regard, in the first embodiment, by a constant width W ₁ of the first wiring, it is possible to suppress the occurrence of electromigration. Second Embodiment A second embodiment of the wiring structure of the semiconductor device according to the present invention will be described below with reference to FIG. FIG. 3 shows the second participant.
FIG. 6 is a plan view for explaining a conventional example. In the second reference example ,
A case where wide wirings are brought close to each other will be described. In a second reference example , in a semiconductor device,
A first wiring 32 having a width of about 5 μm is provided as a wiring structure on a Si substrate 30 as a semiconductor base. Further, a second wiring 34 having a width of about 5 μm is provided as a structure close to, that is, adjacent to, the first wiring 32 on the substrate 30. Each of the first and second wirings is formed on the substrate 30 by TiN having a thickness of 1000 ° and a thickness of 1000 to 7000.
Ａｌ of Al and 1000 Å of TiN are sequentially laminated. In the second reference example , continuous rectangular irregularities are provided on the side wall portions 36 and 38 of the first and second wirings adjacent to each other. This unevenness
It is preferable to use a conventionally known photolithography and etching technique. In this embodiment, the depth and width of the unevenness are each 1 μm. The shortest distance between the concavities and convexities of the side wall portions 36 and 38 facing each other should not be smaller than the minimum processing dimension (for example, about submicron). This is because a short circuit may occur from the viewpoint of processing accuracy even when lateral hillocks do not occur below the minimum processing size. <Second Embodiment> A second embodiment of the wiring structure of the semiconductor device according to the present invention will be described below with reference to FIG. FIG. 4 is a plan view for explaining the second embodiment . In the second embodiment , a case will be described in which relatively wide wires are brought close to each other and the width of the wires is made constant. In the second embodiment , in a semiconductor device, a wiring structure of 5 μm is formed on a substrate 40 as a semiconductor base.
The first wiring 42 having a width of about m is provided. Also, the substrate 4
A second wiring 44 having a width of about 5 μm is provided as a structure close to, that is, adjacent to, the first wiring 42 on the zero. Each of the first and second wirings has a thickness of 1 on the substrate 40.
A wiring layer is formed by sequentially laminating 000% of TiN, Al of 1000 to 7000% in thickness, and TiN of 1000% in thickness. In the second embodiment , the side walls 46 and 48 of the first and second wirings adjacent to each other are provided with saw-toothed irregularities. In addition, the shortest distance between the concavities and convexities facing each other should not be smaller than the minimum processing dimension (for example, about submicron). This is because a short circuit may occur from the viewpoint of processing accuracy even when lateral hillocks do not occur below the minimum processing size. Further, in the second embodiment , the side wall portion 46 having the saw-toothed unevenness of the first wiring and the side wall portion 46a to be back-to-back are provided with the unevenness corresponding to the unevenness. 1st wiring width W ₁ of the portion sandwiched between
Is constant. Here, the width of the wiring refers to the width of the wiring along a direction perpendicular to the direction in which the wiring extends (that is, the direction in which current flows). For example, the distance to the tip of the concave portion of the side wall portion 46a made of back-to-back and the convex portion from the tip of the convex portion of the side wall portion 46 (the deepest) corresponds to W _1. Also, the side wall portion 48a to be back-to-back with the side wall portion 48 having the saw-toothed unevenness of the second wiring is provided with the unevenness corresponding to the unevenness, so that the portion sandwiched between the side wall portions is provided. the width W ₂ of the second wiring to the constant.
Therefore, in the second embodiment , the occurrence of electromigration in the first and second wirings can be suppressed. In each of the above-described embodiments, the present invention has been described with respect to an example in which a specific material is used and a specific condition is used. However, the present invention can be variously modified and modified. For example, in the above-described embodiment, the shape of the unevenness is rectangular or saw-toothed. However, in the present invention, the shape of the unevenness can be a desired shape including, for example, a waveform or an aperiodic shape. In each of the above embodiments, the wiring is made of Si.
However, in the present invention, wiring may be provided on an insulating film as a base, for example. According to the wiring structure of the semiconductor device of the present invention, unevenness is provided on the side wall of the wiring structure. As a result, the stress in the lateral direction of the side wall can be reduced. By relaxing the stress, the generation of lateral hillocks can be suppressed. Therefore, it is not necessary to consider the occurrence of lateral hillocks, so that the distance between the structure (for example, adjacent wiring) close to the wiring structure and the protrusion on the side wall portion is reduced to the minimum processing size of the era. A wiring structure can be provided. As a result, the wiring can be more integrated. Further, in the wiring structure having the unevenness on one side wall, the unevenness is provided on the other side wall so that the width of the wiring is constant, so that the occurrence of electromigration can be suppressed.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 (A) is a plan view for explaining a first reference example , and FIG. 1 (B) is a partially enlarged view of FIG. 1 (A). FIG. 2 is a plan view for explaining a first embodiment ; FIG. 3 is a plan view for explaining a second reference example ; FIG. 4 is a plan view for explaining a second embodiment ; [Description of Signs] 10, 20, 30, 40: Substrates 12, 22, 32, 42: First Wiring 14, 24, 34, 44: Second Wiring 16, 26, 26a, 36, 38: Side Wall 46 46a, 48, 48a: Side wall portion 18: Lateral hillock

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-63-66950 (JP, A) JP-A-62-160738 (JP, A) JP-B7-113965 (JP, B2) (58) Field (Int.Cl. ⁷ , DB name) H01L 21/3205 H01L 21/321 H01L 21/3213 H01L 21/768

Claims (1)

(57) Claims: 1. A semiconductor device comprising: a first wiring formed on a substrate; and a second wiring arranged adjacent to the first wiring. The wiring is wider than the second wiring, and has a recess formed on the side facing the second wiring to increase the distance between the wiring and the second wiring .
A projection corresponding to the recess on the side opposite to the side facing the second wiring
A wiring structure of a semiconductor device, wherein a portion is formed .