KR0156496B1 - Thin film pattern - Google Patents
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- KR0156496B1 KR0156496B1 KR1019940024155A KR19940024155A KR0156496B1 KR 0156496 B1 KR0156496 B1 KR 0156496B1 KR 1019940024155 A KR1019940024155 A KR 1019940024155A KR 19940024155 A KR19940024155 A KR 19940024155A KR 0156496 B1 KR0156496 B1 KR 0156496B1
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- G—PHYSICS
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- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
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- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
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- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
- G02F1/13629—Multilayer wirings
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
- G02F1/136295—Materials; Compositions; Manufacture processes
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Abstract
본 발명은 평판표시소자의 금속전극의 형성에 적합한 박막패턴의 적층구조를 개시한다.The present invention discloses a lamination structure of a thin film pattern suitable for forming a metal electrode of a flat panel display device.
금속전극을 절연층이나 기판등의 기층상에 적층하면 양자간의 열팽창 계수의 차이에 의해 금속전극이 분리되어 손상변형이 야기된다.When the metal electrode is laminated on a base layer such as an insulating layer or a substrate, damage to the metal electrode is caused by separation of the metal electrode due to the difference in thermal expansion coefficient between them.
본 발명에서는 기층에 웰을 형성하여, 그 상부에 형성되는 박막패턴의 일부가 이 웰내에 쐐기를 형성하도록 함으로써 부착성을 향상시켰다.In the present invention, the wells are formed in the base layer, and a portion of the thin film pattern formed thereon forms wedges in the wells, thereby improving adhesion.
Description
제1도는 박막패턴의 일례로서 TFT LCD의 버스라인을 보이는 단면도.1 is a cross-sectional view showing a bus line of a TFT LCD as an example of a thin film pattern.
제2도는 본 발명에 따른 버스라인을 보이는 단면도.2 is a cross-sectional view showing a bus line according to the present invention.
제3도는 그 분해 사시도.3 is an exploded perspective view thereof.
제4도는 본 발명의 다른 실시예를 보이는 분해 사시도이다.4 is an exploded perspective view showing another embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
S : 기판(substate) I : 절연층(dielectric layer)S: Substate I: Dielectric layer
M,M1,M2 : 금속전극 W,W' : 웰(Well)M, M1, M2: Metal electrodes W, W ': Well
G,G' : 쐐기(wedge)G, G ': wedge
본 발명은 박막(薄膜) 패턴(pattern)의 적층(積層)구조에 관한 것으로, 특히 평판 표시소자의 금속전극으로 된 버스라인(bus line)의 구현에 적합한 박막패턴의 적층구조에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a laminated structure of thin film patterns, and more particularly, to a laminated structure of thin film patterns suitable for realizing a bus line made of a metal electrode of a flat panel display device.
전자제품들의 경박단소(經薄短少)화 경향에 따라 IC나 LSI등 종래의 반도체 소자뿐 아니라 화상표시소자들도 평판화 되어 가고 있다. 평판표시소자들은 기능막(機能膜)들의 적층과 패터닝(patterning)로 이루어지는데, PDP나 LCD, EL등 다양한 종류의 평판표시소자들이 개발 및 응용되어가고 있다.With the trend toward thinner and shorter electronic products, image display devices as well as conventional semiconductor devices such as ICs and LSIs are becoming flat. The flat panel display devices are formed by stacking and patterning functional films, and various types of flat panel display devices such as PDPs, LCDs, and ELs have been developed and applied.
이러한 평판표시소자들은 고정된 패턴을 표시하는 세그먼트(segment)방식으로부터 래스터(raster)화상을 표시하는 매트릭스(matrix)방식으로 진전되어 왔는데, 최근 브라운관을 대체하여 고화질의 박형 표시소자를 구현하기 위해 더욱 대면적화되고 고정세(高精細)화 되어 가고 있다.These flat panel display devices have evolved from a segment method for displaying a fixed pattern to a matrix method for displaying raster images. It is becoming larger and more fixed.
이에 따라 평판표시소자의 단위 화소(pixel)의 크기는 점차 작아지고 전체적으로 단위화소의 수효가 증가되어, 이를 구성하기위해 형성되어야 할 기능막의 패턴은 더욱 미세해지고 복잡화되어 있다. 이에 따라 각 단위화소의 패턴이 복잡해질 뿐 아니라 이들에 구동전압을 공급하는 버스라인의 길이도 더욱 길어지게 된다. 이러한 길이의 증가는 버스라인의 단면적의 감소와 동시에 이루어지는 것이므로, 버스라인에서의 저항에 의한 전압강하가 커서 평판표시소자가 고정세화 될수록 신호지연이 현저하게 된다.As a result, the size of the unit pixel of the flat panel display device is gradually reduced and the number of unit pixels as a whole increases, so that the pattern of the functional film to be formed to make it is finer and more complicated. As a result, not only the pattern of each unit pixel is complicated, but also the length of the bus line that supplies the driving voltage to the unit pixel becomes longer. Since the increase of the length is coincident with the decrease in the cross-sectional area of the bus line, the voltage drop caused by the resistance in the bus line is so large that the signal delay becomes more significant as the flat panel display device becomes more precise.
이를 해결하기위해 저저항의 금속전극을 버스라인으로 사용하게 되었다. 예를들어 제1도에는 TFT LCD의 버스라인이 도시된 바, 기판(S)상의 절연층(I)위에 금속전극(M)이 형성되어 버스라인을 구성하게 된다.To solve this problem, low-resistance metal electrodes were used as bus lines. For example, in FIG. 1, the bus line of the TFT LCD is shown. The metal electrode M is formed on the insulating layer I on the substrate S to form a bus line.
그러나 금속전극은 도전성은 높으나 열이나 화학물질들에 대한 내구성이 약하다. 이에 따라 패터닝을 위한 식각(etching)공정이나 기능막들의 소성(燒成)등을 위한 열처리 공정에서 금속전극으로 된 버스라인은 쉽게 손상되거나 변형된다. 이러한 금속 버스라인의 손상은 그 길이가 연장되고 폭이 감소됨에 따라 더욱 심해지게 된다. 특히 전술한 TFT LCD에 있어서, 단위화소들의 어레이(array)로부터 외부전압을 접속하는 패드(pad)간에는 버스라인만이 길게 연장되므로 변형이나 손상등이 매우 현저하다.However, metal electrodes have high conductivity but poor resistance to heat and chemicals. Accordingly, the bus line made of a metal electrode is easily damaged or deformed in an etching process for patterning or a heat treatment process for firing functional films. The damage of these metal buslines becomes more severe as their length is extended and their width is reduced. In particular, in the above-described TFT LCD, since only the bus line extends between pads for connecting external voltages from an array of unit pixels, deformation or damage is very remarkable.
이러한 금속전극(M)의 손상변형에 있어서, 전극재질자체의 내구성의 문제는 보호층의 형성이나 후속공정의 조건의 조절등에 의해 어느 정도 해결될 수 있으나, 절연층(I)등 기층(基層)과의 접합성의 문제는 해결이 곤란하여 이 기층과의 접합성이 금속전극(M)의 손상변형의 주된 원인이 되고 있었다.In the damage deformation of the metal electrode (M), the problem of durability of the electrode material itself can be solved to some extent by the formation of a protective layer or the adjustment of the conditions of subsequent processes, but the base layer such as the insulating layer (I) The problem with the bonding property was difficult to solve, and the bonding property with the base layer was the main cause of the damage deformation of the metal electrode M.
즉 절연층(I)이나 기판(S)등의 기층상에 적층된 금속전극(M)은 열팽창계수의 큰 차이에 의해 열처리공정에 있어서 기층과의 접합면에 틈새가 발생되고, 이 틈새로 식각시의 부식액이나 세정시의 물등이 유입되어 그 손상변형이 더욱 심화되는 것이다.That is, the metal electrode M laminated on the base layer such as the insulating layer I or the substrate S has a large gap in the joint surface with the base layer in the heat treatment process due to the large difference in the coefficient of thermal expansion, and is etched by this gap. Corrosion liquid at the time and water at the time of washing flow in, and the damage deformation is intensified.
이러한 문제를 해결하기 위해 금속전극(M)을 형성할 페이스트(paste)내에 접합제를 다량 첨가하는 경우에는 금속전극(M)의 특성이 저하되어 바람직하지 못하며, 아몰포스상태의 금속을 증착시키는 경우 부착성의 문제는 해결되나 그 성막(成膜)비용이 현저하게 상승되어 반도체 소자가 아닌 평판표시소자에는 적용하기가 곤란하였다.In order to solve this problem, when a large amount of a binder is added to the paste to form the metal electrode M, the characteristics of the metal electrode M are deteriorated, which is not preferable, and in the case of depositing an amorphous metal The problem of adhesion was solved, but the film formation cost was significantly increased, making it difficult to apply to flat panel display devices other than semiconductor devices.
이와 같은 종래의 문제점을 감안하여 본 발명의 목적은 미세하고 복잡한 박막패턴의 적층시 그 부착성을 현저히 향상시킬수 있는 적층구조를 제공하는 것이다.In view of such a conventional problem, an object of the present invention is to provide a lamination structure that can significantly improve its adhesion when laminating fine and complex thin film patterns.
상술한 목적을 달성하기 위해 본 발명에 의한 박막패턴의 적층구조는 박막패턴이 형성될 기층에 다수의 웰(well)을 형성하고, 그 위에 박막패턴을 형성하는 것을 특징으로 한다.In order to achieve the above object, the laminated structure of a thin film pattern according to the present invention is characterized in that a plurality of wells are formed in a base layer on which a thin film pattern is to be formed, and a thin film pattern is formed thereon.
이와 같은 구성에 의하면 박막패턴의 일부가 기층의 웰내에 쐐기(wedge)와 같이 박히므로 열팽창의 반복등 외력에 의해 박막패턴이 분리되지 않게 된다.According to such a structure, a part of the thin film pattern is embedded in the well of the base layer like a wedge, so that the thin film pattern is not separated by external force such as repeated thermal expansion.
이러한 본 발명의 구체적 특징과 다른 이점들은 첨부된 도면을 참고한 이하의 바람직한 실시예의 설명으로 더욱 명확해 질 것이다.These specific features and other advantages of the present invention will become more apparent from the following description of the preferred embodiments with reference to the accompanying drawings.
제2도 및 제3도에는 특히 TFT LCD의 버스라인의 구성에 본 발명을 적용한 예가 도시되어 있다. 이 실시예에서 형성될 박막패턴은 금속전극(M)으로 기판(S)상의 절연층(I)위에 형성되는데, 이에 따라 기층은 절연층(I)이 된다.2 and 3 show an example in which the present invention is applied to the configuration of a bus line of a TFT LCD, in particular. The thin film pattern to be formed in this embodiment is formed on the insulating layer I on the substrate S by the metal electrode M, and thus the base layer becomes the insulating layer I.
절연층(I)에는 소정형태의 작은 웰(W)들이 적절한 간격으로 형성되어 있다. 이러한 웰(W)은 절연층(I)의 인쇄시 인쇄층간의 패턴변화에 의해 형성될 수 있으며, 또는 선별적 식각에 의해 이루어질 수 있는데, 선별적 식각에 가장 바람직한 방법은 드라이에칭(dry etching), 특히 레이저 에칭일 것이다.Small wells W of a predetermined type are formed in the insulating layer I at appropriate intervals. The well W may be formed by a pattern change between printing layers during printing of the insulating layer I or by selective etching. The most preferable method for selective etching is dry etching. , In particular laser etching.
한편 금속전극(M)은 이 절연층(I)상에 인쇄 또는 증착등의 방법으로 형성될 수 있는데, 특히 금속 페이스트로 인쇄하는 경우 금속 페이스트가 절연층(I)의 웰(W)내에 진입한뒤 소성등에 의해 경화됨으로써 쐐기(G)를 형성하게 된다.On the other hand, the metal electrode M may be formed on the insulating layer I by printing or vapor deposition. In particular, when printing with the metal paste, the metal paste may enter the well W of the insulating layer I. By hardening by back baking etc., the wedge G is formed.
이와 같이 웰(W)내에 박힌 쐐기(G)는 특히 절연층(I)과 금속전극(M)간의 횡변형에 대해 우수한 물리적 강도를 발휘하여 양자간의 분리를 방지한다. 이에 따라 금속전극(M)이 열처리 과정에서 절연층(I)이나 기판(S)보다 더 큰 팽창계수로 팽창하여도 금속전극(M)은 절연층(I)과 분리되지 않고 지지되고, 이에 따라 금속전극( M)의 손상변형이 방지되는 것이다.The wedge G embedded in the well W thus exhibits excellent physical strength against lateral deformation between the insulating layer I and the metal electrode M, thereby preventing separation between the two. Accordingly, even if the metal electrode M expands with a larger expansion coefficient than the insulating layer I or the substrate S during the heat treatment, the metal electrode M is supported without being separated from the insulating layer I. Damage deformation of the metal electrode M is prevented.
이와 같은 본 발명은 단순히 TFT LCD의 버스라인 뿐 아니라 여러가지 평판표시소자의 전극등 박막패턴의 적층시 적용되어 우수한 지지효과를 발휘할 수 있다.The present invention can be applied not only to the bus line of the TFT LCD but also to the lamination of thin film patterns such as electrodes of various flat panel display devices, thereby exhibiting an excellent supporting effect.
또한 TFT LCD의 적용시에도 여러가지 방식으로 응용될 수 있는데, 예를들어 제4도에는 두 이종(異種)금속에 의한 금속전극(M1,M2)들을 서로 적층하여 도전특성을 더욱 향상시키도록 한 구성이다. 여기서 하측의 제1금속전극(M1)은 절연층(I)에 형성된 웰(W)에 지입한 쐐기(G)로 지지되는데, 이 제1금속전극(M1)에도 웰(W')이 형성되어 상측의 제2금속전극(M2)의 일부가 이 제1금속전극(M1)의 웰(W')내에 쐐기G')를 형성하여 지지되고 있다. 이러한 구성은 절연층(I)과의 부착성뿐 아니라 금속전극(M1,M2)간의 부착성도 향상시켜 균일하고 신뢰성높은 전극구조를 제공하게 된다.In addition, the TFT LCD can be applied in various ways. For example, in FIG. 4, the metal electrodes M1 and M2 made of two dissimilar metals are laminated to each other to further improve conductivity. to be. Here, the lower first metal electrode M1 is supported by the wedge G inserted in the well W formed in the insulating layer I, and the well W 'is formed in the first metal electrode M1. A part of the upper second metal electrode M2 is supported by forming a wedge G 'in the well W' of the first metal electrode M1. This configuration improves the adhesion between the metal electrodes M1 and M2 as well as the adhesion to the insulating layer I to provide a uniform and reliable electrode structure.
이와 같이 본 발명은 기층상에 또는 복수층으로 적층되는 박막패턴의 부착성을 향상시켜 특히 평판표시소자의 미세전극패턴의 정밀한 형성에 큰 효과가 있다.As described above, the present invention improves the adhesion of the thin film pattern laminated on the base layer or in a plurality of layers, and thus has a great effect on the precise formation of the fine electrode pattern of the flat panel display device.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940024155A KR0156496B1 (en) | 1994-09-26 | 1994-09-26 | Thin film pattern |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940024155A KR0156496B1 (en) | 1994-09-26 | 1994-09-26 | Thin film pattern |
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| Publication Number | Publication Date |
|---|---|
| KR960011527A KR960011527A (en) | 1996-04-20 |
| KR0156496B1 true KR0156496B1 (en) | 1998-11-16 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019940024155A KR0156496B1 (en) | 1994-09-26 | 1994-09-26 | Thin film pattern |
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| Country | Link |
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| KR (1) | KR0156496B1 (en) |
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1994
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| KR960011527A (en) | 1996-04-20 |
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