JPS59107539A - Manufacture of multilayer wiring - Google Patents

Abstract

PURPOSE:To obtain the multilayer wiring which is securely connected by a method wherein the first wiring with a protruded part is formed on a substrate, an insulating film is superposed thereon, and the second wiring is superposed on the above by connecting it to the exposed protruded part. CONSTITUTION:An Al wiring layer 3 is selectively formed on the SiO2 film 2 located on an Si substrate 1, an Al layer 4 of the same thickness as above is superposed, and an underlying wiring is formed. Then, after an SiO2 film 5 has been coated on the above by performing a planar type bias sputtering and a flow discharge in Ar, an HF type dry etching process is conducted on the whole surface, and the upper surface of the wiring 4 is exposed. Subsequently, an upper wiring 6 of Al is provided perpendicular to the surface of paper, an SiO2 film 7 is formed again using a planar type bias-sputtering technique, and the multilayer wiring is completed. According to this constitution, an etching can be controlled easily in a highly accurate manner, because an interlayer insulating film is flatly formed, an interlayer connection part in the measurements same as the underlying wiring, and the allowable measurements of mask displacement can be unnecessitated, thereby enabling to improve the degree of integration of the multilayer wiring.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a method for manufacturing multilayer interconnections.A conventional method for connecting interconnections in a semiconductor device having a multilayer interconnection structure generally involves using an insulating film between each interconnection. The idea was to form a through hole and connect it. In forming the through holes, isotropic wet etching or anisotropic dry etching is used.

However, the formation of through holes by wet etching has the drawback that the degree of integration cannot be improved because the surrounding insulating film is etched at the same time as the insulating film is etched in the thickness direction. In addition, forming through holes by dry etching can improve the degree of integration, but it also causes sudden h
The disadvantage is that the formation of a large step makes it extremely difficult to deposit the upper wiring material.

In addition, there was a problem in that the etching-resistant mask for forming through-holes was misaligned with respect to the lower interconnection, and a stepped portion of the fray bus was likely to occur. This phenomenon became more pronounced as the degree of integration increased.

The presence of this stepped portion of the flexible path results in a drawback that it becomes extremely difficult to adhere the upper wiring material.

Furthermore, the interlayer insulating film formed on the lower wiring has a protruding shape. For this reason, when multi-layered, the protrusions grow and create steep steps.

This has the disadvantage that it becomes extremely difficult to deposit the upper wiring material.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing multilayer wiring, which eliminates the above-mentioned drawbacks, connects each wiring appropriately even when the degree of integration increases, and is suitable for multilayer wiring.

Hereinafter, the present invention will be described in detail along with one embodiment.

In addition, in all the figures, parts having similar functions are given the same symbols, and their explanations will not be repeated.

1 to 3 and 5 to 7 are sectional views of main parts of a semiconductor device in each manufacturing process for explaining one embodiment of the present invention, and FIG. The top view, Figure 8, is
1 and 7, and FIG. 9 is a top view of FIG. 7.

In this embodiment, a part of wiring for connecting semiconductor elements such as a memory is described, and a semiconductor device having a two-layer wiring structure of a lower wiring and an upper wiring will be described.

A half-Hf element (not shown) is formed on a semiconductor substrate using a diffusion layer or the like. As a semiconductor substrate, for example, it is made of silicon single crystal and has a resistance of 50 [Ω].
As shown in FIG.
An insulating film 2 of silicon dioxide (SiO2) is formed to a thickness of about 00A. This insulating film 2 may be formed by heat treatment of approximately 10f'>('I').

After the process shown in FIG. 1, a wiring material of aluminum (Aβ) is deposited to a thickness of 1 μmfA degrees by sputtering. A photoresist is formed thereon, and a mask is formed by removing the photoresist except for the connection portion with the upper wiring which will be formed later. When etching is performed using this mask and the mask is removed, a selective wiring section 3 can be formed as shown in FIG.

After that, a wiring layer of aluminum is deposited at about 1pm using sputtering technology, and a photoresist is formed on it to form a mask for the lower wiring of the first layer. Using this mask, etching and etching are performed. When you remove the mask,
As shown in FIG. 3, a lower wiring 4 can be formed. As a result, the lower wiring 4 at the connection portion with the upper wiring which will be formed later is formed in a protruding shape. FIG. 4 is a diagram of the semiconductor device of FIG. 3 viewed from above. .

After the step shown in FIG. 3, as shown in FIG. 5, an insulating film 5 of silicon dioxide is formed by Brehner type bias sputtering technique. The upper surface of this insulating film 5 is formed to be planarized. The planar bias sputtering technique generates glow discharge in an argon (Ar) W atmosphere, and this glow discharge generates argon ions (Ar).
+) wo arise. The Brehner bias sputtering technique accumulates an insulating film, but at the same time it also has an etching effect using argon ions. This etching effect is
This is particularly noticeable in protrusions and corners, where the etching effect is stronger than the accumulation.

Therefore, as shown in FIG. 5, the protrusions of the insulating film 5 remain in stages a and b, but are flattened in stages C. This insulating film 5 can be flattened by forming it to a thickness of about 2.5 μm.

After the step shown in FIG. 5, as shown in FIG. 6, the entire surface is dry-etched using, for example, fluorine, to expose the upper surface or upper surface portion of the lower wiring 4 at the connection portion with the upper wiring that will be formed later. The insulating film 5 is etched so as to be etched.

After the step shown in FIG. 6, as shown in FIG. 7, a second layer of upper wiring 6 is formed using aluminum wiring material. The thickness of this lower wiring 6 is about 1 μm, and is formed perpendicularly to the plane of the paper.
It can be formed using planar bias sputtering technology. Further, as the insulating film 7, nitride (Si
, N4) or phosphor glass for protection. Through these series of steps, the semiconductor device of this embodiment is completed.

FIG. 8 is a sectional view taken along line x-x' of the completed semiconductor device of FIG. 7, and FIG. 9 is a view of the semiconductor device of FIG. 7 viewed from above.

It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without changing the gist thereof. For example, in the above embodiments, a semiconductor device having a two-layer interconnection structure is described, but a semiconductor device having a multilayer wiring structure of three or more layers may be described. Further, although aluminum is used as the wiring material, wiring materials such as polycrystalline silicon, high melting point metal such as molybdenum (Mo), silicide, etc. may also be used.

As explained above, according to the present invention, it is possible to form the connection portion with the upper wiring at the same time as forming the lower wiring,
There is no occurrence of frebus step portions. Furthermore, the problem of adhesion of wiring material at the through-hole opening is eliminated. Therefore, the connection between the lower wiring and the lower wiring can be made reliably, and a highly reliable multilayer wiring can be provided.

Further, even if a multilayer arrangement is formed, the insulating film between each wiring is flattened. This eliminates the protruding growth of the interlayer insulating film that occurs due to the formation of conventional multilayer wiring. Therefore, there is no problem of adhesion of the upper wiring material, and multilayer wiring can be easily provided.

Furthermore, conventionally, when etching a wiring layer, a portion of the wiring layer at the protruding portion of the interlayer insulating film may remain. For this reason, as the degree of integration increases, adjacent wirings that are close to each other may be short-circuited due to the encroachment.
·Ta. However, since the interlayer insulating film is planarized, etching can be controlled easily and accurately, and the above-mentioned problems can therefore be solved.

Furthermore, since the connection between wiring layers can be formed with the same dimensions as the lower wiring, there is no need to take allowable dimensions in consideration of conventional mask misalignment. Therefore, the degree of integration can be improved.

[Brief explanation of the drawing]

1 to 3 and 5 to 7 are cross sections of main parts of a semiconductor device in each manufacturing process for explaining one embodiment of the present invention, and FIG. 8 is a sectional view taken along line xx' in FIG. 7, and FIG. 9 is a top view of FIG. 7. ]...Semiconductor substrate, 2,5.7...Insulating film, 3...
- Selected wiring section, 4...lower wiring, 6...upper wiring. Figure 1? / Figure 2 Figure 3 Figure 4 Figure J Figure 5 Figure 6 Figure 7 Figure X

Claims (1)

[Claims] 1. A step of forming a first wiring having a protrusion on a substrate, a step of forming an insulating film so that the upper surface of the protrusion is exposed, and a step of forming a first wiring having a protrusion on the substrate. 1. A method of manufacturing a multilayer interconnection comprising the step of forming a second interconnection so as to connect the second interconnection. 2. A step of forming a first wiring having a protrusion on the substrate-A, a step of forming an insulating film so that the upper surface of the protrusion is exposed, and a step of forming a first interconnect with a protrusion so as to connect to the exposed protrusion. 2
1. A method of manufacturing a multilayer wiring comprising a step of forming a wiring, wherein the first wiring is formed by overlapping a plurality of conductive materials.