JP3373296B2 - Logic simulation device for integrated circuits - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic simulation device for an integrated circuit, and more particularly to a logic simulation device having an error message filtering function.

[0002]

2. Description of the Related Art A semiconductor integrated circuit is a large-scale circuit integrated in a small space by a miniaturization technique.
Its internal structure is very complicated. In recent years, such integrated circuits have been designed by an efficient method using a computer. The technology essential for integrated circuit design is the logic simulation technology. Normally, from the stage where the integrated circuit was designed,
Up to the stage of actually manufacturing a semiconductor chip, logic simulation is performed many times, and inconvenient portions, design changes are made each time.

A general logic simulation apparatus is constructed by incorporating software for logic simulation into a general-purpose computer, and based on design data of an integrated circuit to be simulated, this integrated circuit is executed on a computer. It is operated in a pseudo manner and the result is output. That is, an output signal predicted to be obtained when a predetermined input signal is given to this integrated circuit is simulated by the logic simulation device. Normally,
A time-varying output signal is produced for a time-varying input signal. A general logic simulation device also has a function of outputting a predetermined error message. That is, when an operation that violates a predetermined design condition occurs inside the logic circuit, this is detected as an error, and a message indicating the error occurrence location and the occurrence time is output together with the error content. Usually, an error message is displayed on the screen of a display device, or an error message is printed on the paper by a printer. The designer can recognize that there is a defect in the design based on this error message, and will take measures such as design change if necessary.

[0004]

The error generated as a result of the logic simulation is gradually eliminated as the design is changed. However, in the initial stage of design, all errors tend to occur everywhere, and the result of the logic simulation is filled with many error messages. Of course, the individual error messages output in this way serve to provide important information for taking measures such as design changes, but
Even with the same error message, there are various error messages from a message indicating the occurrence of a serious error to a message indicating the occurrence of a minor error. In the case of a minor error message, the operation of the entire circuit will not be affected even if no design change is made, and it can be safely ignored. On the other hand, in the case of a serious error message, it may be necessary to change the fundamental circuit design, and if it is overlooked, it may cause a serious trouble in a later process.

However, in the conventional logic simulation apparatus, since all of these various error messages are output without distinction, a large number of minor error messages cover up a serious error message, and a serious error message is buried. There was a high possibility that the mistake of overlooking the item would occur. Also, the result of the logical simulation itself was difficult to see.

Therefore, an object of the present invention is to provide a logic simulation device for an integrated circuit having a filtering function for masking unnecessary error messages so that they are not output.

[0007]

[Means for Solving the Problems]

(1) According to a first aspect of the present invention, in a logic simulation device for an integrated circuit, which performs a logic simulation on an integrated circuit based on predetermined design data, a predetermined input signal is applied to the integrated circuit to be simulated. Sometimes, a logic simulator unit that outputs a predetermined output signal or a predetermined error message that may be output from this integrated circuit as line-by-line character string data, and 1 of the character string data output from this logical simulator unit. A data storage unit configured by arranging n data cells capable of storing rows and defining a series of steps from the first-stage data cell to the n-th data cell And n flag cells defined corresponding to each data cell are arranged,
A flag storage unit in which stages having a series of orders from the flag cell of the first stage to the flag cell of the nth stage is defined, and the data in the data cell of the nth stage is output from the data storage unit, The data in the data cells in the stages (n-1) to (n-1) are transferred to the data cells in the stages 2 to n, and the data for one row output from the logic simulator section is transferred to the first stage. The data transfer processing for one stage of fetching in the data cell of the first stage, the flag in the flag cell of the nth stage are output from the flag storage unit, and the flag cell of the first to (n-1) th stages Each flag in the second to nth stages
The transfer processing unit that performs the one-stage flag transfer process of shifting to the flag cell of the first stage and setting the flag indicating the unmasked state in the flag cell of the first stage and the logic simulator unit output Among various error messages, for each error message that needs to be masked, a predetermined keyword included in the error message, a line range occupied by the character string data forming the error message, and the error message are included in the error message. A condition setting section for setting a predetermined mask condition that a predetermined parameter should take, and a condition setting in the character string data for one line stored in the kth data cell preset as a checkpoint. Check whether the keyword set in the section is included, and if it is included,
For the error message that contains this keyword, identify the data cell that stores this error message by referring to the line range that is set in the condition setting section, and specify the data cell that is stored in this identified data cell. By comparing with a predetermined mask condition set in the condition setting unit, it is determined whether or not this error message should be masked, and if it is determined that the error message should be masked, it corresponds to the specified data cell. Only when the flag output from the flag storage unit and the mask determination unit that sets the flag indicating the masked state in the flag cell is the flag indicating the non-masked state, the flag is output from the data storage unit in synchronization with this flag. And a mask execution unit that outputs the data as data to be finally presented.

(2) A second aspect of the present invention is the above-mentioned first aspect.
In the logic simulation device for an integrated circuit according to the aspect of the present invention, the keyword set by the condition setting unit is included in the character string data for one row stored in the kth data cell by the inspection in the mask determination unit. If it is found that the error message including this keyword has reached the (k + 1) th data cell, the transfer processing unit executes the data transfer processing and the flag transfer processing for the number of stages required. It is something that is done.

(3) A third aspect of the present invention relates to the above-mentioned first aspect.
Alternatively, in the logic simulation apparatus for an integrated circuit according to the second aspect, the error occurrence location and / or the error occurrence time is used as the mask condition set in the condition setting unit, and the error occurrence location or the error occurrence time in the error message is used. The position of the information to be shown is set as a relative position with respect to the line containing the keyword.

[0010]

[Operation] In the logic simulation device for an integrated circuit according to the present invention, the character string data output from the logic simulator section is output after passing through the data storage section. In this data storage unit, there are n stages of data cells capable of storing the character string data of a unit row, and the characters input from the first stage in the so-called FIFO (First In First Out) format. The column data is sequentially transferred one stage at a time and is output from the nth stage. On the other hand, the keyword included in the error message to be masked is set in the condition setting section. When this keyword is found in the character string data transferred in the data storage, the parameter is checked for the error message containing this keyword, and when this parameter meets the specified mask condition, this error message is displayed. A flag indicating a masked state is set in the corresponding character string data. In this way, of the character string data output from the logic simulator unit, a flag indicating a masking state is set for the data to be masked in the process of passing through the data cell of the FIFO format. Therefore, if the character string data output from the data storage unit of this FIFO format is masked so as not to be output, the error message not necessary It is possible to realize a logic simulation device for an integrated circuit having a filtering function that masks and does not output.

[0011]

The present invention will be described below based on illustrated embodiments. FIG. 1 is a block diagram showing the basic configuration of a logic simulation apparatus for an integrated circuit according to an embodiment of the present invention. The main constituent elements of this logic simulation apparatus are a logic simulator unit 10, a data storage unit 20, a flag storage unit 30, a transfer processing unit 40, a condition setting unit 50, a mask determination unit 60, and a mask execution unit 70. Of these components, the logic simulator unit 10 can use the conventional general logic simulation device as it is. That is, the logic simulator unit 10
A device for performing a logic simulation on an integrated circuit based on predetermined design data, and when a predetermined input signal is given to the integrated circuit to be simulated, a predetermined circuit that will be output from this integrated circuit. It has a function of outputting an output signal or a predetermined error message as character string data in units of lines. The feature of the present invention is that the data storage unit 20, the flag storage unit 30, the transfer processing unit 40, and the condition setting are provided in order to allow the logic simulation device (the logic simulator unit 10) that has been generally used in the past to have a filtering function. The point is that new constituent elements such as a section 50, a mask determination section 60, and a mask execution section 70 are added.

When a predetermined logic value is given to the logic simulator unit 10 as an input signal, a predetermined logic value corresponding to this is obtained as an output signal. At this time, if any error occurs, an error message will be output together with the output signal. Such output signals and error messages are normally output from the logic simulator unit 10 as character string data in units of lines. Each character string data in units of rows is sent to the mask execution section 70 through the data storage section 20. The data storage unit 20 starts from a data cell (n boxes in which the characters “data” are described in FIG. 1) capable of storing one line of the character string data output from the logic simulator unit 10. It is configured. A total of n data cells are prepared, and stages having a series of order from the first-stage data cell to the n-th stage data cell are defined. The flag storage unit 30 also includes n flag cells (“flag” in FIG. 1) defined corresponding to each data cell.
And n boxes in which the letters are written) are defined, and similarly to the data cells, stages having a series of orders from the flag cell of the first stage to the flag cell of the nth stage are defined. .

The transfer processing section 40 performs a process of transferring the data and the flag stored in the data cell and the flag cell to the next stage (the stage immediately above in FIG. 1).
To be more specific, the transfer processing unit 40 executes 1
The transfer process for the stage is the following processes from to. The data in the data cell of the nth row is masked by the mask execution unit 7
At the same time, the flag in the flag cell of the nth stage is output to the mask executing section 70. The respective data in the data cells in the first to (n-1) th stages are moved to the data cells in the second to nth stages, respectively, and at the same time, the first to the (n-1) th stages. The respective flags in the flag cells of the second stage are moved to the flag cells of the second to nth stages (in short, the respective data and the respective flags are moved to the next higher stage). The data for one row output from the logic simulator unit 10 is fetched into the first-stage data cell, and a flag indicating the non-masked state is set in the first-stage flag cell.

In short, the data for one row output from the logic simulator unit 10 is sequentially transferred from the data cells of the first stage to the data cells of the nth stage and is given to the mask executing unit 70. At this time, 1 for each data
The flag is defined so as to correspond to the pair 1, and the flag is also transferred at the same time when the data is transferred. This flag is for indicating whether or not to mask the data, and the non-mask flag "0" is added to the data taken into the first-stage data cell for the time being. Then, as will be described later, when passing the vicinity of the checkpoint defined in the k-th stage, the mask determination unit 60 makes a determination, and the data determined to be “masked” is not The mask flag “0” is changed to the mask flag “1”.

The condition setting section 50 is a section for setting conditions for the judgment by the mask judgment section 60. Here, among the various error messages output by the logic simulator unit 10, for some error messages A, B, and C that need to be masked, the predetermined keyword 51 included in the error message and the error message are described. A line range 52 occupied by the constituent character string data and a predetermined mask condition 53 to be taken by a predetermined parameter included in the error message are set. Mask determination unit 6
0 performs the following determination processing based on the setting conditions in the condition setting unit 50. First, it is checked whether or not the keyword 51 is included in the character string data for one row stored in the kth data cell set in advance as a checkpoint. If the keyword 51 is included, by referring to the row range 52 for the error message including the keyword 51, the data cell in which the error message is stored is specified, and the data cell is stored in the specified data cell. It is determined whether or not this error message should be masked by comparing the specified data with a predetermined mask condition 53, and if it is determined that the error message should be masked, the flag cell corresponding to the specified data cell is selected. The process of setting the mask flag “1” is performed. The determination process will be described in detail later with reference to a specific example.

The mask execution unit 70 executes the final mask processing. The mask execution unit 70 is simultaneously supplied with the data from the n-th stage data cell and the flag from the n-th stage flag cell. When the given flag is the non-mask flag “0”, the data given in synchronization with this is output as the data to be finally presented, and the given flag is the mask flag “1”. If it is, the given data is masked and not output. In other words, only the data to which the non-mask flag “0” is added is output from the mask execution unit 70,
The data to which the mask flag “1” is added is masked and is not output. Thus, it becomes possible to output an error message having a filtering function.

Although the basic configuration of the logic simulation apparatus has been described above, each of these components is actually realized by using a computer. For example, the data storage unit 20 and the flag storage unit 30 can be configured by using a temporary storage device such as a RAM in the computer, and the condition setting unit 50 uses a storage device such as a magnetic disk connected to the computer. Can be configured. Further, each element such as the transfer processing unit 40, the mask determination unit 60, and the mask execution unit 70 is a CPU of this computer and this CP.
It can be realized by software for causing U to execute each operation.

Next, the operation of the logic simulation apparatus will be described in detail with reference to a concrete example. Here, a case where an output as shown in FIG. 2 is obtained from the logic simulator unit 10 will be described as an example. As described above, the logic simulator unit 10 has a function of outputting the output signal and the error message as character string data in units of lines. In Figure 2, the number shown in the left column under the heading "Number of lines" is
It is not the data actually output from the logic simulator unit 10, but the line number given for convenience of explanation. Therefore, the data actually output is "0" in the first line.
0000 ”, data such as“ 100 0011 ”in the second line, and“ # time = 5 ”in the seventh line.
30 ns. Data such as ". Here, the data with # added to the beginning of the line is an error message, the data with @ added to the beginning of the line (24th line) is the end character string, and the other data is the output signal. The numerical value of the first half of each output signal shows the time (time), and the numerical value of the latter half shows the output logical value (OUT). For example, the data "0000" in the first line is the time 0ns.
, The output logical value "0000" is obtained, and the data "100 0011" on the second line is the time 100n.
In s, the output logical value “0011” is obtained. In this embodiment, the output logic value is obtained as a 4-bit signal and changes with time.

If no error occurs in the integrated circuit which is the object of the logic simulation, the logic simulator section 10 outputs only the output signals as shown in the first to sixth lines of FIG. 2, but the error occurs. In each case,
2nd to 9th lines, 12th to 14th lines, 19th to 21st lines in FIG.
The error messages 1, 2, and 3 shown in the line are output. When all the steps of the logic simulation are completed, the termination character string "@end" as shown in the 24th line of FIG. 2 is output. The format of the error message and the termination character string varies depending on the logic simulator unit 10 used, but in the example shown in FIG. 2, the error messages 1, 2, and 3 are all 3
The line is a set of error messages, the first line shows the error occurrence time, the center line shows the error type, and the last line shows the error occurrence point. For example, the first line (7th line) of error message 1
Indicates that the error occurrence time is at the time of 530 ns, and the middle line (8th line) indicates “Setup vi
"Olation", and the last line (9th line) shows that the error location is the pin "A [3]" of the element with instance name "U1". Shows. The first line (12th line) of the error message 2 indicates that the error occurrence time is the time 73
It indicates that the time is 0 ns, and the middle row (first
The third line) indicates that the type of error is "address unknown", and the last line (14th line) is
It indicates that the error occurrence location is the pin "A [0]" of the element having the instance name "U2". Similarly, the first line (19th line) of error message 3 is
This indicates that the error occurrence time is at the time of 1150 ns, and the middle line (20th line) shows "Setup vi
"Olation", the last line (21st line) shows that the error location is the pin "A [3]" of the element with instance name "U2". Shows.

Here, the error messages 1 and 3 are
All are the same type of error message as "Setup violation", and this type is called "error message A" here. On the other hand, the error message 2 is another type of error message called "address unknown", and this type is called "error message B" here. Although the error messages 1 and 3 belong to the same error message A, the error occurrence time and the error occurrence location are different. In reality, more kinds of error messages are prepared, and a large number of error messages are output in a mixed manner in the output signal. However, these error messages include both serious ones and minor ones, and if all of them are output without distinction, the serious error messages will be overwritten by the minor error messages and will be overlooked. As mentioned above, there is a risk that it will happen. The filtering function according to the present invention masks a minor error message so that it is not output and selectively outputs the error message.

Now, the operation of the logic simulation apparatus shown in FIG. 1 will be described in detail with reference to the flow chart of FIG. Here, on the premise that the logic simulator unit 10 outputs a specific output signal and error message as shown in FIG. 2 as character string data in units of lines,
The following description will be given.

First, in step S1 of the flowchart of FIG. 3, condition setting for the mask is performed. This is a work for the designer to determine which error message is important and which error message is minor, and specify the error message to be masked. Here, an example in which the type of the error message A described above is masked as a minor error message will be described. In this case, in the condition setting unit 50, for the error message A that needs to be masked, a predetermined keyword 51, a line range 52 occupied by the character string data forming this error message, and a predetermined range included in this error message. Predetermined mask condition 5 that the parameters of
3 will be set.

FIG. 4 is a diagram showing the conditions for the error message A set in this way. Here, the character string "Setup violation" is set as the keyword 51.

A numerical value of "-1 to 1" is set as the line range 52, which indicates the positions of the start line and the end line of the character string data over the three lines forming the error message A. , Relative to the line containing the keyword. Ie line range 5
The number "-1" in 2 means that the start line of this error message is the line of "number of lines-1" containing the keyword (that is, the line immediately before the line containing the keyword). The number "1" in the line range 52 indicates that the end line of this error message is the line "number of lines + 1" containing the keyword (that is, one of the lines containing the keyword). Later line). The error messages 1, 2, and 3 shown in FIG. 2 each consist of all three lines, and since the keywords are included in the central line, the line range 52 is "-1 to 1".
However, depending on the type of error message, various types such as all four lines, all five lines, etc. are used, and the character string in the center line is not always set as a keyword. This line range is not limited to 5
2, various settings are made for each error message type.

As the mask condition 53, in this example,
Two conditions, "error occurrence location" and "error occurrence time" are set. The element having the instance name "U1" is specified as the "error occurrence location" that is the first condition (in this example, no pin is specified), and the second condition "error occurrence time" is specified. as,
The periods of "between 0 and 600 ns" and "after 1000 ns" are designated. Then, in this example, when both of these two conditions are satisfied, it is determined that the error message is "the mask condition is satisfied". In other words, an error occurs in the element with the instance name “U1”, and the error occurrence time is
The mask condition is satisfied only when it is “between 0 and 600 ns” or “after 1000 ns”.

After all, when it is determined whether or not to mask by the condition setting for the error message A as shown in FIG. 4, the keyword "Setup violation" is included and the line range "-1 to 1" is included. An error message whose content described in (1) satisfies the above-mentioned mask condition is judged to be "maskable". Specifically, the error messages 1, 2 shown in FIG.
Error messages 1 and 3 of 3 are "Setup violatio
Although the keyword "n" is included, only the error message 1 satisfies the above mask condition (error message 3 does not satisfy the condition of the error occurrence location). Of course, the setting in the condition setting unit 50 is performed based on the free will of the person who uses the logic simulation apparatus, and any condition setting may be performed.

By the way, the contents of the condition setting as shown in FIG. 4 are actually given to the computer as the description as shown in FIG. 5 in this embodiment. The character string "Setup violation" at the head of the description shown in FIG. 5 indicates the keyword 51, and the character string (-11) following the keyword indicates the line range 52. Next, (ins
The character string t 15) indicates that the instance name is specified as the error occurrence point, and the position of the information indicating the instance name is a relative position with respect to the line including the keyword. Specifically, the numerical value “1” following the character string “inst” indicates the (number of lines including the keyword + 1) line, and the numerical value “5” following this is the line. Of 5
It points to the word (the word is a group of words separated by white space). For example, applying this to error message 1 in Figure 2, "Setup violation
Since the keyword "" is included in the eighth line, the information indicating the instance name is the character "U1" in the fifth word of the (8 + 1) th line. Similarly, the next character string of (time -14) is a character string indicating the position of the information indicating the error occurrence time as a relative position to the line containing the keyword. In particular,
The numerical value "-1" following the character string "time" is
It indicates the line (the number of lines including the keyword-1), and the numerical value "4" following this indicates the fourth word of the line. For example, applying this to error message 1 in Figure 2, "Setup violation
Since the keyword "" is included in the 8th line, the information indicating the error occurrence time is the character "530" in the 4th word of the (8-1) th line.

The character string on the second line in FIG. 5 is the set value of the mask condition. That is, the character string “U1” indicates an instance name that satisfies the condition as an error occurrence point, and is followed by (0 600) and (1000 −).
The character string indicates a period that satisfies the condition as the error occurrence time. In this way, if the conditions as shown in FIG. 5 are set in the condition setting unit 50, when the actual error messages 1, 2, 3, etc. as shown in FIG. It will be understood that the decision "whether or not" can be made uniquely. That is, it is checked whether or not the predetermined keyword 51 is included in the error message, and if the predetermined keyword 51 is included, the error occurrence location and the error occurrence time described in the predetermined position of the error message are checked. It is only necessary to recognize and judge whether or not these satisfy the conditions shown in the second line of FIG.

Now, in step S1 in the flow chart shown in FIG. 3, when the above-mentioned condition setting is completed, the transfer / output processing having a filtering function is finally executed. Here, for convenience of explanation, this process will be concretely described for the case of n = 5 (that is, the case where the data storage unit 20 is composed of five-stage data cells and the flag storage unit 30 is composed of five-stage flag cells) I will show it to you. The checkpoint is defined in the third row.

First, in step S2, the data storage unit 20 and the flag storage unit 30 are initialized. FIG. 6 shows the state immediately after such initialization. In this embodiment, a predetermined "empty data" is set as an initial value for each data cell forming the data storage unit 20, and an initial flag "-1" is set as an initial value for each flag cell forming the flag storage unit 30. I am trying to set it as. As described above, in this embodiment, the non-mask flag "0" or the mask flag "1" is put in each flag cell, but the initial flag "-1" is not the third flag. Is a flag,
It indicates that the corresponding data cell is not the original data but “empty data”.

In the next step S3, the transfer processing unit 40 performs the transfer processing for one stage. That is, as shown in FIG. 7, the first-stage data cell shown in FIG.
The data "00000" of the row is fetched, and the non-mask flag "0" is set in the flag cell of the first stage. At this time, the "empty data" in the fifth-stage data cell and the initial flag "-1" in the fifth-stage flag cell are both sent to the mask execution unit 70.
The mask executing unit 70 determines that the “empty data” sent is not the original data by the initial flag “−1”, and executes the mask process (the process of discarding the sent data without outputting it). To do.

Then, in step S4, the checkpoint data is the end character string (in this example, "@en
It is determined whether the character string is "d"). At this point,
Since the checkpoint contains "empty data",
A negative determination is made, and the process proceeds to step S5. In this step S5, the checkpoint data is a keyword (in this example, “Setup vi
It is determined whether or not the character string "olation" is included. After all, at this point, the checkpoint is "empty data"
Is included, a negative judgment is made, and step S
Return to 3.

By repeating the loop processing of steps S3, S4 and S5 in this manner, eventually, as shown in FIG. 8, the original data is taken in all of the five-stage data cells. At this time, the non-mask flag is set in each flag cell. Since the keyword has not yet appeared at the position of the checkpoint, steps S3 and S are still executed.
The loop of S4 and S5 will be repeatedly executed.
FIG. 9 shows a state in which transfer is performed for three stages from the state of FIG. This is a state in which the 4th to 8th lines shown in FIG. 2 are fetched. At this point, the data of the first to third lines shown in FIG. 2 have already been sent to the mask execution section 70. At this time, since the non-mask flag "0" is added to all of these data, the mask execution unit 70 outputs these data as they are. That is, the mask processing is not executed.

Now, when the transfer of two stages is further carried out from the state shown in FIG. 9, the state shown in FIG. 10 is obtained. This is a state in which the sixth to tenth lines shown in FIG. 2 are captured. In this state, the determination regarding the end character string in step S4 is negative, but the determination regarding the keyword in step S5 is affirmative. That is, the keyword "Se
The string "tup violation" is included. Therefore,
From step S5 to step S6, the keyword "Setu
A determination is made as to whether error messages containing "p violation" should be masked. The method of this determination is as described above. That is, it can be recognized from the description (-11) shown in FIG. 5 that the line range of the error message including "Setup violation" is from one line before to one line after the line including the keyword. And (ins
From the description of t 1 5), it can be confirmed that “U1” shown in the fifth word one line after the line containing the keyword is the error occurrence point, and this is the setting condition of “U1” (2 in FIG. 5). It can be confirmed that it matches the description of the line). Further, from the description of (time-14), it can be confirmed that "530" shown in the fourth word one line before the line containing the keyword is the error occurrence time, which is the setting condition "0-600". It can be confirmed that it matches (the description in the second line of FIG. 5).

Thus, for error message 1,
When the mask determination unit 60 determines that the mask should be performed, the mask flag "1" is set in the flag cells in the row range in step S7. In the case of this example, the flag cells of the second to fourth stages become "1", and the state of FIG. 10 changes to the state of FIG. Here, the process returns to step S3 again, and the transfer process for one stage is repeatedly executed. FIG. 12 shows the state at this time. When transitioning from the state of FIG. 11 to the state of FIG. 12, data “500 1111” is sent to the mask execution unit 70, but this data is masked because the non-mask flag “0” is attached. It is output as it is.

Here again, the loop of steps S3, S4 and S5 is repeatedly executed. 13 is the same as FIG.
It shows a state in which the transfer of three stages is further performed from the state shown in FIG. When shifting from the state of FIG. 12 to the state of FIG.
The ninth line will be sent to the mask execution unit 70.
Since the mask flag “1” is added to the data for these three lines, the mask processing is executed in the mask execution unit 70 and is discarded without being output.
In this way, the mask determination unit 60 “should be masked”.
The mask process is executed by the mask execution unit 70 for the error message determined to be.

By the way, the error message 2 shown in FIG.
Contains a character string "address unknown", but in this embodiment, since this character string is not set as a keyword, the flag is rewritten even if the error message 2 passes the checkpoint. There is no. Therefore, the loop of steps S3, S4 and S5 is repeatedly executed, and the error message 2 is output from the mask execution unit 70 without being masked.

After that, in step S5, the keyword "Setup violation" is found again in FIG.
2, the 18th to 22nd lines in FIG. 2 are fetched. In this state, the determination regarding the keyword in step S5 is affirmative. That is, the character string "Setup violation" that is the keyword is included in the data cell in the third row that is the checkpoint. Therefore, the process proceeds from step S5 to S6, and the error message 3 including this keyword "Setup violation"
A determination is made whether or not to mask. As described above, in the judgment of the error message 3, the condition of the error occurrence time matches, but the condition of the error occurrence point does not match. Therefore, with respect to the error message 3, the mask determination unit 60 determines that “it should not be masked”. Therefore, step S7 is not executed, the flag added for the error message 3 is still the non-mask flag “0”, and even if it is sent to the mask executing unit 70, it is output as it is without being masked. become.

When the character string up to the end character string on the 24th line shown in FIG. 2 is taken in, the character string is no longer output from the logic simulator unit 10. In this case, as shown in FIG. 15, "empty data" is taken in the first-stage data cell, and the initial flag "-1" is set in the first-stage flag cell. When the transfer for one stage is further performed from the state shown in FIG. 15, the state shown in FIG. 16 is obtained. In the state of FIG. 16, the end character string “@end” is located at the checkpoint. Therefore, a positive determination is made in step S4, and the process branches to step S8. This step S8 is a process for discharging all the residual data remaining in the data storage unit 20. Specifically, the transfer processing for (n−k + 1) stages is performed. In this embodiment, the transfer process for three stages is performed, and the state of FIG. 16 becomes the state of FIG.

Thus, the line-by-line character string data output from the logic simulator unit 10, that is, the 7th to 9th lines corresponding to the error message 1 in the character string data of the 1st to 24th lines shown in FIG. Filtering processing that masks the eye data and outputs only the remaining data becomes possible.

The operation of the logic simulation apparatus shown in FIG. 1 has been described above based on a simple concrete example. Finally, a more practical operation example of the logic simulation apparatus will be shown. The lists shown in FIGS. 18 and 19 are
An output signal (a numerical value indicating a time and a 4-bit logical output value) actually output from the logic simulator unit 10 and an error message (a character string prefixed with #) are shown. As shown in the figure, a very large number of error messages are listed, and it is very difficult to see as a whole, and even if a serious error message is included, it may be overlooked. Therefore, conditions are set in the condition setting unit 50 as shown in FIG. 20, and the logic simulation device is operated. In the condition setting shown in FIG. 20, the character string "address unknown" is set as a keyword. FIG. 21 shows character string data actually output from the mask executing unit 70 when such condition setting is performed. Most of the error messages shown in the lists of FIGS. 18 and 19 are removed by the masking process, and the simulation result is very easy to see. When it is desired to remove all the error messages shown in FIG. 21 by the mask processing and leave only the logical output value, the condition setting as shown in FIG. Good. Thus, in the logic simulation device according to the present invention,
The filtering function can be freely changed according to the condition set in the condition setting unit 50, and the simulation result can be output as desired.

Although the present invention has been described above based on the illustrated embodiments, the present invention is not limited to these embodiments. In particular, the flowchart shown in FIG. 3 shows an example of a procedure for operating the logic simulation apparatus shown in FIG. 1, and it is not always necessary to operate in such a procedure. For example, in step S3 of FIG. 3, the transfer process for one stage is always performed, but the transfer process for a plurality of stages can be continuously performed depending on the situation. In particular, immediately after it is determined in step S5 that the checkpoint data contains a keyword, the number of steps required until the last line of the error message containing this keyword reaches the (k + 1) th data cell. The data transfer process of can be performed in step S3.
This is specifically shown below. Now, FIG.
Consider the case where the keyword "Setup violation" is found at the checkpoint in the state shown in. In this case, it is not necessary to check whether or not at least the three lines belonging to the line range of the error message 1 include the keyword. However, in the above-described embodiment, when the keyword is found in step S5, the flag is changed as shown in FIG. 11 through steps S6 and S7, and the transfer process for one stage is performed in the following step S3. In the state shown in FIG. 12, the process of determining whether or not the checkpoint includes a keyword is performed in step S5 for the state of FIG. However, in the state shown in FIG. 12, the process of determining whether or not the keyword is included in the checkpoint is, so to speak, useless and redundant process. This is because the data located at the check point in the state of FIG. 12 is the data included in the row range in the state of FIG. Therefore, as shown in FIG. 10, when a keyword is found in a checkpoint, the last line of the error message including this keyword is the next data cell of the checkpoint (that is, the (k + 1) th data cell). ) You may perform the data transfer processing for the required number of steps before coming to. In this example,
When the state shown in FIG. 10 is obtained, in the transfer processing of the subsequent step S3, the transfer processing of two stages may be performed.

Further, in the above-described embodiment, the data storage unit 20 and the flag storage unit 30 each having n = 5, that is, cells of all five stages are prepared, but the total number of stages of this cell is arbitrarily set. be able to. However, at least when a checkpoint is defined in a predetermined cell, it is necessary to provide a sufficient number of stages so that all the data of a plurality of lines belonging to the line range of the error message can be stored in the data storage unit 20. is there.

[0044]

As described above, according to the logic simulation apparatus for an integrated circuit of the present invention, a so-called FIFO is provided.
The data to be masked can be masked by setting a predetermined flag while passing through multiple rows of data cells in the (First In First Out) format, so that you can mask unnecessary error messages. It is possible to realize a filtering function that prevents the output.

[Brief description of drawings]

FIG. 1 is a block diagram showing a basic configuration of a logic simulation device for an integrated circuit according to an embodiment of the present invention.

FIG. 2 is a list showing an example of line-by-line character string data output from a logic simulator unit 10 in the logic simulation apparatus shown in FIG.

FIG. 3 is a flow chart showing an example of the operation of the logic simulation apparatus shown in FIG.

4 is a diagram showing an example of conditions set in a condition setting unit 50 of the logic simulation apparatus shown in FIG.

5 is a diagram showing an example of a description format for presenting the conditions shown in FIG. 4 to an actual computer.

6 is a diagram showing an initial state of each cell for explaining a specific operation of the logic simulation apparatus shown in FIG.

FIG. 7 is a diagram showing a state in which the transfer processing for one stage is performed and the data for one row is fetched from the state shown in FIG. 6;

8 is a diagram showing a state in which a transfer process for four stages is performed from the state shown in FIG. 7 and a total of five rows of data are fetched.

9 is a diagram showing a state in which a transfer process for three stages is performed from the state shown in FIG. 8 and a part of an error message is captured.

[Fig. 10] From the state shown in Fig. 9, transfer processing for two steps is performed, and the keyword "Setup violation" is added to the checkpoint.
It is a figure showing the state where "" was located.

11 is a diagram showing a state in which flags in three rows belonging to a row range are rewritten in the state shown in FIG.

12 is a diagram showing a state in which a transfer process for one stage is performed from the state shown in FIG.

13 is a diagram showing a state in which transfer processing for three stages has been performed from the state shown in FIG.

FIG. 14 is a process of performing transfer processing for eight steps from the state shown in FIG. 13, and again using the keyword “Setup
It is a figure which shows the state in which "violation" was located.

FIG. 15 is a diagram showing a state in which “empty data” for one row is fetched by performing transfer processing for three stages from the state shown in FIG. 14;

16 is a diagram showing a state in which a transfer process for one stage is performed from the state shown in FIG. 15 and a terminating character string “@end” is located at a checkpoint.

FIG. 17 is a diagram showing a state in which transfer processing for three stages is performed and all data is discharged from the state shown in FIG. 16;

FIG. 18 is a first half portion of a list showing an example of character string data in line units actually output from the logic simulator unit 10 of the logic simulation apparatus shown in FIG. 1.

FIG. 19 is the latter half of the list showing an example of character string data in line units actually output from the logic simulator unit 10 of the logic simulation apparatus shown in FIG.

20 is a diagram showing another example of the conditions set in the condition setting unit 50 of the logic simulation apparatus shown in FIG.

21 is a list of the lists shown in FIG. 18 and FIG.
21 is a list showing an output result of a simulation obtained by performing filtering based on the condition setting shown in FIG. 20.

22 is a diagram showing still another example of the conditions set in the condition setting unit 50 of the logic simulation apparatus shown in FIG.

[Explanation of symbols]

1, 2, 3 ... error message 10 ... Logic simulator section 20 ... Data storage unit 30 ... Flag storage unit 40 ... Transfer processing unit 50 ... Condition setting section 60 ... Mask determination unit 70 ... Mask execution unit

Claims (3)

(57) [Claims] 1. An apparatus for performing a logic simulation on an integrated circuit based on predetermined design data, which is output from the integrated circuit when a predetermined input signal is applied to the integrated circuit to be simulated. A logic simulator unit that outputs a predetermined output signal or a predetermined error message as character string data in units of lines, and a data cell that can store one line of the character string data output from this logic simulator unit Are arranged by n, and the nth
It is configured by arranging n data storage units in which stages having a series of steps are defined up to the data cells in the tier and flag cells defined corresponding to the respective data cells are arranged. A flag storage unit in which stages having a series of orders from the flag cell to the flag cell of the nth stage is defined, and the data in the data cell of the nth stage is output from the data storage unit, The respective data in the (n-1) th stage data cells are transferred to the second to nth stage data cells, respectively, and the data for one row output from the logic simulator section is transferred to the first stage data. The data transfer process for one stage of loading in the cell and the flag in the flag cell of the nth stage are output from the flag storage unit, and
A first stage in which each flag in the (n-1) th stage flag cell is transferred to the second to nth stage flag cells, and a flag indicating a non-masked state is set in the first stage flag cell Minute flag transfer processing and a transfer processing section that performs the transfer processing in synchronization with each other, among the various error messages output by the logic simulator section, for each error message that needs to be masked, a predetermined error message included in the error message A condition setting section that sets a keyword, a line range occupied by the character string data that forms the error message, and a predetermined mask condition that a predetermined parameter included in the error message should take, and a preset check point. In the character string data for one row stored in the kth data cell, the key word set by the condition setting unit is set. If the error message contains this keyword, the error message is stored by referring to the line range set in the condition setting section. By specifying the data cell that is present and comparing the data stored in the specified data cell with the predetermined mask condition set in the condition setting unit, it is determined whether or not this error message should be masked. If it is determined that masking should be performed, a mask determination unit that performs a process of setting a flag indicating a masked state in a flag cell corresponding to the specified data cell, and a flag output from the flag storage unit Only when the flag indicates the unmasked state, the data output from the data storage unit is finally presented in synchronization with this flag. Logic simulation apparatus for integrated circuits, characterized in that it comprises a mask execution unit for outputting as can data. 2. The simulation device according to claim 1, wherein the condition setting unit sets the character string data for one row stored in the k-th data cell by inspection by the mask determination unit. When it is determined that the keyword is included, the transfer processing unit performs the data transfer processing and the flag transfer for the number of stages required until the last line of the error message including the keyword reaches the (k + 1) th data cell. A logic simulation device for an integrated circuit, characterized in that a process is executed. 3. The simulation apparatus according to claim 1, wherein an error occurrence location and / or an error occurrence time is used as a mask condition set in the condition setting unit, and the error occurrence location or error occurrence in the error message is used. A logic simulation device for an integrated circuit, wherein a position of information indicating time is set as a relative position with respect to a line containing a keyword.