JP3371257B2 - Automatic frequency control circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic frequency control circuit, and more particularly to a burst for inputting in a digital demodulator for inputting a plurality of burst signals having a minute frequency difference within a fixed frame period of a 4-phase PSK modulation signal. The present invention relates to an automatic frequency control circuit that enables frequency control for each signal.

[0002]

2. Description of the Related Art An automatic frequency control circuit for an input frequency fluctuation in a conventional digital demodulator will be described with reference to timing charts of signals of respective parts shown in FIGS.

Now, as shown in FIG. 4, the input burst signal A1 has burst signals NO1 to NOn for each frame such as the first and second frame periods. The frequencies are f0 ± Δf + α1 to f0 ± Δf + αn in the first frame, and the second
F0 ± Δf1 + β1, f0 ± Δf1 + β2 in the frame
... Here, the frequency f0 is a reference frequency (for example, 14
0 MHz), and Δf is a common f over the first frame.
It is a frequency deviation from 0, and is randomly distributed in plus or minus. Further, α1 to αn are minute frequency deviations between the burst signals. Similarly, for the second frame, the common deviation from the reference frequency f0 is Δf1, and the minute frequency deviations between the burst signals are β1, β2 ...

As shown in FIG. 3, the configuration and operation of the conventional automatic frequency control circuit is as follows: The input variable burst signal A1 from the input terminal 1 and the voltage variable oscillator 14 for performing the operation described later.
Of the output signal E1 of the frequency converter 2 which outputs the signal A2 from which at least the common frequency deviations Δf and α1 are removed, the divider 3 which divides the signal A2 into two, and the divided signal A3. Phase detectors 4, 5 for inputting B3 and carrier signals B1, B2 having a 90 ° phase difference with each other, phase-detecting the quadrature PSK modulated signals, and outputting so-called I-channel Q-channel demodulated signals A4, B4. A carrier reproducing circuit 8 for reproducing the carrier signal, a 90 ° phase shifter 9 for shifting the carrier signal B1 by 90 °, and a first carrier included when carrier reproducing is performed by the carrier reproducing circuit 8. Δf + α1 to Δf of the frequency deviation component of the frame
+ Αn (Δf1 + β1 to Δf1 + β in the second frame
n) a frequency error detector 10 for detecting the frequency error information C2, an A / D converter 11 for digitally converting the frequency error information C2 for digital processing, and among the digitally converted signals, As shown in FIG. 4, a timing generator 15 that outputs a timing signal F1 that extracts only the frequency error information of the head burst signal of each frame synchronization, and the head burst of the frame cycle one frame before the current frame cycle A flip-flop 16 composed of a plurality of flip-flops having a function of storing average frequency error information of signals, and average frequency error signals D3 and A sent out in synchronization with the average frequency error information of this flip-flop 16 / D
The signal D2 and the adder 12 that outputs the updated signal D2 by inputting and adding the first burst signal D1 at the current point transmitted from the converter 11 in synchronization with the timing signal F1 D / A converter 13 for analog conversion
And a voltage variable oscillator 14 that outputs a corrected frequency signal E1 that finally makes the frequency deviation components Δf + α1 to Δf + αn zero by the analog-converted signal.

Further supplementing the configuration and operation of the conventional example,
As shown in FIG. 4, the timing signal F1 is composed of a clock having a predetermined cycle, and the frequency error information D1 from the A / D converter 11 is output for each clock to adder 12
The error is updated by and the output signal D2 is output. When the correction frequency signal E1 is generated based on this output signal D2, all the burst signals NO2 to NOn in the frame are corrected by the correction frequency signal E1. Further, after the second frame, the above-described operation is repeated and corrected.

[0006]

In this conventional automatic frequency control circuit, the frequency control is applied only to the reference burst signal (the first burst in the conventional example) among the input signals, and the other burst signals are controlled. Is corrected using the correction frequency signal of the leading burst signal, so that if there is a frequency deviation (α2 to αn in FIG. 4) between the burst signals, the reference burst is completely frequency controlled. However, the other burst signals have the drawback that the frequency deviation from the reference burst is not completely absorbed.

It is an object of the present invention to provide an automatic frequency control circuit which enables frequency control in burst units when there is a frequency deviation between an input burst signal and a plurality of burst signals.

[0008]

According to the automatic frequency control circuit of the present invention, a plurality of burst signals are arranged in each frame period of a quadrature PSK modulated signal, and carrier signals of the burst signals have frequency deviations. A carrier reproduction circuit for reproducing the carrier signal included in a digital demodulation circuit for demodulating an input burst signal, and a frequency error detection circuit for outputting a detection signal of a frequency deviation corresponding to each burst signal extracted from the carrier reproduction circuit. A timing generator for generating a timing signal for extracting a specific burst signal among the detection signals, and a frequency variable signal for digitally processing the specific burst signal extracted by the timing signal to correct a frequency deviation Inputting the frequency variable signal and the input burst signal. In the automatic frequency control circuit having a frequency converter that outputs a corrected signal, the timing generator generates timing signals for extracting all burst signals arranged in each frame period, and Memory means for storing the average error information of the bit string up to 1 bit before the current bit of the burst signal inputted as an input, and the processing for reading the average error information of the memory means and calculating the current bit and frequency correction. And means.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a timing chart of signals of respective parts of this embodiment. 1, the same parts as those in FIG. 3 are designated by the same reference numerals. Here, the input burst signal is the same as the input burst signal A1 described in the conventional example. That is, in this embodiment, the timing generator 15A improved from the conventional example of FIG.
And selector 17, memory circuit 18, address counter 1
It is configured by adding 9.

Next, the operation of this embodiment will be described. In conclusion, the burst signal A1 input from the input terminal 1 is frequency-converted by the frequency converter 2 that operates as described below, and the input frequency errors Δf + α1 to Δf + αn (Δf1 + β1, Δf1 + β2 ... In the second frame) are removed. The signal A2 is first distributed to two routes in the distributor 3, demodulated in the phase detectors 4 and 5, and output to the output terminal 6,
7 outputs I channel and Q channel signals A4 and B4. The output data is input to the carrier reproducing circuit 8 to generate a reproduced carrier signal B1 required for the phase detectors 4 and 5. Further, the frequency information C from the carrier reproducing circuit 8
1 is input to the frequency error detector 10 and the frequency error information C2 is detected. At this time, when the frequency error information C2 is an analog voltage, it is converted into digital data by the A / D converter 11. The frequency error information D1 and the average frequency error information D3 converted into digital data are input to the adder 12 and updated to the latest frequency error information D2. After that, it is converted into an analog voltage by the D / A converter 13 and is input to the voltage variable oscillator 14 to control the frequency, whereby the frequency error of the input signal can be removed.

Next, the operation of the portion added in this embodiment will be described. Frequency A for each input burst signal burst in FIG.
When there is a burst signal train having a constant cycle such as 1, the timing signal F1 of the timing generator 15A
Is set so that it occurs at each place where the burst signal exists as shown in FIG. Further, as shown in FIG. 2, the memory address G1 from the address counter 19 corresponds to the burst number, and the addresses 1 to n of the first frame
Signal F from the timing generator 15A so that
Controlled by 4. When the burst number 1 is input to the selector 18, the memory circuit 1 is placed at the beginning of the burst signal.
In order to extract the frequency error information of the burst number from No. 8, the signal H1 is generated by the memory read pulse F2 in FIG.
Is read out, passes through the selector 17, and is flip-flop 16
To enter. After that, the selector 17 is switched to control so that the updated frequency error information D2 from the adder 12 is input to the flip-flop 16. Further, at the end of burst NO1, the updated latest frequency error information D2 is written in the memory circuit 18 again by the memory write pulse F3 of FIG. Next, the burst number 2 is also operated in the same procedure. This makes it possible to calculate the frequency error information for each burst and store it in the memory address assigned to each burst. Since the frequency is corrected for each burst as described above,
It becomes possible to absorb the minute frequency deviations α1 to αn between the bursts.

[0012]

As described above, the present invention is provided with a timing generator for each burst, a memory circuit, an address counter and a selection circuit to store average frequency error information for each burst at different addresses of the memory circuit. Enable and
By setting the address by the address counter according to the burst number, frequency control and correction can be performed in burst units.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the present embodiment.

FIG. 3 is a block diagram of a conventional automatic frequency control circuit.

FIG. 4 is a timing chart illustrating a conventional example.

[Explanation of symbols]

1 input terminal 2 frequency converter 3 distributors 4,5 phase detector 6,7 output terminals 8 Carrier regeneration circuit 9 90 ° phase shifter 10 Frequency error detector 11 A / D converter 12 adder 13 D / A converter 14 Variable voltage oscillator 15A, 15 timing generator 16 flip-flops 17 selector 18 memory circuits 19 address counter

─────────────────────────────────────────────────── --Continued from the front page (56) References JP-A-4-4040 (JP, A) JP-A-5-152852 (JP, A) JP-A-5-167468 (JP, A) JP-A-62-1 132457 (JP, A) Patent 2582462 (JP, B2) Patent 3152358 (JP, B2) Japanese Patent Publication No. 4-22377 (JP, B2) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04L 27 / 00

Claims (3)

(57) [Claims] 1. A digital demodulation circuit for arranging a plurality of burst signals in each frame period of a quadrature PSK modulated signal, and demodulating an input burst signal in which carrier signals of the burst signals have frequency deviations. A carrier reproduction circuit for reproducing a carrier signal, and a frequency error detection circuit for outputting a detection signal of a frequency deviation corresponding to each burst signal extracted from the carrier reproduction circuit,
A timing generator for generating a timing signal for extracting a specific burst signal among the detection signals, and an oscillator for digitally processing the specific burst signal extracted by the timing signal to generate a frequency variable signal for correcting a frequency deviation And an automatic frequency control circuit having a frequency converter for inputting the frequency variable signal and the input burst signal and outputting a signal with a corrected frequency deviation, all of the timing generators arranged in each frame period. Timing generating means for generating a timing signal for extracting the burst signal, memory means for storing average error information of a bit string up to one bit before the current bit of the extracted and input burst signal, and the memory means. The average error information is read and the current bit and frequency correction are calculated. Automatic frequency control circuit; and a management unit. 2. The timing generating means outputs a write signal for writing the average error information calculated by the processing means to the memory means, and a read signal for reading the written information at a predetermined timing. The automatic frequency control circuit according to claim 1. 3. The automatic frequency control circuit according to claim 1, wherein said memory means has an address for storing average error information corresponding to a new burst signal executed by said processing means.