JP3364266B2 - Bump formation method - Google Patents
Bump formation methodInfo
- Publication number
- JP3364266B2 JP3364266B2 JP5698993A JP5698993A JP3364266B2 JP 3364266 B2 JP3364266 B2 JP 3364266B2 JP 5698993 A JP5698993 A JP 5698993A JP 5698993 A JP5698993 A JP 5698993A JP 3364266 B2 JP3364266 B2 JP 3364266B2
- Authority
- JP
- Japan
- Prior art keywords
- bump
- substrate
- bumps
- chip
- electrode pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
- 238000000034 method Methods 0.000 title claims abstract description 51
- 230000015572 biosynthetic process Effects 0.000 title description 3
- 239000000463 material Substances 0.000 claims description 24
- 230000001681 protective effect Effects 0.000 claims description 4
- 239000000758 substrate Substances 0.000 abstract description 43
- 229910000679 solder Inorganic materials 0.000 abstract description 28
- 230000002950 deficient Effects 0.000 abstract 2
- 239000006185 dispersion Substances 0.000 abstract 1
- 238000004806 packaging method and process Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 14
- 230000007547 defect Effects 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- 238000007650 screen-printing Methods 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- 230000008018 melting Effects 0.000 description 5
- 238000002844 melting Methods 0.000 description 5
- 238000007598 dipping method Methods 0.000 description 3
- 230000005496 eutectics Effects 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 229910001220 stainless steel Inorganic materials 0.000 description 3
- 239000010935 stainless steel Substances 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 238000007740 vapor deposition Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000010304 firing Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4867—Applying pastes or inks, e.g. screen printing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/1147—Manufacturing methods using a lift-off mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3452—Solder masks
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
Landscapes
- Engineering & Computer Science (AREA)
- Ceramic Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Connections Effected By Soldering, Adhesion, Or Permanent Deformation (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明はバンプの形成法および電
子部品の実装法に関する。さらに詳しくは、半導体チッ
プなどの電子部品またはプリント基板などの配線基板の
電極パッド上に、外部リードなどとの接続用に設けられ
た金属突起物であるバンプを形成するバンプ形成法およ
び該形成法を用いた電子部品の実装法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bump forming method and an electronic component mounting method. More specifically, a bump forming method and a bump forming method for forming bumps, which are metal protrusions provided for connection with external leads, on electrode pads of electronic components such as semiconductor chips or wiring boards such as printed boards. The present invention relates to a mounting method of electronic parts using.
【０００２】[0002]
【従来の技術】最近、電子機器の小型化に伴ない、たと
えば集積回路（ＩＣ）などを組み込んだ半導体装置も、
樹脂でモールドしてリード線を導出したものではなく、
ＣＯＢ（チップオンボード）やＣＯＧ（チップオングラ
ス）などにみられるように、半導体チップ（以下、チッ
プという）の電極パッドにバンプが形成されたいわゆる
ベアチップの状態で直接プリント基板などの配線基板
（以下、基板という）の電極パッドに接続する方法が増
えつつある。この方式では、一般にチップの電極パッド
上にバンプが形成され、基板の電極パッドが直接バンプ
に接続される。また、他の方法として基板側の電極パッ
ドにバンプを形成したり、または双方の電極パッドに形
成する方法も行われている。バンプの形成法として、従
来は主として、ディップ（浸漬）法で形成されたり、ス
クリーン印刷により形成する方法が検討されている。2. Description of the Related Art With the recent miniaturization of electronic equipment, semiconductor devices incorporating integrated circuits (ICs) have become
It is not a resin molded lead wire,
As seen in COB (chip on board), COG (chip on glass), etc., a wiring board (such as a printed circuit board) directly in a so-called bare chip state in which bumps are formed on electrode pads of a semiconductor chip (hereinafter referred to as a chip). There is an increasing number of methods for connecting to electrode pads of a substrate). In this method, bumps are generally formed on the electrode pads of the chip, and the electrode pads of the substrate are directly connected to the bumps. As another method, a method of forming bumps on the electrode pads on the substrate side or forming bumps on both electrode pads is also used. As a bump forming method, conventionally, a dipping (immersion) method or a method of forming the bump by screen printing has been mainly studied.
【０００３】また、スクリーン印刷などの方法でバンプ
を形成した基板とチップの電極パッドを接続してチップ
を基板上に実装するばあい、図４（ａ）に示されるよう
に、まずチップ21と基板22との各々の電極パッド24、25
上にハンダなどからなるバンプ23ａ、23ｂを形成する。
基板22は、図４（ｂ）に示されるように、銅などからな
る電極パッド25が設けられ、基板22の表面にソルダーレ
ジスト26が塗布され、電極パッド25上に開口部27が形成
されている。電極パッド25上にバンプ23ｂを形成するば
あい、基板22の表面に前記開口部27と同一形状の孔28を
有するマスク29を開口部27と孔28とが一致するように位
置合わせをして配置したのち、スクリーン印刷または蒸
着法などによりバンプ材料32を付着させ、そののち焼成
することにより開口部27内にバンプ23ｂを形成する。バ
ンプ材料を付着したのちまたはバンプ形成後、マスク29
は除去される。また、他の方法として、ディップ法など
でも形成される。Further, when the substrate on which bumps are formed by a method such as screen printing is connected to the electrode pads of the chip to mount the chip on the substrate, first, as shown in FIG. Each electrode pad 24, 25 with the substrate 22
Bumps 23a and 23b made of solder or the like are formed on the top.
As shown in FIG. 4B, the substrate 22 is provided with an electrode pad 25 made of copper or the like, a solder resist 26 is applied to the surface of the substrate 22, and an opening 27 is formed on the electrode pad 25. There is. When the bump 23b is formed on the electrode pad 25, a mask 29 having a hole 28 having the same shape as the opening 27 is aligned on the surface of the substrate 22 so that the opening 27 and the hole 28 are aligned with each other. After the arrangement, the bump material 32 is attached by screen printing or vapor deposition, and then fired to form the bump 23b in the opening 27. Mask 29 after depositing bump material or after bump formation
Are removed. Further, as another method, it is also formed by a dip method or the like.
【０００４】また、図４（ａ）に示されるようにチップ
21の表面には電極パッド24の周辺にチッ化ケイ素膜など
からなるパッシベーション膜30が形成されており、パッ
シベーション膜30に設けられた電極コンタクト用の開口
部31内にスクリーン印刷、蒸着法などでバンプ23ａが形
成される。ついでそれぞれのバンプを位置合わせし、そ
れを突き合わせるように基板22とチップ21を平行に向か
い合わせ、リフローすることにより基板側のバンプ23ｂ
を溶かして基板22とチップ21を接続させる。このときチ
ップ側のバンプ23ａとして高融点（290 〜300 ℃）のハ
ンダを用い、基板側のバンプ23ｂとして共晶ハンダ（融
点183 ℃程度）を用いることによって基板側のバンプ23
ｂのみを溶かし、接着する。Further, as shown in FIG.
A passivation film 30 made of a silicon nitride film or the like is formed around the electrode pad 24 on the surface of the electrode 21. The bump 23a is formed. Then, the bumps 23b on the substrate side are aligned by aligning the respective bumps, facing the substrate 22 and the chip 21 in parallel so as to abut them, and performing reflow.
Is melted to connect the substrate 22 and the chip 21. At this time, a high melting point (290 to 300 ° C.) solder is used as the chip side bump 23 a, and a eutectic solder (melting point about 183 ° C.) is used as the substrate side bump 23 b.
Melt and bond only b.
【０００５】[0005]
【発明が解決しようとする課題】しかしながらチップ21
および基板22に形成されるバンプ23ａ、23ｂにはバンプ
材料の体積にしたがって高さのバラつきが20％程度発生
する。一般にチップおよび基板側の電極はともに一辺約
100 μｍ程度の正方形であり、バンプの高さとしてはチ
ップ側に約50μｍ、基板側に20μｍ程度のバンプを形成
する。これに20％程度のバラつきを考慮するとチップ側
のバンプは最大60μｍ程度の高さであり、したがってチ
ップと基板間隔（図５（ａ）中のｘ）も最大60μｍ以上
になると考えられる。[Problem to be Solved by the Invention] However, the chip 21
The bumps 23a and 23b formed on the substrate 22 have a height variation of about 20% depending on the volume of the bump material. Generally, both the chip and substrate electrodes are on one side.
The height of the bump is about 50 μm on the chip side, and the bump is about 20 μm on the substrate side. Considering the variation of about 20%, the bumps on the chip side have a maximum height of about 60 μm, and therefore, the distance between the chip and the substrate (x in FIG. 5A) is considered to be 60 μm or more at the maximum.
【０００６】このとき他のバンプで図５（ａ）のよう
に、チップ側と基板側のバンプの高さ（図５（ａ）の
ｙ、ｚ）がともに最小値（各々約40μｍ、16μｍ）をと
ると、この箇所においてチップと基板のバンプは接続さ
れない（オープン）状態となる。At this time, as for other bumps, as shown in FIG. 5A, the heights of the bumps on the chip side and the substrate side (y and z in FIG. 5A) are both minimum values (about 40 μm and 16 μm, respectively). Then, the chip and the bump of the substrate are not connected (open) at this position.
【０００７】一方、オープン状態の発生を防止するため
ハンダの量を増加させてバンプを高くすると図５（ｂ）
のように隣接するバンプ同士が連結してショート不良が
発生するという問題がある。On the other hand, if the bump amount is increased by increasing the amount of solder in order to prevent the occurrence of the open state, FIG.
As described above, there is a problem that adjacent bumps are connected to each other to cause a short circuit defect.
【０００８】本発明では、かかる問題を解消し、オープ
ンやショートの不良が発生せず、かつ、通常のバンプ材
料のバラツキがあってもバンプを接続できるようなバン
プの形成法およびそれを用いた電子部品の実装法を提供
することを目的とする。In the present invention, such a problem is solved, a defect of opening or short circuit does not occur, and a bump forming method that can connect the bumps even if there is a variation in the usual bump material, and a method thereof are used. It is intended to provide a mounting method for electronic components.
【０００９】本発明のバンプ形成法は、電極パッド上に
設けられた保護絶縁膜の開口部に対応する孔を有するマ
スクを前記開口部に位置合わせして配設し、該マスク上
からバンプ材料を供給したのち焼成することによりバン
プを形成するバンプの形成法であって、前記保護絶縁膜
の開口部を前記マスクの孔より小さく形成することを特
徴とするものである。According to the bump forming method of the present invention, a mask having a hole corresponding to the opening of the protective insulating film provided on the electrode pad is aligned with the opening , and the bump material is placed on the mask. A method of forming a bump by firing after supplying the above, wherein the opening of the protective insulating film is formed smaller than the hole of the mask.
【００１０】また、本発明の電子部品の実装法は、本発
明の配線基板上に設けられた電極パッドと電子部品のチ
ップに設けられた電極パッドとを接続する配線基板への
電子部品の実装法であって、前記配線基板の電極パッド
または電子部品のチップの電極パッドの少なくとも一方
に前記バンプ形成法によるバンプを形成し、該バンプを
介して電子部品を接続するものである。Further, the method of mounting an electronic component of the present invention is a method of mounting an electronic component on a wiring board for connecting an electrode pad provided on the wiring board of the present invention and an electrode pad provided on a chip of the electronic component. A bump is formed by the bump forming method on at least one of the electrode pad of the wiring board and the electrode pad of the chip of the electronic component, and the electronic component is connected via the bump.
【００１１】[0011]
【作用】本発明のバンプ形成法によれば、バンプを形成
するため電極パッド上に設ける絶縁膜の開口部を、それ
に対応するマスクの孔の大きさより小さくすることによ
って、従来のバンプ形成材料と同じ量のバンプ材料が各
開口部およびその周囲の絶縁膜上にも供給され、バンプ
材料を付着したのちに焼成することにより、開口部およ
び絶縁膜上のバンプ材料が表面張力により開口部上に盛
り上がり嵩高いバンプがえられる。すなわち、バンプ材
料の絶対量を増すことなく、背の高いバンプがえられ
る。According to the bump forming method of the present invention, the size of the opening of the insulating film provided on the electrode pad for forming the bump is made smaller than the size of the corresponding hole of the mask, so that the conventional bump forming material is obtained. The same amount of bump material is supplied to each opening and the insulating film around it, and the bump material on the opening and the insulating film is applied to the opening due to surface tension by firing after adhering the bump material. You can get bumpy bumps. That is, a tall bump can be obtained without increasing the absolute amount of bump material.
【００１２】また、本発明の電子部品の実装法によれ
ば、バンプ材料を増やすことなく背の高いバンプを介し
て接続しているため、接触不良とかバンプ材料の過剰に
よる短絡などがなく、確実に各電極端子を接続すること
ができる。Further, according to the mounting method of the electronic component of the present invention, since the bumps are connected through the tall bumps without increasing the bump material, there is no contact failure or short circuit due to excessive bump material, so that there is no problem. Each electrode terminal can be connected to.
【００１３】[0013]
【実施例】つぎに図面を参照しながら本発明について説
明する。The present invention will be described below with reference to the drawings.
【００１４】図１は本発明のバンプの形成法の工程断面
説明図であり、図２は本発明の電子部品の実装法の一工
程を示す断面説明図であり、図３は同じ量のバンプ材料
により底面積を変えたときのバンプの高さの変化を示し
た説明図である。FIG. 1 is a cross-sectional explanatory view of the steps of the bump forming method of the present invention, FIG. 2 is a cross-sectional explanatory view showing one step of the electronic component mounting method of the present invention, and FIG. 3 is the same amount of bumps. It is explanatory drawing which showed the change of the height of the bump when the bottom area was changed with materials.
【００１５】本発明のバンプの形成法の一実施例を図１
を参照しながら説明する。まずプリント基板など表面に
電気回路が形成された基板１に図１（ａ）のように配線
の保護および絶縁のため80μｍ程度の厚さのソルダーレ
ジスト３などの絶縁膜が全面に塗布されており、これを
電極パッド２のバンプ形成部分にエッチングを施して開
口部４を設ける。さらに前記開口部４に対応した孔６を
有するマスク５を図１（ｂ）のように、基板１上に位置
合わせをして配設する。開口部４は従来の大きさより1/
4 程度以下と小さくし、マスク５の孔は従来と同程度の
ままとする。基板とか電子部品などの種類によっても異
なるが、通常は開口部の直径の大きさを50〜60μｍφ、
マスク５の孔の径を100 〜110 μｍ程度とする。One embodiment of the bump forming method of the present invention is shown in FIG.
Will be described with reference to. First, as shown in FIG. 1 (a), an insulating film such as a solder resist 3 having a thickness of about 80 μm is applied to the entire surface of a substrate 1 such as a printed circuit board on which an electric circuit is formed in order to protect and insulate wiring. Then, the bump forming portion of the electrode pad 2 is etched to form the opening 4. Further, as shown in FIG. 1B, a mask 5 having a hole 6 corresponding to the opening 4 is aligned and arranged on the substrate 1. The opening 4 is 1 / though smaller than the conventional size
The size is reduced to about 4 or less, and the holes of the mask 5 are kept the same as the conventional one. The size of the diameter of the opening is usually 50-60 μmφ, although it depends on the type of substrate and electronic parts.
The diameter of the holes of the mask 5 is about 100 to 110 μm.
【００１６】ついでハンダペーストなどのバンプ材料と
なる金属ペーストをスクリーン印刷、蒸着法などの方法
により孔６の内部に形成させる。たとえば、バンプ用材
料のハンダペースト７を図１（ｃ）のようにスクリーン
印刷する。なお９はスキージである。ついで、マスク５
を取り外したのち基板１をオーブン炉または環状炉など
によって220 〜230 ℃に加熱することによりハンダペー
スト７の焼成を行う。加熱後、基板１全体を約30分間放
置し冷却する。その結果、図１（ｄ）のようにバンプ８
が開口部４の上に表面張力のため球形状にもりあがった
形状で形成される。Then, a metal paste which becomes a bump material such as a solder paste is formed inside the hole 6 by a method such as screen printing or vapor deposition. For example, the solder paste 7 of the bump material is screen-printed as shown in FIG. In addition, 9 is a squeegee. Then, mask 5
After removing, the substrate 1 is heated to 220 to 230 ° C. in an oven furnace or a ring furnace to bake the solder paste 7. After heating, the whole substrate 1 is left to cool for about 30 minutes. As a result, as shown in FIG.
Are formed in a spherical shape on the opening 4 due to surface tension.
【００１７】前記ハンダペースト７は、ソルダーレジス
ト３に対してなじまないため、図１（ｄ）のごとくソル
ダーレジスト３上のハンダペースト７はすべて開口部４
の上方に引き寄せられる。したがって嵩高いバンプ８を
形成することができる。Since the solder paste 7 is not compatible with the solder resist 3, all the solder paste 7 on the solder resist 3 has openings 4 as shown in FIG. 1D.
Attracted above. Therefore, the bulky bump 8 can be formed.
【００１８】ここで、マスク５はステンレス、ニッケル
やタングステンなどの薄板からなり、バンプを形成すべ
き基板１に設けられた電極パッド２に対応して孔６が形
成されている。このマスク５は通常50〜300 μｍの厚さ
で形成されている。あまり厚すぎると孔６が垂直に形成
されなくなり、薄すぎるとバンプの形成高さが低くな
り、他の膜などから突出させることができなくなるから
である。Here, the mask 5 is made of a thin plate of stainless steel, nickel, tungsten or the like, and the holes 6 are formed corresponding to the electrode pads 2 provided on the substrate 1 on which bumps are to be formed. The mask 5 is usually formed with a thickness of 50 to 300 μm. This is because if the thickness is too thick, the holes 6 will not be formed vertically, and if it is too thin, the bump formation height will be low, and it will not be possible to project from other films or the like.
【００１９】また、叙上のごとくバンプ８が形成された
基板１に半導体チップなどの電子部品のチップを実装す
るばあい、該チップの電極パッドと基板の電極パッドが
嵩高いバンプを介して接続されるため、オープン不良は
発生しない。このばあい、本発明によるバンプは基板側
の電極パッドに形成されることに限定されず、チップ側
の電極パッドに形成してもよく、さらに双方の電極パッ
ドにバンプを形成すれば、バンプの高さのバラツキを吸
収しオープン不良の低減のため好ましい。When mounting a chip of an electronic component such as a semiconductor chip on the substrate 1 on which the bumps 8 are formed as described above, the electrode pad of the chip and the electrode pad of the substrate are connected via the bulky bump. Therefore, the open defect does not occur. In this case, the bump according to the present invention is not limited to being formed on the electrode pad on the substrate side, and may be formed on the electrode pad on the chip side. It is preferable because it absorbs variations in height and reduces open defects.
【００２０】つぎに本発明のバンプの形成法を用いた電
子部品の実装法の具体例として、基板表面に半導体チッ
プ（以下、チップという）をチップ表面の能動領域が基
板側を向くように（フェイスダウン）実装する例につい
て説明する。Next, as a specific example of a method of mounting an electronic component using the bump forming method of the present invention, a semiconductor chip (hereinafter referred to as a chip) is arranged on the substrate surface so that the active region of the chip surface faces the substrate side ( Face-down) An example of implementation will be described.
【００２１】図２に示されるように、まずチップ10側に
前述のバンプ形成法によりバンプ11を形成する。バンプ
材料としては高融点（たとえば290 〜300 ℃）のハンダ
を材料としたハンダペーストを用いる。チッ化ケイ素
膜、酸化ケイ素膜などからなる絶縁膜13の開口部14は10
0 ×100 μｍ程度で形成される。As shown in FIG. 2, first, the bumps 11 are formed on the chip 10 side by the bump forming method described above. As the bump material, a solder paste made of solder having a high melting point (for example, 290 to 300 ° C.) is used. The opening 14 of the insulating film 13 made of a silicon nitride film, a silicon oxide film, etc.
It is formed in a size of 0 × 100 μm.
【００２２】前記パッシベーション膜13の表面にステン
レス、ニッケルやタングステンなどからなる厚さ約50μ
ｍで、かつ110 ×110 μｍ程度の孔が前記チップ10の電
極パッド12と同じ間隔で設けられたマスクを載置し、前
述の高融点のハンダペーストをスクリーン印刷により各
電極パッド12上に供給する。ついで、330 〜340 ℃で約
３分間焼成して高さが50±10μｍのバンプを形成した。The surface of the passivation film 13 is made of stainless steel, nickel, tungsten or the like and has a thickness of about 50 μm.
m, and a mask with holes of 110 × 110 μm provided at the same intervals as the electrode pads 12 of the chip 10 is placed, and the above-mentioned high melting point solder paste is supplied onto each electrode pad 12 by screen printing. To do. Then, it was baked at 330 to 340 ° C. for about 3 minutes to form bumps having a height of 50 ± 10 μm.
【００２３】つぎに、基板側のバンプを形成する。バン
プ材料として融点が約183 ℃である共晶ハンダのペース
トを用いた。Next, the bumps on the substrate side are formed. A eutectic solder paste having a melting point of about 183 ° C. was used as the bump material.
【００２４】基板１の電極パッド２の上部のソルダーレ
ジスト３の開口部を約50μｍφで形成する。前記ソルダ
ーレジスト３の表面にステンレス、ニッケルやタングス
テンなどからなる厚さ約30μｍで、かつ直径が約100 μ
ｍφ程度の孔が前記基板の電極パッドと同じ間隔で設け
られたマスクを載置し、共晶ハンダからなるハンダペー
ストをスクリーン印刷により各電極パッドに塗布した。
ついで前述のようにバンプを形成した基板１とチップ10
とを図２のようにバンプ同士が接着するように位置あわ
せし、基板１とチップ10とを平行に保持しながら圧着す
る。圧着は、バンプの温度が220 ℃程度になるようリフ
ロー炉の温度を設定し１〜２分間加熱すると共に、１チ
ップあたり20〜100 ｇｆで加圧して基板１側のバンプの
みを融解させ接着する。以上の操作により基板へのチッ
プの実装が完了する。An opening of the solder resist 3 on the electrode pad 2 of the substrate 1 is formed with a diameter of about 50 μmφ. The surface of the solder resist 3 is made of stainless steel, nickel or tungsten, and has a thickness of about 30 μm and a diameter of about 100 μm.
A mask having holes of about mφ provided at the same intervals as the electrode pads of the substrate was placed, and a solder paste composed of eutectic solder was applied to each electrode pad by screen printing.
Then, the substrate 1 and the chip 10 on which the bumps are formed as described above.
Are aligned so that the bumps are bonded to each other as shown in FIG. 2, and the substrate 1 and the chip 10 are pressed in parallel while being held in parallel. For pressure bonding, set the temperature of the reflow furnace so that the temperature of the bumps is about 220 ° C. and heat it for 1 to 2 minutes, and pressurize at 20 to 100 gf per chip to melt and bond only the bumps on the substrate 1 side. . By the above operation, the mounting of the chip on the substrate is completed.
【００２５】本発明によるバンプの形成法によれば、高
いバンプを形成でき、しかも材料の量のバラつきがあっ
ても余り高さが変動しない理由について説明する。According to the bump forming method of the present invention, the reason why a high bump can be formed and the height does not fluctuate too much even if the amount of material varies will be described.
【００２６】たとえば従来の浸漬法で図３（ａ）〜
（ｂ）のように100 ×100 μｍの電極パッド16に高さ20
μｍのバンプ15を形成すると、上部のほとんどは球の一
部のような形状のバンプとなるがそれと同量のバンプ材
料で、本発明の方法により基板およびチップの電極パッ
ドにバンプを形成すると、理論的には図３（ｃ）〜
（ｄ）に示されるように上半分は半球状、下半分は開口
部に一致する50μｍφの底部をもつ、円柱状であり、4
7.8μｍの高さとなる。また、ハンダの量（形成される
バンプの体積）には20％程度のバラつきが発生するとす
れば本発明の方法により形成されたバンプの高さは42〜
56μｍの範囲であり、これは従来の方法によるバンプの
高さのバラつきと比べると極めて小さなバラツキであ
る。その結果、オープン不良が発生しなくなる。またバ
ンプ材料全体の量は従来と変わっていないため、バラツ
キによりバンプが高く形成されても隣り同士のバンプで
接触することもない。For example, by the conventional dipping method, as shown in FIGS.
As shown in (b), the height is 20 on the electrode pad 16 of 100 × 100 μm.
When the bump 15 of μm is formed, most of the upper part becomes a bump having a shape like a part of a sphere, but with the same amount of bump material, when the bump is formed on the electrode pad of the substrate and the chip by the method of the present invention, Theoretically, FIG.
As shown in (d), the upper half has a hemispherical shape, and the lower half has a columnar shape with a bottom of 50 μmφ matching the opening.
The height is 7.8 μm. If the amount of solder (volume of bumps to be formed) varies by about 20%, the height of bumps formed by the method of the present invention is 42-
The range is 56 μm, which is an extremely small variation compared with the variation in bump height obtained by the conventional method. As a result, open defects do not occur. Further, since the amount of the entire bump material is the same as that of the conventional one, even if the bumps are formed high due to variations, the adjacent bumps do not come into contact with each other.
【００２７】また、本実施例中ではスクリーン印刷によ
りバンプ材料を供給したがマスクを用いた蒸着法によっ
ても同様である。すなわち、本発明では、ハンダなどの
金属ペーストをマスキングを施すことにより電極パッド
およびその周辺部に選択的に形成することができる薄膜
形成法であればいかなる方法も適用できる。また、基板
１上のバンプ８は接続前に一度リフローを行い半球状に
しておいてもよい。Further, in the present embodiment, the bump material is supplied by screen printing, but the same applies by the vapor deposition method using a mask. That is, in the present invention, any method can be applied as long as it is a thin film forming method that can be selectively formed on the electrode pad and its peripheral portion by masking a metal paste such as solder. Further, the bumps 8 on the substrate 1 may be reflowed once before connection to be formed into a hemispherical shape.
【００２８】また、本実施例では半導体チップを実装す
る例で説明したが、本発明は半導体チップに限られず、
リードレスで回路基板などに接続されるリードレスの抵
抗、コンデンサー、配線などの他の電子部品にバンプを
形成したり、実装するばあいにも適用することができ
る。さらに、バンプは電子部品以外にも回路基板などの
接続部などにも形成されるばあいがあり、いずれのバン
プの形成のばあいにも本発明を適用することができる。In the present embodiment, an example of mounting a semiconductor chip has been described, but the present invention is not limited to a semiconductor chip,
It can also be applied when bumps are formed or mounted on other electronic components such as leadless resistors, capacitors, and wirings that are connected to a circuit board or the like by leadless. Further, the bumps may be formed not only on the electronic components but also on the connection parts such as the circuit board, and the present invention can be applied to any of the bumps.
【００２９】[0029]
【発明の効果】本発明によれば、同量のハンダで水平方
向に拡がらずに嵩高い、しかもバラツキの少ないバンプ
を形成することができる。そのため従来のディップ法に
比べて電極間隔を大幅に縮小（1/4 程度）することがで
き、近年のＣＯＢの小型化、高密度化に対応できる。According to the present invention, it is possible to form bumps with the same amount of solder, which are bulky without spreading in the horizontal direction and have little variation. Therefore, the electrode interval can be significantly reduced (about 1/4) as compared with the conventional dipping method, and it is possible to cope with the recent miniaturization and high density of COB.
【００３０】また、上述のバンプ形成法を用いればオー
プン不良、ショート不良がほとんど発生しないため、歩
留りよく電子部品の実装を行うことができ、コストダウ
ンに寄与する。Further, when the above-mentioned bump forming method is used, open defects and short defects hardly occur, so that electronic components can be mounted with high yield, which contributes to cost reduction.
【図１】本発明のバンプの形成法を説明する工程断面説
明図である。FIG. 1 is a process cross-sectional explanatory diagram illustrating a bump forming method of the present invention.
【図２】本発明の電子部品の実装法を説明する断面説明
図である。FIG. 2 is a cross-sectional explanatory diagram illustrating a method of mounting an electronic component of the present invention.
【図３】同じ量のバンプ材料により、底面積を変えたと
きのバンプの高さの変化を説明する図である。FIG. 3 is a diagram illustrating a change in bump height when a bottom area is changed by using the same amount of bump material.
【図４】（ａ）は従来の電子部品の実装法の説明図であ
り、（ｂ）は基板にバンプ材料を供給する工程の断面説
明図である。FIG. 4A is an explanatory diagram of a conventional electronic component mounting method, and FIG. 4B is a sectional explanatory diagram of a step of supplying a bump material to a substrate.
【図５】従来の電子部品の実装例を示す図で、（ａ）は
オープン不良の説明図、（ｂ）はショート不良の説明図
である。5A and 5B are diagrams showing a mounting example of a conventional electronic component, FIG. 5A is an explanatory diagram of an open defect, and FIG. 5B is an explanatory diagram of a short circuit defect.
１ 基板 ２ 電極パッド ３ ソルダーレジスト ４ 開口部 ５ マスク ６ 孔 ７ ハンダペースト ８ バンプ 10 チップ 11 バンプ 12 電極パッド 13 パッシベーション膜 14 開口部 1 substrate 2 electrode pad 3 Solder resist 4 openings 5 masks 6 holes 7 Solder paste 8 bumps 10 chips 11 bump 12 electrode pad 13 passivation film 14 opening
Claims (2)
開口部に対応する孔を有するマスクを前記開口部に位置
合わせして配設し、該マスク上からバンプ材料を供給し
たのち焼成することによりバンプを形成するバンプの形
成法であって、前記保護絶縁膜の開口部を前記マスクの
孔より小さく形成することを特徴とするバンプの形成
法。1. A mask having a hole corresponding to an opening of a protective insulating film provided on an electrode pad is aligned with the opening , and a bump material is supplied from above the mask and then baked. A bump forming method for forming a bump by the above, wherein the opening of the protective insulating film is formed smaller than the hole of the mask.
子部品のチップに設けられた電極パッドとを接続する配
線基板への電子部品の実装法であって、前記配線基板の
電極パッドまたは電子部品のチップの電極パッドの少な
くとも一方に請求項１記載の方法によるバンプを形成
し、該バンプを介して前記両電極パッドを接続する電子
部品の実装法。2. A method of mounting an electronic component on a wiring board for connecting an electrode pad provided on the wiring board and an electrode pad provided on a chip of the electronic component, which is the electrode pad of the wiring board or the electronic component. A method for mounting an electronic component, wherein bumps are formed on at least one of electrode pads of a chip of the component by the method according to claim 1, and the electrode pads are connected via the bumps.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5698993A JP3364266B2 (en) | 1993-03-17 | 1993-03-17 | Bump formation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5698993A JP3364266B2 (en) | 1993-03-17 | 1993-03-17 | Bump formation method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06267964A JPH06267964A (en) | 1994-09-22 |
| JP3364266B2 true JP3364266B2 (en) | 2003-01-08 |
Family
ID=13042909
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5698993A Ceased JP3364266B2 (en) | 1993-03-17 | 1993-03-17 | Bump formation method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3364266B2 (en) |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2724526B1 (en) * | 1994-09-14 | 1996-12-13 | Peugeot | METHOD FOR FORMING SOLDERING PLOTS ON CONDUCTIVE PORTIONS OF A PRINTED CIRCUIT |
| EP0818811B1 (en) * | 1996-07-05 | 1999-12-15 | Hewlett-Packard Company | Method of making solder bumps |
| DE19634646A1 (en) * | 1996-08-27 | 1998-03-05 | Pac Tech Gmbh | Selective soldering process |
| SG73469A1 (en) | 1996-11-20 | 2000-06-20 | Ibiden Co Ltd | Solder resist composition and printed circuit boards |
| US6461953B1 (en) | 1998-08-10 | 2002-10-08 | Fujitsu Limited | Solder bump forming method, electronic component mounting method, and electronic component mounting structure |
| US6190940B1 (en) * | 1999-01-21 | 2001-02-20 | Lucent Technologies Inc. | Flip chip assembly of semiconductor IC chips |
| US6228681B1 (en) * | 1999-03-10 | 2001-05-08 | Fry's Metals, Inc. | Flip chip having integral mask and underfill providing two-stage bump formation |
| JP3879642B2 (en) | 2002-09-20 | 2007-02-14 | セイコーエプソン株式会社 | Solder printing mask, wiring board and manufacturing method thereof, electro-optical device and manufacturing method thereof, and electronic apparatus and manufacturing method thereof |
| JP4210171B2 (en) | 2003-02-25 | 2009-01-14 | 京セラ株式会社 | Flip chip type IC manufacturing method |
| KR100871031B1 (en) * | 2007-06-01 | 2008-11-27 | 삼성전기주식회사 | Forming method of bump for the printed circuit board |
| JP5243735B2 (en) * | 2007-06-18 | 2013-07-24 | ローム株式会社 | Circuit board and semiconductor device |
| US8492262B2 (en) * | 2010-02-16 | 2013-07-23 | International Business Machines Corporation | Direct IMS (injection molded solder) without a mask for forming solder bumps on substrates |
| JP6004441B2 (en) | 2013-11-29 | 2016-10-05 | インターナショナル・ビジネス・マシーンズ・コーポレーションＩｎｔｅｒｎａｔｉｏｎａｌ Ｂｕｓｉｎｅｓｓ Ｍａｃｈｉｎｅｓ Ｃｏｒｐｏｒａｔｉｏｎ | Substrate bonding method, bump forming method, and semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2788694B2 (en) | 1992-09-25 | 1998-08-20 | ローム株式会社 | Method of forming bump electrode in electronic component |
-
1993
- 1993-03-17 JP JP5698993A patent/JP3364266B2/en not_active Ceased
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2788694B2 (en) | 1992-09-25 | 1998-08-20 | ローム株式会社 | Method of forming bump electrode in electronic component |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06267964A (en) | 1994-09-22 |
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