JP3344364B2 - Lead frame and semiconductor device using the same - Google Patents
Lead frame and semiconductor device using the sameInfo
- Publication number
- JP3344364B2 JP3344364B2 JP14414299A JP14414299A JP3344364B2 JP 3344364 B2 JP3344364 B2 JP 3344364B2 JP 14414299 A JP14414299 A JP 14414299A JP 14414299 A JP14414299 A JP 14414299A JP 3344364 B2 JP3344364 B2 JP 3344364B2
- Authority
- JP
- Japan
- Prior art keywords
- capacitor
- lead
- bonding
- lead frame
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
- H01L2924/30111—Impedance matching
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体チップが搭
載されたリードフレーム及びそれを使用した半導体装置
に関し、特に、リード端子上にコンデンサを内蔵して信
号の直流成分をカット（ＤＣカット）できるようにした
リードフレーム及びそれを使用した半導体装置に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame on which a semiconductor chip is mounted and a semiconductor device using the same, and more particularly, a capacitor is built in a lead terminal so that a DC component of a signal can be cut (DC cut). And a semiconductor device using the same.
【０００２】[0002]
【従来の技術】一般に、高周波信号を扱う半導体素子が
搭載されたリードフレーム型半導体装置においては、外
部回路とのインピーダンスのマッチングをとるため、又
は直流成分の伝達を阻止（ＤＣカット）して信号を高速
で伝達するために容量成分が設けられている。2. Description of the Related Art Generally, in a lead frame type semiconductor device on which a semiconductor element for handling a high-frequency signal is mounted, a signal is obtained by matching impedance with an external circuit or by preventing transmission of a DC component (DC cut). Is provided at a high speed to transmit the signal at high speed.
【０００３】従来、このようなマッチング又はＤＣカッ
トのために、パッケージの外側の基板上に配線パターン
を形成し、その適所にスリット等を設けてコンデンサ等
のチップ部品を搭載していた。Conventionally, for such matching or DC cutting, a wiring pattern is formed on a substrate outside a package, and a slit or the like is provided in an appropriate position to mount a chip component such as a capacitor.
【０００４】ＤＣカットとは、８００ＭＨｚ以上の周波
数の信号である高周波信号のみを伝達（導通）させる方
法であり、１００ｐＦ程度のコンデンサを配線パターン
のスリット部へ搭載することにより、高周波におけるイ
ンピーダンスを低くする。[0004] The DC cut is a method of transmitting (conducting) only a high-frequency signal which is a signal of a frequency of 800 MHz or more. By mounting a capacitor of about 100 pF on a slit portion of a wiring pattern, impedance at a high frequency is reduced. I do.
【０００５】この場合、信号周波数をｆ、搭載コンデン
サの容量をＣとすると、インピーダンスＩｍｐは、下記
数式１で求められる。In this case, assuming that the signal frequency is f and the capacitance of the mounted capacitor is C, the impedance Imp is obtained by the following equation (1).
【０００６】[0006]
【数１】Ｉｍｐ＝１／（２×π×ｆ×Ｃ）## EQU1 ## Imp = 1 / (2 × π × f × C)
【０００７】従って、例えば導通させたい信号の周波数
ｆを８００ＭＨｚ、搭載コンデンサの容量Ｃを１００ｐ
Ｆとすると、数式１より８００ＭＨｚの場合のインピー
ダンスは１．９９（Ω）≒２．０（Ω）となる。このイ
ンピーダンスは十分小さいため、８００ＭＨｚ以上の信
号では問題なくこのコンデンサを導通する。Therefore, for example, the frequency f of the signal to be made conductive is 800 MHz, and the capacity C of the mounted capacitor is 100 p.
Assuming that F, the impedance at 800 MHz is 1.99 (Ω) ≒ 2.0 (Ω) according to Equation 1. Since this impedance is sufficiently small, this capacitor is conducted without any problem with a signal of 800 MHz or more.
【０００８】一方、８００ＭＨｚ以下の周波数の信号に
おいては、周波数が低くなればなるほど高インピーダン
スになり、信号の損失が大きくなる。例えば、導通させ
たい信号を１００ＭＨｚ、搭載コンデンサを１００ｐＦ
とすると、数式１よりインピーダンスＩｍｐは約１６
（Ω）となり、高周波信号の場合に比べて高いため、こ
のコンデンサにより低周波信号の伝達が阻止される。On the other hand, in the case of a signal having a frequency of 800 MHz or less, the lower the frequency, the higher the impedance, and the greater the loss of the signal. For example, the signal to be made conductive is 100 MHz, and the mounted capacitor is 100 pF
From Equation 1, the impedance Imp is about 16
(Ω), which is higher than that of a high-frequency signal. Therefore, transmission of a low-frequency signal is prevented by this capacitor.
【０００９】上述の如くしてＤＣカットを行うことがで
きるが、この方法では信号の入出力端子部へ夫々１００
ｐＦのチップコンデンサを設けることが必要となる。従
って、パッケージ外側の搭載部品を無くさない限り、シ
ステムの小型化を図ることはできない。The DC cut can be performed as described above. In this method, 100
It is necessary to provide a chip capacitor of pF. Therefore, the size of the system cannot be reduced unless the mounted components outside the package are eliminated.
【００１０】また、１００ｐＦのコンデンサを半導体チ
ップ内部の半導体基板上に形成しようとすると、基板上
に５０００ｍ2の面積が必要（１００ｍ2／２ｐＦ）とな
り、従ってこのようなコンデンサを半導体チップ内に納
めることは、面積上及びコスト上の面から不可能であ
る。Further, if a capacitor of 100 pF is to be formed on a semiconductor substrate inside a semiconductor chip, an area of 5000 m 2 is required on the substrate (100 m 2/2 pF). Therefore, such a capacitor cannot be accommodated in the semiconductor chip. However, this is not possible in terms of area and cost.
【００１１】そこで、特開平２−６２０６９号公報に
は、半導体チップ上へコンデンサ部品を搭載することが
提案されている（従来例１）。図３はこの従来例１の半
導体装置を示す断面図である。Therefore, Japanese Patent Laid-Open Publication No. Hei 2-62069 proposes mounting a capacitor component on a semiconductor chip (conventional example 1). FIG. 3 is a cross-sectional view showing the semiconductor device of the first conventional example.
【００１２】図３に示すように、リードフレーム１２上
に半導体集積回路チップ１３が搭載され、チップ１３の
端子とリードフレーム１２のリード端子とをボンディン
グワイヤ１４でボンディングすることによりリードフレ
ーム１２と半導体集積回路チップ１３とが電気的に接続
されている。そして、下面にコンデンサ１６が形成され
たコンデンサ部品としてのシリコンチップ１７が半導体
集積回路チップ１３上に搭載され、半導体集積回路チッ
プ１３の電極１８とシリコンチップ１７の電極１９とは
ハンダ２０のリフローにより接続されている。更に、モ
ールド樹脂１５で全体が封止されている。As shown in FIG. 3, a semiconductor integrated circuit chip 13 is mounted on a lead frame 12, and the terminals of the chip 13 and the lead terminals of the lead frame 12 are bonded to each other by bonding wires 14. The integrated circuit chip 13 is electrically connected. Then, a silicon chip 17 as a capacitor component having a capacitor 16 formed on the lower surface is mounted on the semiconductor integrated circuit chip 13, and the electrodes 18 of the semiconductor integrated circuit chip 13 and the electrodes 19 of the silicon chip 17 are reflowed by solder 20. It is connected. Further, the whole is sealed with a mold resin 15.
【００１３】しかしながら、この従来例１においては、
組み立て工程において、高精度のマウント装置が必要に
なる他、組み立て工程が増えるためにコストが増大する
という問題点がある。However, in the conventional example 1,
In the assembling process, there is a problem that a high-precision mounting device is required, and the cost is increased due to an increase in the number of assembling processes.
【００１４】そこで、特開平９−８２８７９号公報に
は、チップ部品をパッケージ内部に直接組み立てること
が提案されている（従来例２）。図４は特開平９−８２
８７９号公報に記載された樹脂封止型半導体装置を示す
図であって、（ａ）は平面図、（ｂ）は（ａ）の矢印Ｃ
から見た側面図である。Japanese Patent Application Laid-Open No. 9-82879 proposes to assemble chip components directly inside a package (prior art 2). FIG.
879 is a view showing a resin-sealed semiconductor device described in Japanese Patent Application Publication No. 879, where (a) is a plan view and (b) is an arrow C in (a).
It is the side view seen from.
【００１５】図４に示すように、リードフレーム２１の
冷却体部２２にトランジスタチップ２３が高温ハンダで
接合され、端子部２４ｂ，２４ｃに集積回路チップ２５
ａ及びダイオードチップ２５ｂが高温ハンダで接合さ
れ、端子部の裏面で端子部２４ｂ，２４ｄ間に抵抗体２
６ａとコンデンサ２７ａとが中温ハンダで接合され、端
子部２４ｃ，２４ｅ間に抵抗体２６ｂとコンデンサ２７
ｂとが同様に中温ハンダで接合され、冷却体部２２と端
子部２４ａ〜２４ｄの一部が破線で示すようにモールド
樹脂２８によりモールド封止されている。As shown in FIG. 4, a transistor chip 23 is joined to a cooling portion 22 of a lead frame 21 by high-temperature solder, and integrated circuit chips 25 are attached to terminal portions 24b and 24c.
a and the diode chip 25b are joined by high-temperature solder, and the resistor 2
6a and the capacitor 27a are joined by middle temperature solder, and the resistor 26b and the capacitor 27a are connected between the terminal portions 24c and 24e.
Similarly, the cooling member 22 and a part of the terminal portions 24a to 24d are molded and sealed with the molding resin 28 as indicated by broken lines.
【００１６】また、従来例２においては、チップ部品を
パッケージ内部に組み立てるため、パッケージ容積がチ
ップ部品の容量より十分大きく、パッケージサイズがチ
ップ部品より極めて大きいことを前提としており、近時
の高密度実装に対応するために小型化が要求されるパッ
ケージには搭載することができない。In the second conventional example, since the chip components are assembled inside the package, it is assumed that the package volume is sufficiently larger than the capacity of the chip components and the package size is extremely larger than the chip components. It cannot be mounted on a package that requires miniaturization to support mounting.
【００１７】更に、実開昭６１−９０２５６号公報に
は、ボンディングワイヤがボンディングされる部分のリ
ード引き出し線にコンデンサを内蔵した集積回路（Ｉ
Ｃ）パッケージが提案されている（従来例３）。図５は
実開昭６１−９０２５６号公報に開示されているコンデ
ンサを内蔵したＩＣパッケージを示す断面図である。図
５（ａ）に示すＩＣパッケージは、パッケージ基板３１
に導体３６が接合され、その上に誘電体３７が重ねら
れ、更にその上にリード引き出し線３５が配線されてい
る。集積回路チップ３２はパッケージ基板３１上に搭載
され、その集積回路チップ３２のパッド３４とリード引
き出し線３５とがボンディング線３３によって接続され
ている。リード引き出し線３５と導体３６は全部又は一
部が誘電体３７を介して重なっており、コンデンサの電
極を形成している。リード引き出し線３５は外部リード
を介して外部回路に接続され、導体３６はグランド端子
に接続され、リード引き出し線３５を交流的に接地して
いる。Further, Japanese Utility Model Application Laid-Open No. 61-90256 discloses an integrated circuit (I) in which a capacitor is built in a lead lead wire at a portion where a bonding wire is bonded.
C) A package has been proposed (conventional example 3). FIG. 5 is a sectional view showing an IC package having a built-in capacitor disclosed in Japanese Utility Model Laid-Open No. 61-90256. The IC package shown in FIG.
Is connected to a conductor 36, a dielectric 37 is superimposed on the conductor 36, and a lead wire 35 is further wired thereon. The integrated circuit chip 32 is mounted on a package substrate 31, and the pads 34 of the integrated circuit chip 32 are connected to lead leads 35 by bonding wires 33. All or a part of the lead wire 35 and the conductor 36 overlap with the dielectric 37 interposed therebetween, and form an electrode of the capacitor. The lead wire 35 is connected to an external circuit via an external lead, the conductor 36 is connected to a ground terminal, and the lead wire 35 is AC grounded.
【００１８】一方、図５（ｂ）に示す従来例３の他のＩ
Ｃパッケージにおいては、パッケージ基板３１にリード
引き出し線３５が接合され、その上に誘電体３７を介し
て導体３６が重ねられている。ボンディング線３３は導
体３６の上に接続され、リード引き出し線３５に接続さ
れる端子を接地することによりバイパスコンデンサが形
成されている。このようにいずれのＩＣパッケージにお
いても、このリード引き出し線部にコンデンサが形成さ
れており、これにより端子を交流接地し低インピーダン
ス化を図っている。On the other hand, in the conventional example 3 shown in FIG.
In the C package, a lead wire 35 is bonded to a package substrate 31, and a conductor 36 is superposed on the lead wire 35 via a dielectric 37. The bonding wire 33 is connected to the conductor 36, and a terminal connected to the lead wire 35 is grounded to form a bypass capacitor. As described above, in any of the IC packages, the capacitor is formed in the lead lead-out portion, and the terminal is AC grounded to reduce the impedance.
【００１９】[0019]
【発明が解決しようとする課題】しかしながら、この従
来例３のＩＣパッケージでは、チップ製造前にコンデン
サを付ける端子を決めておく必要があり、チップ製造後
は、コンデンサを付ける端子を選択することはできなか
った。However, in the IC package of the conventional example 3, it is necessary to determine a terminal to which a capacitor is to be attached before manufacturing the chip. could not.
【００２０】本発明はかかる問題に鑑みてなされたもの
であって、小型化した半導体パッケージ内部のリード端
子上にコンデンサを設け、組み立て時にそのコンデンサ
を接続すべきリード端子を選択することができるリード
フレーム及びそれを使用した半導体装置を提供すること
を目的とする。The present invention has been made in view of such a problem, and a lead is provided on a lead terminal inside a miniaturized semiconductor package, and a lead terminal to which the capacitor is to be connected can be selected at the time of assembly. It is an object to provide a frame and a semiconductor device using the same.
【００２１】[0021]
【課題を解決するための手段】本発明に係るリードフレ
ームは、半導体チップが搭載されるアイランド部と、ボ
ンディングワイヤが接続される第１のボンディング部を
有する複数個のリード端子と、前記各リード端子におけ
る前記第１のボンディング部以外の２以上の位置に局部
的に形成された各２個以上の容量絶縁膜と、前記各容量
絶縁膜上に形成された上部電極とを有し、前記上部電
極、容量絶縁膜及びリード端子から各リード端子につい
て２個以上のコンデンサが構成され、前記上部電極はボ
ンディングワイヤが接続される第２のボンディング部と
しても機能することを特徴とする。A lead frame in accordance with the present invention Summary of] the plurality of lead terminals having a island portion on which a semiconductor chip is mounted, a first bonding portion that Bo <br/> down loading wire is connected And two or more capacitive insulating films locally formed at two or more positions other than the first bonding portion in each of the lead terminals, and an upper electrode formed on each of the capacitive insulating films. Each of the lead terminals from the upper electrode, the capacitive insulating film and the lead terminals.
Thus, two or more capacitors are formed, and the upper electrode also functions as a second bonding portion to which a bonding wire is connected.
【００２２】また、前記第１のボンディング部が、前記
リード端子における前記アイラン部側の端から２００μ
ｍ以下の部分に形成されていることが好ましい。 The first bonding portion may
200 μm from the end of the lead terminal on the island side
It is preferably formed in a portion of m or less.
【００２３】本発明に係る半導体装置は、前記リードフ
レームと、前記アイランド部に搭載された半導体チップ
と、前記半導体チップの各パッドと前記第１のボンディ
ング部又は前記第２のボンディング部とを選択的に接続
するボンディングワイヤと、を有することを特徴とす
る。 The semiconductor device according to the present invention is characterized in that:
And a semiconductor chip mounted on the island portion
And each pad of the semiconductor chip and the first bond
Selective connection with the bonding part or the second bonding part
And a bonding wire that performs
You.
【００２４】本発明に係る半導体装置は、前記半導体チ
ップ及びコンデンサは樹脂により封止されていることを
特徴とする。 The semiconductor device according to the present invention is characterized in that the semiconductor chip
The capacitors and capacitors are sealed with resin.
Features.
【００２５】本発明においては、組み立て時のボンディ
ング工程において、半導体チップのボンディングパッド
とリード端子上のボンディング部とを接続するか、又は
前記ボンディングパッドとリード端子上のコンデンサの
上部電極とを接続するかを選択することができる。これ
により、組み立て時に、コンデンサを利用せずに直流成
分を導通するようにすることもできるし、また前記コン
デンサを利用してリード端子にコンデンサを選択し、そ
のリード端子でマッチング又はＤＣカットを行うことも
できる。In the present invention, in the bonding step at the time of assembly, the bonding pad of the semiconductor chip is connected to the bonding portion on the lead terminal, or the bonding pad is connected to the upper electrode of the capacitor on the lead terminal. You can choose. Thereby, at the time of assembly, a DC component can be conducted without using a capacitor, and a capacitor is selected as a lead terminal using the capacitor, and matching or DC cutting is performed at the lead terminal. You can also.
【００２６】また、各リード端子に複数個のコンデンサ
を設けることにより、容量値を調節することができる。Further, by providing a plurality of capacitors for each lead terminal, the capacitance value can be adjusted.
【００２７】[0027]
【発明の実施の形態】以下、本発明の参考例及び実施例
に係るリードフレーム及びそれを使用した半導体装置に
ついて、添付の図面を参照して具体的に説明する。図１
は、本発明の参考例に係るリードフレーム及びそれを使
用した半導体装置を示す図であって、（ａ）は平面図、
（ｂ）は（ａ）の矢印Ａから見た側面図である。図１に
示すように、リードフレーム１は半導体チップ２を搭載
するためのアイランド部３と、複数個のリード端子４
と、により構成されている。各リード端子４はボンディ
ング部５と、ボンディング部５以外の位置に局部的に形
成された容量絶縁膜６と、容量絶縁膜６上に形成された
上部電極７と、を有し、リード端子４、容量絶縁膜６及
び上部電極７からコンデンサ８が構成されている。ボン
ディング部５はアイランド部３側の端から２００μｍま
でとし、それ以外の位置に必要な容量を得ることができ
るだけの面積に高誘電体物質を堆積することにより容量
絶縁膜６が形成されている。また、上部電極７は容量絶
縁膜６と同程度の面積の金属パッドで形成されている。
このように構成されたリードフレーム１のアイランド部
３に半導体チップ２が搭載されており、半導体チップ２
の各パッド９とリード端子４上のボンディング部５又は
コンデンサ８の上部電極７とが選択的に接続されるボン
ディングワイヤ１０ａ，１０ｂを有する。更に、リード
フレーム、リードフレーム上の半導体チップ２、選択さ
れたボンディングワイヤ１０ａ，１０ｂ及びリード端子
４上のコンデンサ８はモールド封止１１によりパッケー
ジ化されている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A lead frame according to a reference example and an embodiment of the present invention and a semiconductor device using the same will be specifically described below with reference to the accompanying drawings. FIG.
1A is a diagram showing a lead frame according to a reference example of the present invention and a semiconductor device using the same, FIG.
(B) is a side view seen from arrow A of (a). As shown in FIG. 1, a lead frame 1 includes an island portion 3 for mounting a semiconductor chip 2 and a plurality of lead terminals 4.
, And is constituted. Each lead terminal 4 includes a bonding portion 5, a capacitance insulating film 6 locally formed at a position other than the bonding portion 5, and an upper electrode 7 formed on the capacitance insulating film 6. , A capacitor insulating film 6 and an upper electrode 7 constitute a capacitor 8. The capacity of the bonding portion 5 is set to 200 μm from the end on the island portion 3 side, and a capacitor insulating film 6 is formed by depositing a high dielectric substance in an area where a required capacity can be obtained at other positions. The upper electrode 7 is formed of a metal pad having an area approximately equal to that of the capacitor insulating film 6.
The semiconductor chip 2 is mounted on the island portion 3 of the lead frame 1 thus configured.
Bonding wires 10a and 10b for selectively connecting each of the pads 9 to the bonding portion 5 on the lead terminal 4 or the upper electrode 7 of the capacitor 8. Further, the lead frame, semi-conductor chip 2 on the lead frame, the capacitor 8 on the bonding wires 10a, 10b and the lead terminal 4 selected are packaged by a mold seal 11.
【００２８】本参考例に係る半導体装置によれば、本参
考例に係るリードフレームを使用することにより、高周
波デバイスの特性を考慮し、組み立て工程における結線
時にボンディングワイヤを選択することができる。即
ち、直流の導通が必要なときは半導体チップ２のパッド
９からリード端子４へボンディングワイヤ１０ａを選択
して直接結線することができる。また、直流の導通が必
要なく、直流カットして高周波の信号を導通させたいと
きはパッド９からコンデンサ８の上部電極７へボンディ
ングワイヤ１０ｂを選択して結線することにより、この
リード端子にコンデンサ８を接続することができる。According to the semiconductor device according to the present embodiment, the ginseng
By using a lead frame according to the considered example, in consideration of the characteristics of the high frequency device, it is possible to select a bonding wire during connection in the assembly process. That is, when direct current conduction is required, the bonding wire 10a can be selected and directly connected from the pad 9 of the semiconductor chip 2 to the lead terminal 4. Further, when DC conduction is not required and it is desired to cut off the DC and conduct a high-frequency signal, a bonding wire 10b is selected and connected from the pad 9 to the upper electrode 7 of the capacitor 8, thereby connecting the capacitor 8 to the lead terminal. Can be connected.
【００２９】本参考例において、リード端子４上に形成
されたコンデンサ８を半導体装置に組み込むか、又は組
み込まないことが組み立て工程でボンディングワイヤを
どこに接合するかにより選択可能であるために、汎用的
に製造されたリードフレームを用いて用途の異なる半導
体装置を製造することが可能となり、生産コストを低減
することができる。[0029] In this reference example, to either embed the capacitor 8 formed on the lead terminals 4 in the semiconductor device, or not it is to incorporated can be selected by either joining where a bonding wire during the assembly process, general It is possible to manufacture semiconductor devices having different applications by using the lead frame manufactured as described above, and it is possible to reduce the production cost.
【００３０】また、コンデンサ８はモールド封止１１内
のリード端子４上に形成されているため、パッケージと
外部回路とのインピーダンスのマッチングをとるため、
又は直流成分の伝達を阻止して信号を高速で伝えるため
に、パッケージ外側基板上にコンデンサ等のチップ部品
を設ける必要がなくパッケージを小型化及び軽量化する
ことができる。Further, since the capacitor 8 is formed on the lead terminal 4 in the mold sealing 11, in order to match the impedance between the package and the external circuit,
Alternatively, it is not necessary to provide a chip component such as a capacitor on the package outer substrate in order to transmit a signal at a high speed by preventing the transmission of a DC component, so that the package can be reduced in size and weight.
【００３１】次に、本発明の実施例について説明する。
図２は本発明の実施例に係るリードフレーム及びそれを
使用した半導体装置を示す図であって、（ａ）は平面
図、（ｂ）は（ａ）の矢印Ｂから見た側面図である。本
実施例は参考例においてリード端子４上に形成されたコ
ンデンサを１個から２個に増設したものである。[0031] Next, a description will be given of the actual施例of the present invention.
Figure 2 is a diagram showing a semiconductor device using the lead frame and it according to the actual施例of the present invention, (a) is a plan view, (b) is a side view seen from the arrow B of (a) is there. In this embodiment, the number of capacitors formed on the lead terminal 4 in the reference example is increased from one to two.
【００３２】図２に示すように、各リード端子４は、参
考例と同様なボンディング部５と、ボンディング部５以
外の位置に局部的に形成された２つの容量絶縁膜６ａ,
６ｂと、各容量絶縁膜６ａ,６ｂ上に形成された上部電
極７ａ,７ｂと、を有し、リード端子４、容量絶縁膜６
ａ,６ｂ及び上部電極７ａ,７ｂから２つのコンデンサ８
ａ,８ｂが構成されている。また、リードフレーム１の
アイランド部３に半導体チップ２が搭載されており、こ
のチップ２上のパッド９から直接リードフレーム端子４
のボンディング部５に結線されるボンディングワイヤ１
０ａと、パッド９からコンデンサ８ａの上部電極７ａに
結線されるボンディングワイヤ１０ｂと、コンデンサ８
ａの上部電極７ａからコンデンサ８ｂの上部電極７ｂに
結線されるボンディングワイヤ１０ｃとが各リード端子
４について選択的に設けられている。As shown in FIG. 2, the lead terminals 4, ginseng
Remarks Examples similar to the bonding portion 5, two capacitor insulating film 6a that is locally formed at a position other than the bonding portion 5,
6b and upper electrodes 7a and 7b formed on the respective capacitor insulating films 6a and 6b.
a, 6b and two electrodes 8 from the upper electrodes 7a, 7b.
a, 8b. The semiconductor chip 2 is mounted on the island portion 3 of the lead frame 1, and the lead frame terminals 4 are directly connected to the pads 9 on the chip 2.
Bonding wire 1 connected to the bonding portion 5
A bonding wire 10b connected from the pad 9 to the upper electrode 7a of the capacitor 8a;
A bonding wire 10c connected from the upper electrode 7a to the upper electrode 7b of the capacitor 8b is selectively provided for each lead terminal 4.
【００３３】前述の参考例はコンデンサ容量自体の調整
はできなかったが、本実施例は組み立て時に２個のコン
デンサ８ａ，８ｂ及びボンディング部５に対してボンデ
ィングワイヤをどのように結線するかを選択することに
よりコンデンサの容量値を調整することができる。即
ち、ボンディングワイヤ１０ａ，１０ｂ及び１０ｃを組
み合わせることにより、モールド領域１１内のリード端
子４上に形成したコンデンサ８ａ，８ｂをマッチング用
についても適用することができる。なお、図２におい
て、パッド９とコンデンサ８ａ又は８ｂとのみをボンデ
ィングワイヤにより接続することとしてもよい。[0033] While reference example described above could not adjust the capacitance itself, the actual施例the two capacitors 8a during assembly, the how to connect the bonding wire against 8b and the bonding portion 5 The selection makes it possible to adjust the capacitance value of the capacitor. That is, by combining the bonding wires 10a, 10b and 10c, the capacitors 8a and 8b formed on the lead terminals 4 in the mold area 11 can be applied for matching. In FIG. 2, only the pad 9 and the capacitor 8a or 8b may be connected by a bonding wire.
【００３４】また、リード端子上のコンデンサは２個以
上形成されてもよい。また、リード端子４上の容量絶縁
膜６において、堆積する高誘電体物質の体積量を変える
ことによっても、更に上部電極７の金属パッドの大きさ
を変えることによっても容量の調節をすることができ
る。従って、容量値の異なる複数のコンデンサをリード
端子上に形成することにより、容量値のより細かい調整
をすることができる。Further, two or more capacitors may be formed on the lead terminals. Further, in the capacitance insulating film 6 on the lead terminal 4, the capacitance can be adjusted by changing the volume of the high dielectric substance to be deposited or by changing the size of the metal pad of the upper electrode 7. it can. Therefore, by forming a plurality of capacitors having different capacitance values on the lead terminals, more fine adjustment of the capacitance value can be performed.
【００３５】なお、本発明は上記実施例に限定されず、
種々の変形が可能である。各リード端子に形成しておく
コンデンサの数は、１又は２個に限らず、３個以上とし
てもよく、これにより、容量値の調整がより一層容易に
なる。The present invention is not limited to the above embodiment,
Various modifications are possible. The number of capacitors formed on each lead terminal is not limited to one or two, but may be three or more, which makes it easier to adjust the capacitance value.
【００３６】[0036]
【発明の効果】以上詳述したように、本発明によれば、
モールドパッケージ内のリードフレームの端子部上にボ
ンディング部とこのボンディング部以外の位置に複数の
コンデンサを形成したので、そのリード端子について、
組み立て工程において、直流を導通させるか又は導通さ
せないかをボンディングワイヤをどこに接合するかで選
択することができ、また、半導体パッケージの外部にマ
ッチング及びＤＣカットのためのコンデンサを設ける必
要がなくなるため、半導体装置の小型化及び軽量化が実
現できる。As described in detail above, according to the present invention,
Since a bonding portion and a plurality of capacitors were formed at positions other than the bonding portion on the terminal portion of the lead frame in the mold package,
In the assembling process, it is possible to select whether or not to conduct the direct current depending on where the bonding wire is bonded, and it is not necessary to provide a capacitor for matching and DC cut outside the semiconductor package, The size and weight of the semiconductor device can be reduced.
【図１】本発明の参考例に係るリードフレーム及びそれ
を使用した半導体装置を示す図であって、（ａ）は平面
図、（ｂ）は（ａ）の矢印Ａから見た側面図である。1A and 1B are views showing a lead frame and a semiconductor device using the same according to a reference example of the present invention, wherein FIG. 1A is a plan view, and FIG. 1B is a side view as viewed from an arrow A in FIG. is there.
【図２】本発明の実施例に係るリードフレーム及びそれ
を使用した半導体装置を示す図であって、（ａ）は平面
図、（ｂ）は（ａ）の矢印Ｂから見た側面図である。[Figure 2] A diagram showing a semiconductor device using the lead frame and the same according to the actual施例of the present invention, (a) is a plan view, (b) is a side view seen from an arrow B of (a) It is.
【図３】特開平２−６２０６９号公報に開示されている
半導体装置を示す断面図である。FIG. 3 is a sectional view showing a semiconductor device disclosed in Japanese Patent Application Laid-Open No. 2-62069.
【図４】特開平９−８２８７９号公報に記載された樹脂
封止型半導体装置を示す図であって、（ａ）は平面図、
（ｂ）は（ａ）の矢印Ｃから見た側面図である。FIG. 4 is a view showing a resin-sealed semiconductor device described in Japanese Patent Application Laid-Open No. 9-82879, wherein FIG.
(B) is a side view seen from arrow C of (a).
【図５】（ａ）及び（ｂ）は実開昭６１−９０２５６号
公報に開示されているコンデンサを内蔵した集積回路パ
ッケージを示す断面図である。FIGS. 5A and 5B are cross-sectional views showing an integrated circuit package having a built-in capacitor disclosed in Japanese Utility Model Laid-Open Publication No. 61-90256.
１；リードフレーム ２；半導体チップ ３；アイランド部 ４；リード端子 ５；ボンディング部 ６，６ａ,６ｂ；容量絶縁膜 ７，７ａ,７ｂ；上部電極 ８，８ａ,８ｂ；コンデンサ ９；パッド １０ａ,１０ｂ,１０ｃ；ボンディングワイヤ １１；モールド領域 １２；リードフレーム １３；半導体集積回路チップ １４；ボンディングワイヤ １５；モールド樹脂 １６；コンデンサ １７；シリコンチップ １８，１９；接続電極 ２０；ハンダ ２１；リードフレーム ２２；冷却体部 ２３；トランジスタチップ ２４ａ，２４ｂ，２４ｃ，２４ｄ，２４ｅ；端子部 ２５ａ；集積回路チップ ２５ｂ；ダイオードチップ ２６ａ，２６ｂ；抵抗体 ２７ａ，２７ｂ；コンデンサ ２８；モールド樹脂 ２９；アルミ線 ３０；金線 ３１；パッケージ基板 ３２；集積回路チップ ３３；ボンディング線 ３４；パッド ３５；リード引き出し線 ３６；導体 ３７；誘電体 DESCRIPTION OF SYMBOLS 1; Lead frame 2; Semiconductor chip 3; Island part 4; Lead terminal 5; Bonding part 6, 6a, 6b; Capacitance insulating film 7, 7a, 7b; Upper electrode 8, 8a, 8b; Capacitor 9; Pad 10a, 10b Bonding wire 11; Mold area 12; Lead frame 13; Semiconductor integrated circuit chip 14; Bonding wire 15; Mold resin 16; Capacitor 17; Silicon chips 18, 19; Connection electrode 20; Solder 21; Lead frame 22; Body 23; Transistor chips 24a, 24b, 24c, 24d, 24e; Terminal 25a; Integrated circuit chip 25b; Diode chips 26a, 26b; Resistors 27a, 27b; Capacitor 28; Mold resin 29; Aluminum wire 30; 31; package substrate 32; collection Circuit chip 33; bonding wire 34; pad 35; lead lead wire 36; conductor 37; dielectric
Claims (5)
と、ボンディングワイヤが接続される第１のボンディン
グ部を有する複数個のリード端子と、前記各リード端子
における前記第１のボンディング部以外の２以上の位置
に局部的に形成された各２個以上の容量絶縁膜と、前記
各容量絶縁膜上に形成された上部電極とを有し、前記上
部電極、容量絶縁膜及びリード端子から各リード端子に
ついて２個以上のコンデンサが構成され、前記上部電極
はボンディングワイヤが接続される第２のボンディング
部としても機能することを特徴とするリードフレーム。A plurality of lead terminals having an island portion on which a semiconductor chip is mounted, a first bonding portion to which a bonding wire is connected, and a plurality of lead terminals other than the first bonding portion in each of the lead terminals; And two or more capacitive insulating films locally formed at the position of, and an upper electrode formed on each of the capacitive insulating films. Wherein two or more capacitors are formed, and the upper electrode also functions as a second bonding portion to which a bonding wire is connected.
ド端子における前記アイランド部側の端から２００μｍ
以下の部分に形成されていることを特徴とする請求項１
に記載のリードフレーム。2. The method according to claim 1, wherein the first bonding portion is 200 μm from an end of the lead terminal on the island portion side.
Claim 1, characterized in that it is formed in the following parts
The lead frame according to 1.
と、前記アイランド部に搭載された半導体チップと、前
記半導体チップの各パッドと前記第１のボンディング部
又は前記第２のボンディング部とを選択的に接続するボ
ンディングワイヤと、を有することを特徴とする半導体
装置。3. The lead frame according to claim 1, wherein the semiconductor chip is mounted on the island portion, and each pad of the semiconductor chip is connected to the first bonding portion or the second bonding portion. And a bonding wire for selectively connecting.
により封止されていることを特徴とする請求項３に記載
の半導体装置。4. The semiconductor device according to claim 3 , wherein the semiconductor chip and the capacitor are sealed with a resin.
周波信号を伝達させるものであることを特徴とする請求
項３又は４に記載の半導体装置。5. The semiconductor device according to claim 3, wherein said capacitor transmits a high-frequency signal of 800 MHz or more.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14414299A JP3344364B2 (en) | 1999-05-24 | 1999-05-24 | Lead frame and semiconductor device using the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14414299A JP3344364B2 (en) | 1999-05-24 | 1999-05-24 | Lead frame and semiconductor device using the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000332190A JP2000332190A (en) | 2000-11-30 |
| JP3344364B2 true JP3344364B2 (en) | 2002-11-11 |
Family
ID=15355212
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14414299A Expired - Fee Related JP3344364B2 (en) | 1999-05-24 | 1999-05-24 | Lead frame and semiconductor device using the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3344364B2 (en) |
-
1999
- 1999-05-24 JP JP14414299A patent/JP3344364B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2000332190A (en) | 2000-11-30 |
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