JP2003332515A - Semiconductor integrated circuit device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To increase a power source noise reduction effect and reduce a mounting area. <P>SOLUTION: A re-wiring layer 23 including a wiring layer 24 for a power source and a wiring layer 25 for the ground is formed on a semiconductor integrated circuit chip 21. The respective wiring layers are connected with external electrodes formed on the chip 21 by using connection holes. Positions of the connection holes 26, 27 formed in the wiring layers 24, 25 are adjusted in such a manner that the size and pitch of a junction member formed on the uppermost layer of the re-wiring layer 23 are conformable to sizes and pitches of electrodes of electronic components 22. As a result, the electronic components 22 different in sizes and pitches of electrodes can be mounted on the chip 21. When the electronic components 22 are noise countermeasure components, a wiring length for electrically connecting the components 22 with the chip 21 can be reduced to a minimum. The inductance of the wiring length is reduced, and power source system noise can remarkably be reduced. The mounting area can be also reduced. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device having a semiconductor integrated circuit chip mounted thereon and a method of manufacturing the same, and more particularly to a semiconductor integrated circuit device suitable for mounting noise suppression components and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, a small electronic device having a high-speed processing function represented by image processing, communication processing, and multimedia processing uses a semiconductor integrated circuit chip which has a high operation speed and a high degree of integration. Has been realized. In order to realize such an electronic device, stable operation of the semiconductor integrated circuit chip having a high operation speed and a high degree of integration, that is, suppressing the power supply noise voltage to a predetermined value or less,
It is important to prevent malfunction of the semiconductor integrated circuit chip.

The power supply noise voltage is generated due to the fluctuation of the current consumption due to the operation of the electronic circuit and the impedance of the power supply system. Here, as a method for reducing the impedance of the power supply system, a method using a bypass capacitor is known. This is to connect a capacitor between different types of power supplies or between the wiring between the power supply and ground, and to install this capacitor near the electronic circuit to reduce the impedance of the power supply system to the electronic circuit. is there.

As a method of arranging a bypass capacitor for the purpose of reducing the impedance of such a power supply system, various methods as shown below have been conventionally proposed.

FIG. 5 is a sectional view showing a part of an electronic circuit device in which a conventional bypass capacitor is arranged. In this electronic circuit device, in order to reduce the power supply noise of the semiconductor integrated circuit chip 2 which is sealed and constitutes the package 1,
It has the following configuration. That is, the mounting board 3
Is a power supply electric wiring layer 5 electrically connected to the power supply external terminal 4 in the package 1 and a ground external terminal 6
And an electrical wiring layer for ground 7 electrically connected to. Then, the bypass capacitor 8 is arranged as a so-called external component in the peripheral portion of the package 1 on the mounting substrate 3 and is electrically connected to the power supply electric wiring layer 5 and the ground electric wiring layer 7 (hereinafter , The first conventional example).

Another example is a package as shown in FIG. In this package, the semiconductor integrated circuit chip 13 and the capacitor 14 are mounted on the same lead frame 12 in the package 11.
Thus, the capacitor 14 and the semiconductor integrated circuit chip 13
The length of the wiring (bonding wire 15 and lead frame 12) for connecting to and is shortened to reduce the inductance (hereinafter referred to as the second conventional example).
Further, as described in Japanese Patent Publication No. 2500310, there is proposed one in which a capacitor is formed of a metal layer in a cap that seals a semiconductor integrated circuit chip.

[0007]

However, the conventional method of arranging the bypass capacitors described above has the following problems. That is, in the case of the first conventional example shown in FIG. 5, since the bypass capacitor 8 is arranged as an external component, even if an attempt is made to reduce the noise from the power supply electric wiring layer 5 by the bypass capacitor 8, the semiconductor integrated circuit is used. There is an electric wiring length between the power supply electrode (not shown) of the circuit chip 2 and the power supply electrode (not shown) of the bypass capacitor 8 via the power supply electric wiring layer 5. The effect of reducing noise becomes insufficient due to the inductance of the electric wiring length.

Further, since the bypass capacitor 8 is externally attached to the package 1, the mounting substrate 3
It is necessary to secure an area in which the bypass capacitor 8 is installed. Therefore, there is also a problem that the installation area of the bypass capacitor 8 becomes an obstacle to the reduction of the mounting area.

Also in the case of the second conventional example, similarly,
Since the capacitors 14 are arranged in a plane in the package 11, the capacitors 14 are arranged in the semiconductor integrated circuit chip 13
Is externally attached to. Therefore, it is necessary to secure a region on the lead frame 12 where the capacitor 14 is installed. Therefore, the package 11 itself becomes large.

Therefore, an object of the present invention is to provide a semiconductor integrated circuit device having a large effect of reducing power supply noise and a small mounting area, and a method of manufacturing the semiconductor integrated circuit device.

[0011]

To achieve the above object, a first invention is to mount a semiconductor integrated circuit chip on a wiring laminated substrate and electrically connect the wiring laminated substrate and the semiconductor integrated circuit chip. In a semiconductor integrated circuit device which is connected, encapsulates the semiconductor integrated circuit chip, and is provided with a plurality of external connection terminals on the wiring laminated substrate, patterned on the surface of the semiconductor integrated circuit chip via an insulating film. A wiring layer is formed by sandwiching each of one or more conductor layers with an insulating layer.Electronic components are mounted on the wiring layer and provided on the uppermost layer of the electronic component and the wiring layer. The electrodes are electrically connected to each other, and the wiring layer and the electronic component are sealed together with the semiconductor integrated circuit chip.

In one embodiment, in the semiconductor integrated circuit device according to the first aspect of the invention, there are a plurality of conductor layers forming the wiring layer, which are provided on the uppermost layer of the wiring layer and electrically connected to the electronic component. The plurality of electrodes that are electrically connected to each other are electrically connected to the different conductor layers described above through the connection holes. Here, the connection hole is a concept that also includes a conductor formed on the inner surface and the vicinity surface of the hole formed in the insulating layer sandwiching the conductor layer.

According to each of the above constructions, the wiring layer is formed on the surface of the semiconductor integrated circuit chip, the electronic component is mounted on the wiring layer, and the electrode provided on the uppermost layer of the wiring layer and the electronic component. And are electrically connected. Thus
Ground bounce noise is reduced by directly mounting the electronic component on the semiconductor integrated circuit chip. Furthermore, it is not necessary to externally attach the electronic component, and the mounting area is reduced. Further, if the lowermost insulating layer in the wiring layer is formed of, for example, a polyimide resin, the thermal stress between the semiconductor integrated circuit chip and the electronic component to be mounted is relieved.

In one embodiment, in the semiconductor integrated circuit device according to the first aspect of the invention, the semiconductor integrated circuit chip has a built-in semiconductor element, and the element surface of the semiconductor element is face-up.

According to this embodiment, the element surface of the semiconductor element incorporated in the semiconductor integrated circuit chip is faced up. Therefore, the external electrodes of the semiconductor element can be formed on the upper surface of the semiconductor integrated circuit chip,
It is possible to electrically connect the conductor layer of the wiring layer and the semiconductor integrated circuit chip with the shortest wiring length.

According to one embodiment, in the semiconductor integrated circuit device of the first invention, external electrodes are provided on the semiconductor integrated circuit chip, and each external electrode is
Electrically connected to the different conductor layers constituting the wiring layer via connection holes, the electronic component,
These are noise suppression components including bypass capacitors and filters.

According to this embodiment, the noise countermeasure component is mounted on the semiconductor integrated circuit chip, and the noise countermeasure component and the semiconductor integrated circuit chip are electrically connected via the wiring layer. ing. Therefore, the wiring length between the noise countermeasure component and the semiconductor integrated circuit chip becomes the shortest, the inductance of the wiring length is reduced, and the noise of the power supply system is reduced.

Further, in one embodiment, in the semiconductor integrated circuit device of the first invention, external electrodes are provided on the semiconductor integrated circuit chip, and each external electrode is
Electrically connected to the different conductor layers constituting the wiring layer via connection holes, the electronic component,
A semiconductor integrated circuit chip different from the above semiconductor integrated circuit chip.

According to this embodiment, since another semiconductor integrated circuit chip can be mounted directly on the above semiconductor integrated circuit chip, the existing semiconductor integrated circuit chip can be easily and three-dimensionally processed without processing. When mounted, many semiconductor integrated circuits can be mounted in a small area. Furthermore, the connection distance between the two semiconductor integrated circuit chips is shortened, and the electrical characteristics are improved.

In a second aspect of the present invention, a semiconductor integrated circuit chip is mounted on a wiring laminated substrate, the wiring laminated substrate and the semiconductor integrated circuit chip are electrically connected, and a plurality of external layers are formed on the wiring laminated substrate. A method of manufacturing a semiconductor integrated circuit device having a connection terminal, comprising: forming a first insulating film on a surface of a semiconductor integrated circuit chip mounted on the wiring laminated substrate; and insulating the first insulating film. Forming a multilayer wiring layer formed by stacking layers and electric wiring layers, forming a second insulating film on the multilayer wiring layer, and forming a connection hole in a part of the second insulating film. The step of exposing a part of the surface of the uppermost electric wiring layer in the multilayer wiring layer, and the step of forming a connecting member at a portion exposed from the connection hole in the uppermost electric wiring layer. And electrons on the second insulating film And a step of electrically connecting the electronic component and the connecting member with each other, and a step of sealing the semiconductor integrated circuit chip, the first insulating film, the multilayer wiring layer, the second insulating film and the electronic component. It is characterized by having.

According to the above structure, the multilayer wiring layer is formed on the surface of the semiconductor integrated circuit chip, the electronic component is mounted on the multilayer wiring layer, and the connection member provided on the uppermost layer of the multilayer wiring layer and the above The electrical parts are electrically connected. In this way, the electronic component is directly mounted on the semiconductor integrated circuit chip, so that ground bounce noise is reduced. Furthermore, it is not necessary to externally attach the electronic component, and the mounting area is reduced.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described in detail below with reference to the embodiments shown in the drawings.

<First Embodiment> FIG. 1 is a longitudinal sectional view showing the structure of a semiconductor integrated circuit device according to the present embodiment. 2 shows a manufacturing procedure of the semiconductor integrated circuit device shown in FIG. The present semiconductor integrated circuit device and the manufacturing method thereof will be described below with reference to FIGS.

The semiconductor integrated circuit device shown in FIG. 1 has a semiconductor integrated circuit chip 21 and an electronic component 2 such as a noise countermeasure component.
It is configured to be equipped with 2. The semiconductor integrated circuit chip 21 includes a plurality of MOSFETs formed on a semiconductor substrate.
It has a semiconductor element (not shown) such as (metal oxide semiconductor field effect transistor) and a first multilayer wiring layer (not shown) electrically connected to this semiconductor element. In the semiconductor integrated circuit chip 21, a power supply electric wiring layer and a ground electric wiring layer that form the first multilayer wiring layer are provided, and a protective film is formed on the uppermost layer of the first multilayer wiring layer.
(Not shown) is formed. Also, external electrodes (not shown) for various electric wiring layers are formed on the semiconductor integrated circuit chip 21.
Are formed.

A rewiring layer (second multilayer wiring layer) 23 having a power wiring layer 24 and a ground wiring layer 25 is formed on the semiconductor integrated circuit chip 21. The power supply wiring layer 2 is formed on the external electrode of the power supply electric wiring layer formed on the upper surface of the semiconductor integrated circuit chip 21.
4 are electrically connected by connection holes (not shown). Similarly, the ground wiring layer 25 is electrically connected to the external electrode of the ground electric wiring layer by a connection hole (not shown). Further, on the electrodes (not shown) of the power supply wiring layer 24 and the electrodes (not shown) of the ground wiring layer 25 provided on the rewiring layer 23, electronic components 22 such as a bypass capacitor and a filter are provided. Is mounted and electrically connected. The electrodes of the power supply wiring layer 24 and the power supply wiring layer 24 on the rewiring layer 23 are connected to each other through the connection hole 2
It is electrically connected by 6. Similarly, the electrode of the ground wiring layer 25 and the ground wiring layer 25 are electrically connected by the connection hole 27.

The external electrodes of the semiconductor integrated circuit chip 21 are arranged around the semiconductor integrated circuit chip 21 at a pitch of 100 μm to 200 μm. However,
The size and pitch of the electrodes for mounting the electronic component 22 are larger than the size and pitch of the external electrodes. Therefore, the size and pitch of the electrodes of the power supply wiring layer 24 and the electrodes of the ground wiring layer 25 on the rewiring layer 23 are expanded with respect to the size and pitch of the external electrodes.

By thus forming the redistribution layer 23 on the semiconductor integrated circuit chip 21, as shown in FIG. 1, electronic components 22 having different electrode sizes and pitches are mounted on the semiconductor integrated circuit chip 21. It is possible. Incidentally, 28 is a wiring laminated substrate, 29 is an external terminal, and the external terminal 29 and the semiconductor integrated circuit chip 2 are
1 is electrically connected. Further, 30 is a resin for molding.

A method of manufacturing the semiconductor integrated circuit device having the above structure will be described below according to the manufacturing procedure shown in FIG.

First, as shown in FIG. 2A, an inorganic insulating film 31 is formed on the main surface 21a of the semiconductor integrated circuit chip 21. The inorganic insulating film 31 is made of, for example, a silicon oxide film or a silicon nitride film. The external electrodes 32 on the semiconductor integrated circuit chip 21 are made of, for example, aluminum, aluminum-copper alloy, aluminum-silicon alloy, aluminum-copper-silicon alloy, or the like. Further, the first insulating layer 33 is formed on the semiconductor integrated circuit chip 21. Then, an opening is provided on the inorganic insulating film 31 and the external electrode 32 in the first insulating layer 33 to form a first connection hole 34. The external electrode 32 is formed by the first connection hole 34.
The upper surface of is exposed. The first insulating layer 33 is made of, for example, a polyimide resin and has a function of relieving thermal stress between the first insulating layer 33 and the electronic component 22 mounted on the semiconductor integrated circuit chip 21. The thickness of the first insulating layer 33 is, for example, about 5 μm.

Next, as shown in FIG. 2B, a metal film is formed on the entire surface of the first insulating layer 33 by a plating technique, and unnecessary regions are removed by a photolithography technique and a selective etching method. For example, the first wiring layer 35 as the ground wiring layer 25 is formed. Thus, the semiconductor element of the semiconductor integrated circuit chip 21 and the first wiring layer 35 are electrically connected to each other through the external electrode 32a and the first connection hole 34a. The first wiring layer 35
Is made of, for example, copper or a copper alloy.

Next, as shown in FIG. 2C, a second insulating layer 36 is laminated on the first wiring layer 35 to form a first wiring layer 35.
Cover. Like the first insulating layer 33, the second insulating layer 36 is also made of, for example, a polyimide resin. And the second
An opening 37 and a second connection hole 38 are formed in the insulating layer 36. In that case, the opening 37 is formed on the external electrode 32, and the second connection hole 38 is formed on the first wiring layer 35 other than the location of the external electrode 32. Therefore, the opening 37
Thus, the first wiring layer 35 on the external electrode 32 is exposed.

Next, as shown in FIG. 2D, a second wiring layer 39 as a power wiring layer 24 is formed on the entire surface of the second insulating layer 36 in the same manner as the first wiring layer 35. To form. Then, after filling the opening 37 and the second connection hole 38 with a conductive paste 40 such as silver, a base metal film (not shown) is formed inside the opening 37 and the second connection hole 38. This base metal film is formed by stacking chromium, nickel, copper and gold in order from the bottom layer, for example. As a result, the base metal films are electrically connected to the second wiring layer 39. Thus, the semiconductor element of the semiconductor integrated circuit chip 21 and the second wiring layer 39 are electrically connected to each other through the external electrode 32b, the first connection hole 34b and the second connection hole 38b.

Further, an inorganic insulating film 41 is formed on the entire surface of the second wiring layer 39, thereby covering the outer periphery of the opening where electrodes and bonding members will be formed later and the upper surface of the uppermost wiring layer. . The inorganic insulating film 41 is mainly used for the second wiring layer 3
9 is a film corresponding to a so-called surface protection film that protects 9 from moisture and the outside air, and is composed of, for example, a single film of a silicon oxide film or a laminated film of a silicon oxide film and a silicon nitride film,
Its thickness is, for example, about 1.6 μm. An opening 42 is provided in the inorganic insulating film 41 at a position between the opening 37 and the second connection hole 38, and the upper surface of the underlying metal film is exposed by the opening 42.

Next, a solder or the like as the bonding member 43 with the electronic component 22 is formed on the exposed base metal film by a vapor deposition method or a plating method. Then, the electronic component 22 is mounted by the mounting machine on the inorganic insulating film 41 on which the bonding member 43 is formed. After that, the joining member (solder) 43 is melted by using a reflow furnace or a heating device such as a laser to attach an electrode (not shown) of the electronic component 22 to the joining member 43.
Then, the electronic component 22 is fixed to the rewiring layer 23 including the first wiring layer 35 and the second wiring layer 39.

As a result, the electronic component 22 and the first wiring layer 35 are electrically connected to each other through the second connection hole 38b, the conductive paste 40b and the joining member 43b. Also,
The electronic component 22 and the second wiring layer 39 are formed of the conductive paste 4
0a and the joining member 43a are electrically connected.

In the above description, for convenience of explanation, the rewiring layer 23 and the electronic component 22 are formed on the individual semiconductor integrated circuit chips 21, but the semiconductor integrated circuit is actually formed. Rewiring layer 2 for the processed wafer
3 is formed and the electronic component 22 is mounted. And
By dicing the wafer, on which the rewiring layer 23 has been formed and the electronic components 22 have been mounted, into individual chip sizes, the state shown in FIG. 2D is obtained.

Thereafter, as shown in FIG. 1, the semiconductor integrated circuit chip 21 is die-bonded on the wiring laminated substrate 28 with Ag paste or the like. Then, the semiconductor integrated circuit chip 2
The electrode (not shown) formed on the upper surface of
Through the connection hole 44 of the above, it is connected to the electrode (not shown) on the wiring laminated substrate 28 by wire bonding using the wire 45. After that, the whole is molded with a resin 30 and packaged.

Here, the connection hole 44 to the redistribution layer 23 is formed.
Is formed at the location of the electrodes on the semiconductor integrated circuit chip 21 while forming the openings when the insulating layers 31, 33, 36 and 41 are sequentially formed, and when the wiring layers 35 and 39 are sequentially formed. Then, the insulating layer is patterned so as to be separated from the surroundings only in the vicinity of the inner wall surface of the opening of each insulating layer. Then, finally, the inside of the opening can be filled with the conductive paste 40. In addition, when the power supply to the semiconductor integrated circuit chip 21 and the electronic component 22 and the connection to the ground are performed from the power supply wiring layer 24 and the ground wiring layer 25 of the rewiring layer 23, the connection hole The formation may be performed upward from the power supply wiring layer 24 or the ground wiring layer 25.

Next, the packaged wiring laminated substrate 2
Solder balls are arranged on the back surface of 8 and the solder balls are melted to form the external terminals 29 to complete the semiconductor integrated circuit device. The semiconductor integrated circuit device thus formed is mounted on the mounting substrate via the external terminal 29.

As described above, in the semiconductor integrated circuit device according to this embodiment, the semiconductor integrated circuit chip 2 is used.
On the wiring layer 1 for power supply and wiring layer 25 for ground
The rewiring layer 23 is formed by sandwiching the wiring layers 35 and 39 containing the insulating layers 33, 36 and 41 with the inorganic insulating film 31 interposed therebetween. Then, the respective wiring layers are formed on the corresponding external electrodes 32 formed on the semiconductor integrated circuit chip 21,
They are connected by connection holes 34 and 38. Therefore, the wiring layers and the insulating layers are formed so that the size and the pitch of the openings 42 formed in the inorganic insulating film 41, which is the uppermost layer of the rewiring layer 23, match the size and the pitch of the electrodes of the electronic component 22 to be mounted. By adjusting the positions of the connection holes in the layer while maintaining the electrical connection, the electronic components 22 having different electrode sizes and pitches can be mounted on the semiconductor integrated circuit chip 21. Then, the electronic component 22 and the wiring layer of the rewiring layer 23 are electrically connected by the connection holes.

As a result, it is possible to reduce the ground bounce noise. Further, the opening 4 formed to mount the electronic component 22 such as the bypass capacitor.
2 can be widened, and the vapor deposition area of solder or the like and the printing area can be widened. Therefore, the electronic component 22 can be mounted easily and surely.

Further, as described above, the electronic component 2 is
When the electronic component 22 is used as a noise countermeasure component such as the bypass capacitor or the filter in order to mount 2 on the semiconductor integrated circuit chip 21, the noise countermeasure component 22 and the semiconductor integrated circuit chip 21 are electrically connected. The wiring length can be minimized. Therefore, the inductance of the wiring length can be reduced, and the noise of the power supply system in the present semiconductor integrated circuit device can be significantly reduced as compared with the conventional case. Further, it is not necessary to attach the electronic component 22 to the semiconductor integrated circuit chip 21 externally. Therefore,
The mounting area can be reduced.

By the way, in the above description, the second wiring layer 39 is used as the power supply wiring layer 24. However, in FIG. 2D, the second wiring layer 39 is separated between the joining member 43a and the joining member 43b by patterning, and the second wiring layer 39 on the joining member 43b side is located at the location of the opening 37. The first wiring layer 35 (ground wiring layer 25)
It is connected to the. That is, the second wiring layer 39 on the joining member 43a side functions as the power supply wiring layer 24, but the second wiring layer 39 on the joining member 43b side is the ground wiring layer 2
It is functioning as 5.

As described above, by changing the patterning shape of each wiring layer constituting the rewiring layer 23, the function of the same wiring layer is changed in the middle, or the depth of the wiring layer having the same function is changed. It can be changed.

<Second Embodiment> FIG. 3 is a longitudinal sectional view showing the structure of a semiconductor integrated circuit device according to the present embodiment. The semiconductor integrated circuit device shown in FIG. 3 is obtained by replacing a part of the electronic component 22 mounted on the semiconductor integrated circuit chip 21 shown in FIG. 1 with a second semiconductor integrated circuit chip.

In FIG. 3, the first semiconductor integrated circuit chip 51, the electronic component 52, the rewiring layer 53, the power supply wiring layer 54,
Ground wiring layer 55, wiring laminated substrate 56, external terminal 57
1 and the wire 58 shown in FIG.
The semiconductor integrated circuit chip 21, the electronic component 22, the rewiring layer 23, the power supply wiring layer 24, the ground wiring layer 25, the wiring laminated board 28, the external terminals 29 and the wires 45 shown in FIG. To do.

The method for mounting the second semiconductor integrated circuit chip 59 on the first semiconductor integrated circuit chip 51 is the same as the method for mounting the electronic component 52, and is the same as the procedure shown in FIG. . The semiconductor integrated circuit chip 59
As the joining member used when mounting the
A solder-based material can be used as in the case of. Further, a method of forming gold bumps on the electrodes of the semiconductor integrated circuit chip 59 and connecting and fixing them through an anisotropic conductive film or the like can be applied.

According to the present embodiment, since the second semiconductor integrated circuit chip 59 can be mounted directly above the first semiconductor integrated circuit chip 51, the stacked CSP can be mounted.
Like the (chip size package) and the three-dimensional LSI (large-scale integrated circuit), by mounting the semiconductor integrated circuit chips three-dimensionally, many semiconductor integrated circuits can be mounted in a small area. Further, according to the present embodiment, it is possible to mount an existing semiconductor integrated circuit chip on the insulating layer. Therefore, unlike the case of a three-dimensional LSI, a three-dimensional structure can be formed without requiring a complicated process of processing and stacking a semiconductor integrated circuit chip.

Further, the semiconductor integrated circuit chip 51,
The connection distance between the 59 can be shortened, and the electrical characteristics can be improved.

<Third Embodiment> FIG. 4 is a longitudinal sectional view showing a structure of a semiconductor integrated circuit device according to the present embodiment. In FIG. 4, the semiconductor integrated circuit chip 61, the electronic component 62, the rewiring layer 63, the power wiring layer 64, the ground wiring layer 65, the wiring laminated board 66, and the external terminal 67 are the same as those in the first embodiment. The semiconductor integrated circuit chip 21, the electronic component 22, the rewiring layer 23, the power wiring layer 24,
This is the same as the ground wiring layer 25, the wiring laminated substrate 28, and the external terminal 29, and detailed description thereof will be omitted.

In the semiconductor integrated circuit device shown in FIG. 1 in the first embodiment, the rewiring layer 23 is used when the electrode on the wiring laminated substrate 28 and the electrode on the semiconductor integrated circuit chip 21 are connected by the wire 45. A wire 45 is connected to an electrode (not shown) formed on the uppermost layer of the. Then, the electrode and the electrode on the semiconductor integrated circuit chip 21 are connected to the rewiring layer 2
The connection is made through a connection hole 44 provided in No. 3.

On the other hand, in the present embodiment,
As shown in FIG. 4, when connecting the electrode (not shown) on the wiring laminated substrate 66 and the electrode (not shown) on the semiconductor integrated circuit chip 61 with the wire 68, the rewiring layer 66 is optional. In this place (in the case of this embodiment, both ends of the rewiring layer 66), the electrode 69 formed on the semiconductor integrated circuit chip 61 is connected.

Such a wire connection structure is provided when the rewiring layer 63 is formed on the semiconductor integrated circuit chip 61.
It is covered with a resist film so that the rewiring layer 63 is not formed on the electrode to which the wire 68 is connected. Then, after the redistribution layer 63 is formed, the resist film is removed by etching, and the electrode 69 is formed on the electrode.

According to the present embodiment, by adopting the wire connection structure as described above, the height from the wiring laminated substrate 66 to the uppermost portion of the wire 68 can be adjusted in the case of the first and second embodiments. The height of the entire package can be reduced.

The present invention has been described with reference to the embodiments. However, the present invention is not limited to the above embodiments. For example, in each of the above-described embodiments, the rewiring layers 23, 53, 63 are connected to the power wiring layer 2
2 of 4,54,64 and wiring layers 25,55,65 for ground
Although the case where the rewiring layers 23, 53,
The 63 may be composed of two or more layers. Even in the case of two or more layers, the method of forming the wiring layer is the same as the method of forming the rewiring layer 23 in the first embodiment.

In each of the above embodiments, the case where electronic components 22, 52, 62 such as capacitors and filters and the semiconductor integrated circuit chip 59 are mounted on the semiconductor integrated circuit chips 21, 51, 61 are exemplified. Explained. However, the present invention is not limited to the electronic components such as the capacitors and filters and the semiconductor integrated circuit chips described above. Further, in each of the above-mentioned embodiments, the area array type package is described as an example, but it is also applicable to the internal structure of the leaded package represented by QFP (quad flat package) or SOP (small outline package). Needless to say.

[0057]

As is apparent from the above, the semiconductor integrated circuit device according to the first aspect of the present invention has a semiconductor integrated circuit chip mounted on a wiring laminated substrate, on the surface of which a single or a plurality of conductive layers are provided via an insulating film. A wiring layer is formed by sandwiching each of the body layers with an insulating layer, an electronic component is mounted on the wiring layer, and an electrode provided on the uppermost layer of the wiring layer is electrically connected to the electronic component. Therefore, the electronic component can be directly mounted on the semiconductor integrated circuit chip. Therefore,
Ground bounce noise can be reduced.

Furthermore, it is not necessary to attach the above electronic parts externally, and the mounting area can be reduced. Furthermore, by forming the lowermost insulating layer in the wiring layer with, for example, a polyimide resin, thermal stress between the semiconductor integrated circuit chip and the electronic component mounted can be relieved.

Further, by forming a conductor layer via an insulating film covering the semiconductor integrated circuit chip, mutual interference between a signal from another circuit including the electronic component and the semiconductor integrated circuit chip is prevented. be able to. Therefore, a highly reliable semiconductor integrated circuit device can be provided.

The semiconductor integrated circuit device of one embodiment is
Since the element surface of the semiconductor element built in the semiconductor integrated circuit chip is faced up, the external electrodes of the semiconductor element can be formed on the upper surface of the semiconductor integrated circuit chip. Therefore, it is possible to electrically connect the conductor layer of the wiring layer and the semiconductor integrated circuit chip with the shortest wiring length.

The semiconductor integrated circuit device of one embodiment is
External electrodes are provided on the semiconductor integrated circuit chip, and each of the external electrodes is electrically connected to the different conductor layers forming the wiring layer via connection holes, and the electronic parts are connected to a bypass capacitor and a filter. Since it is a noise countermeasure component including, the noise countermeasure component and the semiconductor integrated circuit chip mounted on the semiconductor integrated circuit chip,
It can be electrically connected through the wiring layer. Therefore,
It is possible to shorten the wiring length between the noise countermeasure component and the semiconductor integrated circuit chip to reduce the inductance of the wiring length and reduce the noise of the power supply system.

Further, the semiconductor integrated circuit device of one embodiment is
External electrodes are provided on the semiconductor integrated circuit chip, and each of the external electrodes is electrically connected to the different conductor layers forming the wiring layer through connection holes to connect the electronic component to the semiconductor integrated circuit. Since the semiconductor integrated circuit chip is different from the chip, another semiconductor integrated circuit chip can be mounted directly on the semiconductor integrated circuit chip. Therefore, it is possible to easily and three-dimensionally mount an existing semiconductor integrated circuit chip without processing it and mount many semiconductor integrated circuits in a small area. Further, it is possible to improve the electrical characteristics by shortening the connection distance between the semiconductor integrated circuit chips.

In the method for manufacturing a semiconductor integrated circuit device according to the second invention, an insulating layer and an electric wiring layer are formed on the surface of the semiconductor integrated circuit chip mounted on the wiring laminated substrate via the first insulating film. A multi-layered wiring layer formed by stacking layers, a connection hole is formed in a part of the second insulating film formed on the multi-layered wiring layer to expose the electric wiring layer, and an electron is formed on the second insulating film. Since the component is mounted and the connecting member formed at the exposed portion is electrically connected to the electronic component, the electronic component can be directly mounted on the semiconductor integrated circuit chip. Therefore, ground bounce noise can be reduced.

At this time, if the connection holes for electrically connecting the semiconductor integrated circuit chip and the electronic parts are formed in the multilayer wiring layer, the connection holes in each of the electric wiring layers of the multilayer wiring layer are electrically connected to each other. By adjusting the positional relationship while maintaining the physical connection, the fine pitch external electrodes provided on the semiconductor integrated circuit chip and the electrodes of the electronic component having a relatively large pitch can be electrically connected. It will be possible. Further, the position of the electronic component on the semiconductor integrated circuit chip can be arbitrarily moved. That is, according to the present invention, the element mounting area of the semiconductor integrated circuit chip can be effectively used. Further, the electric wiring length between the semiconductor integrated circuit chip and the electronic component can be minimized to reduce the inductance of the electric wiring length.

Furthermore, it is not necessary to externally attach the electronic parts, the mounting area can be reduced, and a small semiconductor integrated circuit device can be obtained. It Further, by forming the lowermost insulating layer in the multilayer wiring layer from, for example, a polyimide resin, it is possible to reduce thermal stress between the semiconductor integrated circuit chip and the electronic components to be mounted.

Further, by forming an electric wiring layer via an insulating film covering the semiconductor integrated circuit chip,
Mutual interference between a signal from another circuit including the electronic component and the semiconductor integrated circuit chip can be prevented. Therefore, a highly reliable semiconductor integrated circuit device can be manufactured.

[Brief description of drawings]

FIG. 1 is a vertical sectional view of a semiconductor integrated circuit device of the present invention.

FIG. 2 is a diagram showing a manufacturing procedure of the semiconductor integrated circuit device shown in FIG.

FIG. 3 is a vertical sectional view of a semiconductor integrated circuit device different from that of FIG.

FIG. 4 is a vertical cross-sectional view of a semiconductor integrated circuit device different from FIGS. 1 and 3.

FIG. 5 is a vertical sectional view of an electronic circuit device in which a conventional bypass capacitor is arranged.

FIG. 6 is a vertical sectional view of a package in which a conventional bypass capacitor is arranged.

[Explanation of symbols]

21, 51, 59, 61 ... Semiconductor integrated circuit chip, 22, 52, 62 ... Electronic components, 23, 53, 63 ... Rewiring layer, 24, 54, 64 ... power supply wiring layer, 25,55,65 ... Ground wiring layer, 26, 27, 34, 38, 44 ... Connection holes, 28, 56, 66 ... wiring laminated substrate, 29,57,67 ... External terminals, 30 ... Resin, 31, 41 ... Inorganic insulating film, 32 ... External electrode, 33, 36 ... Insulating layer, 35, 39 ... Wiring layer, 37,42 ... Opening, 43 ... Joining member, 45,58,68 ... Wire, 69 ... Electrode.

Claims (6)

[Claims] 1. A semiconductor integrated circuit chip is mounted on a wiring laminated substrate, the wiring laminated substrate and the semiconductor integrated circuit chip are electrically connected, the semiconductor integrated circuit chip is sealed, and the wiring laminated substrate is formed. In a semiconductor integrated circuit device provided with a plurality of external connection terminals, on the surface of the semiconductor integrated circuit chip, through an insulating film,
A wiring layer is formed by sandwiching each of the patterned one or more conductor layers with an insulating layer. An electronic component is mounted on the wiring layer, and the electronic component and the uppermost layer of the wiring layer are stacked. The semiconductor integrated circuit device is characterized in that it is electrically connected to an electrode provided in the semiconductor integrated circuit chip, and the wiring layer and the electronic component are sealed together with the semiconductor integrated circuit chip. 2. The semiconductor integrated circuit device according to claim 1, wherein there are a plurality of conductor layers that form the wiring layer, and the conductor layer is provided on the uppermost layer of the wiring layer and electrically connected to the electronic component. The semiconductor integrated circuit device, wherein each of the plurality of electrodes is electrically connected to the different conductor layers from each other through connection holes. 3. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit chip contains a semiconductor element, and the element surface of the semiconductor element is face-up. A characteristic semiconductor integrated circuit circuit device. 4. The semiconductor integrated circuit device according to claim 2 or 3, wherein external electrodes are provided on the semiconductor integrated circuit chip, and the external electrodes are different from each other forming the wiring layer. A semiconductor integrated circuit device, which is electrically connected to the conductor layer via a connection hole, and wherein the electronic component is a noise countermeasure component including a bypass capacitor and a filter. 5. The semiconductor integrated circuit device according to claim 2 or 3, wherein external electrodes are provided on the semiconductor integrated circuit chip, and the external electrodes are different from each other forming the wiring layer. A semiconductor integrated circuit device, which is electrically connected to the conductor layer via a connection hole, and wherein the electronic component is a semiconductor integrated circuit chip different from the semiconductor integrated circuit chip. 6. A semiconductor in which a semiconductor integrated circuit chip is mounted on a wiring laminated substrate, the wiring laminated substrate and the semiconductor integrated circuit chip are electrically connected, and the wiring laminated substrate is provided with a plurality of external connection terminals. A method of manufacturing an integrated circuit device, comprising: a step of forming a first insulating film on a surface of a semiconductor integrated circuit chip mounted on the wiring laminated substrate; and an insulating layer and an electric wiring layer on the first insulating film. A step of forming a multi-layered wiring layer formed by stacking a plurality of layers, a step of forming a second insulating film on the multi-layered wiring layer, and a step of forming a connection hole in a part of the second insulation film to form the multi-layered wiring. Exposing a part of the surface of the uppermost electric wiring layer in the layer; forming a connecting member at a portion exposed from the connection hole in the uppermost electric wiring layer; Electronic components mounted on insulating film And electrically connecting the electronic component and the connecting member, and sealing the semiconductor integrated circuit chip, the first insulating film, the multilayer wiring layer, the second insulating film and the electronic component. A method of manufacturing a semiconductor integrated circuit device having a feature.