JP3342828B2 - Resist coating and developing apparatus and resist coating and developing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resist coating and developing apparatus and a resist coating and developing method for forming a desired resist pattern on a surface of a substrate to be processed such as a semiconductor wafer or an LCD substrate.

[0002]

2. Description of the Related Art For example, in a photolithography process in a semiconductor device manufacturing process, a resist coating process for forming a resist film on the surface of a semiconductor wafer (hereinafter, referred to as a "wafer") and an exposure of the wafer after the resist coating are performed. After the processing, a development processing of performing a development processing on the wafer is performed.

Conventionally, the resist coating process and the developing process are performed in a complex processing system in which various corresponding processing units are provided in a single system, as is well known, for example, from Japanese Patent Publication No. 2-30194. It is performed according to a predetermined sequence with the process interposed.

In recent years, the demand for miniaturization of a resist pattern formed on a wafer surface has been increasing year by year, and strict control of various parameters such as an exposure amount and a development time which affect the line width of the resist pattern has become essential. ing.
In many cases, such parameter control for line width control involves measuring the line width of a resist pattern on the surface of a wafer carried out of a resist coating and developing system by an operator, and the line width satisfies a specified value range. If not, an operation is performed to request the host computer controlling the entire processing system to change the value of a predetermined parameter that affects the line width of the resist pattern.

[0005]

However, with the miniaturization of the resist pattern formed on the surface of the wafer,
There is a problem in that constant improvement in line width accuracy cannot be expected in artificial parameter management for line width control as described above. In many cases, the line width is controlled by correcting the exposure amount of the exposure apparatus. However, simply controlling the exposure amount in this manner still has a high tolerance to the tendency of the resist pattern to become finer. In some cases, accurate line width control cannot be realized. Further, since the conventional line width control of the resist pattern is performed by a feedback method, the wafer before the cycle in which the feedback control is reflected does not satisfy the line width condition, resulting in a loss. Such a loss of the wafer causes an increase in cost-related damage as the diameter of the wafer increases, and becomes a serious problem in the future.

An object of the present invention is to provide a resist coating / developing apparatus and a resist coating / developing method capable of controlling a line width of a resist pattern with high accuracy.

Another object of the present invention is to provide a resist coating / developing apparatus and a resist coating / developing method which do not cause loss of a substrate to be processed in controlling the line width of a resist pattern.

A further object of the present invention is to provide a resist coating and developing apparatus and a resist coating and developing method capable of realizing line width control of a resist pattern in-line to improve productivity.

[0009]

[0010]

[0011]

[0012]

[0013]

[0014]

[0015]

Resist coating and developing apparatus of the present invention, in order to solve the problems], as described in claim 1, the surface of the substrate on which the resist film is selectively exposed on its surface
Developing means for supplying a developing solution to the developing device to perform a developing process;
Before performing the development processing in the image means, the resist and the line width measuring means for measuring the line width of the exposed portion and / or the non-exposed portion of the film, the line width measurement result before Symbol line width measuring means of the target substrate And foreboding
After the development process , based on the appropriate line width set in
Parameters affecting the line width of the resulting resist pattern
Control means for correcting the value of the data before developing the substrate to be processed .

[0016]

[0017]

[0018]

[0019]

[0020]

[0021]

Further, the resist coating and developing apparatus of the present invention
As described in claim 2 , a developing solution is applied to the surface of the substrate to be processed on which the selectively exposed resist film is formed.
Developing means for supplying and developing, and developing by the developing means
Input means for inputting a line width measurement result of an exposed part and / or a non-exposed part of the resist film on the substrate to be processed, and a line width measurement result input by the input means
And development processing based on the preset line width appropriate value.
Influence parameters on line width of resist pattern obtained later
Control means for correcting the value of the meter before the substrate to be processed is subjected to the development processing .

Furthermore, the resist coating and developing apparatus of the present invention, as described in claim 3, claim 1 or 2, wherein
In the resist coating and developing apparatus, the value of the parameter
Is at least the temperature of the developer supplied to the substrate to be processed.
Alternatively, any one of the development processing times in the developing unit is
It is characterized by including .

Further, the resist coating and developing apparatus of the present invention
As described in claim 4 , the laser according to claim 1 or 2
In the mist coating and developing apparatus, after the exposure,
Heating the substrate before performing the developing process in the step
Heating means, wherein the value of the parameter is at least
Either heating temperature or heating time of the heating means
It is characterized by including .

Furthermore, the resist coating and developing apparatus of the present invention, as described in claim 5, claims 1 to 4 Izu
In the resist coating and developing apparatus according to any one of the above,
While rotating the substrate, apply a resist solution to the surface of the substrate to be processed.
A resist coating unit for coating, wherein the control unit is
In addition to correcting the value of the parameter,
Compensate for parameter values that affect the resist coating thickness of the step.
It is characterized in that positive.

Further, the resist coating and developing apparatus of the present invention
As described in claim 6, any of claims 1 to 5
2. The resist coating and developing apparatus according to claim 1, wherein
The control means corrects the value of the parameter and
Compensation of parameter values that affect the exposure processing of the
It is characterized in that positive.

Further, the resist coating and developing apparatus of the present invention
As described in claim 7 , a plurality of substrates to be processed are accommodated.
The cassette is loaded and unloaded to and from the outside,
A cassette for taking the substrate to be taken in and out of the cassette;
And a predetermined processing for the substrate to be processed.
Multiple single-wafer processing units for processing
Processing station and external exposure equipment
Interface for transferring the substrate to be processed between
And a resist coating and developing apparatus comprising
At least one of the processing units is a substrate to be processed.
Developing unit that supplies a developing solution to the surface of the
And the interface unit is a processing unit.
Between the exposure unit and the exposure apparatus,
The resist film selectively exposed by the exposure device
An exposed portion of the resist film of the formed substrate to be processed;
And / or line width measuring means for measuring the line width of the unexposed portion
A line width measuring unit, wherein the line width measuring means
Based on the fixed result and the preset appropriate value of the line width,
Resist obtained after development processing in the development processing unit
It is characterized by comprising control means for correcting the value of a parameter that affects the line width of the pattern .

Furthermore, the resist coating and developing apparatus of the present invention, as described in claim 8, a substrate to be processed more revenue
Along with loading and unloading the loaded cassette to and from the outside,
A cassette for taking the substrate in and out of the cassette.
Predetermined for the set station section and the substrate to be processed
Multi-stage processing units with vertical and horizontal processing
Arranged processing station and external exposure
An interface for transferring the substrate to and from the apparatus.
And a resist coating and developing device.
The processing station unit is configured to transfer the substrate to be processed to the
Transport means for loading and unloading to and from each processing unit;
The conveyance path of the conveyance means and the conveyance path are separated.
Front processing unit group and rear processing unit group
And the front-side processing unit group includes a substrate to be processed.
A development processing unit that supplies developer to the surface and performs development
And the back side processing unit group includes the substrate to be processed.
A heat treatment unit for heating, and the heat treatment unit
A cooling unit for cooling the substrate to be heated,
And a resist film selectively exposed by the exposure apparatus
Is formed on the surface of the resist film on the substrate to be processed.
A line width measuring unit for measuring a line width of an exposed portion and / or a non-exposed portion.
And a line width measurement result of the line width measurement unit
Based on the predetermined line width and a predetermined value of the line width.
Resist pattern obtained after development processing in the processing unit
Control means for correcting the value of a parameter that affects the line width of the pattern.

Further, the resist coating and developing apparatus of the present invention
As described in claim 9, the cash register according to claim 8
In the strike coating and developing apparatus, the line width measuring unit is:
That it is provided adjacent to the cooling processing unit.
It is a feature .

Also, the resist coating and developing apparatus of the present invention
As described in claim 10 , a plurality of substrates to be processed are accommodated.
The loaded cassette is loaded and unloaded from the outside, and
A cassette for taking the substrate to be loaded into and out of the cassette.
And a predetermined station with respect to the substrate to be processed.
Multiple single-wafer processing units for processing are arranged in multiple rows and columns.
Processing station, and an external exposure device
Interface for transferring the substrate to and from the device
A resist coating and developing apparatus comprising:
The processing station unit processes the substrate to be processed in each of the processing stations.
Transport means for loading and unloading to and from the processing unit;
The transport path of the feeding means and the front face divided across the transport path
Side processing unit group and back side processing unit group
The front-side processing unit group includes a front surface of the substrate to be processed.
It has a development processing unit that supplies developer to the surface to perform development.
The back side processing unit group is exposed by the exposure apparatus.
The developed substrate is developed by the development processing unit.
Heat treatment means for performing a heat treatment before performing the treatment;
A resist film selectively exposed by an optical device is formed on the surface.
Exposed portions of the resist film of the substrate to be processed and / or
Has a line width measuring means for measuring the line width of the non-exposed area.
A heat treatment unit, and the heating unit
A cooling processing unit for cooling a substrate to be processed,
The result of the line width measurement by the line width measuring means and the appropriateness of the preset line width
Developing processing in the developing processing unit based on the positive value
Patterns that affect the line width of the resist pattern obtained later
It is characterized by comprising control means for correcting the value of the parameter .

Furthermore, the resist coating and developing apparatus of the present invention, as described in claim 11, a plurality of substrate to be processed
When loading and unloading the stored cassettes from / to the outside,
Next, the substrate to be processed is taken in and out of the cassette.
Cassette station section and the substrate to be processed
A plurality of single-wafer processing units that perform predetermined processing
A processing station section that is configured by arranging
An interface for transferring the substrate to be processed with an exposure apparatus.
-A resist coating and developing device composed of a
Thus, the processing station unit is configured to move the substrate to be processed in front.
Transport means for loading and unloading to and from each processing unit;
The conveyance path of the conveyance means and the conveyance path are separated.
Front side processing unit group and back side processing unit group
Wherein the front-side processing unit group includes the substrate to be processed.
Development processing unit that performs development by supplying a developer to the surface of the
And the back-side processing unit group includes:
The exposed substrate is processed by the developing unit.
A heating unit having a heating means for performing a heat treatment before the development treatment is performed.
A heat treatment unit, and the heating unit
The development processing unit performs development processing on the substrate to be processed.
Cooling means for cooling before performing, selected by the exposure apparatus
Wherein the resist film which has been exposed to light is formed on the surface,
Exposed and / or non-exposed portions of the resist film on the substrate
A cooling unit having a line width measuring means for measuring a line width.
A line width measurement result of the line width measurement means and a preset value.
Based on the determined line width appropriate value, the development processing unit
Line width of resist pattern obtained after development process with a mask
And control means for correcting the value of the parameter affecting the parameter .

[0032]

[0033]

[0034]

[0035]

[0036]

[0037]

[0038]

[0039]

The resist coating and developing method of the present invention comprises:
As described in claim 12 , selectively exposed lasers.
Perform development processing on the substrate to be processed on which the
Before the measurement, the line width of the exposed portion and / or the non-exposed portion of the resist film of the substrate to be processed is measured, and the line width measurement result and
Based on the set line width appropriate value, the pattern width affecting the line width of the resist pattern obtained after the development processing is determined.
Before applying the developing process to the substrate to be processed.
And correcting the.

[0041] Further, the resist coating and developing method of the present invention, as described in claim 13, of claim 12, wherein
In the resist coating and developing method, the value of the parameter
Is at least on the substrate to be processed in the developing process.
Either the temperature of the supplied developer or the development processing time
It is characterized by including one .

[0042] Further, the resist coating and developing method of the present invention, as described in claim 14, of claim 12, wherein
In the resist coating and developing method, after measuring the line width,
Before performing the developing process, a heating process of the substrate to be processed is performed.
And the value of the parameter is at least
The heating temperature or the heating time.
No it and it said.

Further, the resist coating and developing method of the present invention comprises:
As described in claim 15 , claims 12 to 14
In the resist coating and developing method according to any one of the claims,
In addition to correcting the parameter values, the coating of the resist film
Parameters affecting resist coating thickness in cloth processing
Data values are corrected.

The resist coating and developing method of the present invention comprises:
Claims 12 to 15 as described in claim 16
In the resist coating and developing method according to any one of the claims,
In addition to correcting the parameter values, the exposure of the resist film
It is characterized in that the value of a parameter affecting the light processing is corrected .

[0045]

According to the present invention, the line width of the exposed portion and / or the non-exposed portion of the resist film on the substrate to be processed, that is, the line width of the latent image pattern is measured, and based on the line width measurement result,
Developer temperature affecting the line width of the resist pattern after development, the development time, the heating temperature of the substrate before development, by correcting between during the heating of the substrate before development, performing line width measurement The line width of the resist pattern formed on the surface of the substrate to be processed itself can be optimized, the loss of the substrate to be processed due to parameter correction for line width control does not occur, and in-line , The line width of the resist pattern can be controlled with high accuracy, and the productivity can be improved.

[0047]

[0048]

[0049]

[0050]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIGS. 1 to 3 show the overall configuration of a semiconductor wafer (hereinafter, referred to as “wafer”) coating and developing system 1 to which the embodiment of the present invention is applied.
2 shows a plane, FIG. 2 shows a front, and FIG. 3 shows a back.

As shown in these figures, the coating and developing processing system 1 of this embodiment carries a wafer cassette CR accommodating a plurality of wafers W into and out of the wafer cassette CR, and transfers wafers to and from the wafer cassette CR. A cassette station 10 for loading and unloading W, and a processing station 11 configured by arranging a plurality of single-wafer-type processing units for performing predetermined processing on wafers W one by one in a vertically and horizontally multistage manner.
And an interface unit 12 for transferring a wafer W to and from an external exposure apparatus (not shown).

In the cassette station 10, as shown in FIG. 1, a plurality of wafer cassettes C, for example, up to four wafer cassettes C are provided at each cassette positioning portion 20a on the cassette mounting table 20.
R are placed in a line in the X direction (vertical direction in FIG. 1) with their respective wafer entrances facing the processing station 11, and the wafer cassettes CR are moved in the X and Z directions (the wafers in the wafer cassette CR). The wafer carrier 21 movably provided in the arrangement direction (vertical direction) performs the operation of taking in and out the wafer W. Further, the wafer carrier 21 is configured to be rotatable in the θ direction, and can transfer the wafer W to the wafer carrier 22 on the processing station 11 side.

The wafer carrier 2 in the processing station 11
Numeral 2 is configured to be movable in the Y direction between the cassette station 10 and the interface unit 12, and to be able to move up and down in the Z direction (vertical direction) and to be rotatable in the θ direction.

Each of the processing units in the processing station 11 is divided into two parts with the transfer path of the wafer transfer body 22 interposed therebetween. Here, when a set of processing units for one row in the upper and lower rows is referred to as one processing unit group, each processing unit in the processing station 11 includes, for example, eight processing unit groups G ₁ , G ₂ , G ₃ , G ₄ , G _5. , G ₆ , G ₇ , G ₈ , of which the second, fourth, sixth, and eighth processing unit groups G ₂ , G ₄ , G ₆ , G ₈ are, for example, as shown in FIG. The first, third, fifth, and seventh processing unit groups G ₁ , G ₃ , G ₅ , and G ₇ are arranged on the front side of the system, and are arranged, for example, on the back side of the system as shown in FIG. I have.

As shown in FIG. 2, the second, fourth, sixth and eighth processing unit groups G ₂ , G ₄ , G ₆ and G ₈ are respectively
A resist coating unit (COT) stacked in two stages
And a developing unit (DEV).

As shown in FIG. 3, the first processing unit group G ₁ includes a cooling unit (COL) for cooling the wafer W, an alignment unit (ALIM) for aligning the wafer W, and an exposure process. A pre-baking unit (PRE) for performing a heating process on the previous wafer W
BAKE) and a post-baking unit (POBAKE) for performing a heating process on the wafer W after the exposure process.
They are arranged in order from the bottom.

Further, the third processing unit G ₃ includes a cooling unit (COL) for performing a cooling process on the wafer W,
An adhesion unit (A) for performing a hydrophobic treatment for improving the fixability of the resist solution applied to the surface of the wafer W
D), a pre-baking unit (PREBAKE) for performing a heating process on the wafer W before the exposure process and a post-baking unit (POBAKE) for performing a heating process on the wafer W after the exposure process are provided in order from the bottom. Have been.

Fifth and seventh processing units G ₅ , G
Reference numeral ₇ denotes a cooling unit (COL) for performing a cooling process on the wafer W, an extension cooling unit (EXTCOL), and a prebaking unit (PREBAKE) for performing a heating process on the wafer W before the exposure process.
Further, post-baking units (POBAKE) for performing a heating process on the wafer W after the exposure process are arranged in order from the bottom.

As described above, the cooling unit (COL) and the extension cooling unit (EXTCOL) each having a low processing temperature are arranged in the lower stage, and the prebaking unit (PREBAKE), the postbaking unit (POBAKE) and the adhesive unit each having a high processing temperature. By arranging the John units (AD) in the upper stage, thermal mutual interference between the units can be reduced.

The interface section 12 includes a portable pickup cassette CR, a stationary buffer cassette B
R, the peripheral exposure device 23, the wafer carrier 24, and the latent image pattern formed by the exposed portion and the non-exposed portion on the surface of the exposed wafer W, and the line width of the latent image pattern (line of the exposed portion) A latent image line width measuring device 25 for measuring the width and / or the line width of the non-exposed portion) is provided. The wafer carrier 24 moves in the X direction and the Z direction to perform an operation of transferring the wafer W to the cassettes CR and BR and the peripheral exposure device 23. The wafer transfer body 24 is also rotatable in the θ direction, and transfers the wafer W between the wafer transfer body 22 on the processing station 11 side and a wafer transfer table (not shown) on the external exposure apparatus side. Is configured to do so.

As shown in FIG. 4, the developing unit (DEV) rotates while holding the wafer W horizontally by vacuum suction in a processing container 27 defined by the atmosphere of the transfer section 26 for the wafer W. The configured spin chuck 28
And a cup 29 surrounding the outer and lower sides of the spin chuck 28 and having a drain port 28a and an exhaust port 28b at the bottom, and a developer supply device 31 connected to a developer tank (not shown). A developing solution supply nozzle 30 for discharging the developing solution onto the surface of the wafer W held on the spin chuck 28;

An opening 27a for loading / unloading the wafer W is provided on one side surface of the processing container 27. The opening 27a is opened and closed by a shutter 27b driven by driving means such as a cylinder (not shown). It is configured. A motor 33 for rotating and driving the spin chuck 28 is provided below the processing container 27, and an elevating means (not shown) for raising and lowering the spin chuck 28 is provided.

On the other hand, an air inlet 27c is provided in the ceiling of the processing container 27, and a filter 32 is disposed in the air inlet 27c so that air purified by the filter 32 is supplied. Is configured.

The developing solution supply device 31 adjusts (corrects) the temperature of the developing solution supplied to the developing solution supply nozzle 30 in accordance with a control command given from a central processing unit (CPU) 45 (not shown). It has a temperature controller.

Further, a post baking unit (POB)
AKE) is, as shown in FIG. 4, a disk-shaped wafer B placed and baked in a container 51 having a wafer W loading / unloading port 51a and a shutter 51b for opening and closing the loading / unloading port 51a. Is provided. A heating resistor 53 is built in the heating plate 52, and the current supplied to the heating resistor 53 is adjusted by a baking temperature controller (not shown) under the control of a central processing unit (CPU) 45. It has become.

The latent image line width measuring device 25 in the interface section 12 is electrically connected to a central processing unit (CPU) 45. The central processing unit (CPU) 45
In accordance with a built-in control program, the line width measurement value of the latent image pattern input from the latent image line width measurement device 25 is compared with a preset line width appropriate value, and the line width measurement value falls within the appropriate value range. When the deviation is detected, control is performed to correct the value of a parameter that affects the line width of the resist pattern in a process after exposure so as to optimize the line width of the resist pattern after development.

In the present embodiment, focusing on the post-baking temperature and / or the developing solution temperature as parameters affecting the line width of the developed resist pattern, the difference between the measured line width of the latent image pattern and the appropriate value is considered. An optimum post-baking temperature and / or developer temperature correction value according to the difference is obtained, and a control command for parameter correction is given to the baking temperature controller and / or the developer temperature controller.

Next, the flow of processing by the coating and developing system will be described with reference to FIG.

First, in the cassette station 10,
The wafer carrier 21 accesses the cassette CR containing the unprocessed wafers W on the cassette mounting table 20, and takes out one wafer W from the cassette CR (step 51). Thereafter, the wafer carrier 21 transfers the wafer W to the wafer carrier 22 on the processing station 11 side. Wafer transfer member 22 is moved to the first processing unit group G ₁ of the alignment unit (ALIM), to transfer the wafer W into the alignment unit (ALIM).

When the orientation alignment and centering of the wafer W are completed in the alignment unit (ALIM), the wafer carrier 22 receives the aligned wafer W, and the adhesion unit (3) of the third processing unit group G ₃ is received. AD), the wafer W is carried in, and a hydrophobic treatment is performed (step 52).

The wafer W that has been subjected to the hydrophobizing process is then carried into a predetermined pre-baking unit (PREBAKE) by the wafer carrier 22 and baked (step 53), and then is cooled to a predetermined cooling unit (CO).
L). This cooling unit (COL)
The wafer W is set at a set temperature before the resist coating process, for example, 2
Cool to 3 ° C. (step 54).

When the cooling process is completed, the wafer W is transferred by the wafer transfer body 22 to a predetermined resist coating unit (CO).
T) and the resist coating unit (COT)
Then, a resist is applied to the surface of the wafer W (step 55).

When the resist coating process is completed, the wafer carrier 22 transfers the wafer W to a resist coating unit (COT).
From the pre-baking unit (PRE)
BAKE). Here, the wafer W is heated at a predetermined temperature, for example, 100 ° C. for a predetermined time (step 56), whereby the residual solvent is evaporated and removed from the coating film on the wafer W.

Thereafter, the wafer W is transferred to the extension / cooling unit (@TC
OL). Here, the wafer W is cooled to a temperature suitable for the next step, ie, the peripheral exposure processing by the peripheral exposure device 23, for example, 24 ° C. (Step 57).

After that, the wafer carrier 22 transfers the wafer W to the wafer carrier 24 of the interface unit 12.
The wafer carrier 24 carries the wafer W into the peripheral exposure device 23 in the interface unit 12. Here, the wafer W undergoes an exposure process on its peripheral portion (not shown).

When the peripheral exposure processing is completed, the wafer carrier 24 unloads the wafer W from the peripheral exposure device 23 and transfers it to a wafer receiving table (not shown) on the adjacent exposure device side (step 58). In this case, the wafer W may be temporarily stored in the buffer cassette BR as needed before being transferred to the exposure apparatus.

When the entire surface pattern exposure processing in the exposure apparatus is completed and the wafer W is returned to the wafer receiving table on the exposure apparatus side, the wafer carrier 24 of the interface section 12 accesses the wafer receiving table to perform the exposure processing. Later wafer W
Is received (step 59), and the wafer W is loaded into the latent image line width measuring device 25 provided in the interface section 12.

In the latent image line width measuring device 25, the wafer W
After the latent image pattern composed of the exposed portion and the non-exposed portion on the surface is optically recognized, the line width of the latent image pattern (the line width of the exposed portion and / or the line width of the non-exposed portion) is measured. (Step 60) The line width measurement result of the latent image pattern is sent to the central processing unit (CPU) 45.

The central processing unit (CPU) 45 shown in FIG.
As shown in (5), when the line width measurement value of the latent image pattern sent from the latent image line width measuring device 25 is input (step 60).
1) The line width measurement value is compared with a preset line width appropriate value to determine whether or not the line width measurement value is within the range of the appropriate value (step 602). If not,
In order to optimize the line width of the resist pattern after development, optimum correction values for the post-baking temperature and the developer temperature according to the difference between the measured line width and the appropriate value are obtained (step 60).
3).

That is, the CPU 45 gives a command for each parameter correction value to the baking temperature controller and the developing solution temperature controller, respectively, and the PEB processing step (step 604) and the developing processing step (step 605).
Are respectively feed-fed controlled. CPU4
5 gives a command corresponding to each parameter correction value to the spin chuck 61 and the resist solution temperature adjusting device 63 of the resist coating unit (COT) and the shutter drive unit and the focus drive unit of the exposure device, respectively. Step 606) and the exposure processing step (Step 60)
7) is feedback-controlled.

On the other hand, if it is determined in step 602 that the measured line width is within the appropriate range, no command is issued from the CPU 45 and the processing is continued without changing each processing condition.

Thereafter, the wafer W is carried out of the latent image line width measuring device 25 by the wafer carrier 24 and transferred to the wafer carrier 22 on the processing station 11 side. In this case, the wafer W may be temporarily stored in the buffer cassette BR in the interface unit 12 as necessary before being transferred to the processing station 11 side.

The wafer carrier 22 receives the received wafer W
Into a predetermined post-baking unit (POBAKE). This post baking unit (POBAK
In E), the wafer W is placed on the hot plate 52 and baked for a predetermined time (step 61). Here, the post-baking temperature is determined by a central processing unit (CPU) 45.
Is controlled by a baking temperature controller (not shown) to an optimum temperature corresponding to the difference between the measured value of the line width of the latent image pattern and the appropriate value.

Thereafter, the baked wafer W is carried into one of the cooling units (COL) by the wafer carrier 22, and the cooling unit (CO)
Within L), the wafer W is returned to normal temperature (step 62).
Subsequently, the wafer W is carried into a predetermined developing unit (DEV) by the wafer carrier 22.

In the developing unit (DEV), the wafer W is placed on the spin chuck 28, and the developing solution (T) is applied to the resist on the surface of the wafer W by, for example, a spray method.
(MAH solution) is uniformly applied to perform development (step 63). In this development process, the temperature of the developer was controlled by a central temperature processor (CPU) 45 according to the difference between the line width measurement value of the latent image pattern and the appropriate value by a developer temperature controller (not shown). Adjusted to the optimal temperature.

After the development, a rinsing liquid is applied to the wafer surface, and the developing liquid is washed off. Thereafter, the wafer carrier 22 unloads the wafer W from the developing unit (DEV), and then moves the wafer W to a predetermined post-baking unit (PO).
BAK #), the wafer W is loaded again. In this post-baking unit (POBAKE), the wafer W is heated at, for example, 100 ° C. for a predetermined time (step 6).
4) Thereby, the resist swollen by the development is hardened, and the chemical resistance is improved.

When the post-baking is completed, the wafer carrier 22 transfers the wafer W to the post-baking unit (PO).
BAKE), and then the wafer W is loaded into a predetermined cooling unit (COL) to perform a cooling process (step 65). Here, after the wafer W returns to normal temperature,
The wafer carrier 22 transfers the wafer W to the wafer carrier 21 on the cassette station 10 side. Then, the wafer carrier 21 transfers the received wafer W to the cassette mounting table 20.
The wafer is inserted into a predetermined wafer accommodating groove of the cassette CR for accommodating the processed wafer (step 66).

As described above, in the present embodiment, after exposure, the line width of the latent image pattern formed on the surface of the wafer W is measured by the latent image line width measuring device 25, and the measured line width is set in advance. If the value is out of the appropriate range, parameters that affect the line width of the developed resist pattern in the post-exposure process to optimize the line width of the developed resist pattern, for example, the post-baking temperature and the development. By correcting the liquid temperature, it is possible to control the line width of the resist pattern in-line, thereby improving the productivity. In addition, a feed-forward method can be applied to the wafer W itself in which the line width of the latent image pattern is measured. And the line width of the resist pattern can be controlled, and the loss of the wafer W due to the execution of the line width control of the resist pattern does not occur. That.

The present invention is not limited to the embodiment described above, and various modifications can be made within the scope of the technical concept.

For example, in the above embodiment, the values of the parameters of the post-baking temperature and the developer temperature before the development are corrected at the same time. However, any one of the post-baking temperature and the developer temperature is corrected. The value of the parameter may be corrected. Further, in the post-exposure process, the parameters affecting the line width of the resist pattern obtained after the development include, in addition to the post-baking temperature and the developer temperature before the development, the wafer W is heated before the development. The post-baking time, which is the heating time, the developing time, the concentration of the developing solution, and further, the baking temperature is raised to a predetermined temperature after loading the wafer W into the post-baking unit (POBAKE) (for example, 1
(A preheating temperature of 00 ° C. to 150 ° C.).

FIG. 7 shows the PEB temperature (° C.) on the horizontal axis.
FIG. 7 is a characteristic diagram showing the result of examining the correlation between the two, with the average line width (μm) of the pattern taken on the vertical axis. The applied resist is TDUR-P007 with a suitable amount of PGME as a solvent.
A was added. Here, "TDUR-P00
"7" refers to a product resist of Tokyo Ohka Kogyo Co., Ltd. made of acetal protecting group resin. "PGMEA" refers to propylene glycol monomethyl ether acetate. The processing time at each PEB temperature was 90 seconds. The target value of the line width was 0.25 μm.

As is apparent from FIG. 7, the line width of the pattern tends to decrease as the PEB temperature increases.
When the EB temperature was in the range of 95 to 115 ° C., the line width of the pattern was close to the target value and stabilized.

FIG. 8 shows the PEB time (sec) on the horizontal axis.
FIG. 7 is a characteristic diagram showing the result of examining the correlation between the two, with the average line width (μm) of the pattern taken on the vertical axis. The coating resist has the same composition as described above. The processing temperature at each PEB time was 110 ° C. The target value of the line width was 0.25 μm.

As is apparent from FIG. 8, the pattern line width tends to decrease as the PEB time becomes longer.
B time 70 seconds, 90 seconds, 110 seconds, 130 seconds, 150
In seconds, the pattern line width is 0.255 μm, 0.250
μm (target value), 0.245 μm, 0.240 μm,
0.235 μm was obtained in each case.

FIG. 9 is a characteristic diagram showing the result of examining the correlation between the relative humidity (%) of the PEB treatment atmosphere on the horizontal axis and the average line width (μm) of the pattern on the vertical axis. is there. The coating resist has the same composition as described above. Each PE
The B treatment was performed at a temperature of 110 ° C. for 90 seconds. The target value of the line width was 0.25 μm.

As is clear from FIG. 9, the pattern line width tends to gradually decrease as the relative humidity of the PEB processing atmosphere increases, and the relative humidity is 36.6%, 40%, and 45%.
% And 50%, the pattern line width is 0.255 μm,
0.2525 μm, 0.250 μm (target value), 0.2
425 μm were each obtained.

FIG. 10 shows the development time (second) on the horizontal axis.
FIG. 7 is a characteristic diagram showing the result of examining the correlation between the two, with the average line width (μm) of the pattern taken on the vertical axis. Each PEB
The treatment was performed at 110 ° C. for 90 seconds. The target value of the line width was 0.25 μm. The development was performed at room temperature using a tetramethylammonium hydroxide (TMAH) solution.

As is apparent from FIG. 10, the pattern line width tends to gradually decrease as the developing time becomes longer.
When the development time is 40 seconds, 50 seconds, 60 seconds, and 70 seconds, the pattern line width is 0.264 μm, 0.259 μm, 0.2
50 pm (target value) and 0.244 μm were obtained.

Various timings can be selected when measuring the line width of the pattern or the pattern latent image. Therefore, the latent image line width measuring device 25 is provided in the coating and developing processing system 1.
It can be provided at various places inside. For example, FIG.
As shown in FIG. 1, a latent image line width measuring device was provided (LILW
M) The unit 25a may be provided in the processing unit group of the process unit 11. As shown in FIG. 5, the wafer W can be carried into the (LILWM) unit 25a, and the line width of the pattern latent image can be measured before the PEB process. Note that such a (LILWM) unit 25a is preferably provided at a position that is least likely to be thermally affected by the prebaking (PREBAKE) unit and the POS and baking (POBAKE) unit. For example, (LI) next to the cooling (COL) unit
It is optimal to provide an LWM) unit 25a.

Also, post baking (POBAKE)
The latent image line width measuring device 25 may be built in the unit. Such post-paking (POBAK)
In the unit E), as shown in FIG. 12, the resist can be subjected to the PEB process and the line width of the pattern latent image can be simultaneously measured, so that the throughput can be improved.

Also, a latent image line width measuring device 25 is provided in a predetermined cooling unit (COL) into which the post-baked wafer W is carried in, for example, at the same time as the cooling process of the wafer W or immediately before and after the cooling. You may comprise so that width measurement may be performed. In this case, as shown in FIG. 13, in order to realize the line width control of the feedforward method based on the line width measurement result of the latent image pattern, the parameters (developer temperature, development time, developer concentration) in the development process are adjusted. It is desirable that only the value is to be corrected in that no loss of the wafer W occurs. In some cases, a configuration may be adopted in which parameters of the post-baking step are also corrected at the same time.

In the above embodiment, the line width control of the feedforward system is realized. As shown in FIG. 14, the line width of the developed resist pattern is measured by a line width measuring device (LWM) 25b (LWM). Based on the difference between the measured line width and the appropriate value, resist coating conditions (spin chuck rotation speed, resist solution concentration, resist solution supply amount, etc.) and exposure conditions (exposure time , Exposure focal length, etc.), baking temperature, baking time, developing temperature, and developing time. By such parameter feedback control, highly accurate line width control of the resist pattern can be realized in-line in the system, and the yield can be reliably improved.

In the above embodiment, the case where the line width measuring device is provided in the system has been described. However, the latent image line width measuring device may be provided in the exposure device. In such a system, as shown in FIG. 15, the line width of the latent image pattern formed on the wafer surface after exposure is measured by a latent image line width measuring device in the exposure device, and the coating and developing system is used to measure the line width. The width measurement result is input from the exposure apparatus, and parameters such as the baking temperature, the baking time, the developing temperature, and the developing time are corrected based on the input data. By the way, parameters affecting the line width of the resist pattern in the post-exposure process, particularly parameters in the development process (developer temperature, development time, developer concentration, etc.)
Correction affects not only the line width of the resist pattern but also the thickness of the resist film. Therefore, as shown in FIG. 16, when the values of the parameters in the developing process are corrected, it is useful to make appropriate corrections to the parameters that affect the thickness of the resist film in the process before the exposure at the same time. Becomes

Hereinafter, an embodiment of a coating and developing system in which the difference between the line width measurement result of the latent image pattern and the appropriate value is reflected in parameter correction in the resist coating process will be described.

As shown in FIG. 17, the resist coating unit (CO
T) is a spin chuck 58 configured to rotate while holding the wafer W horizontally by vacuum suction in a processing container 57 partitioned from the atmosphere of the transfer section 26 of the wafer W.
A cup 59 surrounding the outer and lower sides of the spin chuck 58 and having an exhaust port 58a and a drain port 58b at the bottom, and a resist for discharging a resist solution onto the surface of the wafer W held on the spin chuck 58 Supply nozzle 6
0.

An opening 57a for loading / unloading the wafer W is provided on one side surface of the processing container 57. The opening 57a is opened and closed by a shutter 57b driven by driving means such as a cylinder (not shown). It is configured. In addition, a motor 61 for rotating and driving the spin chuck 58 is provided below the processing container 57, and an elevating means (not shown) for raising and lowering the spin chuck 58 is provided. The motor 61 is constituted by a servomotor, and is capable of controlling the rotation speed of the spin chuck 58 with high accuracy under the control of the central processing unit (CPU) 45.

On the other hand, an air inlet 57c is provided in the ceiling of the processing vessel 57, and a filter 62 is disposed in the air inlet 57c so that air purified by the filter 62 is supplied. Is configured.

At a position near the resist supply nozzle 60, a resist liquid temperature controller 63 for adjusting the temperature of the resist liquid is attached. The resist liquid temperature controller 63 is formed by, for example, a temperature control mechanism that circulates and supplies a thermostatic liquid whose temperature has been controlled in a jacket surrounding the supply pipe 64. The resist supply nozzle 60 configured as described above is on standby above the spin chuck 58 when not in use, moves above the spin chuck 58 when in use, and moves through the pump ( (Not shown), the resist solution is sent to the resist supply nozzle 60, and is applied (supplied) to the surface of the wafer W held on the spin chuck 58.

Further, the pre-baking unit (PREB)
AKE) is, as shown in FIG. 17, a disc-shaped wafer B placed and baked in a container 71 having a wafer W loading / unloading port 71a and a shutter 71b for opening and closing the loading / unloading port 71a. A heating plate 73 is provided. A heating resistor 74 is built in the heating plate 73, and a current supplied to the heating resistor 74 is adjusted by a pre-baking temperature controller (not shown) under the control of a central processing unit (CPU) 45. It has become.

Furthermore, a resist coating unit (COT)
A film thickness sensor 6 for detecting the film thickness of a resist film applied on the surface of the wafer W held on the spin chuck 58;
The detection signal detected by the film thickness sensor 65 is sent to the central processing unit 45 (CPU). The central processing unit 45 (CPU) determines the thickness of the resist film sent from the film thickness sensor 65 and the line width of the latent image pattern sent from the latent image line width measuring device 25 based on the detected value. The resist solution temperature controller 63 and the motor 61 are used to optimize parameters affecting the film thickness of the resist film, for example, the resist solution temperature, the wafer rotation speed during resist coating, and the pre-baking temperature before resist coating.
And a control command to a pre-baking temperature controller (not shown). That is, as shown in FIG. 18, after forming a resist film on the surface of the wafer W, the motor 61 is stopped, and the film thickness sensor 65 and the spin chuck 58 are relatively moved to arbitrarily move a plurality of locations on the wafer W. The thickness of the resist film (for example, 40 locations on one wafer) is
(Step 131). This detection signal is sent to a central processing unit (CPU) 45 to determine whether or not the thickness of the resist film is within a proper value range, that is, FIG.
It is determined whether or not the appropriate film thickness is within the range from the allowable upper limit value a1 to the allowable lower limit value a2 (step 13).
2). If the film thickness of the resist film is out of the allowable range, the rotation speed of the motor 61 is corrected to control the film thickness to be within the allowable range (step 133). For example, when the film thickness is larger than the allowable upper limit value (case b in FIG. 19A), the rotation speed of the motor 61 is increased to reduce the film thickness, and conversely, the film thickness is smaller than the allowable lower limit value. In this case (case c in FIG. 19A), the number of rotations of the motor 61 is reduced to increase the film thickness.

Here, a central processing unit (CPU)
Reference numeral 45 indicates that the measured line width is not within the proper value range by performing a comparison operation between the measured line width of the latent image pattern sent from the latent image line width measuring device 25 and the appropriate value (step 134). In the case, similarly to the system of the above-described embodiment, the value of a parameter that affects the line width of the resist pattern is changed in the post-exposure process so as to optimize the line width of the resist pattern after development, and the latent image pattern is also changed. A correction corresponding to the difference between the measured line width and the appropriate value is added to the control amount of the motor rotation speed (step 135).

Next, the central processing unit (CPU) 45
Whether the thickness of the resist film is uniform, that is, FIG.
As shown in (1), it is determined whether the profile of the resist film is within an allowable range, that is, within a1 to a2 (step 136). If the profile of the resist film is out of the allowable range, the temperature of the resist solution and / or the prebaking temperature is adjusted to make the film thickness uniform (steps 137 and 138). Here, the film thickness sensor 65 is used.
Is provided in the resist coating unit (COT), but a film thickness sensor 65 is provided outside the resist coating unit (COT) to detect the film thickness of the resist film applied on the surface of the wafer W. Is also good. When the thickness of the resist film is measured by the film thickness sensor 65, a substrate for measurement, for example, a dummy wafer is held on the spin chuck 58 and the resist liquid is applied (supplied) from the resist supply nozzle 60 before the operation of the apparatus. With spin chuck 5
Measurement (detection) after rotating 8 to form resist film
The measurement (detection) timing is arbitrary, such as, for example, whether to perform the process each time the coating process of one lot (for example, 25) wafers W is completed or to perform the process each time the coating process of each wafer W is completed.

As described above, according to the present embodiment, it is possible to control the thickness and line width of the resist film in an in-line manner, thereby improving the productivity and reducing the value of the parameter during the development process. By changing the value of the parameter that determines the thickness of the resist film during the resist coating process in anticipation of the change in the thickness of the resist film due to the change, more accurate film thickness control becomes possible.

The line width of the latent image pattern formed on the resist film after the exposure or the line width of the resist pattern is measured, and the developing time and the developing solution are adjusted to optimize the line width after the development based on the measurement result. The apparatus for controlling the temperature, the post-baking temperature, the pre-baking temperature and the like have been described. As shown in FIG. 20, the line width of the latent image pattern or the line width of the resist pattern is measured, and the It is also possible to provide a command from the resist coating and developing system to the controller of the exposure apparatus so as to correct parameters related to the exposure process, such as the exposure time, exposure focus, and the ultraviolet intensity of the exposure light source. Further, the result of measuring the line width of the latent image pattern or the line width of the resist pattern may be transmitted from the resist coating and developing system to the controller of the exposure apparatus, and the exposure apparatus may calculate correction values for various parameters. .

The apparatus for applying and developing a resist solution on the surface of a semiconductor wafer has been described above.
Needless to say, the present invention can be applied to an apparatus for applying and developing a resist solution on the surface of a CD substrate or the like.

[0117]

[0118]

According to the present invention, to measure the line width of the line width, i.e. the latent image pattern in the exposed portion and / or the unexposed portions of the resist film of the substrate, on the basis of the line width measurement results, development The developer temperature that affects the line width of the resist pattern after development, the development time, the heating temperature of the substrate before development,
By correcting between during the heating of the substrate before development, it is possible to optimize the line width of the resist pattern to be formed on the target substrate surface itself was linewidth measurement, since the line width control In addition to the loss of the substrate to be processed due to the parameter correction described above, the line width of the resist pattern can be controlled with high precision by in-line in the apparatus, and the productivity can be improved.

[0119]

[0120]

[0121]

[Brief description of the drawings]

FIG. 1 is a plan view showing the overall configuration of a semiconductor wafer coating and developing processing system according to an embodiment of the present invention.

FIG. 2 is a front view of the coating and developing processing system shown in FIG. 1;

FIG. 3 is a rear view of the coating and developing system shown in FIG. 1;

FIG. 4 is a diagram showing a configuration of a developing unit and a post-baking unit in the processing station shown in FIG.

FIG. 5 is a view showing a processing flow of the coating and developing processing system shown in FIG. 1;

FIG. 6 is a flowchart showing a procedure for controlling a line width of a resist pattern in the coating and developing system shown in FIG. 1;

FIG. 7 is a characteristic diagram showing a correlation between a PED temperature and an average line width.

FIG. 8 is a characteristic diagram showing a correlation between a PED time and an average line width.

FIG. 9 is a characteristic diagram showing a correlation between PED relative humidity and average line width.

FIG. 10 is a characteristic diagram showing a correlation between a development time and an average line width.

FIG. 11 is a rear view of a coating and developing processing system according to another embodiment of the present invention.

FIG. 12 is a diagram showing a processing flow of a coating and developing processing system according to another embodiment of the present invention.

FIG. 13 is a view showing a processing flow of a coating and developing processing system according to still another embodiment of the present invention.

FIG. 14 is a view showing a processing flow of a coating and developing processing system according to still another embodiment of the present invention.

FIG. 15 is a diagram showing a processing flow of a coating and developing processing system according to another embodiment of the present invention.

FIG. 16 is a diagram showing a processing flow of a coating and developing processing system according to another embodiment of the present invention.

FIG. 17 is a diagram showing a configuration of a resist coating unit and a pre-baking unit in a coating and developing processing system according to another embodiment of the present invention.

FIG. 18 is a flowchart showing a procedure of resist film thickness control and line width control in a coating and developing processing system according to another embodiment of the present invention.

FIG. 19 is a diagram showing a relationship between a resist film thickness and a wafer diameter.

FIG. 20 is a diagram showing a processing flow of a coating and developing processing system according to another embodiment of the present invention.

[Explanation of symbols]

W: semiconductor wafer (substrate to be processed) POBAKE: post-baking unit (heating means) COT: resist coating unit (resist coating means) DEV: developing unit (developing means) COL: recooling unit (cooling means) 25 ... Latent image line width measuring device (line width measuring means) 45 ... Central processing arithmetic unit (control means)

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-7-212630 (JP, A) JP-A-5-315220 (JP, A) JP-A 8-264408 (JP, A) JP-A 8- 213313 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/027

Claims (16)

(57) [Claims] A developing solution is supplied to a surface of a substrate, on which a resist film selectively exposed is formed, on a surface of the substrate.
A developing unit for performing management, before performing the developing process in the developing unit, and a line width measuring means for measuring the resist line width of the exposed portion and / or the non-exposed portion of film of the substrate to be treated, before Symbol line Line width measurement result of width measurement means and preset line width
The resist obtained after the development process based on the appropriate value of
The parameter values that affect the line width of the pattern
A resist coating / developing apparatus comprising: a control unit for performing correction before performing a development process on the processing substrate . 2. A developing process, comprising supplying a developing solution to a surface of a substrate on which a resist film selectively exposed is formed.
A developing unit that sense that, before applying the developing process in the developing unit, an input unit for inputting the measurement result of the resist line width of the exposed portion and / or the non-exposed portion of film of the substrate to be processed, the input means preset the line width measurement results input by
Is obtained after the development process based on the
Of parameter that affects line width of resist pattern
And control means for correcting before the substrate to be processed is subjected to the developing process . 3. The resist coating and developing apparatus according to claim 1, wherein the value of the parameter is at least one of a temperature of a developing solution supplied to the substrate to be processed and a developing processing time in the developing unit. And a resist coating and developing apparatus. 4. The resist coating and developing apparatus according to claim 1, further comprising a heating unit for heating the substrate to be processed after exposure and before performing a developing process by the developing unit, wherein the value of the parameter is set. Wherein at least one of the heating temperature and the heating time of the heating means is included. 5. The resist coating and developing apparatus according to claim 1, further comprising: a resist coating unit configured to apply a resist liquid to a surface of the substrate while rotating the substrate. Is a resist coating and developing apparatus which corrects the value of the parameter and corrects the value of a parameter which affects the resist coating thickness of the resist coating means. 6. The resist coating and developing apparatus according to claim 1, wherein said control means corrects the value of said parameter,
A resist coating and developing apparatus for correcting a value of a parameter affecting an exposure process of the resist film. 7. A cassette station for loading and unloading a cassette accommodating a plurality of substrates to be processed to and from the outside, and for loading and unloading the substrates to and from the cassette; A processing station unit configured by arranging a plurality of single-wafer processing units that perform the above-described processing in multiple rows and columns, and an interface unit that transfers the substrate to be processed to and from an external exposure apparatus. A resist coating and developing apparatus, wherein at least one of the processing units is a developing processing unit that supplies a developing solution to a surface of the substrate to be processed and performs a developing process; Along with the exposure apparatus, the resist film selectively exposed by the exposure apparatus is formed on the surface of the substrate to be processed, A line width measuring unit having a line width measuring unit for measuring a line width of an exposed portion and / or a non-exposed portion of the dist film, wherein a line width measurement result of the line width measuring unit and a predetermined line width A resist coating and developing apparatus comprising: a control unit that corrects a value of a parameter that affects a line width of a resist pattern obtained after the development processing in the development processing unit, based on the value. 8. carry to and from external cassette in which a plurality accommodating a substrate to be processed, as well as unloading a cassette station unit for loading and unloading the substrate to be processed with respect to the cassette, predetermined with respect to the substrate to be processed A processing station unit configured by arranging a plurality of single-wafer processing units that perform the above-described processing in multiple rows and columns, and an interface unit that transfers the substrate to be processed to and from an external exposure apparatus. In the resist coating and developing apparatus, the processing station unit is separated by a transport unit for loading and unloading the substrate to be processed into and out of each of the processing units, a transport path of the transport unit, and the transport path. A front side processing unit group and a back side processing unit group, wherein the front side processing unit group supplies a developing solution to a surface of the substrate to be processed and performs development. A heat treatment unit that heats the substrate to be processed, a cooling unit that cools the substrate to be heated by the heat treatment unit, and an exposure apparatus. A line width measurement unit configured to measure a line width of an exposed portion and / or a non-exposed portion of the resist film of the substrate on which the selectively exposed resist film is formed on the surface; A control unit that corrects a value of a parameter that affects a line width of a resist pattern obtained after the development processing in the development processing unit based on a line width measurement result of the unit and an appropriate value of a preset line width. A resist coating and developing apparatus comprising: 9. The resist coating and developing apparatus according to claim 8, wherein the line width measuring unit is provided adjacent to the cooling processing unit. 10. carry to and from external cassette in which a plurality accommodating a substrate to be processed, as well as unloading a cassette station unit for loading and unloading the substrate to be processed with respect to the cassette, predetermined with respect to the substrate to be processed A processing station unit configured by arranging a plurality of single-wafer processing units that perform the above-described processing in multiple rows and columns, and an interface unit that transfers the substrate to be processed to and from an external exposure apparatus. In the resist coating and developing apparatus, the processing station unit is separated by a transport unit for loading and unloading the substrate to be processed into and out of each of the processing units, a transport path of the transport unit, and the transport path. A front-side processing unit group and a rear-side processing unit group, wherein the front-side processing unit group supplies a developing solution to a surface of the substrate to be processed to perform development. A heating unit configured to perform a heating process on the substrate to be processed exposed by the exposure device before performing the development process by the development processing unit; and the exposure device. A heat treatment unit comprising: a line width measuring means for measuring a line width of an exposed portion and / or a non-exposed portion of the resist film of the substrate on which the resist film selectively exposed at the surface is formed. A cooling processing unit that cools the substrate to be processed, heated by the heating unit, based on a line width measurement result of the line width measuring unit and an appropriate value of a preset line width, A resist coating and developing apparatus comprising a control unit for correcting a value of a parameter affecting a line width of a resist pattern obtained after a developing process in a processing unit. 11. A cassette station for loading and unloading a cassette accommodating a plurality of substrates to be processed to and from the outside, and loading and unloading the substrate to be processed into and out of the cassette; A processing station unit configured by arranging a plurality of single-wafer processing units that perform the above-described processing in multiple rows and columns, and an interface unit that transfers the substrate to be processed to and from an external exposure apparatus. In the resist coating and developing apparatus, the processing station unit is separated by a transport unit for loading and unloading the substrate to be processed into and out of each of the processing units, a transport path of the transport unit, and the transport path. A front-side processing unit group and a rear-side processing unit group, wherein the front-side processing unit group supplies a developing solution to a surface of the substrate to be processed to perform development. A heating unit having a processing unit, wherein the back-side processing unit group includes a heating unit for performing a heating process on the substrate to be processed exposed by the exposure apparatus before performing the developing process by the developing unit. Cooling means for cooling the substrate to be processed heated by the heating means before performing development processing in the development processing unit; and a resist film selectively exposed by the exposure apparatus is formed on the surface. A line width measuring unit for measuring a line width of an exposed portion and / or a non-exposed portion of the resist film of the processed substrate, wherein the line width measuring unit measures the line width. A control unit that corrects a value of a parameter that affects a line width of a resist pattern obtained after the development processing in the development processing unit based on a result and an appropriate value of a preset line width. A resist coating and developing apparatus. 12. The method according to claim 11, wherein the selectively exposed resist film has a surface.
Before performing development processing on the substrate to be formed formed on the substrate, the line width of the exposed portion and / or the non-exposed portion of the resist film of the substrate to be processed is measured, and the line width measurement result and a preset line are measured.
Based on the appropriate value of the width, the laser obtained after the development processing
Set the parameter values that affect the line width of
A resist coating and developing method , wherein the correction is performed before the development processing is performed on the substrate to be processed . 13. The resist coating and developing method according to claim 12, wherein the value of the parameter includes at least one of a temperature of a developing solution supplied to the substrate to be processed in the developing process and a developing process time. A resist coating and developing method. 14. The resist coating and developing method according to claim 12, wherein the substrate to be processed is subjected to a heating process after the line width is measured and before the developing process is performed, and the value of the parameter is:
A resist coating and developing method comprising at least one of a heating temperature and a heating time in the heat treatment. 15. The resist coating and developing method according to claim 12, wherein the value of the parameter is corrected and the value of a parameter that affects the resist coating thickness in the resist film coating process is corrected. And a resist coating and developing method. 16. The resist coating and developing method according to claim 12, wherein the value of the parameter is corrected, and the value of a parameter affecting the exposure processing of the resist film is corrected. Resist coating and developing method.