JP3342778B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a structure of a metal insulator metal (MIM) capacitor of a semiconductor device and a method of manufacturing the same.

[0002]

2. Description of the Related Art FIGS. 22 and 23 are a top view and a sectional view, respectively, showing the structure of an MIM capacitor (hereinafter simply referred to as a capacitor) of a conventional semiconductor device. In both figures, 1P is a semi-insulating semiconductor substrate, 2P is a through-hole (hereinafter, referred to as a via hole) formed in the semiconductor substrate 1P, and 3P is a base electrical layer formed so as to cover the upper surface of the via hole 2P. Wiring, 4P is insulating film, 5P is insulating film 4P
The upper metal 6P disposed and formed above the via hole 2P away from the via hole 2P is formed below the semiconductor substrate 1P and is formed so as to be electrically connected to the underlying electric wiring 3P in the via hole 2P. Lower electric wiring.

Next, the electrical operation will be described. The presence of the insulating film 4P between the upper metal 5P and the underlying electrical wiring 3P forms a capacitor, and further reduces the lower electrical wiring 6P.
And the underlying electrical wiring 3P are connected by the via hole 2P, thereby forming the upper wiring and the lower electrical wiring 6P of the semiconductor substrate.
And operates as a coupling capacitor.

[0004] FIG.
FIG. 1 is a vertical view of a capacitor of a conventional semiconductor device disclosed in Japanese Patent Application Laid-Open Publication No. 1 (1999). Here, the capacitor is via hole 2
It is formed on the upper surface of P.

[0005]

Since the conventional semiconductor device is formed in the vicinity of the via hole as described above, a microcrack originating from the via hole occurs during a thermal cycle and cooling during assembly. This state is shown in FIGS. In these figures, 7 is a micro crack.

When such micro cracks occur,
Cracks are formed in the insulating film of the capacitor portion, and since the thickness of the insulating film is thin, the microcracks (which cause a step) cause the upper metal layer (5P in FIG. 23) and the lower metal layer (5P in FIG. 23) of the capacitor. 23P) of FIG. 23 occurs, resulting in a short-circuit failure.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and it is an object of the present invention to prevent a capacitor from cracking even if a microcrack occurs from a via hole, thereby preventing a failure. Is the primary purpose. It is a second object of the present invention to provide a method of manufacturing a semiconductor device having a structure capable of preventing a short circuit failure due to the occurrence of such micro cracks.

[0008]

The invention according to claim 1 is
Forming a reinforcing metal layer on the upper surface of the semiconductor substrate;
The area of the upper surface of the reinforcing metal layer is larger than that of the reinforcing metal layer.
Forming a small underlying metal layer on the substrate;
Plate, the reinforcing metal layer and the base metal layer.
Forming an edge film; and forming an underlayer in the upper surface of the insulating film.
On the portion corresponding to the upper surface of the metal layer,
Forming an upper metal layer having a smaller area than the above,
The lower surface of the semiconductor substrate hits the lower portion of the reinforcing metal layer.
Until the lower surface of the reinforcing metal layer is exposed from the portion
Forming a through hole by etching the semiconductor substrate;
An inner surface of the through hole, an exposed lower surface of the reinforcing metal layer,
And forming a lower electric wiring layer on the lower surface of the semiconductor substrate.
And a degree.

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According to the first aspect of the present invention, the upper metal, the insulating film,
And the capacitor part consisting of the underlying metal
Semiconductor via a reinforcing metal layer that is larger in area than metal
It is formed on the upper surface of the substrate. Then, under the reinforcing metal layer
Since the through hole is formed in the
On the upper surface of the through hole via the metal layer
You.

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【Example】

Embodiment 1 Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of a semiconductor device according to the first embodiment. In FIG. 1, reference numeral 1 denotes a semi-insulating semiconductor substrate, for example, a GaAs substrate (hereinafter referred to as GaAs substrate).
Reference numeral 2 denotes a through hole (hereinafter, referred to as a via hole) formed in the GaAs substrate 1, and reference numeral 8 denotes a reinforcing metal layer formed on the upper surface of the via hole 2 so as to cover the through portion. In addition, it is formed so that its area is larger than that of the underlying electric wiring 3 described later. Reinforcing metal layer 8
Is made of, for example, a Ti film having a thickness of 2 μm to 10 μm. 3
Is an underlying electric wiring (base metal) formed on the reinforcing metal layer 8, 4 is an insulating film formed so as to cover the upper surface of the underlying electric wiring 3 and the reinforcing metal layer 8, For example, it is made of a silicon nitride film. Reference numeral 5 denotes an upper metal formed on the upper surface of the insulating film 4 so as to be smaller in area than the underlying electric wiring 3, and 6 is formed on the lower surface of the GaAs substrate 1 and the inner surface of the via hole 2. This is the lower electrical wiring.

The method for manufacturing the above semiconductor device will be described below. In the following description, as the semiconductor substrate 1, G
An aAs substrate is used. In addition, the base electric wiring 3 is referred to as a base metal layer 3, the upper metal 5 is referred to as an upper metal layer 5, and the lower electric wiring 6 is referred to as a lower electric wiring layer 6, respectively.

First, a resist 18 having a predetermined pattern is formed on the upper surface of the GaAs substrate 1 by photolithography. Next, a reinforcing metal layer 8, for example, Ti is formed by vacuum evaporation (FIG. 2), and the reinforcing metal layer 8 is patterned by a lift-off process. After that, the resist 18 is removed by an ashing process. As a result, only the reinforcing metal layer 8 on the upper surface of the GaAs substrate 1 remains.

Next, as shown in FIG. 3, a resist 11 having an opening on the upper surface of the reinforcing metal layer 8 is formed by photolithography, and a plating power supply layer (not shown) is provided on the upper surface of the resist 11. Then, a resist 12 is formed on the resist 11 with the same opening. Then, the underlying metal layer 3, for example, Au is patterned on the upper surface of the reinforcing metal layer 8 by electrolytic plating.

Thereafter, the resists 12 and 13 are removed by ashing. Thereby, the base metal layer 3 smaller in area than the reinforcing metal layer 8 is formed on the upper surface of the reinforcing metal layer 8.

Next, an insulating film 4, for example, a silicon nitride film is provided on the upper surfaces of the base metal layer 3, the reinforcing metal layer 8 and the GaAs substrate 1 by plasma CVD. 3
An upper metal layer 5 having a smaller area than that of the upper metal layer 5, for example, Au is formed (FIG. 4).

Next, the Ga under the reinforcing metal layer 8
Photolithography and wet etching are performed on the As substrate 1 to form a via hole 2 (FIG. 5). That is, etching is performed using an etchant made of a mixture of tartaric acid and water, for example, until the lower surface of the reinforcing metal layer 8 is exposed from the lower surface of the GaAs substrate 1 below the reinforcing metal layer 8. In this case, the reinforcing metal layer 8 serves as an etching stopper layer.

Next, a lower electric wiring layer 6, for example, Au is formed on the lower surface of the GaAs substrate 1, the inner surface of the via hole 2, and the lower surface of the reinforcing metal layer 8 by plating. Thereby, the MIM capacitor shown in FIG. 1 is formed.

In the capacitor configured as described above, the occurrence of micro cracks is prevented as follows. That is, at the time of heat cycle and cooling during assembly,
Stress is generated in the via hole 2 due to thermal expansion and contraction caused by a difference in thermal expansion coefficient between the GaAs substrate 1 and the package and the die bonding material. Even if micro cracks occur in the GaAs substrate 1 due to the thermal stress, the reinforcing metal layer 8 is formed to be larger in area than the upper metal 5 and the underlying electric wiring 3. The stress is absorbed by the metal layer 8 for use, and as a result, microcracks do not occur in the capacitor portion (the insulating film 4 thereof).

As described above, according to this embodiment, the capacitor is arranged on the upper surface of the via hole, and has a larger area than the upper metal layer (upper metal 5) and the lower metal layer (base metal 3). Since the large lower metal layer (reinforcement metal layer 8) reinforces, even if a microcrack occurs in the semiconductor substrate starting from the via hole, the microcrack distortion is caused by the reinforcement metal under the capacitor in the capacitor insulating film. As a result, no crack occurs in the insulating film, and no short-circuit fault occurs.

Embodiment 2 FIGS. 6 and 7 show the configuration of a semiconductor device according to a second embodiment. FIG. 6 and FIG.
It is the top view and sectional view of the capacitor part of the semiconductor device concerning a 2nd example, respectively.

6 and 7, those having the same reference numerals as those in FIG. 1 have the same names as those in FIG. Reference numeral 9 in FIG. 6 denotes a connection portion that electrically connects the individual upper metal members 5 divided into a plurality of blocks.

In the first embodiment described above, the reinforcing metal layer 8 having a large area is formed under the underlying electric wiring 3. In the second embodiment, however, the capacitor portion having a structure not using the reinforcing metal layer is used. Is shown.

In the second embodiment, as shown in FIGS.
The upper metal 5 is divided into a plurality of blocks each having a side length of about 10 μm, and these blocks are electrically connected to each other by a part (connection portion 9) of the upper metal. Therefore, a portion sandwiched between each of the upper metal 5 and the underlying electric wiring 6 forms a capacitor, and a capacitor portion is formed by connecting these in parallel.

Hereinafter, a method of manufacturing a semiconductor device according to the second embodiment will be described. First, the underlying metal layer 3 is formed on the upper surface of the GaAs substrate 1 by photolithography and a lift-off process, and the insulating film 4 is formed on the upper surface of the GaAs substrate 1 and the upper surface of the underlying metal layer 3 by plasma CVD.
To form Then, after depositing and depositing an upper metal layer on the upper surface of the insulating film 4, the upper metal is patterned by photolithography and a lift-off process to be divided into a plurality of blocks. The upper metal 5 which is the divided individual block is connected to a connection portion 9 made of an upper metal layer.
Are electrically connected by As a result, a state is formed in which the capacitors for the number of blocks are connected in parallel (FIGS. 6 and 7).

Next, the lower surface of the underlying metal layer 3 is exposed from the lower surface of the GaAs substrate 1 below the divided upper metal 5 by photolithography and wet etching (etchant: a mixture of tartaric acid and water). Ga
The As substrate 1 is etched to form a via hole 2. In this case, the underlying metal layer 3 becomes an etching stopper layer.

Next, a lower electric wiring layer 6, for example, Au is formed by plating on the lower surface of the GaAs substrate 1, the inner surface of the via hole 2, and the exposed lower surface of the base metal layer 3, thereby forming an MIM capacitor.

With the above configuration, it is possible to prevent the occurrence of microcracks in the capacitor portion. That is, in the present configuration, due to the stress at the time of thermal expansion and contraction of the GaAs substrate 1 caused by the thermal cycle and the cooling during the assembly,
As shown in FIG. 7, deformation (distortion) of the underlying electric wiring 3 occurs. However, since the area of each upper metal 5 is small,
The stress applied to the insulating film 4 is reduced, and as a result, no crack occurs in the capacitor portion.

(Modification of Second Embodiment) Instead of the connection portion 9 in the second embodiment, a configuration in which the upper metal members 5 are electrically connected by aerial wiring may be adopted. The manufacturing method according to the modification of the second embodiment in this case will be described below with reference to FIGS.
This will be described based on the cross-sectional view of FIG.

First, the underlying metal layer 3 is formed on the upper surface of the GaAs substrate 1 by photolithography and a lift-off process, and the insulating film 4 is formed on the upper surface of the underlying metal layer 3 and the upper surface of the GaAs substrate 1 by plasma CVD. . Further, on the upper surface of the insulating film 4 corresponding to the upper part of the base metal layer 3, a plurality of upper metal layers 5, each of which is electrically disconnected, are formed by photolithography and lift-off. Then, a resist 19 is applied to the upper surface of each upper metal layer 5 and the upper surface of the insulating film 4, and the resist 19 is patterned by photolithography so as to have an opening on the upper surface of each upper metal layer 5. Further, after forming a plating power supply layer (not shown) on the upper surface of the resist 19, the resist 2
0 is formed and patterned. The resist 19 also fills the space between the upper metal layers (blocks) 5. Then, an aerial wiring 9a, for example, Au for connecting the upper surfaces of the adjacent upper metal layers 5 is formed by electrolytic plating (FIG. 8). After that, the resists 11 and 12 are removed.

Next, the GaAs below each block 5
Via holes 2 are formed by photolithography and wet etching from the lower surface of the s substrate 1 until the lower surface of the underlying metal layer 3 is exposed (FIG. 9). Also in this case, the underlying metal layer 3 serves as an etching stopper layer, and the etchant is, for example, a mixed solution of tartaric acid and water. Thereafter, the lower electric wiring layer 6, for example, Au is formed on the lower surface of the GaAs substrate 1, the inner surface of the via hole 2, and the lower surface of the base metal layer 3 by plating, thereby forming an MIM capacitor.

According to this modification, the same effect can be obtained according to the same principle as that of the second embodiment.

Third Embodiment FIG. 10 shows a top view of a capacitor portion of a semiconductor device according to a third embodiment. In addition, sectional views taken along lines II-II and III-III in FIG. 10 are shown in FIGS. 12 and 11, respectively. These figures 1
In FIGS. 0 to 12, those having the same reference numerals as those in FIG. 1 have the same names. The underlying electric wiring 3 is formed by an island-shaped portion 3a, a connecting portion 3b, and a receiving portion 3c.
0 is a through hole.

In the semiconductor device according to the third embodiment, the through hole 10 is provided in the underlying electrical wiring 3, and the capacitor portion of the underlying electrical wiring 3 is formed in the central island-like portion 3a (the underlying metal island-like portion). Things. Moreover, although the capacitor portion is supported by the receiving portion 3c and the connecting portion 3c, it is just placed in the air on the upper surface of the via hole 2.

Hereinafter, a manufacturing method according to the third embodiment will be described with reference to the cross-sectional views of FIGS.

First, the underlying metal layer 3 is formed on the upper surface of the GaAs substrate 1 by photolithography and a lift-off process.
After forming an island-shaped portion 3a, its connection portion 3c, and a receiving portion 3b, further forming an insulating film 4 on the upper surface of the base metal layer 3 and the upper surface of the GaAs substrate 1 by plasma CVD or the like, Only the insulating film 4 formed on the upper surface is removed by patterning. Thereby, the insulating film 4 is formed only on the upper surface of the base metal layer 3 (3a, 3b, 3c). Thereafter, the upper metal layer 5 is formed on the upper surface of the insulating film 4 formed on the island-shaped portion 3a by photolithography and lift-off (FIG. 13). FIG.
3 to 15 are cross-sectional views taken along line III-III.

Next, a resist 13 is formed on the entire upper surface of the semiconductor substrate 1 and each of the layers 4 and 5, and a resist 14 is patterned on the lower surface of the GaAs substrate 1 by photolithography.

Next, using the resist 14 as a mask, the lower surface of the GaAs substrate 1 under the underlying metal layers 3a, 3b, 3c is removed from the lower surface of the resist 13 by wet etching (etchant: a mixed solution of tartaric acid and water). The via hole 2 is formed by etching until the lower surface of the island-shaped portion 3a is exposed (FIG. 14). At this time,
The resist 13 and the underlying metal layers 3a, 3b, 3c form an etching stopper layer. Finally, a lower electric wiring layer 6, for example, Au is formed by plating on the lower surface of the GaAs substrate 1, the inner surface of the via hole 2, and the lower surface of the island-shaped portion 3a, thereby forming an MIM capacitor.

In the third embodiment, the stress generated by the expansion and contraction of the GaAs substrate 1 due to the thermal cycle and cooling during assembly can be absorbed by the underlying electric wiring bridge portion 3c. No crack occurs in No. 4.

Fourth Embodiment FIG. 16 is a sectional view of a capacitor portion of a semiconductor device according to a fourth embodiment. In the figure, components having the same reference numerals as those in FIG. 1 have the same names. In addition, 2a is a lower via hole, 2b is an upper via hole, and 2a and 2b correspond to the via hole 2 of FIG. 1 divided into two.

In the fourth embodiment, the base electric wiring 3 and the insulating film 4 are formed in this order on the upper surface of the lower electric wiring 6 in the middle of the via hole composed of 2a and 2b, that is, in the middle of the inside of the semiconductor substrate 1. And an insulating film 4
The upper ground electrode 5 is formed on the upper surface of the substrate and along the inner surface of the upper surface via hole 2b.

Hereinafter, a method of manufacturing a semiconductor device according to the third embodiment will be described with reference to the cross-sectional views of FIGS.

First, a resist 15 patterned by photolithography is formed on the upper surface of the GaAs substrate 1, and anisotropic etching is performed using the resist 15 as a mask to form an upper via hole 2b (FIG. 17).

Next, an underlying metal layer 3, for example, Au, is formed on the bottom of the upper via hole 2b by photolithography and a lift-off process. Further, the upper surface of the underlying metal layer 3, the inner surface of the upper via hole 2a and the Ga
An insulating film 4 is formed on the upper surface of the As substrate 1 by plasma CVD.
For example, after forming a silicon nitride film, a resist 16 having a pattern shown in FIG. 18 is formed by photolithography. Then, the insulating film 4 is etched using the resist 16 as a mask to form the upper metal layer 5 patterned by photolithography (FIG. 19).

Next, a patterned resist 17 is formed on the lower surface of the GaAs substrate 1 and the lower portion of the GaAs substrate 1 is wet-etched (etchant: for example, using the resist 17 as a mask until the lower surface of the underlying metal layer 3 is exposed. Then, a lower surface via hole 2a is formed (FIG. 20). Also in this case, the underlying metal layer 3 functions as an etching stopper layer. After that, the resist 17 is removed.

Finally, the lower electric wiring layer 6, for example, Au is formed on the lower surface of the GaAs substrate 1, the inner surface of the lower surface via hole 2a, and the lower surface of the GaAs substrate 1 by plating, thereby forming the MIM capacitor.

As a result, since the capacitor portion is formed between the upper via hole 2b and the lower via hole 2a (an intermediate portion of the semiconductor substrate 1), the expansion and contraction stress of the GaAs substrate 1 due to the thermal cycle and the cooling during assembly is reduced. As a result, cracks do not occur in the capacitor portion.

[0074]

According to the first aspect of the present invention, the upper metal
And a reinforcing metal layer that is larger in area than the underlying metal
Can be formed on the bottom of the metal, i.e. on the top of the through hole
You. This reinforcing metal layer starts from the through hole by thermal expansion and contraction.
Micro-cracks on the semiconductor substrate
To prevent short circuit failure.

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[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a configuration of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a manufacturing process of the semiconductor device according to the first embodiment;

FIG. 3 is a sectional view illustrating a manufacturing process of the semiconductor device of the first embodiment;

FIG. 4 is a sectional view illustrating a manufacturing step of the semiconductor device of the first embodiment;

FIG. 5 is a sectional view illustrating a manufacturing process of the semiconductor device of the first embodiment;

FIG. 6 is a top view illustrating a configuration of a semiconductor device according to a second embodiment of the present invention;

FIG. 7 is a sectional view illustrating a configuration of a semiconductor device according to a second embodiment of the present invention;

FIG. 8 is a cross-sectional view showing a manufacturing process of a modification of the second embodiment.

FIG. 9 is a cross-sectional view illustrating a manufacturing process of a modification of the second embodiment.

FIG. 10 is a top view illustrating a configuration of a semiconductor device according to a third embodiment of the present invention.

FIG. 11 is a sectional view illustrating a configuration of a semiconductor device according to a third embodiment of the present invention;

FIG. 12 is a sectional view illustrating a configuration of a semiconductor device according to a third embodiment of the present invention;

FIG. 13 is a cross-sectional view showing a manufacturing step of the third embodiment.

FIG. 14 is a cross-sectional view illustrating a manufacturing process of the third embodiment.

FIG. 15 is a cross-sectional view illustrating a manufacturing step of the third embodiment.

FIG. 16 is a sectional view illustrating a configuration of a semiconductor device according to a third embodiment of the present invention;

FIG. 17 is a cross-sectional view showing a manufacturing step of the fourth embodiment.

FIG. 18 is a cross-sectional view showing the manufacturing process of the fourth embodiment.

FIG. 19 is a cross-sectional view showing a manufacturing step of the fourth embodiment.

FIG. 20 is a cross-sectional view showing the manufacturing process of the fourth embodiment.

FIG. 21 is a cross-sectional view showing a manufacturing step of the fourth embodiment.

FIG. 22 is a top view illustrating a configuration of a conventional semiconductor device.

FIG. 23 is a cross-sectional view illustrating a configuration of a conventional semiconductor device.

FIG. 24 is a cross-sectional view illustrating a configuration of a conventional semiconductor device.

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate, 2 via hole, 2a bottom via hole, 2b top via hole 3 base electric wiring,
3a island-shaped part, 3b receiving part, 3c underground electric wiring bridge part, 4 insulating film, 5 upper ground metal, 6 lower electric wiring, 7 micro crack, 8 reinforcing metal layer, 9
Connection part, 9a Aerial wiring.

Claims (1)

(57) [Claims] 1. A reinforcing metal layer is formed on an upper surface of a semiconductor substrate.
And the area on the upper surface of the reinforcing metal layer is larger than that of the reinforcing metal layer.
Forming a small underlying metal layer, the semiconductor substrate, the reinforcing metal layer and the underlying metal layer
Forming an insulating film on the upper surfaces of, in the upper surface of the insulating film, it falls under the upper surface of the underlying metal layer
Over the portion where the area is smaller than the underlying metal layer.
Forming a metal layer and forming a metal layer under the reinforcing metal layer within the lower surface of the semiconductor substrate.
Until the lower surface of the reinforcing metal layer is exposed from the contacting part
Forming a through hole by etching the semiconductor substrate;
And the inner surface of the through hole, the exposed lower surface of the reinforcing metal layer,
And forming a lower electric wiring layer on the lower surface of the semiconductor substrate.
A degree, a method of manufacturing a semiconductor device characterized by comprising.