CN107275315A - A kind of structure of compound semiconductor back of the body gold capacitor and preparation method thereof - Google Patents

A kind of structure of compound semiconductor back of the body gold capacitor and preparation method thereof Download PDF

Info

Publication number
CN107275315A
CN107275315A CN201710390074.4A CN201710390074A CN107275315A CN 107275315 A CN107275315 A CN 107275315A CN 201710390074 A CN201710390074 A CN 201710390074A CN 107275315 A CN107275315 A CN 107275315A
Authority
CN
China
Prior art keywords
electrode plate
metal layer
substrate
layer
radiating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201710390074.4A
Other languages
Chinese (zh)
Inventor
王勇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Integrated Circuit Co Ltd Is Pacified By Xiamen City Three
Xiamen Sanan Integrated Circuit Co Ltd
Original Assignee
Integrated Circuit Co Ltd Is Pacified By Xiamen City Three
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Integrated Circuit Co Ltd Is Pacified By Xiamen City Three filed Critical Integrated Circuit Co Ltd Is Pacified By Xiamen City Three
Priority to CN201710390074.4A priority Critical patent/CN107275315A/en
Publication of CN107275315A publication Critical patent/CN107275315A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64Impedance arrangements
    • H01L23/642Capacitive arrangements
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • H01L28/60Electrodes
    • H01L28/65Electrodes comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • H01L28/60Electrodes
    • H01L28/75Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • H01L28/60Electrodes
    • H01L28/82Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions

Abstract

The invention discloses structure of a kind of compound semiconductor back of the body gold capacitor and preparation method thereof, MIM capacitor is made in substrate within the radiating connector of front and back, first electrode plate, dielectric layer and second electrode plate stack gradually and extend the bottom surface and side to cover the radiating connector along the radiating connector inwall respectively and extend to the back side for covering substrate described in the radiating connector periphery, wherein first electrode plate is physically contacted in the radiating connector bottom surface with metal connecting line layer, second electrode plate earthing.MIM capacitor is blended in the intrinsic structure of chip by the present invention, and its shared area in integrated circuits is significantly reduced while capacitance is increased, device miniaturization is realized;And radiating is realized by special mim structure, without setting thermal column in addition, simplify structure.

Description

A kind of structure of compound semiconductor back of the body gold capacitor and preparation method thereof
Technical field
The present invention relates to semiconductor devices, the structure of more particularly to a kind of compound semiconductor back of the body gold capacitor and its making Method.
Background technology
MIM capacitor is widely used as storage electric charge, coupling, filtering device, in semiconductor integrated circuit The making of its in manufacturing process is an important process procedure.Known MIM capacitor includes upper and lower battery lead plate and is located in Dielectric layer between the two, and the capacitance of capacitor and the area of battery lead plate be directly proportional.With the development of microelectric technique, it is Improve the overall performance of semiconductor devices to reach faster arithmetic speed, bigger memory data output and more work( Can, the capacity requirement to capacitor is increasingly improved.
Known mim capacitor structure is made on semiconductor base, and in order to increase the capacity of capacitor, prior art is past Toward the method using increase electrode for capacitors plate suqare, this obviously increases the area that capacitor takes integrated circuit, constrained The miniaturization of semiconductor devices, thus become increasingly to weigh the problem of electric capacity occupied area is reduced on the premise of ensuring performance Will.
The content of the invention
It is an object of the invention to the deficiency for overcoming prior art, there is provided the structure that a kind of compound semiconductor carries on the back gold capacitor And preparation method thereof.
The technical solution adopted for the present invention to solve the technical problems is:
A kind of compound semiconductor carries on the back the structure of gold capacitor, including chip and the MIM capacitor for being arranged at chip back surface;Institute Chip is stated including compound semiconductor substrate and located at the metal connecting line layer of the substrate front surface, the substrate has through just Face and the radiating connector at the back side, the radiating connector expose the metal connecting line layer;The MIM capacitor includes first electrode Plate, dielectric layer and second electrode plate, first electrode plate, dielectric layer and second electrode plate are stacked gradually and connected respectively along the radiating The extension of interface inwall covers the radiating connector periphery institute to cover the bottom surface and side of the radiating connector and extend to The back side of substrate is stated, wherein first electrode plate is physically contacted in the radiating connector bottom surface with metal connecting line layer, second Electrode plate earthing.
Optionally, the first electrode plate and second electrode plate include barrier metal layer and the conductive gold stacked gradually respectively Belong to layer, the wherein thickness of barrier metal layer is 20-100nm, and the thickness of conductive metal layer is 400-1600nm.
Optionally, the barrier metal layer is TiW, and conductive metal layer is Au.
Optionally, the thickness of the dielectric layer is 50-200nm.
Optionally, the dielectric layer is SiN.
Optionally, substrate described in the first electrode plate, second electrode plate and dielectric layer to the radiating connector periphery The back side extension length it is incremented by successively.
Optionally, the second electrode plate is connected to be grounded in encapsulating structure with package support.
The preparation method that a kind of above-claimed cpd semiconductor carries on the back gold capacitor, comprises the following steps:
1) chip for completing front processing procedure is provided, the chip includes compound semiconductor substrate and located at the substrate Positive metal connecting line layer;
2) the chip wax is fitted on substrate in the way of facing down;
3) grind after being thinned, the radiating connector of front and back run through in formation in the substrate by photoetching process, The radiating connector exposes the metal connecting line layer surface;
4) it is sequentially depositing to form the bottom surface for covering the radiating connector and side and the base for covering radiating connector periphery First electrode plate, dielectric layer and the second electrode plate of bottom back side, to form mim capacitor structure;
5) by after chip turn-over, peeling liner bottom is simultaneously cleaned;
6) second electrode plate earthing.
Optionally, step 4) include following sub-step:
A) bottom surface of the deposition covering radiating connector and side and the first barrier metal layer for covering backside of substrate, thick Spend for 20-100nm;
B) the first conductive metal layer of the first barrier metal layer of deposition covering, thickness is 400-1600nm;
C) the first barrier metal layer and the first conductive metal layer of the backside of substrate outside the first predeterminable area are removed, is remained Remaining the first barrier metal layer and the first conductive metal layer forms the first electrode plate, wherein first predeterminable area includes The back side of substrate described in the radiating connector and its periphery;
D) deposition forms the dielectric layer of covering first electrode plate and backside of substrate, and thickness is 50-200nm;
E) the second barrier metal layer of blanket dielectric layer is deposited, thickness is 20-100nm;
F) the second conductive metal layer of the second barrier metal layer of deposition covering, thickness is 400-1600nm;
G) the second barrier metal layer and the second conductive metal layer of the backside of substrate outside the second predeterminable area are removed, is remained Remaining the second barrier metal layer and the second conductive metal layer forms the second electrode plate, wherein second predeterminable area is covered And more than first predeterminable area.
Optionally, first conductive metal layer and/or the second conductive metal layer are to first pass through physical vapour deposition (PVD) 100- 600nm metal level is as plating seed, and the metal level for then electroplating 300-1000nm is made.
The beneficial effects of the invention are as follows:
1. MIM capacitor design is increased in the radiating connector used for chip cooling by the side of connector The surface area of big pole plate, so as to increase effectively capacitance, relative to the MIM capacitor that tradition is located at chip surface, the present invention will It is blended in the intrinsic structure of chip, and its shared face in integrated circuits is significantly reduced while capacitance is increased Product, realizes device miniaturization.
2. MIM capacitor is arranged in radiating connector and chip back surface, and one pole plate of the mim capacitor structure is extended to It is physically contacted with the metal connecting line layer of front wafer surface, another pole plate ground connection, on the one hand without setting pin configuration can be real in addition The line of existing MIM capacitor and control, on the other hand realize radiating by special mim structure, without setting thermal column in addition, Simplify structure.
3. preparation method is simple, suitable for production application.
Brief description of the drawings
Fig. 1 is the structural representation that a kind of compound semiconductor carries on the back gold capacitor.
Fig. 2 is the process chart that a kind of compound semiconductor carries on the back gold capacitor preparation method, wherein being followed successively by respectively by a to u Structural representation obtained by step.
Embodiment
The present invention is described in further detail below in conjunction with drawings and Examples.The present invention each accompanying drawing be only signal with The present invention is easier to understand, its specific ratio can be adjusted according to design requirement.Opposed member in figure described in text Upper and lower relation, for those skilled in the art will be understood that and refer to the relative position of component, therefore can all overturn and be in Existing identical component, this should all belong to the scope disclosed by this specification together.In addition, the number of the element and structure shown in figure, It is merely illustrative, number is not limited with this, can be actually adjusted according to design requirement.
With reference to Fig. 1, a kind of compound semiconductor carries on the back the structure of gold capacitor, including chip 1 and is arranged at the back side of chip 1 MIM capacitor 2.Chip 1 has completed front processing procedure, including compound semiconductor substrate 11, and the front of substrate 11, which makes, has realization pre- If some components of integrated circuit function and be laid with for carry out component line, lead metal connecting line layer 12.Substrate 11 material is III-V compound, such as GaAs.Substrate 11 has the radiating connector 13 through front and back, described Radiating connector 13 exposes the metal connecting line layer 12, the formation one side of radiating connector 13 is open, the one side relative with opening For the groove-like structure on 12 surface of metal connecting line layer.
The MIM capacitor 2 includes first electrode plate 21, dielectric layer 22 and second electrode plate 23, first electrode plate 21, medium Layer 22 and second electrode plate 23 are stacked gradually and connected respectively along the radiating connector 13 inwall extension with covering the radiating The bottom surface and side of mouth 13 simultaneously extend to the back side for covering substrate 11 described in radiating connector 13 periphery, wherein first electrode Plate 21 is physically contacted in the radiating connector bottom surface with metal connecting line layer 12, and second electrode plate 23 is grounded.MIM capacitor 2 Among embedded substrate 11, extend to form structure of the overall middle part to radiating connector sunken inside along the radiating inwall of connector 13, its The surface area of two battery lead plates except include covering radiating the bottom surface of connector 13 and the back side of peripheral foot section 11 area, in addition to The area of covering radiating connector 13 side, so as in the case where taking identical chips external area, increase battery lead plate Surface area, so as to add capacitance.Because the depth for the connector 13 that radiates is equal to the thickness of substrate 11, and substrate 11 generally has There is larger thickness, thus the incrementss of its capacitance are larger.In subsequent encapsulating structure, the second electrode plate 23 is in encapsulation It is connected to be grounded with package support in structure.And first electrode plate 21 is in the radiating bottom surface of connector 13 and the metal Connecting line layer 12 is physically contacted, during work, applies voltage to first electrode plate 21 by metal connecting line layer 12, without setting in addition Electrode connecting line road is put, overall structure is simplified.
The first electrode plate 21 includes the first barrier metal layer 211 and the first conductive metal layer 212 stacked gradually, its In the thickness of the first barrier metal layer 211 be 20-100nm, the thickness of the first conductive metal layer 212 is 400-1600nm.Second The structure of battery lead plate 23 and first electrode plate 21 are identical, also including the second barrier metal layer 231 and the second conductive metal layer 232.Its In the first conductive metal layer 212 and the second conductive metal layer 232 respectively from conductive, the metal of good heat conductivity, such as your gold Category, the first barrier metal layer 211 and the one side of the second barrier metal layer 231 are used to stop noble metal to compound semiconductor substrate With dielectric layer diffusion;On the other hand play a part of adhesion, improve noble metal and compound semiconductor substrate and dielectric layer Binding ability, it is to avoid peel off.In addition, barrier metal layer also needs preferable heat conductivility.It is preferred that, barrier metal layer is TiW, conductive metal layer is Au.The thickness of dielectric layer is 50-200nm, is preferably the SiN of good heat conductivity from dielectric material.
Substrate described in the first electrode plate 21, second electrode plate 23 and dielectric layer 22 to radiating connector 13 periphery The back side extension length it is incremented by successively.It is preferred that, whole back sides of the covering first electrode of dielectric layer 22 plate 21 and substrate, the Two battery lead plates 23 are on dielectric layer 22, and coverage covers and including first electrode plate 21.First electrode plate 21 is covered It is physically contacted to the back side of the radiating peripheral foot section of connector 13 and with the metal connecting line layer 12 of substrate front surface, substrate front surface component The heat of generation can be conducted to backside of substrate by first electrode plate 21, serve the effect of radiating.The electricity of dielectric layer 22 and second Pole plate 23 further increases radiating effect, i.e. MIM capacitor 2 while playing the work of radiating from the big material of thermal conductivity factor With, without in addition set thermal column, simplify structure.In addition, dielectric layer 22 covers whole back sides of substrate, it is electric except MIM is used as Outside the dielectric layer of appearance, the effect at protection group bottom 11 is also acted, is reduced in actual process for making for first electrode The damage of plate, improves the reliability of electric capacity.The length of the basad back side of second electrode plate 23 extension is more than first electrode plate 21, increases Greatly with the contact surface of bottom package support, be conducive to current lead-through and radiating.By the setting of said structure, with first electrode plate Area control the effective area of electric capacity, reduce parameter, be easy to structure design and analysis.
The preparation method for carrying on the back gold capacitor with reference to Fig. 2, above-claimed cpd semiconductor, comprises the following steps:
1. refer to Fig. 2 a, III-V chip complete front processing procedure, the chip include compound semiconductor substrate GaAs with And located at the positive metal connecting line layer M1 of the substrate GaAs.
2. referring to Fig. 2 b, chip wax Wax is fitted in the way of facing down on sapphire wafer Sapphire.
3. referring to Fig. 2 c, after grinding is thinned, coating radiating connector etching needs the photoresistance PR of mask.
4. referring to Fig. 2 d, by exposure imaging, connector figure is prepared.
5. referring to Fig. 2 e, the radiating connector of substrate GaAs front and backs is run through with dry etching formation.
6. referring to Fig. 2 f, photoresistance PR is removed with chemical agents such as 1-METHYLPYRROLIDONEs.
7. refer to Fig. 2 g, in wafer surface physical vapour deposition (PVD) double layer of metal, TiW and Au.TiW be used as adhesion and Barrier layer, thickness is in 200A to 1000A.Au is used as plating seed, and thickness is in 1000A to 6000A.
8. referring to Fig. 2 h, layer of Au is prepared in wafer surface with plating mode, thickness is in 3000A to 10000A.
9. Fig. 2 i are referred to, it is exposed and developed to prepare photoresistance pattern in wafer surface by coating, to prepare the first of electric capacity Battery lead plate.
10. referring to Fig. 2 j, with the mode of inverse plating, the exposed Au outside photoresistance is etched.
11. referring to Fig. 2 k, with the mode of dry etching, the exposed TiW outside photoresistance is etched.
12. referring to Fig. 2 l, photoresistance is removed with chemical agents such as 1-METHYLPYRROLIDONEs.
13. referring to Fig. 2 m, the dielectric materials such as layer of sin are deposited with PECVD mode in wafer surface is situated between as electric capacity electricity Matter.Thickness is in 500A to 2000A.
14. refer to Fig. 2 n, in wafer surface physical vapour deposition (PVD) double layer of metal, TiW and Au.TiW is used as adhesion And barrier layer, thickness is in 200A to 1000A.Au is used as plating seed, and thickness is in 1000A to 6000A.
15. referring to Fig. 2 o, layer of Au is prepared in wafer surface with plating mode, thickness is in 3000A to 10000A.
16. Fig. 2 p are referred to, it is exposed and developed to prepare photoresistance pattern in wafer surface by coating.To prepare the of electric capacity Two battery lead plates.The photoresistance pattern coverage of this step is less than the photoresistance pattern of step 9, so that obtained second electrode plate is more than First electrode plate.
17. referring to Fig. 2 q, with the mode of inverse plating, the exposed Au outside photoresistance is etched.
18. referring to Fig. 2 r, with the mode of dry etching, the exposed TiW outside photoresistance is etched.
19. referring to Fig. 2 s, photoresistance is removed with chemical agents such as 1-METHYLPYRROLIDONEs.
20. referring to Fig. 2 t, after chip turn-over, sapphire is peeled off.
21. referring to Fig. 2 u, the object construction of the present invention is just formed after cleaning.The Au of bottom and support shape in encapsulating structure Into connection, one end as capacity earth.
Above-described embodiment only be used for further illustrate the present invention a kind of compound semiconductor the back of the body gold capacitor structure and its Preparation method, but the invention is not limited in embodiment, what every technical spirit according to the present invention was made to above example Any simple modification, equivalent variations and modification, each fall within the protection domain of technical solution of the present invention.

Claims (10)

1. a kind of compound semiconductor carries on the back the structure of gold capacitor, it is characterised in that:Including chip and it is arranged at chip back surface MIM capacitor;
The chip includes compound semiconductor substrate and the metal connecting line layer located at the substrate front surface, and the substrate has Through the radiating connector of front and back, the radiating connector exposes the metal connecting line layer;
The MIM capacitor includes first electrode plate, dielectric layer and second electrode plate, first electrode plate, dielectric layer and second electrode Plate stacks gradually and extends the bottom surface and side to cover the radiating connector along the radiating connector inwall respectively and prolong Extend the back side for covering substrate described in the radiating connector periphery, wherein first electrode plate in the radiating connector bottom surface with The metal connecting line layer physical contact, second electrode plate earthing.
2. compound semiconductor according to claim 1 carries on the back the structure of gold capacitor, it is characterised in that:The first electrode plate Include the barrier metal layer and conductive metal layer stacked gradually respectively with second electrode plate, the thickness of wherein barrier metal layer is 20-100nm, the thickness of conductive metal layer is 400-1600nm.
3. compound semiconductor according to claim 2 carries on the back the structure of gold capacitor, it is characterised in that:The barrier metal layer For TiW, conductive metal layer is Au.
4. compound semiconductor according to claim 1 or 2 carries on the back the structure of gold capacitor, it is characterised in that:The dielectric layer Thickness be 50-200nm.
5. compound semiconductor according to claim 1 carries on the back the structure of gold capacitor, it is characterised in that:The dielectric layer is SiN。
6. compound semiconductor according to claim 1 carries on the back the structure of gold capacitor, it is characterised in that:The first electrode The length of the back side extension of substrate is incremented by successively described in plate, second electrode plate and dielectric layer to the radiating connector periphery.
7. compound semiconductor according to claim 1 carries on the back the structure of gold capacitor, it is characterised in that:The second electrode plate It is connected to be grounded with package support in encapsulating structure.
8. the preparation method that a kind of any one of claim 1-7 compound semiconductors carry on the back gold capacitor, it is characterised in that including Following steps:
1) chip for completing front processing procedure is provided, the chip includes compound semiconductor substrate and located at the substrate front surface Metal connecting line layer;
2) the chip wax is fitted on substrate in the way of facing down;
3) grind after being thinned, it is described by photoetching process in forming the radiating connector through front and back in the substrate The connector that radiates exposes the metal connecting line layer surface;
4) it is sequentially depositing the substrate back of the body to form the bottom surface and side that cover the radiating connector and cover radiating connector periphery First electrode plate, dielectric layer and the second electrode plate in face, to form mim capacitor structure;
5) by after chip turn-over, peeling liner bottom is simultaneously cleaned;
6) second electrode plate earthing.
9. preparation method according to claim 8, it is characterised in that step 4) include following sub-step:
A) deposition covers bottom surface and side and the first barrier metal layer for covering backside of substrate of the radiating connector, and thickness is 20-100nm;
B) the first conductive metal layer of the first barrier metal layer of deposition covering, thickness is 400-1600nm;
C) the first barrier metal layer and the first conductive metal layer of the backside of substrate outside the first predeterminable area are removed, it is remaining First barrier metal layer and the first conductive metal layer form the first electrode plate, wherein first predeterminable area is including described The back side for the substrate described in connector and its periphery that radiates;
D) deposition forms the dielectric layer of covering first electrode plate and backside of substrate, and thickness is 50-200nm;
E) the second barrier metal layer of blanket dielectric layer is deposited, thickness is 20-100nm;
F) the second conductive metal layer of the second barrier metal layer of deposition covering, thickness is 400-1600nm;
G) the second barrier metal layer and the second conductive metal layer of the backside of substrate outside the second predeterminable area are removed, it is remaining Second barrier metal layer and the second conductive metal layer form the second electrode plate, wherein second predeterminable area is covered and big In first predeterminable area.
10. preparation method according to claim 9, it is characterised in that:First conductive metal layer and/or the second conduction Metal level is to first pass through physical vapour deposition (PVD) 100-600nm metal level as plating seed, then electroplates 300-1000nm's Metal level is made.
CN201710390074.4A 2017-05-27 2017-05-27 A kind of structure of compound semiconductor back of the body gold capacitor and preparation method thereof Pending CN107275315A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201710390074.4A CN107275315A (en) 2017-05-27 2017-05-27 A kind of structure of compound semiconductor back of the body gold capacitor and preparation method thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710390074.4A CN107275315A (en) 2017-05-27 2017-05-27 A kind of structure of compound semiconductor back of the body gold capacitor and preparation method thereof
PCT/CN2018/086007 WO2018219101A1 (en) 2017-05-27 2018-05-08 Back metal capacitor structure of compound semiconductor and manufacturing method therefor

Publications (1)

Publication Number Publication Date
CN107275315A true CN107275315A (en) 2017-10-20

Family

ID=60065307

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710390074.4A Pending CN107275315A (en) 2017-05-27 2017-05-27 A kind of structure of compound semiconductor back of the body gold capacitor and preparation method thereof

Country Status (2)

Country Link
CN (1) CN107275315A (en)
WO (1) WO2018219101A1 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018219101A1 (en) * 2017-05-27 2018-12-06 厦门市三安集成电路有限公司 Back metal capacitor structure of compound semiconductor and manufacturing method therefor
CN109920757A (en) * 2019-01-31 2019-06-21 厦门市三安集成电路有限公司 A kind of dorsal segment technique improving compound semiconductor device unfailing performance
CN110752207A (en) * 2019-09-10 2020-02-04 福建省福联集成电路有限公司 Back capacitor structure and manufacturing method
TWI720936B (en) * 2019-10-31 2021-03-01 大陸商廈門市三安集成電路有限公司 Compound semiconductor element and its back copper manufacturing process method
CN112466852A (en) * 2021-01-28 2021-03-09 成都市克莱微波科技有限公司 Manufacturing method of bypass capacitor and bypass capacitor

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0888320A (en) * 1994-09-19 1996-04-02 Mitsubishi Electric Corp Semiconductor device and its manufacture
JPH08236698A (en) * 1995-02-27 1996-09-13 Nec Eng Ltd Semiconductor device
CN104115270A (en) * 2011-12-14 2014-10-22 英特尔公司 Metal-insulator-metal (MIM) capacitor with insulator stack having a plurality of metal oxide layers

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102456749A (en) * 2010-10-20 2012-05-16 中芯国际集成电路制造(上海)有限公司 Metal-insulator-metal (MIM) capacitor structure and manufacturing method thereof
CN102446915B (en) * 2011-09-08 2013-09-11 上海华力微电子有限公司 Novel metal-insulator-metal (MIM) capacitor structure and manufacturing method thereof
KR20140097428A (en) * 2011-12-21 2014-08-06 인텔 코오퍼레이션 Fully encapsulated conductive lines
CN107275315A (en) * 2017-05-27 2017-10-20 厦门市三安集成电路有限公司 A kind of structure of compound semiconductor back of the body gold capacitor and preparation method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0888320A (en) * 1994-09-19 1996-04-02 Mitsubishi Electric Corp Semiconductor device and its manufacture
JPH08236698A (en) * 1995-02-27 1996-09-13 Nec Eng Ltd Semiconductor device
CN104115270A (en) * 2011-12-14 2014-10-22 英特尔公司 Metal-insulator-metal (MIM) capacitor with insulator stack having a plurality of metal oxide layers

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
潘桂忠: "《MOS集成电路工艺与制造技术》", 30 June 2012, 上海科学技术出版社 *
胡耀志 等: "《机电产品微细加工技术与工艺》", 28 February 1993, 广东科技出版社 *

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018219101A1 (en) * 2017-05-27 2018-12-06 厦门市三安集成电路有限公司 Back metal capacitor structure of compound semiconductor and manufacturing method therefor
CN109920757A (en) * 2019-01-31 2019-06-21 厦门市三安集成电路有限公司 A kind of dorsal segment technique improving compound semiconductor device unfailing performance
CN109920757B (en) * 2019-01-31 2020-08-25 厦门市三安集成电路有限公司 Back section process for improving reliability of compound semiconductor device
CN110752207A (en) * 2019-09-10 2020-02-04 福建省福联集成电路有限公司 Back capacitor structure and manufacturing method
TWI720936B (en) * 2019-10-31 2021-03-01 大陸商廈門市三安集成電路有限公司 Compound semiconductor element and its back copper manufacturing process method
CN112466852A (en) * 2021-01-28 2021-03-09 成都市克莱微波科技有限公司 Manufacturing method of bypass capacitor and bypass capacitor

Also Published As

Publication number Publication date
WO2018219101A1 (en) 2018-12-06

Similar Documents

Publication Publication Date Title
CN107275315A (en) A kind of structure of compound semiconductor back of the body gold capacitor and preparation method thereof
CN102479771B (en) Semiconductor device and manufacture method thereof and semiconductor package part
CN103681367B (en) Method for packing and packaging
JP2902988B2 (en) Electronic module and method of forming the same
JP5578447B2 (en) Die stacking with annular vias with concave sockets
CN103824836B (en) Quasiconductor load-carrying unit and semiconductor package part
TWI264253B (en) Method for fabricating conductive connection structure of circuit board
CN109003938A (en) Semiconductor contact structure, memory construction and preparation method thereof
JP2008016855A (en) Semiconductor device with laminated chip and method for manufacturing it
TW200531246A (en) Semiconductor package
CN102637713B (en) Method for packaging image sensor comprising metal micro-bumps
CN109801896A (en) High desnity metal-insulator-metal capacitor
CN105990263A (en) MIM capacitor and method forming the same
CN111312697A (en) Three-dimensional stacking integrated structure, multi-chip integrated structure and preparation method thereof
CN106169428A (en) For slowing down chip-packaging structure and the method for packing of electromagnetic interference
JP4138232B2 (en) Dual etched bond pad structure for reducing stress and allowing circuitry to be placed under the pad and method for forming the same
CN108109985A (en) Multichip stacking encapsulation method and packaging body
CN111293090A (en) Connection structure and forming method thereof
CN104867923B (en) Self-supplied electronic device architecture and preparation method thereof
CN108336019A (en) The method and wafer level packaging structure of conductive plunger are formed in a kind of wafer-level packaging
CN102437135A (en) Wafer-level columnar bump packaging structure
CN206076221U (en) For slowing down the chip-packaging structure of electromagnetic interference
KR101774234B1 (en) Method for fabricating of semiconductor device
TWI565025B (en) Semiconductor package and manufacturing method thereof
CN106206634A (en) A kind of image sensor architecture and preparation method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20171020

WD01 Invention patent application deemed withdrawn after publication