JP3327571B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a high withstand voltage and a high speed operation, such as a semiconductor rectifier, a bipolar transistor and an electrostatic induction transistor.

[0002]

2. Description of the Related Art As is well known, developments have been made to improve the characteristics of semiconductor devices such as rectifiers, and particularly to improve the switching speed, forward and reverse characteristics, and various semiconductor devices have been proposed.

FIG. 19 shows a structure of a rectifier using a normal PN junction. 1 is a metal electrode forming an ohmic junction, 2
Is P ⁺ − Type semiconductor layer, 3 is an N− type semiconductor layer, 4 is N ⁺ −
Reference numeral 5 denotes an ohmic metal electrode, A denotes an anode, and C denotes a cathode.

In general, the forward characteristics of the indicated such rectifier 19 V _F -J _F 6 - As the (forward voltage drop forward current) characteristic diagram of (a), and the reverse characteristic FIG.
A characteristic curve as shown in (a) of the V _R -J _R (reverse voltage-reverse leakage current) characteristic diagram of FIG.

On the other hand, when the applied voltage is switched from the forward direction to the reverse direction, the PN junction is completely restored to the reverse characteristic due to the existence of the holes having a low moving speed injected into the N− type semiconductor layer 3 in large quantities. It takes a long time, for example, several hundred nsec or more as a time (reverse recovery time trr) until it is not suitable for use in a high-speed circuit. In order to eliminate such disadvantages,
Conventionally, various structures have been proposed. For example, FIG.
By diffusing heavy metals such as gold and platinum into the rectifier,
It is common practice to promote the annihilation of minority carriers (holes).

In such a structure using heavy metal diffusion, t
Although rr can be reduced to about 1/10, the reverse leakage current and the forward voltage drop are larger than those of a normal PN junction rectifier, and the loss increases.

Further, although the rectifier using a Schottky barrier junction has been proposed as a rectifier for the purpose of speeding the forward, the V _F -J _F characteristic diagram of FIG. 6 such characteristics of (b) shows, for the reverse direction, showing a such characteristic of (b) of the V _R -J _R characteristic diagram of FIG. That is,
Although the switching speed and the forward voltage drop are improved as compared with the ordinary PN junction rectifier, the reverse leakage current and the withstand voltage are improved as is apparent from the comparison between FIGS. 7A and 7B. Can not.

In order to improve the above-mentioned disadvantages of the Schottky barrier type junction, Japanese Patent Publication No. 59-35183 and Japanese Patent Application Laid-Open No.
Although 4582 has been proposed, it is not sufficient in providing requirements for suppressing reverse leakage current and for speeding up.

[0009]

SUMMARY OF THE INVENTION An object of the present invention is to solve the problems of the conventional PN junction type and Schottky barrier junction type semiconductor devices and to provide a new semiconductor device having a high breakdown voltage and a high speed. Another object of the present invention is to provide a semiconductor device with small forward voltage drop and reverse leakage current. Another object of the present invention is to provide a semiconductor device having a short reverse recovery time.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. 1 and 2 show a unit cell of a rectifier according to a first embodiment of the present invention, and FIG. 3 shows a rectifier including a plurality of unit cells. Note that the same reference numerals as those in FIG. 19 indicate the same parts.

In FIGS. 1 and 2, the unit cell of the rectifier is N ⁺ And a semiconductor substrate having a semiconductor layer 4 and an N-type semiconductor layer 3. The N − type semiconductor layer 3 has a P ⁺ having a depth D. -Type semiconductor layer 2 is provided to form a PN junction. The N- electrode exposed by providing the metal electrode 1 on the substrate surface
A contact surface e is formed with the surface of the mold semiconductor layer 3. P ⁺ The depth D of the-type semiconductor layer 2 is given by the distance from the contact surface e. Further, the contact surface e, that is, N exposed on the substrate surface
Immediately below the − type semiconductor layer 3, P ⁺ The closest distance between the opposing portions of the -type semiconductor layer 2 or the PN junction is given by W. In this case, P ⁺ Since the above-mentioned portion of the − type semiconductor layer 2 exists outside the contact surface e, in other words, does not exist inside the contact surface e, the closest distance W exposes the N − type semiconductor layer 3 on the substrate surface. Substantially given by the width. N ⁺ -Type semiconductor layer 4
Is provided with an ohmic metal electrode 5. As is clear from FIG. 3, the N− type semiconductor layer 3 exposed on the substrate surface is a square having a width (nearest distance) W.

No voltage is applied between the anode A and the cathode C of such a rectifier, that is, the depletion layer 6 at zero bias extends into the N- type semiconductor layer 3 having a low impurity concentration. Its width is given by Wbi.

FIG. 1 shows that the relationship between the width W of the N− type semiconductor layer 3 exposed on the substrate surface and the width Wbi of the depletion layer 6 is W <2W.
2 shows the structure given by bi, and FIG.
2 shows a structure provided by 2Wbi. An important requirement in the structures of FIGS. 1 and 2 is that P ⁺ The relationship between the depth D of the type semiconductor 2 and the closest distance W is set to D ≧ 0.5 W.

Since the depth D is given by the distance from the contact surface e, for example, the portion of the contact surface e is P ⁺ In the case of a structure protruding from the surface of the − type semiconductor layer 2, the depth is from the protruding contact surface, and when the closest distance W is below the contact surface e (inside the N− type semiconductor layer 3). Is the distance at that location.

As shown in FIG. 3, the N-type semiconductor layer 3 exposed on the substrate surface is a square having a width (nearest distance) W, but as shown in FIG. 4, it is exposed on the substrate surface. The N− type semiconductor layer 3 may be formed in a stripe shape having a width (closest distance) W. FIG. 5 is a sectional view thereof.

The rectifier shown in FIG. 1 is formed, for example, as follows. N ⁺ having a specific resistance of 0.010 Ω-cm -Type semiconductor layer 4 and grown on the semiconductor layer by an epitaxial growth technique, having a specific resistance of 5 Ω-cm and a thickness of 14 μm.
A semiconductor substrate having the N− type semiconductor layer 3 is prepared.
Next, a P- type impurity is selectively introduced into the N- type semiconductor layer 3 so that the N- type semiconductor layer 3 exposed on the substrate surface has a thickness of 2 μm.
P ⁺ having a depth D of 3 μm so as to form a square having a width (nearest distance) W of -Type semiconductor layer 2 is formed. N-type semiconductor layer 3 exposed by providing Ti electrode 1 on the substrate surface
And a contact surface e. In this case, a Schottky barrier junction is formed between the metal electrode 1 and the N− type semiconductor layer 3, and the metal electrode 1 and the P ⁺ An ohmic junction is formed with the negative type semiconductor layer 2. Instead of Ti, Mo, W,
Cr, Al or the like may be used. N ⁺ The − type semiconductor layer 4 contains 10 ²¹ Atoms / cm ^{3 of} phosphorus. After that, the ohmic metal electrode 5 is provided by Cr. Thereafter, the semiconductor substrate is divided into chips of 1.6 × 1.6 mm to obtain a rectifier.

In such a rectifier, the width Wbi of the depletion layer 6 at the time of zero bias is given by 1.05 μm.
Note that the width Wbi of the depletion layer 6 varies depending on the manufacturing of the specific resistance of the N− type semiconductor layer 3 or P ⁺ −
It varies in the range of 1 to 1.5 μm depending on the formation conditions of the mold semiconductor layer 2 and the like.

In the first embodiment, the N-type semiconductor layer 3
Schottky barrier junction between P ⁺ and metal electrode 1, P ⁺ Although an ohmic junction was made between the − type semiconductor layer 2 and the metal electrode 1, P ⁺ By changing the impurity concentration of the − type semiconductor layer 2 or the N − type semiconductor layer 3, a Schottky barrier junction is formed between 3-1 and 2-1 and an ohmic junction is formed between 3-1 and 2-1. Ohmic junction between 3-1 and 2-1
The gap between −1 can be formed by a Schottky barrier junction.

[0019] Figure 6 is a V _F -J _F characteristic diagram showing the forward characteristics of the rectifier having a junction combined variously,
Figure 7 is a V _R -J _R characteristic diagram showing the reverse characteristics thereof.

That is, in FIGS. 6 and 7, the forward characteristic and the reverse characteristic by the structure of the present invention are (c)
This is shown by the curves (d), (e) and (f), respectively. The curves (c) to (f) show the following N− type semiconductor layer 3 or P ⁺ 2 shows a combination of the junction between the − type semiconductor layer 2 and the metal electrode 1. Curve (c): ohmic contact between 3-1 and 2
Curve (d): ohmic contact between 3-1 and 2
Curve (e): Schottky barrier junction between 3-1 and 2
Ohmic contact between -1 Curve (f): Schottky barrier junction between 3-1 and 2
As described above, the curve (a) shows the characteristics of the rectifier using the PN junction, and the curve (b) shows the characteristics of the rectifier using the Schottky barrier junction.

As is apparent from these characteristics,
(C), (d), (e) and the Do J _F region small in the forward characteristics in rectifier having a structure (f), a conventional Schottky barrier rectifier characteristic (b) the PN junction rectifier characteristics ( becomes V _F value between a), reverse characteristics are understood to be a same characteristics and properties of the PN junction rectifier (a). 8 and 9 show the relationship between the width (nearest distance) W of the N− type semiconductor layer 3 exposed on the substrate surface and the width W _bi of the depletion layer at zero bias.

That is, FIG. 8 shows a W-J _R (nearest distance-reverse leakage current) characteristic diagram, and FIG. 9 shows a W-V _F (nearest distance-forward voltage drop) characteristic diagram. These are D = 0.1W and D = 0.0 out of the scope of the present invention in the relationship between D and W.
The 5 W curve is also shown.

In the W-J _R characteristic shown in FIG. 8, it can be seen that those having a structure of D = 0.05 W or D = 0.1 W outside the range of the present invention have a remarkably large reverse leakage current J _R.
It is apparent that the reverse leakage current _JR becomes extremely small when D ≧ 0.5 W in the range of W <3 W _bi . Further, FIG.
0 shows a W-trr (closest distance-reverse recovery time) characteristic diagram of the rectifier of the present invention.

FIG. 10 shows that D =
The value of W is shown. The solid line shows the case where the area between 2-1 is ohmic. Although trr is slightly increased as compared with the single junction Schottky barrier junction rectifier, it is practically equivalent.

In FIG. 10, a broken line indicates a case where a Schottky barrier is formed between 2-1 and a characteristic with extremely small trr is obtained. That is, when a forward bias is applied between the anode A and the cathode C, the Schottky barrier junction between 2-1 is reverse-biased and P ⁺ The forward bias voltage is hardly applied to the N junction. Therefore P ⁺ Although almost no holes are injected from the − type semiconductor layer 2 into the N − type semiconductor layer 3, as a result, the forward characteristics have characteristics of high series resistance shown in FIGS. 6 (d) and 6 (f). 10, high-speed switching characteristics can be obtained as shown by the broken line in FIG.

As described above, even if the structure satisfies the important requirement of the present invention, D ≧ 0.5 W, FIG.
As shown in FIGS. 9 and 10, their characteristics are W and W
It turns out that it is influenced by the relation of _bi . That is, W ≦ 3W
By satisfying the condition of _bi or W ≧ W _bi , the rectifier of the present invention exhibits more excellent characteristics. Next, a rectifier according to a second embodiment of the present invention will be described. 11 to 14 are similar to the first embodiment of the present invention.
Fig. 4 shows a unit cell of the rectifier, and its plan view is the same as Figs.

In this embodiment, in addition to D ≧ 0.5 W in the first embodiment, the angle formed between the contact surface e or the surface of the N− type semiconductor layer 3 and the tangent s passing through the point f on the PN junction. θ is set to 60 ° ≦ θ ≦ 120 °. In this case, the point f on the PN junction passes through the top of the depletion layer 6 at zero bias and the contact surface e or the exposed N−
It is given at the intersection with the straight line g extending parallel to the surface of the type semiconductor layer 3.

FIG. 11 shows the N− type semiconductor layer 3 and the metal electrode 1.
Contact surface e between P ⁺ FIG. 3 shows a unit cell of a rectifier having a structure more protruding than a contact surface between a negative type semiconductor layer 2 and an electrode metal 1, wherein an angle θ between a contact surface e and a tangent s passing through a point f on a PN junction is an acute angle. For example, 60 °, and the range is 60 ° ≦ θ <90 °. In this case, unlike the first embodiment shown in FIGS. 1 and 2, P ⁺ Since the opposing portions of the − type semiconductor layer 2 exist inside the contact surface e, the closest distance W is P ⁺ -Type semiconductor layer 2 is given by the distance between the above-mentioned portions or PN junctions facing each other. Also, P ⁺ Since the depth D of the − type semiconductor layer 2 is a depth from the contact surface e, it is equal to the protruding contact surface e and P ⁺ −type semiconductor layer 2.

FIG. 11, FIG. 12, FIG. 13 and FIG.
14 shows a unit cell of a rectifier in which the angle θ is changed in a range of 60 ° ≦ θ ≦ 120 °, and the angle θ is sequentially increased, and in FIG. 14, the angle θ is 120 °. In this case, P ⁺
Although the depth D of the − type semiconductor layer 2 is a depth from the contact surface e, the closest distance W is substantially given by the width of the N − type semiconductor layer 3 exposed on the substrate surface.

Further, the rectifier in the second embodiment is the first rectifier.
It is manufactured in the same manner as in the embodiment. Also, their V _F -J _F
Forward characteristics and V _R -J _R reverse characteristics are the same as FIGS. 6 and 7 in the first embodiment. FIG. 15 shows θ-J
_{An R} (angle-reverse leakage current) characteristic diagram is shown.

As apparent from FIG. 15, in order to exhibit the characteristics as shown in FIGS. 7 (c), (d), (e) and (f), the range is 60 ° ≦ θ ≦ 120 °. There is a need. That is, when θ is smaller than 60 °, and 12
If it exceeds 0 °, the reverse leakage current J _R increases even if the condition of D ≧ 0.5 W is satisfied, and the object of the present invention cannot be achieved. FIG. 15 shows a curve in the case where D = W, when 3-1 is formed by a Schottky barrier junction and 2-1 is formed by a Schottky barrier junction or an ohmic junction. Here, the sample in which θ was changed was prepared by one or a combination of a heat diffusion condition from a boron source, a polishing from a surface, and an ion implantation technique. Further, as shown in FIG. 15, the relationship between the closest distance W and the width W _bi of the depletion layer at zero bias is shown as a parameter.

FIG. 16 shows V _R -E _J with D as a parameter.
A (reverse voltage-electric field strength) characteristic diagram is shown. Here, E _J is the electric field strength across the junction (contact surface e) between 3-1.

As is apparent from FIG. 16, it is understood that the electric field intensity E _J saturates at a small value in the range of D ≧ 0.5 W which is the above condition. It is clear from a generally known theoretical formula that when E _J is saturated with a small value, the reverse leakage current J _R also becomes a small current value having no voltage dependency. When D = 0.05 W or D = 0.1 W which is out of the range of the above conditions, E _J has a large voltage-dependent value. Regarding the reverse recovery time trr, FIG.
This is the same as the W-trr (closest distance-reverse recovery time) characteristic diagram of FIG.

As described above, even if the two conditions of 60 ° ≦ θ ≦ 120 ° and D ≧ 0.5 W are satisfied in the second embodiment, as shown in FIGS. Is affected by the relationship between W and W _bi . That is, by satisfying the condition of W ≦ 3W _bi or W ≧ W _bi , the semiconductor rectifier of the present invention exhibits more excellent characteristics.

As is clear from the second embodiment,
The present inventor has proposed that P ⁺ -Type semiconductor layer 2 and metal electrode 1 are in ohmic contact with minority carrier injection,
D ≧ 0.5W, W _bi ≦ W ≦ 3W _bi and 60 ° ≦ θ ≦ 1
In the structure satisfying the condition of 20 °, the metal electrode 1 and N
It has been found that, regardless of whether the contact with the negative type semiconductor layer 3 is Schottky contact or ohmic contact, a remarkably peculiar phenomenon occurs in the reverse recovery characteristic.

That is, the minority carriers (holes) excessively injected into the N − -type semiconductor layer 3 during the very short time of the initial few nanoseconds at the time of the reverse current flow become P-type in the direction of the metal electrode 1. ⁺ And the majority carriers (electrons) in the N− type semiconductor layer 3 are simultaneously converted into the excess minority carriers (electrons).
2) flows in the metal electrode 1 in the opposite direction to the potential direction, and the holes and electrons are recombined and disappear in the metal electrode 1. The flow of these carriers for a very short time is not observed at the external electrode. After that, the remaining minority carriers are P ⁺ −
Spontaneously disappears in the N − type semiconductor layer 3 below the type semiconductor layer 2. Therefore, extremely excellent trr characteristics can be obtained. FIG. 17 shows a third embodiment of the present invention, and shows a structure in which the present invention is applied to an emitter of a bipolar transistor, for example, a diffusion type PNP transistor.

That is, this bipolar transistor has a P
⁺ A collector region formed of a negative-type semiconductor layer 122, a base region formed of an N- type semiconductor layer 123, and a plurality of P ⁺ formed in the base region. An emitter region formed of a negative type semiconductor layer 125, a collector electrode 121 provided in the collector region, a base electrode 126 provided in the base region through an opening of the insulating film 124, and an exposed base. And an emitter electrode 127 formed in the base region and the emitter region to form a Schottky barrier junction with the base region. In this case, as in the first and second embodiments, the P ⁺ The depth of the type semiconductor layer 125,
The width of the base region exposed on the surface, the contact surface e or the surface of the base region and P ⁺ The angle (not shown) between the tangent s passing through the point f on the N junction and the tangent s is given by D, W and θ, respectively, and D ≧ 0.5W, W _bi ≦ W ≦ 3W _bi and / or It has a condition of 60 ° ≦ θ ≦ 120 °.

P ⁺ having a normal emitter structure NP ⁺ In the type transistor, the minority carriers injected from the emitter region are accumulated in the base region, and the switching time t
_{Although the OFF} cannot be reduced, in the bipolar transistor having the above-described emitter structure, the minority carrier holes accumulated in the base region escape from the emitter region to the emitter electrode 127 at the beginning of the turn-off period. At the same time, majority carrier electrons in the base region are
Reaching the 27 side at a high speed of several nanoseconds, the same amount of holes and electrons recombine in the emitter electrode, and the switching time t _OFF can be extremely shortened. In addition, since a large amount of majority carriers flow into the base region from the Schottky junction,
Compared with the conventional structure, the base resistance is strongly modulated to reduce the resistance. As a result, the saturation characteristics and h _FE of V _CE are significantly improved.

For example, an emitter electrode 127 is formed of Ti using an N-type semiconductor layer 123 having a specific resistance of 5 Ω-cm, and an exposed base region (N-type semiconductor layer 123) is formed.
And a Schottky barrier junction between them and W = 2μ
When m, D = 3 μm and θ = 95 °, the following good results were obtained.

[0040] FIG. 18 shows a fourth embodiment of the present invention, and shows a structure in which the present invention is applied to a gate portion of a static induction transistor (SIT).

This static induction transistor has a metal electrode 1
N ⁺ with 31 A plurality of P ⁺ layers formed in the channel region with the drain region including the − type semiconductor layer 132, the channel region including the N − type semiconductor layer 133, and the insulating film 134. − Type semiconductor layer 135 and exposed channel region and P ⁺ - a isolation portion,該Ge - - gate consisting of gate electrode 136. - -type semiconductor layer 135 is formed on, gate to form a Teyan'neru region and the Schottky barrier junction is formed in the channel region adjacent to the isolation portion, N ⁺ − Type semiconductor layer 137
And a source provided in the source region.
Electrode 138. In this case, as in the third embodiment, P ⁺ forming the gate portion is used. -Type semiconductor layer 13
5, the width of the channel region exposed on the surface, the contact surface e or the surface of the channel region and P ⁺ An angle (not shown) formed with a tangent s passing through a point f on the N junction is
D, W and θ, and D ≧ 0.5W, W
_bi ≦ W ≦ 3W _bi and / or 60 ° ≦ θ ≦ 120 °.

In a conventional static induction transistor, a single P
⁺ When the gate made of the-type semiconductor layer is forward biased, minority carriers are injected and accumulated in the channel region of the N-type semiconductor layer, so that the switching time of the electrostatic induction transistor is delayed and the limit as a high frequency compatible device is limited. is there.

On the other hand, in the above-mentioned static induction transistor having the gate structure, the minority carrier holes accumulated in the channel region are turned off at the beginning of the turn-off period.
⁺ -Type semiconductor layer 135 passes through to gate electrode 136, and at the same time, majority carrier electrons in the channel region reach gate electrode 136 having a Schottky barrier junction at a high speed of several nanoseconds to form a gate portion. The same amount of holes and electrons recombine within the metal electrode.

As a result, in the conventional electrostatic induction transistor, the extinction of minority carriers accumulated in the channel region naturally disappears in accordance with the carrier lifetime, whereas in the present invention, the gate contacting the channel region in the present invention. Since the gate electrode has a Schottky barrier junction, a large concentration gradient and an internal electric field gradient are formed in the carrier concentration. Therefore, the minority carriers accumulated in the channel region disappear at a very high speed due to the concentration gradient and the internal electric field gradient. After that, the remaining small amount of minority carriers disappears spontaneously according to the lifetime. Therefore, according to the present invention, a switching time is remarkably improved, and an electrostatic induction transistor having good high-frequency characteristics can be obtained.

For example, using an N-type semiconductor layer 133 having a specific resistance of 100 Ω-cm, a gate electrode 136 is formed of Al, and an exposed channel region (N-type semiconductor layer 1) is formed.
33) and a Schottky barrier junction between
= 5 μm, D = 5 μm, and θ = 95 °, good results were obtained.

[0046]

As described above, the semiconductor device of the present invention can obtain a high withstand voltage and high-speed characteristics, and can be used for various industrial devices including power devices. It can be widely applied as a semiconductor device such as a switch element, and the effect is extremely large.

[Brief description of the drawings]

FIG. 1 shows a rectifier (W <2) according to a first embodiment of the present invention.
It is a sectional view showing a unit cell of W _bi ).

FIG. 2 shows a rectifier (W> 2) according to a first embodiment of the present invention.
It is a sectional view showing a unit cell of W _bi ).

FIG. 3 is a plan view of a rectifier in which a number of unit cells of FIG. 1 or 2 are arranged.

FIG. 4 is a plan view of a rectifier in which a number of unit cells of FIG. 1 or 2 are arranged.

FIG. 5 is a sectional view taken along line XX of FIG. 4;

[6] rectifier V _F -J _F - a (forward voltage drop forward current) characteristic diagram.

[7] rectifier V _R -J _R - a (reverse voltage reverse leakage current) characteristic diagram.

[8] rectifier W-J _R (closest distance - reverse leakage current)
It is a characteristic diagram.

FIG. 9: W-V _{F of the} rectifier (closest distance-forward voltage drop)
It is a characteristic diagram.

FIG. 10 is a W-trr (closest distance-reverse recovery time) characteristic diagram of the rectifier.

FIG. 11 is a sectional view showing a unit cell of a rectifier according to a second embodiment of the present invention.

FIG. 12 is a sectional view showing a unit cell of another rectifier according to a second embodiment of the present invention.

FIG. 13 is a sectional view showing a unit cell of another rectifier according to a second embodiment of the present invention.

FIG. 14 is a sectional view showing a unit cell of still another rectifier according to a second embodiment of the present invention.

FIG. 15 is a characteristic diagram of θ-J _R (angle-reverse leakage current) of the rectifier.

FIG. 16 is a V _R -E _J (reverse voltage-electric field strength) characteristic diagram of the rectifier.

FIG. 17 is a cross-sectional view illustrating a bipolar transistor according to a third embodiment of the present invention.

FIG. 18 is a cross-sectional view illustrating a static induction transistor according to a fourth embodiment of the present invention.

FIG. 19 is a sectional view showing a conventional rectifier.

[Explanation of symbols]

1. Metal electrode 2. P ⁺ Conductive semiconductor layer 3 ... N conductive semiconductor layer 4 ... N ⁺ Conductive semiconductor layer 5 ... ohmic metal electrodes A ... anode C ... cathode W ... closest distance W width V _F of the _bi ... zero bias when the depletion layer 6 ... forward voltage J _F ... forward current V _R ... reverse mutual Voltage J _R … Reverse leakage current trr… Reverse recovery time θ… Angle e… Contact surface f… Contact on PN junction s… Tangential line on PN junction D… Depth from contact surface e B… Base E… Emitter G… Gate S… Source DR… Drain

────────────────────────────────────────────────── ─── Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI H01L 29/872 (72) Inventor Shinji Kuri 10-13 Minamimachi, Hanno City, Saitama Prefecture Shindengen Kogyo Co., Ltd. (72) Invention Person Akira Sugiyama 10-13, Minami-cho, Hanno-shi, Saitama Pref. Shindengen Kogyo Co., Ltd. (56) References JP-A-60-31271 (JP, A) JP-A-3-105975 (JP, A) (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/02 H01L 29/48 H01L 29/72 H01L 29/80

Claims (6)

(57) [Claims] A semiconductor substrate having a 1. A one conductivity type semiconductor layer to form the one conductivity type semiconductor layer and the PN junction, and a plurality of exposure of the one conductivity type semiconductor layer on a surface of the one conductivity type semiconductor layer A reverse conductivity type semiconductor layer provided so as to define a region, comprising a plurality of exposed regions of the one conductivity type semiconductor layer and a metal electrode provided over the reverse conductivity type semiconductor layer, A depth D between a contact surface formed by one of a plurality of exposed regions of the one conductivity type semiconductor layer and the metal electrode and a bottom of the opposite conductivity type semiconductor layer; co when the relationship between the minimum distance W between the regions be under the surface opposing the opposite conductivity type semiconductor layer to D ≧ 0.5 W
The contact surface or the surface of the one conductivity type semiconductor layer;
Depletion layer at zero bias generated in the semiconductor layer of one conductivity type
The top surface of the contact surface or the surface of the one conductivity type semiconductor layer
Tangent passing through the intersection of a straight line extending in parallel with the PN junction
Wherein the angle θ is 60 ° ≦ θ ≦ 120 ° . Wherein when the width of the depletion layer was W _b1, the closest distance W is a semiconductor device according to claim 1, characterized in that the W _b1 ≦ W ≦ 3W _b1. 3. The contact surface between the metal electrode and the one conductivity type semiconductor layer and the contact surface between the metal electrode and the opposite conductivity type semiconductor layer are formed by either ohmic contact or Schottky barrier contact. 3. The semiconductor device according to claim 1, wherein: 4. The semiconductor device according to claim 1, wherein the semiconductor substrate is made of a semiconductor having a high impurity concentration, and the semiconductor layer has a low impurity concentration. Semiconductor device. 5. A semiconductor device according to claim 1, wherein said semiconductor substrate is a collector made of a reverse conductivity type semiconductor having a high impurity concentration, said one conductivity type semiconductor layer is a base having a low impurity concentration, and said metal electrode including said contact surface is an emitter. Claim 1.
4. The bipolar transistor according to any one of claims 1 to 3, 6. The semiconductor substrate according to claim 1, wherein the semiconductor substrate has a drain made of one conductivity type semiconductor having a high impurity concentration, the one conductivity type semiconductor layer has a channel having a low impurity concentration, and the metal electrode including the contact surface serves as a gate. 4. The static induction transistor according to claim 1, further comprising a source provided in the conductive semiconductor layer and made of a semiconductor having a high impurity concentration.