JP3317147B2 - Malfunction prevention method, malfunction prevention circuit, and audio processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a malfunction prevention method,
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a malfunction prevention circuit and a voice processing device, and more particularly to a malfunction prevention method, a malfunction prevention circuit, a malfunction prevention method thereof, and a malfunction prevention that can prevent a malfunction caused by noise with a simple processing method and a simple digital circuit. The present invention relates to an audio processing device to which a circuit is applied.

[0002] An audio signal processing apparatus to which a digital signal processor (DSP) is applied has been widely put into practical use. The main function of this audio signal processing device is to convert an audio signal that is normally pulse code modulated (PCM) at a rate of 64 kb / s,
For example, band compression is performed digitally to 8 Kb / s or 16 Kb / s signals. However, since there is a strong demand for miniaturization of equipment such as a portable radio telephone equipped with an audio signal processing device, audio signal processing is performed by a DSP. The need to handle even the peripheral functions of the device is increasing.

[0003] That is, the audio processing unit of the audio signal processing device performs band compression processing on the pulse code modulated audio signal. Further, the control unit selects an audio compression processing method according to an externally applied signal and handles a dialing signal. Therefore, an image diagram of the audio signal processing device to which the DSP is applied, including the peripheral functions, is as shown in FIG.

Since most of the dialing signals are signals from mechanical contacts, there is a possibility that so-called chattering may be on a normal signal. In addition, since the signal received in the method for selecting the audio compression processing method is transmitted via a relatively long transmission path, noise may be picked up during transmission.

[0005] If chattering of the dialing signal cannot be removed, a misconnection will occur, which will cause economical inconvenience to the user and make the user uncomfortable. Also, if the noise on the control signal for selecting the voice compression processing method cannot be removed, the band compression method of the caller and the called party cannot be matched because the band compression method is selected incorrectly. Not only will the call be disabled, but both users will hear pulsed noise that exceeds their patience limits.

Therefore, even if a signal containing noise is received,
It is very important that malfunction due to noise can be prevented.

[0007]

2. Description of the Related Art Conventionally, a method of outputting a received signal as recognized is performed. Therefore, the received signal is mixed with noise, and if the received signal is recognized in the noise portion, the output signal becomes erroneous.

In order to avoid this, although not shown, conventionally, a resistor is inserted in a series branch in an input circuit for receiving a signal mixed with noise, and a terminal opposite to the input terminal of the resistor is connected to a potential. Is connected to a certain point (usually a ground point) to form an integration circuit by connecting a capacitor, and the integration time constant of the integration circuit is set to be longer than an expected duration of noise. Removes noise.

In a voice processing apparatus, a noise suppression circuit using the above-mentioned integration circuit is applied to a dialing signal input circuit and a signal input circuit for specifying a voice compression processing method.

[0010]

Therefore, it is possible to practically remove noise by forming an integrating circuit in the input circuit.

However, now is in the age of LSI, and a lot of complicated functions are realized in a very small area. The above-described integrating circuit using a resistor and a capacitor is not impossible to realize in an LSI, but the area of the portion forming the integrating circuit is increased, which has a considerable influence on the design of the LSI itself. In order to avoid this, if the integration circuit is formed of individual components outside the LSI, even if a chip component is used, the area of the portion forming the integration circuit is incomparable with the digital circuit realized in the LSI. It will be big.

In addition, although the image diagram of FIG. 14 shows a case where a signal from a single mechanical contact is taken in, this signal may be formed of a plurality of bits. In such a case, the above problem becomes more serious.

In view of the above problems, the present invention relates to a malfunction preventing method, a malfunction preventing circuit, and an audio processing device. A malfunction which can prevent malfunction caused by noise can be prevented by a simple processing method and a simple digital circuit. Prevention method,
An object of the present invention is to provide a malfunction preventing circuit and a sound processing device to which the malfunction preventing method or the malfunction preventing circuit is applied.

[0014]

The first means of the present invention is as follows.
A first register for storing an external input signal and a second register for transferring and storing a signal stored in the first register are provided. First, an output signal is arbitrarily set, and an external input signal is set. Reading a signal into a first register, making a first determination as to whether the external input signal read into the first register is equal to the signal stored in the second register, If the result of the determination is Yes, a second determination is made as to whether the signals stored in the two registers are equal to “1,1”, and the second determination result is Yes.
, The output signal is set to “1”, if the second determination result is No, the output signal is set to “0”, and if the first determination result is No, The output signal set as described above is transmitted without changing the output signal, and the signal stored in the first register is transferred / stored in the second register. Is completed, a signal from the outside is newly read into the first register, and thereafter, the above processing is repeated to prevent malfunction.

For example, when the output signal is to be kept at "1", the first register continuously stores "1".
Is stored, and therefore "1" is also stored continuously in the second register. At this time, it is assumed that the signal stored in the first register has been affected by noise.

According to the first means of the present invention, even if the input signal stored in the first register is affected by noise, the signal stored in the second register at that time is not affected by noise. Since it has not been received, the output signal remains at "1". At the next timing, the influence of the noise on the input signal stored in the first register disappears, and the signal stored in the first register under the influence of the noise in the past is stored in the second register. Therefore, the output signal does not change. At the next timing, the first and second registers store signals that are not affected by noise, so that there is no change in the output signal. Therefore, even if noise is mixed in the input signal, the output signal becomes a continuous "1", and the effect of noise is eliminated in the output signal.

The second means of the present invention is a malfunction preventing circuit which performs the same logical operation as the first means performs for setting an output signal. Assuming that the signal stored in the first register is A, the signal stored in the second register is B, and the past output signal is C, the first means outputs the newly set output. This means that the signal is given by the logical formula (A × (B + C)) + (B × C).

Therefore, according to the second means of the present invention for realizing the above logical expression, even if noise is mixed in the input signal,
An output signal from which the influence of noise has been removed can be obtained. A third means of the present invention is an audio processing device to which the above-mentioned malfunction prevention method or malfunction prevention circuit is applied.

Since the above malfunction prevention method is realized by software in a processor originally provided in the speech processing device, the hardware scale of the speech processing device does not change even if the malfunction prevention function is provided. Further, since the malfunction prevention circuit can be constituted by a simple logic circuit, it can be constituted in a control unit originally provided in the audio processing device.
Substantially no change occurs in the hardware scale of the audio processing device.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a flowchart of a malfunction preventing method according to the present invention. The operation will be described below along the reference numerals in FIG.

S1. The output signal C is temporarily set. This may be "1" or "0". S2. An input signal A stored in a first register;
The signal B stored in the second register and transferred and stored in the signal A is read.

S3. It is determined whether the signal A is equal to the signal B. S4. In step S3, if A and B are equal (Yes), it is determined whether both A and B are equal to "1" or whether A and B are both equal to "0".

S5. In step S4, if both A and B are "1" and equal (Yes), the current output signal C
Is "1". S6. In step S4, also when both A and B are "1" and not equal (No), it is determined whether or not the current output signal C is "1".

S7. If the output signal C is "1" (Yes) in step S6, and if the output signal C is not "1" (No) in step S5, the output signal C
To change.

S8. At step S6, the output signal C is not "1" (No), at step S5, the output signal C is "1" (Yes), and at step S3.
If the signal A and the signal B stored in the two registers are not equal (No), the output signal C is not changed.

S9. The output signal determined in step S8 is output. S10. The signal A stored in the first register is transferred and stored in the second register, and the process returns to step S2.

Thereafter, steps S2 to S10
Is repeated. Here, the above operation will be specifically described. First, the output signal C is set to “1”. It is also assumed that the signal A stored in the first register and the signal B stored in the second register are both "1".

In this case, since the signal A and the signal B are equal to "1", the process proceeds to Yes in step S3, and also proceeds to Yes in step S4. Then, since C is "1", the process proceeds to Yes in step S5, so that the process reaches step S8, and the output signal C is maintained at "1".

Therefore, when both the signal A and the signal B are "1",
If the current output signal C is "1", the next output signal C
Is determined to be “1”. Similarly, by assuming the signal A, the signal B, and the past output signal C and performing the above processing, the output signal C for all cases can be obtained.

FIG. 2 shows what is obtained in this manner.
7 is a truth table corresponding to the flowchart of FIG. It can be seen from this that when the signal A and the signal B are both “0”, the output signal is “0” regardless of the past output signal C.
When both the signal A and the signal B are “1”, the output signal is “1” regardless of the past output signal C, and when the signal A and the signal B are not equal, Is "0" when the output signal C is "0", and the output signal is "1" when the past output signal C is "1".
become.

That is, the output signal becomes "1" (true) depending on whether the signal B is true and the past output signal C is true,
This is the case when the signal A is true and the signal B or the past output signal C is true.

Expressing this as a logical expression, the output signal is given by (A × (B + C)) + (B × C).

FIG. 3 is a time chart (No. 1) corresponding to the flowchart of FIG. 1, showing a case where an external input signal changes between "1" and "0". An external input signal is stored in a first register by a clock. Therefore, the signal stored in the first register is as shown in FIG.

This is transferred and stored in the second register by the clock. Therefore, the signal stored in the second register is as shown in FIG. In the case of FIG. 3, since the initial values of A and B are both "1", the past output signal C
Irrespective of the above, the output signal is determined to be "1", and the output signal is kept at "1" at least while both the signal A and the signal B are "1".

Next, the signal A changes to "0" and the signal B is maintained at "1".
Is "1", the output signal is also "1" at that time. Next, when both the signal A and the signal B are "0", the output signal becomes "0" regardless of the past output signal C, so that the output signal changes to "0".

The output signal is maintained at "0" while at least the signal A and the signal B are both "0". Then
In a state where the signal A changes to “1” and the signal B is maintained at “0”, the past output signal C is “0”, so that the next output signal also remains “0”.

Further, when the signal A is kept at "1" and the signal B is changed to "1", the output signal becomes "1" regardless of the past output signal. 1 ", and thereafter, the output signal remains at" 1 ".

That is, this indicates that the output signal becomes a signal corresponding to the input signal. FIG. 4 is a time chart (part 2) corresponding to the flowchart of FIG. 1, showing a case where noise is superimposed where an external input signal should be a continuous signal of "1".

An external input signal is stored in a first register by a clock. The first register stores a signal which changes to "0" in a phase where noise exists as shown in FIG. 4A. And

Since A is transferred and stored in the second register by the clock, the signal stored in the second register is as shown in FIG. 4B. In this case, signal A and signal B
Is "1", the output signal becomes "1" regardless of the past output signal C, and at least the signal A
The signal is kept at "1" while the signal and the signal B are at "1".

Next, in a state where the signal A changes to "0" and the signal B is maintained at "1", the past output signal C becomes "1".
Therefore, the output signal is also kept at "1". Next, in a state where the signal A returns to “1” and the signal B changes to “0”, the output signal is also kept at “1” because the past output signal C is also “1”.

When both the signal A and the signal B maintain "1", the output signal remains at "1". That is, even if noise is superimposed when the external input signal should be "1", the output signal is not affected by the noise. If the above processing is not performed, the output signal becomes the same as A in FIG. 4 and a malfunction occurs due to noise, so that the effect of the processing of the present invention is great.

In the case of FIG. 4, there is no problem because the clock is read only once during the continuation of the noise. In such a case, if “0” can be read continuously in the phase where noise exists,
It becomes the same as the case where the input signal from the outside changes in a normal state, and it becomes impossible to remove the influence of noise.

However, since the duration of the noise can be statistically grasped by the nature of the noise source, if the clock cycle is set longer than the duration of the noise with reference to the knowledge, the noise becomes 2
It can be prevented from being read more than once. Therefore, it is possible to substantially eliminate the influence of noise.

FIG. 5 shows a first embodiment of a malfunction prevention circuit according to the present invention. In FIG. 5, 1a is a first flip-flop, 1b is a second flip-flop, 1c
Is a third flip-flop, 2a is a first OR circuit, 2b is a second OR circuit, 3a is a first AND circuit, and 3b is a second AND circuit.

An input signal is supplied to a data terminal of a first flip-flop, and an output of the first flip-flop is supplied to a data terminal of a second flip-flop. Also, the data terminal of the third flip-flop is
An output signal is supplied.

Here, assuming that the output of the first flip-flop is A, the output of the second flip-flop is B, and the output of the third flip-flop is C, B is determined by the first OR circuit. And C are calculated by the first logical product circuit, the logical product of B and C is calculated by the first logical product circuit, and the logical product of A and the logical sum of the output of the first logical sum circuit is calculated by the second logical product circuit. Is calculated, and the second OR circuit calculates the logical sum of the outputs of the first and second AND circuits.

Therefore, it can be seen that the logical operation function of the configuration of FIG. 5 can be represented by the logical expression (A × (B + C)) + (B × C).

FIG. 6 is a time chart (No. 1) of the configuration of FIG. 5 and shows a case where the input signal normally changes between "1" and "0". Since the input signal is read by the clock and stored in the first register, the signal stored in the first register is as shown in FIG.

Since the signal A is transferred and stored in the second register by the clock, the signal stored in the second register is as shown in FIG. 6B. Therefore, the output signal is C
However, A, B and C are applied to the first AND circuit and the first OR circuit and the second OR circuit shown in FIG. Then, when it is confirmed that the output of the second OR circuit becomes a signal equal to C,
It can be verified that the circuit of FIG. 5 performs a desired operation.

The output of the second AND circuit is A × (B
+ C), and the output of the first AND circuit is as shown in FIG. 6B × C.
A signal shown by (A × (B + C)) + (B × C) in FIG. 6 is obtained. Since this is a signal equal to C in FIG. 6, the configuration of FIG. 5 can generate an output signal corresponding to the input signal.

FIG. 7 is a time chart (No. 2) of the configuration of FIG. 5, showing a case where noise is superimposed when the input signal should be "1". Since the input signal is read by the clock and stored in the first register, the signal stored in the first register is as shown in A of FIG.

Since the signal A is transferred and stored in the second register by the clock, the signal stored in the second register is as shown in FIG. 7B. Therefore, the output signal is C
However, A, B and C are applied to the first AND circuit and the first OR circuit and the second OR circuit shown in FIG. Then, when it is confirmed that the output of the second OR circuit becomes a signal equal to C,
It can be verified that the circuit of FIG. 5 performs a desired operation.

The output of the second AND circuit is A × (B
+ C), and the output of the first AND circuit becomes B × C in FIG. 7.
A signal shown by (A × (B + C)) + (B × C) in FIG. 7 is obtained. Since this is a signal equal to C in FIG. 7, even if noise is superimposed on the input signal, the configuration of FIG. 5 can eliminate the influence of the noise.

If the clock can read the noise at an incorrect level twice or more consecutively due to the long duration of the noise, the influence of the noise cannot be eliminated. , Can be avoided by setting the clock period longer than the duration of the noise that can be statistically known.

FIG. 8 is a time chart (No. 3) of the configuration of FIG. 5 and shows a case where noise is superimposed on the rising phase of the input signal. Since the input signal is read by the clock and stored in the first register, the signal stored in the first register is as shown in A of FIG.

Since the signal A is transferred and stored in the second register by the clock, the signal stored in the second register is as shown in FIG. 8B. Therefore, the output signal is C
However, A, B and C are applied to the first AND circuit and the first OR circuit and the second OR circuit shown in FIG. Then, when it is confirmed that the output of the second OR circuit becomes a signal equal to C,
It can be verified that the circuit of FIG. 5 performs a desired operation.

The output of the second AND circuit is A × (B
+ C), and the output of the first AND circuit is as shown in FIG. 6B × C.
A signal shown by (A × (B + C)) + (B × C) in FIG. 8 is obtained. Since this is a signal equal to C in FIG. 8, the configuration of FIG. 5 can generate an output signal corresponding to the input signal.

If the clock has a long duration and the clock can read the noise twice or more consecutively at an incorrect level, the influence of the noise cannot be eliminated. However, this is the same as described above. , Can be avoided by setting the clock period longer than the duration of the noise that can be statistically known.

FIG. 9 shows a second embodiment of the malfunction prevention circuit according to the present invention. In FIG. 9, 1a is a first flip-flop, 1b is a second flip-flop, 1c
Is a third flip-flop, 2a is a first OR circuit, 2b is a second OR circuit, 3a is a first AND circuit, 3b is a second AND circuit, and 3c is a third logical circuit. The product circuit 4 is a NOT circuit.

The input signal is applied to the data terminal of the first flip-flop, the output of the first flip-flop is applied to the data terminal of the second flip-flop, and the data of the third flip-flop. An output signal is applied to the terminal. If the output of the first flip-flop is A, the output of the second flip-flop is B, and the output of the third flip-flop is C, the logical product of A and B is obtained by the first logical product circuit. Is calculated by the second logical product circuit, and the logical product circuit of the output of the first logical product circuit and the NOT signal of C is calculated, and A is calculated by the first logical sum circuit.
And B, and the third logical product circuit calculates the logical product of the output of the first logical sum circuit and C, and the second logical sum circuit calculates the output of the second logical product circuit. And the logical sum of the output of the third AND circuit.

Therefore, the logical expression indicating the operation of the configuration of FIG. 9 is ((notC) × (A × B)) + (C × (A + B)). When this logical expression is transformed, it turns out to be the same as the logical expression already described, and if a truth table is prepared, the same truth table as that shown in FIG. 2 is obtained. Therefore, the configuration of FIG. 9 is also a circuit that can prevent malfunction due to noise.

However, since the time charts are shown in FIGS. 6 to 8 redundantly, they are omitted. The malfunction prevention circuit that generates an output signal for a 1-bit input signal has been described above. However, in general, the input signal is often a multi-bit parallel signal.

If the signal is data itself and the number of parallel bits of the output signal must be equal to the number of parallel bits of the input signal, the above logical operation is performed by software for each bit of the input signal and the input is performed. An output signal having the same number of bits as the signal may be obtained, or the circuit of FIG. 5 or 9 may be provided for each bit of the input signal.

When the signal is a setting signal of some kind and the input signal is represented by multiple bits but the output signal may be one bit, the A stored in the first register is used.
_i (i = 1 to n) and B stored in the second register
_i (i = 1 to n) are treated as independent input signals,
The output signal may be generated based on the truth table shown in FIG. 10 in which the input is a plurality of bits and the output is 1 bit.

That is, in the case of performing the calculation by software, using all A _i (i = 1 to n) and B _i (i = 1 to n),
When A _i and B _i are all “1”, the output signal is set to “1” regardless of the past output signal C, and A _i and B _i are set.
There the output signal regardless of the whether the past output signal C when all "0" is set to "0", when the "1" to A _i and B _i "0" are mixed, past output If the signal C is "0", the output signal is set to "0". If the past output signal C is "1", the output signal is set to "1".

FIG. 11 shows a third embodiment of the malfunction prevention circuit according to the present invention, in which the input signal is a setting signal, the input signal is represented by a plurality of bits, and the output signal may be 1 bit. 1 shows the configuration.

In FIG. 11, 1 is a flip-flop, 2 is a two-input AND circuit, 5 is an n-bit serial-parallel conversion circuit, 6 is an n-bit flip-flop group, 7
a is a first (n + 1) input AND circuit, 7b is a second (n + 1) input AND circuit, and 8 is a (n + 1) input OR circuit.

In the configuration of FIG. 11, one input signal is applied to the input terminal with n serial bits, and the input signal is developed into a parallel signal by an n-bit serial-parallel conversion circuit. 5 is changed to an n-bit flip-flop group, the first and second AND circuits in FIG. 5 are changed to (n + 1) input AND circuits, and the first logical circuit in FIG. Although the sum circuit has been changed to an (n + 1) input OR circuit, the basic operation is shown in FIG.
The configuration is exactly the same.

Here, FIG. 11 based on the configuration of FIG.
Has shown the configuration of the malfunction prevention circuit in the case where the input signal is a setting signal, the input signal is represented by a plurality of bits, and the output signal may be 1 bit, but the configuration of FIG. Even so, a malfunction prevention circuit having a similar function can be realized. This configuration can be easily derived,
Illustration is omitted.

FIG. 12 shows a first embodiment of the audio signal processing apparatus according to the present invention. 12, 10 is an audio signal processing device, 11 is a control unit in the audio signal processing device,
12 is a processor of the control unit, 13 is a first register for storing an input signal, 14 is a second register for storing a past input signal (a signal transferred from the first register), 1
5 is a third register for storing the generated output signal, 16
Denotes an audio processing unit in the audio signal processing device. Note that parts of the audio signal processing device that are not directly related to the technology of the present invention are not shown.

The input signal is stored in the first register, and at the same time, the signal stored in the first register is transferred to the second register. An output signal is stored in the third register.

The processor reads the signals stored in the first, second, and third registers, performs an operation corresponding to the logical expression described above, determines an output signal, and outputs the output signal to the third register. I do.

The output signal stored in the third register is supplied to an audio processing unit, and is used as a selection signal of an audio processing method. If the output signal is generated directly from the input signal and used as a signal for selecting the audio processing method, if noise is superimposed on the input signal, the wrong audio processing method will be selected. The system cannot be matched, and the speaker will hear severe pulse noise. However, by applying the malfunction prevention method of the present invention, the fear is eliminated.

The essential configuration does not change even if the input signal is a parallel signal of a plurality of bits. FIG. 13 shows a second embodiment of the audio signal processing device of the present invention. 13, 10a is an audio signal processing device, 11a is a control unit in the audio signal processing device, 12a is a processor of the control unit,
Reference numeral 17 denotes a malfunction prevention circuit, and reference numeral 16 denotes an audio processing unit in the audio signal processing device. In FIG. 13, parts of the audio signal processing device that are not directly related to the technology of the present invention are not shown.

The input signal is input to the malfunction prevention circuit.
The malfunction prevention circuit is specifically shown in FIG. 5 or FIG. 9 or FIG.
This configuration has the configuration shown in FIG. 1 and generates an output signal by eliminating the influence of noise superimposed on the input signal. The output signal is supplied to a processor and also to an audio processing unit, and is used as a selection signal of an audio processing method.

If an output signal is directly generated from an input signal and is used as a signal for selecting an audio processing method, an incorrect audio processing method is selected when noise is superimposed on the input signal. Cannot be matched with the voice processing method of the present invention, and the speaker hears severe pulse noise. However, by applying the malfunction prevention method of the present invention, the fear is eliminated.

Here, the embodiment of the audio signal processing apparatus shown in FIGS. 12 and 13 is to prevent a malfunction for a setting signal for generating an audio processing system selection signal. It is also possible to perform a malfunction prevention on the input, and it is also possible to perform it by software or by hardware. By doing so, it is possible to prevent generation of click noise due to erroneous recognition of the voice input signal by noise.

Although there are various types of audio band compression techniques, in the method of generating an output audio signal by correlating with the previous audio data, once an erroneous recognition occurs, the effect continues for a considerably long time. . Therefore, by preventing erroneous recognition (erroneous operation), it is possible to prevent deterioration in voice quality.

Further, it is of course possible to apply to both the setting signal and the audio signal at the same time. Further, even when the control signal is a control signal such as a setting signal, the control signal is not limited to the selection signal of the audio processing method.

That is, the malfunction preventing method and the malfunction preventing circuit of the present invention can be applied to any signal in the audio signal processing device. And, of course, the malfunction prevention method and malfunction prevention circuit of the present invention can be applied to all information communication devices.

[0082]

As described in detail above, by applying the malfunction preventing method and the malfunction preventing circuit of the present invention, malfunctions caused by noise superimposed on the input signal can be prevented, and the audio signal processing device can be realized. In addition to ensuring the reliability of the operation of the information communication device including the information communication device, the transmission quality of the information communication device including the audio signal processing device can be secured.

[Brief description of the drawings]

FIG. 1 is a flowchart of a malfunction prevention method according to the present invention.

FIG. 2 is a truth table corresponding to the flowchart of FIG.

FIG. 3 is a time chart (part 1) corresponding to the flowchart of FIG. 1;

FIG. 4 is a time chart (part 2) corresponding to the flowchart of FIG. 1;

FIG. 5 is a first embodiment of a malfunction prevention circuit according to the present invention.

FIG. 6 is a time chart of the configuration of FIG. 5 (part 1).

FIG. 7 is a time chart of the configuration of FIG. 5 (part 2).

FIG. 8 is a time chart (part 3) of the configuration of FIG. 5;

FIG. 9 shows a second embodiment of the malfunction prevention circuit of the present invention.

FIG. 10 is a truth table in a case where the input may be plural bits and the output may be one bit.

FIG. 11 shows a third embodiment of the malfunction prevention circuit of the present invention.

FIG. 12 shows a first embodiment of an audio signal processing device according to the present invention.

FIG. 13 shows a second embodiment of the audio signal processing device of the present invention.

FIG. 14 is an image diagram of an audio signal processing device.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 flip-flop 1a first flip-flop 1b second flip-flop 1c third flip-flop 2 two-input OR circuit 2a first OR circuit 2b second OR circuit 3a first logic Product circuit 3b second AND circuit 4 negation circuit 5 n-bit serial-parallel conversion circuit 6 n-bit flip-flop group 7a first (n + 1) input AND circuit 7b second (n + 1) input AND circuit 8 (n + 1) input OR circuit 10 Audio signal processing device 10a Audio signal processing device 11 Control unit 11a Control unit 12 Processor 12a Processor 13 First register 14 Second register 15 Third register 16 Audio processing Part 17 Malfunction prevention circuit

────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Noboru Kobayashi 4-1-1, Kamikodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (56) References JP-A-63-63215 (JP, A) 59-37732 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 3/02 H03K 5/1254 H03K 17/00

Claims (5)

(57) [Claims] About 1. A input signal A and the input signal A and shifted signal B and the past output signal C, when the said A and said B are equal both at one logic level, the logic level of the C Regardless of the logic level of A, the output signal is determined to a particular logic level, and if both A and B are equal at the other logic level, the output signal is determined regardless of the logic level of C.
A malfunction prevention method comprising: determining a logic level different from the specific logic level; and determining, when A and B are different, an output signal equal to C regardless of C. . 2. A multi-bit input signal A _i (i = 1 to 2)
n; n is a positive integer), a signal B _i (i = 1 to n; n is a positive integer) obtained by shifting the input signal A _i , and a past output signal C
For, if the A _i and the B _i are equal for all one logic level, the Ikagani though the output signal of the logic level of the C determines the particular logic level, the A _i and the B _i is If equal at all the other logic level, the Ikagani though the output signal of the logic level of the C determines a logic level different from the said particular logic level, different in the a _i and the B _i A malfunction prevention method characterized in that, when logic levels are mixed, an output signal is determined to be equal to C regardless of C. About wherein the input signal A and the input signal A and shifted signal B and the past output signal C, when the said A and said B are equal both at one logic level, the logic level of the C Regardless of the output signal, an output signal of a specific logic level is generated, and when A and B are both equal at the other logic level, the output signal is output at the same logic level as C. Regardless of the output signal
Generating an output signal having a logic level different from the specific logic level , and, when A and B are different, generating an output signal equal to C regardless of C; Characteristic malfunction prevention circuit. 4. A multi-bit input signal A _i (i = 1 to 4)
n; n is a positive integer), a signal B _i (i = 1 to n; n is a positive integer) obtained by shifting the input signal A _i , and a past output signal C
If A _i and B _i are all equal at one logic level, an output signal of a specific logic level is generated regardless of the logic level of C, and A _i and B _i are If all are equal at the other logic level, the output signal is independent of the C logic level.
To generate an output signal of a logic level different from the specific logic level, and if different logic levels are mixed in the A _i and the B _i , an output signal equal to the C regardless of the C A malfunction prevention circuit characterized by generating a signal. 5. A method according to claim 1 or malfunction prevention method according to any the serial <br/> mounting according to claim 2, or claim 3 or claim 4 Neu
An audio signal processing device to which any one of the malfunction prevention circuits described in any of the above is applied.