JPS63306729A - Clock crossover circuit - Google Patents

Abstract

PURPOSE:To preclude the possibility of an error in a readout data even if a write clock has a fluctuation by devising the circuit such that a difference between the count of a write address counter and a readout address counter is always not less than the setting value. CONSTITUTION:A data write means 10 writes a write data in parallel by using a write clock according to the address designation of a built-in write address counter and a multiplex means 11 uses a readout clock so as to multiplex the signal and to output the result according to the address designation of a built-in readout address counter. Moreover, a phase difference detection means 9 restarts the readout address counter from the initial value when a difference between the counts of the write address counter and the readout address counter, that is, a phase difference between a load shift pulse and a strobe pulse reaches a setting value or below thereby making the value not less than the setting value at all times. Thus, the possibility of the readout data in error is reduced even with the presence of fluctuation in the write clock.

Description

[Detailed Description of the Invention] [Summary] In a clock switching circuit, write data is written in parallel using the output of a write address counter, and then multiplexed and output using the output of a read address counter.

At this time, by using the phase difference detection means to prevent the difference between the count values of the write address counter and the read address counter from becoming less than a set value, the possibility of errors in the read data is reduced even if there is fluctuation in the write clock. It was made in a similar manner.

[Industrial application field]

The present invention relates to an improvement in a clock switching circuit 2 used in, for example, a satellite communication terminal equipment using punctured codes.

-IIQ, coding for automatically detecting and correcting errors that occur when transmitting data using a communication channel is performed by adding redundant bits to this data according to a certain rule.

At this time, if there is no bandwidth limit on the transmission path, the data can be transmitted as is, but on a transmission path with strict bandwidth restrictions, such as a satellite communication line, it is desirable to transmit as much data as possible, so the added redundant bits are appropriately erased. For example, by inserting data into 77
8, and may be sent as data with a higher coding rate (called punctured code).

Here, the coding rate 1/2 indicates that redundant focus l is added to data bit 1, and 778 indicates that redundant bit 1 is added to data bit 7.

On the other hand, on the receiving side, redundant bits are removed and clock switching is performed to convert data from the satellite line clock, which contains jitter caused by Doppler shift, etc., to data that is synchronized with the terrestrial line clock, which does not include jitter. The above data is extracted, but it is necessary that there is little possibility of data loss during this clock change.

[Conventional technology]

FIG. 4 is an explanatory diagram of the satellite communication terminal equipment.

In the figure, a signal received by an antenna (not shown) passes through a low-noise amplifier, 3 frequency converters, and a demodulator (not shown), and Lch and Qch data with a coding rate of 7/8, for example, are extracted. It will be done.

After the phase of this data is determined by the phase determining section 1, the speed converting section 2 removes redundant bits, switches the clock, and inserts dummy bits into the removed bits to increase the coding rate to 1.
72 data and FEC (forward e.g.
(error correction) The decoding unit 3 extracts the original data.

Next, FIG. 5 is a block diagram of a conventional example, and FIG. 6 is an explanatory diagram of the operation of FIG. 5. Here, the symbols on the left side of FIG. 6 indicate the waveforms of the portions with the same symbols in FIG. Below, the encoding rate is 778. The operation of FIG. 5 will be explained with reference to FIG. 6 assuming that the input data is two series of Ich and Qch.

In FIG. 5, after the write counter 4 and the read counter 7 are initialized by externally applying an initialization pulse when the power is turned on or communication is started (for example, the count value is set to 0).
count of the write clock (hereinafter abbreviated as W-CK) and read clock (hereinafter abbreviated as R-(abbreviated as J)) shown in Figure 6-○ and Figure 6-■. I do.

In addition, the input Ich and Qch write data (hereinafter abbreviated as W-DT) with a coding rate of 7/8 are Ich
and sequentially to the Qch serial shift register 5, -GK
(See Figure 6~■).

On the other hand, a strobe pulse (hereinafter abbreviated as STB) shown in FIG. 6-0 is applied to the parallel register 6 from the write counter 4 every four counts. Therefore,
The Ich 4 bits and Qch 4 bits written in the serial shift register 5, a total of 8 bits -DT, is the STB.
The signals are loaded all at once into the parallel register 6 at the rising point of (see FIG. 6--). Next, 7 bits of the 8-bit data written in the parallel register 6, excluding 1 redundant bit, are used as a load shift pulse (hereinafter abbreviated as LS) sent from the read counter 7.
After being loaded in parallel to the parallel-to-serial converter 8 at the rising point of , the data is serially read out by R-CK to obtain read data (see Fig. 6 - 2 and 2).

[Problems to be Solved by the Invention] However, as shown in the problem explanation diagrams in FIGS. 5 and 7, data is lost when J-7 is superimposed on W-CK due to line noise, Doppler, etc. etc. may occur.

That is, for example, the 4-bit W-DT for Ich written in the serial shift register 5 is loaded into the parallel register 6 by the STB as shown in FIG. 7-a, and then the LS
Then, the data is loaded into the parallel-serial converter 8 as shown in FIG. 7-b (in FIG. 7, 4-bit W-DTs are collectively indicated as DT-1, etc.).

Now, as shown in Figure 7-3TB, ST is detected by Doppler etc.
The rising point of B approaches the rising point of LS, and as it fluctuates, L
If it appears before the rising point of S (Fig. 7 = state of STB ■), an error will occur in the data written to the parallel-serial converter 8 (■-1. -〇-2 of Fig. 7-b)
reference).

That is, there is a problem in that if jitter is superimposed on W-CK, errors such as data loss or double reading may occur.

[Means for solving problems]

The above problem is solved by the clock switching circuit shown in FIG.

Here, 10 sequentially writes write data according to the address specification of the built-in write address counter.

In the data writing means, reference numeral 11 denotes a multiplexing means for reading the data written in the data writing means according to the designation of a built-in read address counter, multiplexing the read data on the time axis, and outputting the multiplexed data.

Further, 9 is when the difference between the count values of the write address counter and the read address counter becomes less than the set value,
This is a phase difference detection means that resets the readout counter and starts counting from an initial value.

[Effect]

In the present invention, the data writing means 10 writes write data in parallel using a write clock according to the address specification of a built-in write address counter, and then the multiplexing means 11 uses a read clock according to the address specification of a built-in read address counter. Multiplex and output.

Further, the phase difference detection means 9 detects the difference between the count values of the write address counter and the read address counter, that is, L
When the phase difference between S and STB becomes less than the set value, the read address counter is restarted from the initial value so that it does not always become less than the set value.

In other words, the read clock does not come close to within the set phase difference from the write clock, and since the parallel write data is multiplexed with the read clock and output, there is a possibility that the read data will be erroneous even if there is fluctuation in the write clock. becomes less.

〔Example〕

FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is an explanatory diagram of the operation of FIG. 2. In addition, the symbol on the left side in Fig. 3 is the second
The waveforms of the portions with the same symbols in the figure are shown. Further, the write address counter lO1 and the buffer memo January 02 are the constituent parts of the data writing means 10, and the read address counter 111. Multiplexer 112 represents a component of multiplexing means 111.

Hereinafter, the operation of FIG. 2 will be explained with reference to FIG. 3, assuming that the coding rate is 7/8.

First, the quaternary write address counter 101 counts one GK that is input, and counts it from 0 to 3 as shown in Figure 3-0.
The count value is repeatedly output.

Therefore, W-DT is sequentially sent to the part of the address corresponding to the above count value in the buffer memory 102 using W-CK.

However, each bit is stretched by a factor of 4 as shown in FIG. In addition, when QA rises to O, Ich
The W-DT of the Qch is written at the rising edge of 1, and the LDT of the Qch is written respectively (see FIG. 3 - ■, ■).

Then, the 4 bits x 2 = 8 bits of data of Lch and Qch written in the buffer memory 102 is applied to the multiplexer 112, but the output of the hexadecimal read address counter 111 that counts R-CK is used. When QA is O, Ich -DT data is sequential, and when it is I, Qch W-DT data is sequential.

7-bit multiplexed read data as shown in FIG. 3-■ is obtained by selection corresponding to the count value (see FIG. 3--). Note that 1 bit is a redundant bit, so it is not read out.

Here, the phase detector 91 is the write address counter 1
01 and the count value of the read address counter 111, and when the difference, that is, the phase difference between the write address and the read address, becomes less than the set value, reset the read address counter 111 and start counting from the initial value. Make it greater than or equal to the value.

Also, the output 01 of Qa of the read address counter (the shaded part in FIG. 3--) is shown in FIG. 3--.

If you set the phase so that it is approximately in the center of , 1 bit will be expanded to 4 bits.

Even if the W-CX fluctuates due to the shifter, the possibility of read data being lost is reduced.

That is, in addition to preventing the phase difference between the write address and the read address from becoming less than the set value, the number of stages of the panzer memory 102 is increased in response to the fluctuation width of W-CK, and the read data is stretched longer. The possibility of error can be reduced.

〔Effect of the invention〕

As described in detail above, according to the present invention, there is an effect that the possibility of occurrence of an error is reduced when switching between different speed clocks.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram of an embodiment of the invention, Fig. 3 is an explanatory diagram of the operation of Fig. 2, Fig. 4 is an explanatory diagram of the satellite terminal equipment, Fig. 5 6 is a block diagram of a conventional example, FIG. 6 is an explanatory diagram of the operation of FIG. 5, and FIG. 7 is an explanatory diagram of problems. In the figure, 9 is a phase difference detection means, 10 is a data writing means, and 11 is a multiplexing means. ■LQ θθ θl θ θ3 10 // /
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Claims (1)

[Scope of Claims] Data writing means (10) for writing write data in parallel according to the address designation of a built-in write address counter; and reading the data written to the data writing means according to the designation of a built-in read address counter; When the difference between the count values of the write address counter and the read address counter becomes equal to or less than a set value, the multiplexing means (11) multiplexes and outputs the multiplexed data on the time axis, and resets the read address counter to an initial value. 1. A clock switching circuit comprising: phase difference detection means (9) for performing a counting operation.